LTC3831EGN-1 [Linear]
High Power Synchronous Switching Regulator Controller for DDR Memory Termination; 高功率同步开关稳压控制器，用于DDR存储器终端
| 型号： | LTC3831EGN-1 |
| 厂家： | 
Linear |
| 描述： | High Power Synchronous Switching Regulator Controller for DDR Memory Termination |
| 文件： | 总20页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3831-1
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
U
FEATURES
DESCRIPTIO
VOUT as Low as 0.4V
The LTC®3831-1 is a high power, high efficiency switch-
ing regulator controller designed for DDR memory termi-
nation. The LTC3831-1 generates an output voltage equal
to 1/2 of an external supply or reference voltage. The
LTC3831-1 uses a synchronous switching architecture
with N-channel MOSFETs. Additionally, the chip senses
output current through the drain-source resistance of the
upper N-channel FET, providing an adjustable current
limit without a current sense resistor.
■
■
High Power Switching Regulator Controller
for DDR Memory Termination
■
VOUT Tracks 1/2 of VIN or External VREF
■
No Current Sense Resistor Required
■
Low VCC Supply: 3V to 8V
■
Maximum Duty Cycle >91% Over Temperature
■
Drives All N-Channel External MOSFETs
■
High Efficiency: Up to 95%
■
Programmable Fixed Frequency Operation:
The LTC3831-1 operates with input supply voltage as low
as 3Vandwithamaximumdutycycleof>91%.Itincludes
a fixed frequency PWM oscillator for low output ripple
operation. The 300kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831-1 supply current drops to <10µA.
100kHz to 500kHz
■
External Clock Synchronization Operation
■
Programmable Soft-Start
■
Low Shutdown Current: <10µA
■
Overtemperature Protection
■
Available in 16-PUin Narrow SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
■
DDR SDRAM Termination
■
SSTL_2, SSTL_3 Interface
■
HSTL Interface
U
TYPICAL APPLICATIO
0.75V DDR Memory Termination Application
V
DDQ
1.5V
Efficiency vs Load Current
100
T
= 25°C
A
12V
+
90
80
70
60
50
40
30
20
10
0
220µF
V
V
= 1.8V
= 1.5V
DDQ
DDQ
0.1µF
4.7µF
3.3V
PV
CC2
PV
CC1
4.7k
V
CC
TG
2.2µF
SS
I
MAX
1.3µH
V
1k
TT
OUT
0.01µF
(V
)
LTC3831-1 I
FB
0.75V
±10A
FREQSET
SHDN
BG
+
SHDN
PGND
GND
180µF
COMP
+
68pF
1k
22nF
R
4
0
1
2
3
5
6
7
8
9
10
38311 TA01a
FB
LOAD CURRENT (A)
–
R
3831 TAO1b
38311f
1
LTC3831-1
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage
ORDER PART
TOP VIEW
V
CC ....................................................................... 9V
NUMBER
TG
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BG
PV
V
PVCC1,2 ................................................................ 14V
Input Voltage
PV
CC1
CC2
LTC3831EGN-1
PGND
GND
CC
IFB, IMAX ............................................... –0.3V to 14V
R+, R–, FB, SHDN, FREQSET ..... –0.3V to VCC + 0.3V
Junction Temperature (Note 9)............................. 125°C
Operating Temperature Range (Note 4) .. –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
I
I
FB
MAX
–
R
FB
FREQSET
COMP
SS
GN PART MARKING
38311
+
R
SHDN
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 1.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
3
TYP
MAX
8
UNITS
V
Supply Voltage
●
●
5
V
V
V
V
CC
PV
PV , PV Voltage
CC1 CC2
(Note 7)
3
13.2
2.9
CC
UVLO
FB
V
V
Undervoltage Lockout Voltage
Feedback Voltage
2.4
V + = 1.5V, V – = 0V, V
R
= 1.25V
●
0.738
0.75
0.762
R
COMP
∆V
Output Load Regulation
Output Line Regulation
I
V
= 0A to 10A (Note 6)
= 4.75V to 5.25V
2
0.1
mV
mV
OUT
OUT
CC
I
I
Supply Current
Figure 1, V
= V
CC
●
●
0.7
1
1.6
10
mA
µA
VCC
SHDN
V
= 0V
SHDN
PV Supply Current
CC
Figure 1, V
= 0V
= V (Note 3)
●
●
20
0.1
30
10
mA
µA
PVCC
SHDN
CC
V
SHDN
∆f
Internal Oscillator Frequency
FREQSET Floating
●
230
300
1.2
360
kHz
V
OSC
V
V
V
V
V
at Minimum Duty Cycle
at Maximum Duty Cycle
SAWL
COMP
COMP
2.2
V
SAWH
Maximum V
V
= 0V, PV = 7V
CC1
2.85
10
V
COMPMAX
COMP
FB
∆f /∆I
Frequency Adjustment
kHz/µA
dB
OSC FREQSET
A
Error Amplifier Open-Loop DC Gain
Error Amplifier Transconductance
Error Amplifier Output Sink/Source Current
●
●
50
65
V
g
1600
2000
100
2400
µmho
µA
m
I
I
COMP
MAX
I
Sink Current
V
= V
CC
9
4
12
12
15
20
µA
µA
MAX
IMAX
(Note 10)
●
I
Sink Current Tempco
V
= V (Notes 6, 10)
3300
ppm/°C
MAX
IMAX
CC
38311f
2
LTC3831-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 1.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current
Soft-Start Source Current
●
●
●
●
2.4
IH
IL
0.8
1
V
I
I
I
V
V
V
= V
CC
0.1
–12
1.6
µA
IN
SHDN
= 0V, V
= 0V, V = V
CC
–8
–16
µA
SS
SS
IMAX
IFB
Maximum Soft-Start Sink Current
Undercurrent Limit
= V , V = 0V, V = V (Note 8),
mA
SSIL
IMAX
CC IFB
SS
CC
PV
CC1
= 7V (Note 7)
+
+
R
R Input Resistance
53.3
80
kΩ
ns
ns
%
t , t
Driver Rise/Fall Time
Figure 1, PV
Figure 1, PV
= PV
= PV
= 5V (Note 5)
= 5V (Note 5)
●
●
●
250
250
r
f
CC1
CC2
CC2
t
Driver Nonoverlap Time
Maximum TG Duty Cycle
25
91
120
95
NOV
CC1
DC
Figure 1, V = 0V (Note 7), PV
= 7V
MAX
FB
CC1
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 7: PV
must be higher than V by at least 2V for TG to operate at
CC1 CC
95% maximum duty cycle and for the current limit protection circuit to be
active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note9:ThisICincludesovertemperatureprotectionthatisintendedtoprotect
the device during momentary overload conditions. Junction temperature will
exceed 125°C when overtemperature protection is active. Continuous opera-
tionabovethespecifiedmaximumoperatingjunctiontemperaturemayimpair
device reliability.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3831-1 operating frequency, operating voltage and the external
FETs used.
Note 4: The LTC3831EGN-1 is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 10: The minimum and maximum limits for I
over temperature
MAX
includes the intentional temperature coefficient of 3300ppm/°C. This induced
temperature coefficient counteracts the typical temperature coefficient of the
external power MOSFET on-resistance. This results in a relatively flat current
limit over temperature for the application.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
38311f
3
LTC3831-1
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Error Amplifier Transconductance
vs Temperature
Load Regulation
Line Regulation
0.760
0.758
0.756
0.754
0.752
0.750
0.748
0.746
0.744
0.742
0.740
10
8
0.762
0.760
0.758
0.756
0.754
0.752
0.750
0.748
0.746
0.744
0.742
0.740
0.738
2400
2300
2200
2100
2000
1900
1800
1700
1600
T
= 25°C
A
T
= 25°C
A
REFER TO FRONT PAGE APPLICATION
NEGATIVE OUTPUT CURRENT
6
INDICATES CURRENT SINKING
4
2
0
–2
–4
–6
–8
–10
3
4
5
6
7
8
–10 –8 –6 –4 –2
0
2
4
6
8
10
–25
0
50
75 100 125
–50
25
V
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (A)
TEMPERATURE (°C)
CC
3831 G03
3831 G02
3831 G04
Error Amplifier Sink/Source
Current vs Temperature
Error Amplifier Open-Loop Gain
vs Temperature
Output Voltage Temperature Drift
12
10
8
0.762
0.760
0.758
0.756
0.754
0.752
0.750
0.748
0.746
0.744
0.742
0.740
0.738
200
180
70
65
60
55
REFER TO FRONT PAGE APPLICATION
OUTPUT = NO LOAD
6
160
140
4
2
0
120
100
80
–2
–4
–6
–8
–10
–12
60
40
50
–50 –25
0
25
50
75 100 125
–25
0
50
75 100 125
–50
25
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3831 G05
3831 G06
3831 G07
Oscillator Frequency
vs Temperature
Oscillator Frequency
Oscillator (VSAWH – VSAWL
)
vs FREQSET Input Current
vs External Sync Frequency
360
350
340
330
320
310
300
290
280
270
260
250
240
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
700
FREQSET FLOATING
T = 25°C
A
T
= 25°C
A
600
500
400
300
200
100
0
–50 –25
0
25
125
30
10
0
10
20
30
100
200
300
400
500
50
75 100
20
TEMPERATURE (°C)
FREQSET INPUT CURRENT (µA)
EXTERNAL SYNC FREQUENCY (kHz)
3831 G08
3831 G09
3831 G10
38311f
4
LTC3831-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum TG Duty Cycle
vs Temperature
IMAX Sink Current
vs Temperature
Output Overcurrent Protection
0.8
100
99
98
97
96
95
94
93
92
20
18
16
14
12
10
8
V
= 0V
FB
REFER TO FRONT PAGE APPLICATION
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
6
T
= 25°C
A
REFER TO FRONT PAGE APPLICATION
91
4
8
0
2
4
6
10
12
14
–50 –25
0
25
125
–50 –25
0
25
50
75 100 125
50
75 100
OUTPUT CURRENT (A)
TEMPERATURE (°C)
TEMPERATURE (°C)
3831 G13
3831 G11
3831 G12
Output Current Limit Threshold
vs Temperature
Soft-Start Source Current
vs Temperature
Soft-Start Sink Current
vs (VIFB – VIMAX
)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
–8
–9
2.00
1.75
1.50
1.25
T
= 25°C
A
–10
–11
–12
–13
–14
–15
–16
1.00
0.75
0.50
0.25
0
1
0
REFER TO FRONT PAGE APPLICATION
–25
0
50
75 100 125
–125 –100
–50
–50
25
–150
–25
0
50
75 100 125
–75
– V
–50
0
25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(mV)
IFB
IMAX
3831 G15
3831 G16
3831 G14
Undervoltage Lockout Threshold
Voltage vs Temperature
VCC Operating Supply Current
vs Temperature
PVCC Supply Current
vs Oscillator Frequency
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
90
80
70
60
50
40
30
20
10
T
= 25°C
FREQSET FLOATING
A
TG AND BG LOADED
WITH 6800pF,
PV
= 12V
CC1,2
TG AND BG
LOADED
TG AND BG
LOADED
WITH 6800pF,
WITH 1000pF,
PV
= 5V
CC1,2
PV
= 5V
CC1,2
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
0
400
500
100
200
300
TEMPERATURE (°C)
OSCILLATOR FREQUENCY (kHz)
3831 G17
3831 G18
3831 G19
38311f
5
LTC3831-1
TYPICAL PERFOR A CE CHARACTERISTICS
U W
PVCC Supply Current
vs Gate Capacitance
TG Rise/Fall Time
vs Gate Capacitance
Transient Response
80
200
180
160
140
120
100
80
T
= 25°C
T
= 25°C
A
A
70
60
50
40
30
20
VOUT
50mV/DIV
PV
= 12V
CC1,2
t AT PV
f
= 5V
CC1,2
ILOAD
2A/DIV
t AT PV
r
= 5V
CC1,2
60
PV
= 5V
CC1,2
40
50µs/DIV
3831 G22.tif
t AT PV
= 12V
CC1,2
f
10
0
20
t AT PV
= 12V
CC1,2
r
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
GATE CAPACITANCE AT TG AND BG (nF)
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
3831 G21
U
U
U
PI FU CTIO S
TG ( Pin 1): Top Driver Output. Connect this pin to the gate
of the upper N-channel MOSFET, Q1. This output swings
from PGND to PVCC1. It remains low if BG is high or during
shutdown mode.
tor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831-1
can operate with a minimum VFB of 0.4V and maximum
VFB of (VCC – 2V).
PVCC1 (Pin2):PowerSupplyInputforTG.Connectthispin
to a potential of at least VIN + VGS(ON)(Q1). For normal
operation, PVCC1 must also be higher than VCC by at least
2V when TG is high. This allows the use of an external
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100µs puts the LTC3831-1 into
shutdown mode. In shutdown, TG and BG go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allowstheparttooperatenormally.Thispinalsodoubleas
an external clock input to synchronize the internal oscilla-
tor with an external clock.
charge pump to power PVCC1
.
PGND (Pin 3): Power Ground. Both drivers return to this
pin. Connect this pin to a low impedance ground in close
proximity to the source of Q2. Refer to the Layout Consid-
eration section for more details on PCB layout techniques.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, CSS, to implement a soft-start function. If the
LTC3831-1 goes into current limit, CSS is discharged to
reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3831-1.
R–, R+ (Pins 5, 7): These two pins connect to the internal
resistor divider that generate the internal ratiometric ref-
erence for the error amplifier. The reference voltage is set
at 0.5 • (VR+ – VR–).
COMP (Pin 10): External Compensation. This pin inter-
nallyconnectstotheoutputoftheerroramplifierandinput
of the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external resis-
38311f
6
LTC3831-1
U
U
U
PI FU CTIO S
transient response.
througha1kresistor.The1kresistorisrequiredtoprevent
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin floating, the oscillator runs at about 300kHz. A
resistorfromFREQSETtogroundspeedsuptheoscillator;
a resistor to VCC slows it down.
V
CC (Pin 14): Power Supply Input. All low power internal
circuits draw their supply from this pin. This pin requires
a 4.7µF bypass capacitor to GND.
IMAX (Pin 12): Current Limit Threshold Set. IMAX sets the
threshold for the internal current limit comparator. If IFB
drops below IMAX with TG on, the LTC3831-1 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit thresh-
old. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
PVCC2 (Pin 15): Power Supply Input for BG. Connect this
pin to the main high power supply.
BG(Pin16):BottomDriverOutput. Connectthispintothe
gate of the lower N-channel MOSFET, Q2. This output
swings from PGND to PVCC2. It remains low when TG is
high or during shutdown mode. To prevent output under-
shoot during a soft-start cycle, BG is held low until TG first
goes high (FFBG in the Block Diagram).
IFB (Pin 13): Current Limit Sense. Connect this pin to the
switching node at the source of Q1 and the drain of Q2
W
BLOCK DIAGRA
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
V
SHDN
100µs DELAY
CC
POWER DOWN
INTERNAL
OSCILLATOR
PV
TG
PV
BG
CC1
–
+
FREQSET
COMP
S
R
Q
Q
PWM
CC2
FFBG
12µA
PGND
FB
S
Q
ENABLE
BG
QSS
SS
POR
R
+
R
ERR
MAX
24k
+
+
–
–
V
REF
+ 10%
2.66k
2.66k
24k
V
V
V
+ 10%
REF
REF
REF
I
–
FB
CC
+
I
MAX
–
R
DISABLE
12µA
2.2V
1.2V
I
LIM
Q
C
GND
+
–
PV
V
CC1
38311 BD
V
+ 2V
CC
38311f
7
LTC3831-1
TEST CIRCUITS
PV
CC
+
V
V
V
SHDN
CC
CC
0.1µF
10µF
SHDN
PV
PV
I
FB
CC2
CC1
TG RISE/FALL
6800pF
NC
NC
SS
FREQSET
FB
TG
BG
V
LTC3831-1
FB
V
COMP
COMP
1.5V
+
BG RISE/FALL
6800pF
R
–
R
I
GND
PGND
MAX
38311 F01
Figure 1
W U U
U
APPLICATIO S I FOR ATIO
OVERVIEW
THEORY OF OPERATION
The LTC3831-1 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de-
signed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate driv-
ers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 300kHz.
Primary Feedback Loop
The LTC3831-1 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifier, ERR. The error
amplifier compares the output voltage to the internal
ratiometric reference, VREF, and outputs an error signal to
the PWM comparator. VREF is set to 0.5 multiplied by the
voltage difference between the R+ and R– pins, using an
internal resistor divider.
The LTC3831-1 is designed to generate an output voltage
thattracksat1/2oftheexternalvoltageconnectedbetween
the R+ and R– pins. The LTC3831-1 can be used to gener-
atetheterminationvoltage,VTT,forinterfaceliketheSSTL_2
This error signal is compared with a fixed frequency ramp
waveform, from the internal oscillator, to generate a pulse
width modulated signal. This PWM signal drives the
external MOSFETs through the TG and BG pins. The
resulting chopped waveform is filtered by LO and COUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
where VTT is a ratio of the interface supply voltage, VDDQ
.
ItisarequirementintheSSTL_2interfacestandardforVTT
to track the interface supply voltage to improve noise im-
munity. Using the LTC3831-1 to supply the interface ter-
mination voltage allows large current sourcing and sink-
ingthroughtheterminationresistorsduringbustransitions.
TheLTC3831-1includesacurrentlimitsensingcircuitthat
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. Also included is an internal soft-
start feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection.
MAX Feedback Loop
An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
compares the feedback signal to a voltage 10% above
VREF. If the signal is above the comparator threshold, the
MAX comparator overrides the error amplifier and forces
the loop to minimum duty cycle, 0%. To prevent this
38311f
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U
comparator from triggering due to noise, the MAX
comparator’sresponsetimeisdeliberatelydelayedbytwo
to three microseconds. This comparator helps prevent
extremeoutputperturbationswithfastoutputloadcurrent
transients, while allowing the main feedback loop to be
optimally compensated for stability.
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
remains at a reduced voltage until the overload is re-
moved. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the RDS(ON)
of Q1 to measure the output current, the current limiting
circuiteliminatesanexpensivediscretesenseresistorthat
would otherwise be required. This helps minimize the
number of components in the high current path.
Thermal Shutdown
The LTC3831-1 has a thermal protection circuit that dis-
ables both gate drivers if activated. If the chip junction
temperature reaches 150°C, both TG and BG are pulled
low. TG and BG remain low until the junction temperature
drops below 125°C, after which, the chip resumes normal
operation.
The current limit threshold can be set by connecting an
external resistor RIMAX from the IMAX pin to the main VIN
supply at the drain of Q1. The value of RIMAX is determined
by:
Soft-Start and Current Limit
RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX
where:
TheLTC3831-1includesasoft-startcircuitthatisusedfor
start-up and current limit operation. The SS pin requires
an external capacitor, CSS, to GND with the value deter-
mined by the required soft-start time. An internal 12µA
current source is included to charge CSS. During power-
up, the COMP pin is clamped to a diode drop (B-E junction
of QSS in the Block Diagram) above the voltage at the SS
pin. This prevents the error amplifier from forcing the loop
to maximum duty cycle. The LTC3831-1 operates at low
duty cycle as the SS pin rises above 0.6V (VCOMP ≈ 1.2V).
As SS continues to rise, QSS turns off and the error
amplifier takes over to regulate the output.
ILMAX = ILOAD + (IRIPPLE/2)
ILOAD= Maximum load current
IRIPPLE = Inductor ripple current
V – V
V
OUT
(
OUT)(
)
IN
=
f
L
V
( )(
)
OSC
O IN
fOSC = LTC3831-1 oscillator frequency = 300kHz
LO = Inductor value
The LTC3831-1 includes yet another feedback loop to
control operation in current limit. Just before every falling
edge of TG, the current comparator, CC, samples and
holds the voltage drop measured across the external
upperMOSFET,Q1,attheIFB pin.CCcomparesthevoltage
at IFB to the voltage at the IMAX pin. As the peak current
rises,themeasuredvoltageacrossQ1increasesduetothe
drop across the RDS(ON) of Q1. When the voltage at IFB
drops below IMAX, indicating that Q1’s drain current has
exceeded the maximum level, CC starts to pull current out
of CSS, cutting the duty cycle and controlling the output
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between IFB
and IMAX. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX = Internal 12µA sink current at IMAX
The RDS(ON) of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at IMAX is designed with a positive
temperature coefficient to provide first order correction
for the temperature coefficient of RDS(ON)Q1
.
Inorderforthecurrentlimitcircuittooperateproperlyand
toobtainareasonablyaccuratecurrentlimitthreshold,the
IMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across RIMAX to filter switching noise. Other-
wise, noise spikes or ringing at Q1’s source can cause the
I
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actual current limit to be greater than the desired current
where RFSET is a frequency programming resistor con-
nected between FREQSET and the external voltage source
VEXT.Connectingan82kresistorfromFREQSETtoground
limit set point. Due to switching noise and variation of
RDS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuitbeginstotakeeffectwillvaryfromunittounitasthe
forces 15µA out of the pin, causing the internal oscillator
to run at approximately 450kHz. Forcing an external 20µA
currentintoFREQSETcutstheinternalfrequencyto100kHz.
An internal clamp prevents the oscillator from running
slower than about 50kHz. Tying FREQSET to VCC forces
the chip to run at this minimum speed.
R
DS(ON) of Q1 varies. Typically, RDS(ON) varies as much as
±40% and with ±25% variation on the LTC3831-1’s IMAX
current, this can give a ±65% variation on the current limit
threshold.
Shutdown
The LTC3831-1 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allowstheparttooperatenormally.AlowlevelatSHDNfor
more than 100µs forces the LTC3831-1 into shutdown
mode.Inthismode,allinternalswitchingstops,theCOMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831-1 supply current drops to <10µA, although off-
state leakage in the external MOSFETs may cause the total
VIN current to be somewhat higher, especially at elevated
temperatures. If SHDN returns high, the LTC3831-1 re-
runs a soft-start cycle and resumes normal operation.
The RDS(ON) is high if the VGS applied to the MOSFET is
low. This occurs during power up, when PVCC1 is ramping
up.TopreventthehighRDS(ON) fromactivatingthecurrent
limit, the LTC3831-1 disables the current limit circuit if
PVCC1 is less than 2V above VCC. To ensure proper
operation of the current limit circuit, PVCC1 must be at
least 2V above VCC when TG is high. PVCC1 can go low
when TG is low, allowing the use of an external charge
pump to power PVCC1
.
V
IN
LTC3831-1
+
+
R
0.1µF
IMAX
C
IN
External Clock Synchronization
+
12
The LTC3831-1 SHDN pin doubles as an external clock
input for applications that require a synchronized clock.
An internal circuit forces the LTC3831-1 into external
synchronization mode if a negative transition at the SHDN
pin is detected. In this mode, every negative transition on
the SHDN pin resets the internal oscillator and pulls the
ramp signal low. This forces the LTC3831-1 internal
oscillator to lock to the external clock frequency.
I
MAX
12µA
CC
TG
BG
Q1
I
FB
L
O
1k
V
OUT
13
–
Q2
C
OUT
38311 F02
Figure 2. Current Limit Setting
Oscillator Frequency
The LTC3831-1 internal oscillator can be externally syn-
chronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
thisclocksignalmustnotbe>100µsorelsetheLTC3831-1
enters into the shutdown mode.
The LTC3831-1 includes an onboard current controlled
oscillator that typically free-runs at 300kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 300kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V. The fre-
quency can be estimated as:
Figure 3 describes the operation of the external synchro-
nization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that the ramp amplitude is lowered as the
38311f
1.265V – VEXT 10kHz
f = 300kHz +
•
RFSET
1µA
10
LTC3831-1
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external clock frequency goes higher. The effect of this
decrease in ramp amplitude increases the open-loop gain
of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feed-
backlooptobeunstableifthephasemarginisinsufficient.
supply must be above VIN by at least one power MOSFET
VGS(ON) for efficient operation. In addition, this supply
must be higher that VCC by at least 2V for normal opera-
tion. An internal level shifter allows PVCC1 to operate at
voltages above VCC and VIN, up to 14V maximum. This
higher voltage can be supplied with a separate supply, or
it can be generated using a charge pump.
To overcome this problem, the LTC3831-1 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
Gate drive for the bottom MOSFET Q2 is provided through
PVCC2. This supply only needs to be above the power
MOSFETVGS(ON) forefficientoperation. PVCC2 canalsobe
driven from the same supply/charge pump for the PVCC1
,
SHDN
or it can be connected to a lower supply to improve
efficiency.
In a typical low voltage DDR memory termination applica-
tion, VIN or VDDQ can be a low as 1.5V. If the only available
supply for the LTC3831-1 is 3.3V, a tripling charge pump
circuit can be added to power the PVCC1 and PVCC2 pins.
This requires sub-logic level threshold power MOSFET
with RDS(ON) specified at VGS = 2.5V.
200kHz
FREE RUNNING
RAMP SIGNAL
RAMP SIGNAL
WITH EXT SYNC
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
TERMINATION
Figure 5 shows a tripling charge pump circuit that powers
the PVCC1 and PVCC2 pins. This circuit provides (VCC
+
RAMP AMPLITUDE
ADJUSTED
2VIN – 3VF) to PVCC1 while Q1 is ON and (VCC + VIN – 2VF)
to PVCC2 where VF is the ON voltage of the Schottky diode.
ThecircuitrequirestheuseofSchottkydiodestominimize
forward drop across the diodes at start-up. The tripling
charge pump circuit will tend to rectify any ringing at the
drain of Q2 and can provide well more than (VCC + 2VIN)
at PVCC1. A 12V zener diode may be included from PVCC1
toPGNDtopreventtransientsfromdamagingthecircuitry
at PVCC1 or the gate of Q1.
LTC3831
KEEPS RAMP
AMPLITUDE
CONSTANT
UNDER SYNC
38311 F03
Figure 3. External Synchronization Operation
Input Supply Considerations/Charge Pump
V
CC
PV
CC2
PV
CC1
V
IN
The LTC3831-1 requires four supply voltages to operate:
VIN for the main power input, PVCC1 and PVCC2 for MOS-
FETgatedriveandaclean,lowrippleVCCfortheLTC3831-1
internal circuitry (Figure 4). VIN is usually connected to
VDDQ in most DDR memory termination applications.
TG
BG
Q1
L
O
INTERNAL
CIRCUITRY
V
OUT
+
C
Q2
OUT
The VCC supply can be as low as 3V and the quiescent
current is typically 800µA. Place a 4.7µA bypass capacitor
as close as possible to this pin. Gate drive for the top
N-channel MOSFET Q1 is supplied from PVCC1. This
38311 F04
LTC3831-1
Figure 4. Input Supplies
38311f
11
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The charge pump capacitors for PVCC1 refresh when the
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831-1
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the soft-
start capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipationinexternalMOSFETQ1. Thisismostlikelywith
low VCC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
Connecting the Ratiometric Reference Input
The LTC3831-1 derives its ratiometric reference, VREF
,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R+ and R– pins
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R+ and R–.
The LTC3831-1 can operate with a minimum VFB of 0.4V
and maximum VFB of (VCC – 2V). With R– connected to
GND, this gives a VR+ input range of 0.8V to (2 • VCC – 4V).
If VR+ is higher than the permitted input voltage, increase
the VCC voltage to raise the input range.
In a typical DDR memory termination, as shown in the
typical application on the front page, R+ is connected to
VDDQ, the supply voltage of the interface, and R– to GND.
The output voltage VTT is connected to the FB pin, so VTT
The LTC3831-1 overcomes this problem by sensing the
PVCC1 voltage when TG is high. If PVCC1 is less than 2V
above VCC, the maximum TG duty cycle is reduced to 70%
by clamping the COMP pin at 1.8V (QC in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
= 0.5 • VDDQ
.
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to VTT and FB
pin. Figure 6 shows an application that generates a VTT of
For applications using an external supply to power PVCC1
,
0.6 • VDDQ
.
this supply must also be higher than VCC by at least 2V to
ensure normal operation.
3.3V
V
CC
D
1N5817
Z
1N5817
12V
1N5242
1.5V
1N5817
V
IN
0.1µF
PV
CC2
PV
CC1
10µF
0.1µF
TG
Q1
V
CC
2.2µF
L
O
V
OUT
+
BG
Q2
C
OUT
38311 F05
LTC3831-1
Figure 5. Triple Charge Pump Configuration
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12
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U
V
DDQ
1.5V
+
12V
C
IN
220µF
4.7µF
10k
0.1µF
PV
PV
CC1
Q1
MBRS340T3
CC2
3.3V
V
CC
TG
L
O
SS
I
MAX
1.2µH
V
TT
OUT
1k
2.2µF
0.01µF
(V
)
I
LTC3831-1
FB
0.9V
±6A
MBRS340T3
Q2
FREQSET
SHDN
BG
+
SHDN
PGND
GND
C
OUT
470µF
COMP
C
OUT
: SANYO POSCAP 4TPB220M
: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
IN
C1
33pF
2k
R
C
+
C
R
1%
1k
FB
C
C
–
R
10nF
10k
1%
38311 F06
Figure 6. Typical Application with VTT = 0.6 • VDDQ
Power MOSFETs
After the MOSFET threshold voltage is selected, choose
theRDS(ON) basedontheinputvoltage, theoutputvoltage,
allowable power dissipation and maximum output cur-
rent. In a typical LTC3831-1 circuit operating in continu-
ous mode, the average inductor current is equal to the
output load current. This current flows through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
Two N-channel power MOSFETs are required for most
LTC3831-1 circuits. These should be selected based pri-
marily on threshold voltage and on-resistance consider-
ations. Thermal dissipation is often a secondary concern
in high efficiency designs. The required MOSFET thresh-
old should be determined based on the available power
supply voltages and/or the complexity of the gate drive
charge pump scheme. In 3.3V input designs where an
VOUT
V
IN
DC(Q1) =
auxiliary12VsupplyisavailabletopowerPVCC1 andPVCC2
,
standard MOSFETs with RDS(ON) specified at VGS = 5V or
6V can be used with good results. The current drawn from
thissupplyvarieswiththeMOSFETsusedandtheLTC3831-
1’s operating frequency, but is generally less than 50mA.
VOUT V – VOUT
IN
DC(Q2) = 1–
=
V
V
IN
IN
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
LTC3831-1 applications that use 5V or lower VIN voltage
and tripling charge pumps to generate PVCC1 and PVCC2
,
do not provide enough gate drive voltage to fully enhance
standardpowerMOSFETs.Underthiscondition,theeffec-
tive MOSFET RDS(ON) may be quite high, raising the
dissipation in the FETs and reducing efficiency. Logic-
level or sub-logic level FETs are the recommended choice
for 5V or lower voltage systems. Logic-level FETs can be
fully enhanced with a tripling charge pump and will oper-
ate at maximum efficiency.
PMAX(Q1)
DC(Q1)•(ILOAD
PMAX(Q2)
V •PMAX(Q1)
IN
RDS(ON)Q1
RDS(ON)Q2
=
=
=
2
2
)
VOUT •(ILOAD
)
V •PMAX(Q2)
IN
=
2
2
DC(Q2)•(ILOAD
)
(V – VOUT)•(ILOAD)
IN
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
38311f
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efficiency circuit designed for 1.5V input and 0.75V at 5A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a PMAX value of:
decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.
Table 1 highlights a variety of power MOSFETs that are for
use in LTC3831-1 applications.
(0.75V)(5A/0.9)(0.03) = 0.125W per FET
and a required RDS(ON) of:
Inductor Selection
The inductor is often the largest component in an
LTC3831-1 design and must be chosen carefully. Choose
the inductor value and type based on output slew rate re-
quirements. The maximum rate of rise of inductor current
is set by the inductor’s value, the input-to-output voltage
differential and the LTC3831-1’s maximum duty cycle. In
atypical1.5Vinput0.75Voutputapplication,themaximum
rise time will be:
(1.5V)•(0.125W)
RDS(ON)Q1
RDS(ON)Q2
=
=
= 0.01Ω
(0.75V)(5A)2
(1.5V)•(0.125W)
(1.5V – 0.75V)(5A)2
= 0.01Ω
Note that while the required RDS(ON) values suggest large
MOSFETs,thepowerdissipationnumbersareonly0.125W
per device or less; large TO-220 packages and heat sinks
arenotnecessarilyrequiredinhighefficiencyapplications.
SiliconixSi4410DYorInternationalRectifierIRF7413(both
in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semi-
conductor MTD20N03HDL (DPAK) are small footprint
surfacemountdeviceswithRDS(ON) valuesbelow0.03Ωat
5V of VGS that work well in LTC3831-1 circuits. Using a
higher PMAX value in the RDS(ON) calculations generally
DCMAX •(V – VOUT
)
0.713 A
LO µs
IN
=
LO
where LO is the inductor value in µH. With proper fre-
quency compensation, the combination of the inductor
andoutputcapacitorvaluesdeterminethetransientrecov-
ery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
coresaturationrating.A1µHinductorhasa0.713A/µsrise
Table 1. Recommended MOSFETs for LTC3831-1 Applications
TYPICAL INPUT
CAPACITANCE
R
DS(ON)
PARTS
AT 25°C (mΩ)
RATED CURRENT (A)
C
(pF)
θ
(°C/W)
T
(°C)
JMAX
ISS
JC
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
3200
2700
880
1.8
175
10 at 100°C
Siliconix Si4410DY
SO-8
20
35
8
10 at 25°C
8 at 70°C
150
150
150
150
150
175
175
150
ON Semiconductor MTD20N03HDL
D PAK
20 at 25°C
16 at 100°C
1.67
25
Fairchild FDS6670A
S0-8
13 at 25°C
3200
2070
4025
1600
3300
1750
Fairchild FDS6680
SO-8
10
9
11.5 at 25°C
25
ON Semiconductor MTB75N03HDL
DD PAK
75 at 25°C
59 at 100°C
1
IR IRL3103S
DD PAK
19
28
37
64 at 25°C
45 at 100°C
1.4
1
IR IRLZ44
TO-220
50 at 25°C
36 at 100°C
Fuji 2SK1388
TO-220
35 at 25°C
2.08
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
38311f
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timeinthisapplication,resultingina7µsdelayinrespond-
ing to a 5A load current step. During this 7µs, the differ-
ence between the inductor current and the output current
is made up by the output capacitor. This action causes a
temporary voltage droop at the output. To minimize this
effect, the inductor value should usually be in the 1µH to
5µH range for most LTC3831-1 circuits. To optimize
performance, different combinations of input and output
voltages and expected loads may require different induc-
tor values.
Input and Output Capacitors
A typical LTC3831-1 design places significant demands
onboththeinputandtheoutputcapacitors.Duringnormal
steadyloadoperation,abuckconverterliketheLTC3831-1
drawssquarewavesofcurrentfromtheinputsupplyatthe
switchingfrequency. Thepeakcurrentvalueisequaltothe
output load current plus 1/2 the peak-to-peak ripple cur-
rent. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple cur-
rentratingsareoftenbasedononly2000hours(3months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s speci-
fication is recommended to extend the useful life of the
circuit. Loweroperatingtemperaturehasthelargesteffect
on capacitor longevity.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-to-
peak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
(V − VOUT)•(VOUT
)
IN
IRIPPLE
=
fOSC •LO • V
IN
fOSC = LTC3831-1 oscillator frequency = 300kHz
LO = Inductor value
The output capacitor in a buck converter under steady-
state conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3831-1 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. A 5A load step with a 0.05Ω ESR output
capacitor results in a 250mV output voltage shift; this is
20% of the output voltage for a 1.25V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capaci-
tor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
Solving this equation with our typical 1.5V to 0.75V
application with 1µH inductor, we get:
(1.5V – 0.75V)• 0.75V
= 1.25AP-P
300kHz •1µH •1.5V
Peak inductor current at 5A load:
5A + (1.25A/2) = 5.625A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductorswithgradualsaturationcharacteristicsareoften
the best choice.
Electrolytic capacitors, such as the Sanyo MV-WX series,
rated for use in switching power supplies with specified
ripple current ratings and ESR, can be used effectively in
38311f
15
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LTC3831-1 applications. OS-CON electrolytic capacitors
from Sanyo and other manufacturers give excellent per-
formance and have a very high performance/size ratio for
electrolytic capacitors. Surface mount applications can
use either electrolytic or dry tantalum capacitors. Tanta-
lum capacitors must be surge tested and specified for use
in switching power supplies. Low cost, generic tantalums
are known to have very short lives followed by explosive
deaths in switching power supply applications. Other
capacitor series that can be used include Sanyo POSCAPs
and the Panasonic SP line.
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
fZ = 1/[2π(RC)(CC)] and
fP = 1/[2π(RC)(C1)] respectively.
Figure 7b shows the Bode plot of the overall transfer
function.
Although a mathematical approach to frequency compen-
sationcanbeused, theaddedcomplicationofinputand/or
output filters, unknown capacitor ESR, and gross operat-
ing point changes with input voltage, load current varia-
tions, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical
LTC3831-1 application might exhibit 5A input ripple cur-
rent. Sanyo OS-CON capacitors, part number 10SA220M
(220µF/10V), feature 2.3A allowable ripple current at
85°C; three in parallel at the input (to withstand the input
ripple current) meet the above requirements. Similarly,
Sanyo POSCAP 4TPB470M (470µF/4V) capacitors have a
maximum rated ESR of 0.04Ω, three in parallel lower the
net output capacitor ESR to 0.013Ω.
LTC3831-1
V
FB
–
+
V
6
TT
OUT
COMP
10
(V
)
ERR
R
C
Feedback Loop Compensation
V
C1
REF
C
C
The LTC3831-1 voltage feedback loop is compensated at
the COMP pin, which is the output node of the error
amplifier. The feedback loop is generally compensated
with an RC + C network from COMP to GND as shown in
Figure 7a.
38311 F07a
Figure 7a. Compensation Pin Connections
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier com-
pensation network. The inductor and the output capacitor
create a double pole at the frequency:
f
f
= LTC3831 SWITCHING
FREQUENCY
= CLOSED-LOOP CROSSOVER
FREQUENCY
SW
f
Z
CO
20dB/DECADE
fLC = 1/ 2π (LO)(COUT
)
[
]
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
f
P
FREQUENCY
f
LC
f
ESR
f
CO
fESR = 1/ 2π(ESR)(C
)
]
[
OUT
38311 F07b
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
Figure 7b. Bode Plot of the LTC3831-1 Overall Transfer Function
38311f
16
LTC3831-1
W U U
APPLICATIO S I FOR ATIO
U
Table 2 shows the suggested compensation component
value for 1.5V to 0.75V applications based on the 470µF
Sanyo POSCAP 4TPB470M output capacitors.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3831-1. These items are also illustrated graphically in
the layout diagram of Figure 8. The thicker lines show the
high current paths. Note that at 5A current levels or above,
current density in the PC board itself is a serious concern.
Table 3 shows the suggested compensation component
values for 1.5V to 0.75V applications based on 1500µF
Sanyo MV-WX output capacitors.
Table 2. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 470µF Sanyo
POSCAP 4TPB470M Output Capacitors
Table 3. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 1500µF Sanyo
MV-WX Output Capacitors
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
68
L1 (µH)
1.2
C
(µF)
R (kΩ)
C (nF)
C1 (pF)
120
82
OUT
C
C
OUT
C
C
1410
5.6
12
20
12
27
43
24
51
93
3.3
3.3
2.2
3.3
1.5
1.0
1.5
1.0
3.3
4500
15
18
30
30
39
62
62
82
130
2.2
2.2
1
1.2
2820
4700
1410
2820
4700
1410
2820
4700
33
1.2
6000
9000
4500
6000
9000
4500
6000
9000
1.2
22
1.2
56
2.4
33
2.4
1
56
2.4
15
2.4
1
33
2.4
10
2.4
1
27
4.7
15
4.7
1
27
4.7
10
4.7
1
22
4.7
10
4.7
1
10
PV
V
V
V /V
IN DDQ
CC
CC
4.7µF 10k
0.1µF
+
PV
CC
CC2
2.2µF
C
IN
PV
PGND
CC1
OPTIONAL
Q1
Q2
TG
LTC3831-1
I
MBRS340T3
MBRS340T3
MAX
L
O
1k
FREQSET
SHDN
COMP
SS
I
V
OUT
NC
FB
+
R
BG
FB
C1
+
–
C
R
OUT
R
C
GND
PGND
PGND
C
C
SS
C
38311 F08
GND
Figure 8. Typical Schematic Showing Layout Considerations
38311f
17
LTC3831-1
W U U
U
APPLICATIO S I FOR ATIO
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 5A.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
1. In general, layout should begin with the location of the
powerdevices.Besuretoorientthepowercircuitrysothat
a clean power flow path is achieved. Conductor widths
shouldbemaximizedandlengthsminimized.Afteryouare
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
4.TheVCC,PVCC1 andPVCC2 decouplingcapacitorsshould
be as close to the LTC3831-1 as possible. The 4.7µF and
2.2µF bypass capacitors shown at VCC, PVCC1 and PVCC2
will help provide optimum regulation performance.
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An addi-
tional1µFceramiccapacitorbetweenVINandpowerground
is recommended.
2. The GND and PGND pins should be shorted directly at
theLTC3831-1.Thishelpstominimizeinternalgrounddis-
turbances in the LTC3831-1 and prevents differences in
groundpotentialfromdisruptinginternalcircuitoperation.
This connection should then tie into the ground plane at
a single point, preferably at a fairly quiet point in the circuit
such as close to the output capacitors. This is not always
practical, however, due to physical constraints. Another
reasonably good point to make this connection is between
the output capacitors and the source connection of the
bottom MOSFET Q2. Do not tie this single point ground in
the trace run between the Q2 source and the input capaci-
tor ground, as this area of the ground plane will be very
noisy.
6. The VFB pin is very sensitive to pickup from the switch-
ingnode.CareshouldbetakentoisolateVFB frompossible
capacitive coupling to the inductor switching signal.
7. In a typical SSTL application, if the R+ pin is to be con-
nected to VDDQ, which is also the main supply voltage for
the switching regulator, do not connect R+ along the high
current flow path; it should be connected to the SSTL in-
terfacesupplyoutput. R– shouldbeconnectedtotheinter-
face supply GND.
8. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
3.3V
V
DDQ
1.5V
D1
D2
D3
Efficiency vs Load Current
0.1µF
0.1µF
100
+
C
IN
90
80
70
60
50
40
30
20
10
0
220µF
V
= 1.8V
DDQ
0.1µF
4.7µF
2.2µF
PV
CC2
PV
Q1
10k
CC1
TG
B320A
V
= 1.5V
DDQ
V
CC
L
O
1.3µH
SS
I
MAX
V
(V
0.75V
±10A
1k
TT
0.01µF
)
I
FB
LTC3831-1
OUT
Q2
FREQSET
SHDN
BG
PGND
GND
B320A
+
SHDN
C
OUT
180µF
COMP
C1
68pF
R
+
C
T
A
= 25°C
R
1k
38311 F09
FB
4
0
1
2
3
5
6
7
8
9
10
C
C
–
R
C
C
: SANYO POSCAP 4TPB220M
IN
22nF
LOAD CURRENT (A)
: PANASONIC EEFUE0G181R
OUT
38311 F10
D1, D2, D3: MBR0520LT1
Q1, Q2: SILICONIX Si9426DY
Figure 9. DDR Memory Termination with Triple Charge Pump
38311f
18
LTC3831-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
38311f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
19
LTC3831-1
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Minimum V : 1.5V, Uses Standard Logic-Level N-Channel
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Wide V Step-Down Controller for DDR Memory Termination
Current Mode Operation, V
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(V )
IN
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LTC3718
LTC3831
LTC3832
Bus termination Supply for Low Votlage V
1.5V ≤ V , Generates 5V Gate Drive for Standard N-Ch MOSFETs,
IN
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2A ≤ I
≤ 25A
OUT
High Power Synchronous Switching Regulator Controller
for DDR Memory Termination
V
Tracks 1/2 of V or External Reference
OUT
OUT
IN
High Power Synchronous Switching Regulator Controller
is a trademark of Linear Technology Corporation.
V
as low as 0.6V
No R
SENSE
38311f
LT/TP 0304 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2004
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