LTC3835IFE#PBF_技术文档

LTC3863

60V Low I Inverting

Q

DC/DC Controller

DESCRIPTION

FEATURES

The LTC^®3863 is a robust, inverting DC/DC PMOS control-

ler optimized for automotive and industrial applications. It

drives a P-channel power MOSFET to generate a negative

output and requires just a single inductor to complete the

circuit. Output voltages from –0.4V to –150V are typically

achievable with higher voltages possible, only limited by

external components.

n

Wide Operating V Range: 3.5V to 60V

IN

OUT

n

Wide Negative V

Range: –0.4V to Beyond –150V

n

Low Operating I = 70µA

Q

Strong High Voltage MOSFET Gate Driver

Constant Frequency Current Mode Architecture

Verified FMEA for Adjacent Pin Open/Short

Selectable High Efficiency Burst Mode^®Operation or

Pulse-Skipping Mode at Light Loads

The LTC3863 offers excellent light load efficiency, draw-

ing only 70μA quiescent current in a user programmable

Burst Mode operation. Its peak current mode, constant

frequency PWM architecture provides for good control of

switching frequency and output current limit. The switch-

ing frequency can be programmed from 50kHz to 850kHz

with an external resistor and can be synchronized to an

external clock from 75kHz to 750kHz.

n

Programmable Fixed Frequency: 50kHz to 850kHz

Phase-Lockable Frequency: 75kHz to 750kHz

Accurate Current Limit

Programmable Soft-Start or Voltage Tracking

Internal Soft-Start Guarantees Smooth Start-Up

Low Shutdown I = 7µA

Q

Available in Small 12-Lead Thermally Enhanced

MSOP and DFN Packages

The LTC3863 offers programmable soft-start or output

tracking. Safety features include overvoltage, overcurrent

and short-circuit protection including frequency foldback.

APPLICATIONS

n

Industrial and Automotive Power Supplies

Telecom Power Supplies

The LTC3863 is available in thermally enhanced 12-lead

MSOP and 3mm × 4mm DFN packages.

L, LT, LTC, LTM, OPTI-LOOP, Linear Technology, Burst Mode and the Linear logo are registered

trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents including 5731694.

n

Distributed Power Systems

TYPICAL APPLICATION

4.5V to 16V Input, –5V/1.7A Output, 350kHz Inverting Converter

Efficiency

V

IN

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

0

4.5V TO 16V

+

10µF

25V

×2

V

= 12V

IN

OUT

0.47µF

100µF

20V

= –5V

CAP

RUN

V

IN

350kHz

27nF

16mΩ

Si7129

PLLIN/MODE

SS

EFFICIENCY

SENSE

GATE

14.7k

V

OUT

PULSE-SKIPPING MODE

Burst Mode OPERATION

ITH

–5V

LTC3863

150µF

33µF

×2

1.7A

61.9k

B540C

16V

+

FREQ

10µH

×2

511k

SGND

POWER LOSS

0.2

V

FBN

80.6k

3863 TA01a

68pF

V

0.002

0.02

2

FB

PGND

LOAD CURRENT (A)

3863 TA01b

3863f

1

For more information www.linear.com/3863

LTC3863

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Operating Junction Temperature Range (Notes 2, 3, 4)

LTC3863E,I ....................................... –40°C to 125°C

LTC3863H.......................................... –40°C to 150°C

LTC3863MP....................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

Input Supply Voltage (V )......................... –0.3V to 65V

IN

V -V

Voltage ...................................... –0.3V to 6V

Voltage........................................ –0.3V to 10V

IN SENSE

V -V

IN CAP

RUN Voltage............................................... –0.3V to 65V

V

, PLLIN/MODE Voltages ....................... –0.3V to 6V

SS, ITH, FREQ, V Voltages........................ –0.3V to 5V

FBN

FB

MSOP Package .................................................300°C

PIN CONFIGURATION

TOP VIEW

PLLIN/MODE

FREQ

1

2

3

4

5

6

12 GATE

11

10 SENSE

1

2

3

4

5

6

PLLIN/MODE

FREQ

12 GATE

11

10 SENSE

V

IN

V

IN

SGND

13

SGND

SS

13

PGND

9

8

7

CAP

RUN

SS

9

8

7

CAP

RUN

V

FB

V

FB

ITH

V

FBN

ITH

V

FBN

MSE PACKAGE

12-LEAD PLASTIC MSOP

DE PACKAGE

T

= 150°C, θ = 40°C/W, θ = 10°C/W

JA JC

EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB

JMAX

12-LEAD (4mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 43°C/W, θ = 5.5°C/W

JA JC

JMAX

EXPOSED PAD (PIN 13) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3863EMSE#PBF

LTC3863IMSE#PBF

LTC3863HMSE#PBF

LTC3863MPMSE#PBF

LTC3863EDE#PBF

LTC3863IDE#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3863EMSE#TRPBF

LTC3863IMSE#TRPBF

LTC3863HMSE#TRPBF

3863

12-Lead Plastic MSOP

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

12-Lead Plastic MSOP

LTC3863MPMSE#TRPBF 3863

12-Lead Plastic MSOP

LTC3863EDE#TRPBF

LTC3863IDE#TRPBF

LTC3863HDE#TRPBF

LTC3863MPDE#TRPBF

3863

12-Lead (4mm × 3mm) Plastic DFN

LTC3863HDE#PBF

LTC3863MPDE#PBF

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3863f

2

For more information www.linear.com/3863

LTC3863

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply

V

Input Voltage Operating Range

Undervoltage Lockout

3.5

60

V

IN

l

V

UVLO

(V -V ) Ramping Up Threshold

IN CAP

Hysteresis

3.25

3.00

3.50

3.25

0.25

3.8

3.50

V

IN CAP

(V -V ) Ramping Down Threshold

I

Input DC Supply Current

Pulse-Skipping Mode

Q

PLLIN/MODE = 0V, FREQ = 0V,

FB

0.77

50

7

1.2

70

12

mA

µA

V

= 0.83V (No Load)

Burst Mode Operation

PLLIN/MODE = Open, FREQ = 0V,

= 0.83V (No Load)

V

FB

Shutdown Supply Current

RUN = 0V

Output Sensing

Regulated Feedback Voltage V

l

V

REG

= (V – V

)

FBN

V

= 1.2V (Note 5)

ITH

0.791

0.800

0.809

0.005

V

REG

FB

∆V

Feedback Voltage Line Regulation

Feedback Voltage Load Regulation

Error Amplifier Transconductance

V

IN

= 3.8V to 60V (Note 5)

–0.005

%/V

REG

IN

∆V

REG

∆V

ITH

V

ITH

V

ITH

= 0.6V to 1.8V (Note 5)

–0.1

–0.015

0.1

%

g

= 1.2V, ∆I

=

5µA (Note 5)

1.8

mS

nA

m(EA)

FBN

ITH

I

Feedback Negative Input Bias Current

–50

85

–10

50

Current Sensing

l

V

ILIM

Current Limit Threshold (V -V

)

V

= 0.77V

95

103

2

mV

µA

IN SENSE

FB

I

SENSE Pin Input Current

= V

IN

0.1

SENSE

Start-Up and Shutdown

V

RUN Pin Enable Threshold

RUN Pin Hysteresis

V Rising

RUN

1.22

375

1.26

150

10

1.32

V

mV

µA

RUN

RUNHYS

I

Soft-Start Pin Charging Current

V = 0V

SS

Switching Frequency and Clock Synchronization

f

Programmable Switching Frequency

R

= 24.9kΩ

= 64.9kΩ

= 105kΩ

105

440

810

kHz

FREQ

505

f

Low Switching Frequency

High Switching Frequency

Synchronization Frequency

FREQ = 0V

320

485

75

350

535

380

585

750

kHz

V

LO

FREQ = Open

HI

l

SYNC

V

Clock Input High Level into PLLIN/MODE

Clock Input Low Level into PLLIN/MODE

2

CLK(IH)

CLK(LO)

FOLD

V

0.5

V

f

t

Foldback Frequency as Percentage of

Programmable Frequency

V

FB

= 0V, V

= 0V

18

%

FREQ

Minimum On-Time

220

ns

ON(MIN)

3863f

3

For more information www.linear.com/3863

LTC3863

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Gate Driver

l

V

Gate Bias LDO Output Voltage (V -V

)

I = 0mA

GATE

7.6

8.0

0.2

8.5

0.5

V

CAP

IN CAP

Gate Bias LDO Dropout Voltage

Gate Bias LDO Line Regulation

Gate Bias LDO Load Regulation

Gate Pull-Up Resistance

V

IN

= 5V, I

= 15mA

GATE

CAPDROP

∆V

9V ≤ V ≤ 60V, I = 0mA

GATE

0.002

0.03

%/V

%

CAP(LINE)

IN

Load = 0mA to 20mA

Gate High

–3.5

CAP(LOAD)

R

2

Ω

UP

DN

Gate Pull-Down Resistance

Gate Low

0.9

Ω

Overvoltage

V

Overvoltage Lockout Threshold

FB

GATE Going High without Delay,

-V in Percent

10

%

FBOV

V

FB(OV) FB(NOM)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Continuous operation above the specified maximum operating

junction temperature may impair device reliability or permanently damage

the device.

specifications over the –40°C to 125°C operating junction temperature

range are assured by design, characterization and correlation with

statistical process controls. The LTC3863I is guaranteed to meet

performance specifications over the –40°C to 125°C operating junction

temperature range, the LTC3863H is guaranteed over the –40°C to 150°C

operating junction temperature range, and the LTC3863MP is guaranteed

and tested over the full –55°C to 150°C operating junction temperature

range. High junction temperatures degrade operating lifetimes; operating

lifetime is derated for junction temperatures greater than 125°C. The

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors.

Note 3: The junction temperature (T in °C) is calculated from the ambient

J

temperature (T in °C) and power dissipation (P in Watts) as follows:

A

D

T = T + (P • θ )

JA

J

A

D

where θ (in °C/W) is the package thermal impedance provided in the Pin

JA

Configuration section for the corresponding package.

Note 4: The LTC3863 is tested under pulsed load conditions such that T

J

Note 5: The LTC3863 is tested in a feedback loop that adjust V

REG

≈ T . The LTC3863E is guaranteed to meet performance specifications

A

or (V – V ) to achieve a specified error amplifier output voltage

FB

FBN

from 0°C to 85°C operating junction temperature range. The LTC3863E

(on ITH pin).

3863f

4

For more information www.linear.com/3863

LTC3863

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Pulse-Skipping Mode Operation

Waveforms

Burst Mode Operation

Waveforms

Transient Response:

Burst Mode Operation

I

V

LOAD

OUT

1A/DIV

50mV/DIV

V

SW

OUT

V

SW

10V/DIV

200mV/DIV

10V/DIV

I

L

I

L

1A/DIV

500mA/DIV

3863 G03

3863 G02

3863 G01

20µs/DIV

V

= 12V

100µs/DIV

V

I

= 12V

2µs/DIV

V

I

= 12V

IN

OUT

IN

OUT

IN

OUT

= –5V

TRANSIENT = 100mA TO 1.6A

FIGURE 7 CIRCUIT

= 100mA

LOAD

FIGURE 7 CIRCUIT

Transient Response:

Pulse-Skipping Mode Operation

Transient Response: Rising Edge

Pulse-Skipping Mode Operation

Transient Response: Falling Edge

Pulse-Skipping Mode Operation

I

LOAD

1A/DIV

LOAD

1A/DIV

V

OUT

200mV/DIV

OUT

V

OUT

200mV/DIV

I

L

1A/DIV

3863 G04

3863 G05

3863 G06

V

= 12V

100µs/DIV

V

= 12V

10µs/DIV

V

= 12V

10µs/DIV

IN

OUT

IN

OUT

IN

OUT

= –5V

TRANSIENT = 100mA TO 1.6A

FIGURE 7 CIRCUIT

TRANSIENT = 100mA TO 1.6A

FIGURE 7 CIRCUIT

TRANSIENT = 1.6A TO 100mA

FIGURE 7 CIRCUIT

Soft-Start into a Prebiased

Output

Normal Soft-Start

Output Tracking

V

OUT2

RUN

5V/DIV

2V/DIV

V

IN

5V/DIV

V

OUT1

V

2V/DIV

OUT1

2V/DIV

V

OUT2

V

TRACK/SS

200mV/DIV

OUT2

2V/DIV

TRACK/SS

200mV/DIV

TRACK/SS

200mV/DIV

V

OUT1

2V/DIV

3863 G08

3863 G07

3863 G09

1ms/DIV

= –5V

V

I

= 12V

1ms/DIV

V

= 12V

V

I

= 12V

20ms/DIV

IN

OUT1

IN

= 5V, V

= 5V

= –5V

= I

= 5V

= –5V

= I

OUT2

OUT1

OUT2

LOAD1 LOAD2

OUT1

OUT2

LOAD1 LOAD2

PRE-BIAS1 = 2V, PRE-BIAS2 = –2V

= 50mA

I

= 100mA

LOAD

FIGURE 11 CIRCUIT

3863f

5

For more information www.linear.com/3863

LTC3863

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Overcurrent Protection

Short-Circuit Protection

V_INLine Transient Behavior

48V

12V

SHORT-

CIRCUIT

TRIGGER

I

V

LOAD

IN

1A/DIV

20V/DIV

V

OUT

GATE

I

L

5V/DIV

20V/DIV

1A/DIV

SOFT-START

I

L

FOLDBACK

1A/DIV

V

OUT

500mV/DIV

V

OUT

C

DISCHARGE

OUT

RECOVERY

50mV/DIV

3863 G10

3863 G11

3863 G12

V

I

= 12V

20ms/DIV

V

I

= 12V

500µs/DIV

10ms/DIV

= 12V, SURGE TO 48V

IN

OUT

IN

OUT

= –5V

= 1A TO 3.2A

= –5V

= 1A TO SHORT-CIRCUIT

V

LOAD

IN

OUT

= –5V

LOAD2

FIGURE 7 CIRCUIT

I

= 500mA

FIGURE 7 CIRCUIT

Pulse-Skipping Mode Input

Current Over Input Voltage

(No Load)

Burst Mode Input Current Over

Input Voltage (No Load)

Shutdown Current Over Input

Voltage

140

135

130

125

120

115

110

30

25

20

15

10

5

1100

1050

1000

950

V

I

= 12V

V

I

= 12V

V

= 12V

IN

OUT

IN

OUT

= –5V

= 0A

= –5V

= 0A

FIGURE 7 CIRCUIT

LOAD

FIGURE 7 CIRCUIT

900

850

800

750

0

700

0

20

30

(V)

40

50

60

20

30

(V)

40

50

0

20

30

(V)

40

50

60

10

0

10

60

10

V

IN

3863 G13

3863 G15

3863 G14

Output Regulation Over Input

Voltage

Output Regulation Over Load

Current

Output Regulation Over

Temperature

1.0

0.8

1.0

0.5

0

1.0

0.5

0

V

I

= 12V, V

= –5V

V

I

= –5V

V

I

= 12V, V

= –5V

IN

OUT

LOAD

IN

OUT

= 200mA

= 100mA

NORMALIZED AT I

= 1A

LOAD

V

NOMALIZED TO T = 25°C

NOMALIZED AT V = 12V

IN

FIGURE 7 CIRCUIT

OUT

A

0.6

FIGURE 7 CIRCUIT

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

PULSE-SKIPPING MODE

Burst Mode OPERATION

PULSE-SKIPPING MODE

Burst Mode OPERATION

PULSE-SKIPPING MODE

Burst Mode OPERATION

–1.0

–75

–25

25

75

125

175

0

10

20

30

(V)

40

50

60

–0.5

0

0.5

1.0

(A)

1.5

2.0

2.5

V

I

TEMPERATURE (°C)

IN

LOAD

3963 G18

3863 G16

3863 G17

3863f

6

For more information www.linear.com/3863

LTC3863

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Free Running Frequency Over

Input Voltage

Free Running Frequency Over

Temperature

Frequency Foldback % Over

Feedback Voltage

600

550

500

450

400

350

300

120

100

80

60

40

20

0

600

550

500

450

400

350

300

FREQ = OPEN

FREQ = 0V

–75

25

75

125

175

0

400

(mV)

600

800

0

20

30

(V)

40

50

60

–25

200

10

TEMPERATURE (°C)

V

FB

IN

3864 G20

3863 G21

3863 G19

GATE Bias LDO (V_IN- V_CAP) Load

Regulation

GATE Bias LDO (V_IN- V_CAP

Dropout Behavior

)

Current Sense Voltage Over ITH

Voltage

100

90

80

70

60

50

40

30

20

10

0

0.5

0.0

0.1

0.0

V

= 5V

Burst Mode OPERATION

PULSE-SKIPPING

IN

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–0.1

–0.2

–0.3

–0.4

–0.5

–10

0

0.8

1.2

1.6

2

0.4

0

10

(mA)

15

20

5

0

10

(mA)

15

20

5

ITH VOLTAGE (V)

I

GATE

3863 G24

3863 G22

3863 G23

Current Sense Voltage Over

Temperature

SS Pin Pull-Up Current Over

Temperature

RUN Pin Pull-Up Current Over

Temperature

0.65

0.55

0.45

0.35

0.25

100

98

96

94

92

90

14

12

10

8

V

= 0V

V

= 0V

RUN

SS

6

–75

25

75

125

175

–25

–75

25

75

125

175

–75

25

75

125

175

–25

TEMPERATURE (°C)

3863 G27

3863 G25

3863 G26

3863f

7

For more information www.linear.com/3863

LTC3863

PIN FUNCTIONS

PLLIN/MODE (Pin 1): External Reference Clock Input

and Burst Mode Enable/Disable. When an external clock

is applied to this pin, the internal phase-locked loop will

synchronize the turn-on edge of the gate drive signal with

the rising edge of the external clock. When no external

clockisapplied,thisinputdeterminestheoperationduring

light loading. Floating this pin selects low I (40μA) Burst

Mode operation. Pulling to ground selects pulse-skipping

mode operation.

point. The voltage ranges from 0V to 2.9V, with 0.8V cor-

responding to zero sense voltage (zero current).

V

(Pin 7): Feedback Input for an Inverting PWM Con-

FBN

troller. Connect V

to the center of a resistor divider

FBN

between the output and V . The V

threshold is 0V. To

FB

FBN

defeat the inverting amplifier and use the LTC3863 as an

LTC3864 (noninverting buck), tie V > 2V.

Q

FBN

RUN (Pin 8): Digital Run Control Input. A RUN voltage

abovethe1.26Vthresholdenablesnormaloperation,while

a voltage below the threshold shuts down the controller.

An internal 0.4µA current source pulls the RUN pin up to

about 3.3V. The RUN pin can be connected to an external

power supply up to 60V.

FREQ (Pin 2): Switching Frequency Setpoint Input. The

switching frequency is programmed by an external set-

point resistor R

connected between the FREQ pin and

FREQ

signal ground. An internal 20µA current source creates

a voltage across the external setpoint resistor to set the

internal oscillator frequency. Alternatively, this pin can

be driven directly by a DC voltage to set the oscillator

frequency. Grounding selects a fixed operating frequency

of 350kHz. Floating selects a fixed operating frequency

of 535kHz.

CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic

bypass capacitor of at least 0.1µF or 10X the effective

C

of the P-channel power MOSFET, is required

MILLER

from V to this pin to serve as a bypass capacitor for the

IN

internalregulator.Toensurestablelownoiseoperation,the

bypass capacitor should be placed adjacent to the V and

IN

SGND (Pin 3): Ground Reference for Small-Signal Analog

Component (Signal Ground). Signal ground should be

used as the common ground for all small-signal analog

inputsandcompensationcomponents.Connectthesignal

ground to the power ground (ground reference for power

components) only at one point using a single PCB trace.

CAP pins and connected using the same PCB metal layer.

SENSE (Pin 10): Current Sense Input. A sense resistor,

R

, from the V pin to the SENSE pin sets the maxi-

SENSE

IN

mum current limit. The peak inductor current limit is equal

to 95mV/R . For accuracy, it is important that the V

SENSE

IN

pin and the SENSE pin route directly to the current sense

SS (Pin 4): Soft-Start and External Tracking Input. The

LTC3863 regulates the feedback voltage to the smaller of

0.8V or the voltage on the SS pin. An internal 10μA pull-up

current source is connected to this pin. A capacitor to

ground at this pin sets the ramp time to the final regulated

output voltage. Alternatively, another voltage supply con-

nected through a resistor divider to this pin allows the

output to track the other supply during start-up.

resistor and make a Kelvin (4-wire) connection.

V

(Pin 11): Chip Power Supply. A minimum bypass

IN

capacitor of 0.1µF is required from the V pin to power

IN

ground. For best performance use a low ESR ceramic

capacitor placed near the V pin.

IN

GATE (Pin 12): Gate Drive Output for External P-Channel

MOSFET. The gate driver bias supply voltage (V -V

)

IN CAP

V

(Pin 5): Output Feedback Sense. A resistor divider

is regulated to 8V when V is greater than 8V. The gate

FB

IN

from the regulated output point to this pin sets the output

driver is disabled when (V -V ) is less than 3.5V (typi-

IN CAP

voltage. The LTC3863 will nominally regulate V to the

internal reference value of 0.8V. If V is less than 0.4V, the

cal), 3.8V maximum in start-up and 3.25V (typical) 3.5V

FB

maximum in normal operation.

FB

switching frequency will linearly decrease and fold back

to about one-fifth of the internal oscillator frequency to

reduce the minimum duty cycle.

PGND(ExposedPadPin13):GroundReferenceforPower

Components(PowerGround).ThePGNDexposedpadmust

be soldered to the circuit board for electrical contact and

for rated thermal performance of the package. Connect

signal ground to power ground only at one point using a

ITH (Pin 6): Current Control Threshold and Controller

Compensation Point. This pin is the output of the error

amplifier and the switching regulator’s compensation

single PCB trace.

3863f

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For more information www.linear.com/3863

LTC3863

FUNCTIONAL DIAGRAM

V

IN

C

IN

UVLO

V

IN

+

–

3.25V

R

SENSE

GATE

0.4µA

RUN

+

–

LOGIC

CONTROL

1.26V

–

DRV

MP

D1

Q

V

OUT

S

R

C

CAP

IN

C

Burst Mode

OPERATION

OUT

L

LDO

CLOCK

PLLIN/MODE

OUT

V

O.425V

+

–

MODE/CLOCK

DETECT

CAP

– 8V

PLL

SYSTEM

IN

ICMP

20µA

–

+

VCO

FREQ

R

FREQ

+

10µA

EN

SS

SGND

+

–

0.8V

C

SLOPE

COMPENSATION

SS

0.5µA

R

FB1

EA

(G = 1.8mS)

0.88V

+

–

+

V

FBN

OV

m

FB2

C

FB2

V

FB

PGND

ITH

3863 FD

R

ITH

C

ITH1

3863f

9

For more information www.linear.com/3863

LTC3863

OPERATION

LTC3863 Main Control Loop

The resultant differential voltage from V to SENSE is

IN

proportional to the inductor current and is compared to

the peak inductor current setpoint. During normal opera-

tion the P-channel power MOSFET is turned on when the

clock leading edge sets the SR latch through the S input.

The P-channel MOSFET is turned off through the SR latch

The LTC3863 is a nonsynchronous inverting PMOS

controller, where an inverting amplifier is used to

sense the negative output voltage below ground. The

LTC3863 uses a peak current mode control architecture

to regulate the output. A feedback resistor, R , is

FB1

R input when the differential voltage from V to SENSE

IN

placed between V

FB2

and V

and a second resistor,

OUT

FBN

is greater than the peak inductor current setpoint and the

current comparator, ICMP, trips high.

R

, is placed between V and and V . The LTC3863

FBN FB

has a trimmed internal reference, V , that is equal to

REF

(V – V ). The output voltage is equal to –(R /R )

FB

FBN

FB1 FB2

Power CAP and V Undervoltage Lockout (UVLO)

IN

• V whereV isequalto800mVinnormalregulation.

REF

Power for the P-channel MOSFET gate driver is derived

from the CAP pin. The CAP pin is regulated to 8V below

The LTC3863 can also be configured as a noninverting

step-down buck regulator when the V node is pulled

FBN

V in order to provide efficient P-channel operation. The

IN

greater than 2V but held less than 5V, which disables the

power for the V

supply comes from an internal LDO,

IN

CAP

internal inverting amplifier. A feedback resistor, R , is

FB1

which regulates the V -CAP differential voltage. A mini-

placedbetweenV

andV andasecondresistor,R

,

OUT

FB

FB2

mum capacitance of 0.1µF (low ESR ceramic) is required

is placed between V and SGND. In the noninverting

FB

between V and CAP to assure stability.

IN

buck mode the V input is compared to the internal

FB

For V ≤ 8V, the LDO will be in dropout and the CAP volt-

reference, V , by a transconductance error amplifier

IN

REF

age will be at ground, i.e., the V -CAP differential voltage

(EA). The internal reference can be either a fixed 0.8V

IN

will equal V . If V -CAP is less than 3.25V (typical), the

reference, V , or the voltage input on the SS pin. In

IN

REF

LTC3863 enters aUVLOstate where the GATE is prevented

normal operation V regulates to the internal 0.8V refer-

FB

from switching and most internal circuitry is shut down.

ence voltage. The output voltage in normal regulation is

In order to exit UVLO, the V -CAP voltage would have to

equal to (R + R )/R • 800mV.

IN

FB1

FB2

exceed 3.5V (typical).

In soft-start or tracking mode when the SS pin voltage

is less than the internal 0.8V reference voltage, V will

FB

Shutdown and Soft-Start

regulate to the SS pin voltage. The error amplifier output

connects to the ITH (current [I] threshold [TH]) pin. The

voltage level on the ITH pin is then summed with a slope

compensation ramp to create the peak inductor current

set point.

When the RUN pin is below 0.7V, the controller and most

internalcircuitsaredisabled.Inthismicropowershutdown

state, the LTC3863 draws only 7µA. Releasing the RUN

pin allows a small internal pull-up current to pull the RUN

pin above 1.26V and enable the controller. The RUN pin

can be pulled up to an external supply of up to 60V or it

can be driven directly by logic levels.

The peak inductor current is measured through a sense

resistor, R

, placed across the V and SENSE pins.

SENSE

IN

3863f

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For more information www.linear.com/3863

LTC3863

OPERATION

The start-up of the output voltage V

the voltage on the SS pin. When the voltage on the SS

pin is less than the 0.8V internal reference, the V pin is

regulated to the voltage on the SS pin. This allows the SS

pin to be used to program a soft-start by connecting an

external capacitor from the SS pin to signal ground. An

internal10µApull-upcurrentchargesthiscapacitor,creat-

ing a voltage ramp on the SS pin. As the SS voltage rises

from 0V to 0.8V, the output voltage V

from zero to its final value.

is controlled by

In sleep mode, much of the internal circuitry is turned

off, reducing the quiescent current to 70µA while the

load current is supplied by the output capacitor. As the

output voltage and hence the feedback voltage decreases,

the error amplifier’s output will rise. When the output

voltage drops enough, the ITH pin is reconnected to the

output of the error amplifier, the sleep signal goes low,

and the controller resumes normal operation by turning

on the external P-channel MOSFET on the next cycle of

the internal oscillator. In Burst Mode operation, the peak

inductor current has to reach at least 25% of current

limit for the current comparator, ICMP, to trip and turn the

P-channel MOSFET back off, even though the ITH voltage

may indicate a lower current setpoint value.

OUT

FB

rises smoothly

OUT

Alternatively,theSSpincanbeusedtocausethestart-upof

totrackthatofanothersupply.Typically,thisrequires

V

OUT

connecting the SS pin to an external resistor divider from

theothersupplytoground(seeApplicationsInformation).

Under shutdown or UVLO, the SS pin is pulled to ground

and prevented from ramping up.

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3863 will skip pulses during light loads. In

thismode,ICMPmayremaintrippedforseveralcyclesand

force the external MOSFET to stay off, thereby skipping

pulses. This mode offers the benefits of smaller output

ripple, lower audible noise, and reduced RF interference,

attheexpenseoflowerefficiencywhencomparedtoBurst

Mode operation.

If the slew rate of the SS pin is greater than 1.2V/ms, the

output will track an internal soft-start ramp instead of the

SS pin. The internal soft-start will guarantee a smooth

start-up of the output under all conditions, including in the

case of a short-circuit recovery where the output voltage

will recover from near ground.

Frequency Selection and Clock Synchronization

Light Load Current Operation (Burst Mode Operation

or Pulse-Skipping Mode)

The switching frequency of the LTC3863 can be selected

using the FREQ pin. If the PLLIN/MODE pin is not being

driven by an external clock source, the FREQ pin can be

tied to signal ground, floated, or programmed through

an external resistor. Tying FREQ to signal ground selects

350kHz, while floating selects 535kHz. Placing a resistor

between FREQ and signal ground allows the frequency to

be programmed between 50kHz and 850kHz.

The LTC3863 can be enabled to enter high efficiency Burst

Mode operation or pulse-skipping mode at light loads. To

select pulse-skipping operation, tie the PLLIN/MODE pin

to signal ground. To select Burst Mode operation, float

the PLLIN/MODE pin.

In Burst Mode operation, if the V is higher than the refer-

FB

ence voltage, the error amplifier will decrease the voltage

on the ITH pin. When the ITH voltage drops below 0.425V,

the internal sleep signal goes high, enabling sleep mode.

The ITH pin is then disconnected from the output of the

error amplifier and held at 0.45V.

The phase-locked loop (PLL) on the LTC3863 will syn-

chronize the internal oscillator to an external clock source

when connected to the PLLIN/MODE pin. The PLL forces

the turn-on edge of the external P-channel MOSFET to be

aligned with the rising edge of the synchronizing signal.

3863f

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For more information www.linear.com/3863

LTC3863

OPERATION

Theoscillator’sdefaultfrequencyisbasedontheoperating

frequency set by the FREQ pin. If the oscillator’s default

frequency is near the external clock frequency, only slight

adjustments are needed for the PLL to synchronize the

external P-channel MOSFET’s turn-on edge to the rising

edge of the external clock. This allows the PLL to lock

rapidly without deviating far from the desired frequency.

In the event of an output short circuit or overcurrent con-

dition that causes the output voltage to drop significantly

while in current limit, the LTC3863 operating frequency

will fold back. Anytime the output feedback V voltage is

FB

less than 50% of the 0.8V internal reference (i.e., 0.4V),

frequency foldback is active. The frequency will continue

to drop as V drops until reaching a minimum foldback

FB

frequency of about 18% of the setpoint frequency. Fre-

quency foldback is designed, in combination with peak

current limit, to limit current in start-up and short-circuit

conditions.Settingthefoldbackfrequencyasapercentage

ofoperatingfrequencyassuresthatstart-upcharacteristics

scale appropriately with operating frequency.

The PLL is guaranteed from 75kHz to 750kHz. The clock

input levels should be greater than 2V for HI and less

than 0.5V for LO.

Fault Protection

When the V voltage is above +10% of the regulated

FB

voltage of 0.8V, this is considered as an overvoltage con-

dition and the external P-MOSFET is immediately turned

off and prevented from ever turning on until V returns

FB

below +7.5%.

3863f

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LTC3863

APPLICATIONS INFORMATION

TheLTC3863isanonsynchronousinverting,currentmode,

constant frequency PWM controller. It drives an external

P-channel power MOSFET which connects to a Schottky

power diode acting as the commutating catch diode. The

input range extends from 3.5V to 60V. The output range

has no theoretical minimum or maximum, but the duty

factor and external components practically limit the out-

put to one-tenth and ten times the input voltage. Higher

output ratios can be obtained with transformers and more

efficient external components.

LTC3863

V

FB

R

C

FB2

V

FBN

3863 F01

FB1

V

OUT

Figure 1. Setting the Output Voltage

Great care should be taken to route the V and V

FB

FBN

lines away from noise sources, such as the inductor or

SW node or the GATE signal that drives the external P-

channel MOSFET.

TheLTC3863offersahighlyefficientBurstModeoperation

with 70µA quiescent current, which delivers outstanding

efficiency in light load operation. The LTC3863 is a low

pin count, robust and easy-to-use inverting power supply

solution in applications which require high efficiency and

operate with widely varying input and output voltages.

The integrator capacitor, C , should be sized to ensure

FB2

the negative sense amplifier gain rolls off and limits high

frequency gain peaking in the DC/DC control loop. The

integrator capacitor pole can be safely set to be two times

theswitchingfrequencywithoutaffectingtheDC/DCphase

margin according to the following equation. It is highly

ThetypicalapplicationonthefrontpageisabasicLTC3863

application circuit. The LTC3863 can sense the inductor

current through a high side series sense resistor, R

,

SENSE

recommended that C be used in most applications.

FB2

placedbetweenV andthesourceoftheexternalP-channel

IN

1

MOSFET. Once the required output voltage and operating

frequency have been determined, external component

selection is driven by load requirements, and begins with

C_FB2

=

2•π •2•FREQ_SW

the selection of inductor and R

. Next, the power

SENSE

Switching Frequency and Clock Synchronization

MOSFET and catch diode are selected. Finally, input and

output capacitors are selected.

The choice of operating frequency is a trade-off between

efficiencyandcomponentsize.Loweringtheoperatingfre-

quencyimprovesefficiencybyreducingMOSFETswitching

losses but requires larger inductance and/or capacitance

to maintain low output ripple voltage. Conversely, raising

the operating frequency degrades efficiency but reduces

component size.

Output Voltage Programming

The output voltage is programmed by connecting a

feedback resistor divider from the output to the V pin

FB

as shown in Figure 1. The output voltage in steady-state

operation is set by the feedback resistors according to

the equation:

R_FB1

V_OUT= –0.8V •

R_FB2

3863f

13

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

The LTC3863 can free-run at a user programmed switch-

ing frequency, or it can synchronize with an external

clock to run at the clock frequency. When the LTC3863 is

synchronized, the GATE pin will synchronize in phase with

the rising edge of the applied clock in order to turn the

external P-channel MOSFET on. The switching frequency

of the LTC3863 is programmed with the FREQ pin, and the

external clock is applied at the PLLIN/MODE pin. Table 1

highlights the different states in which the FREQ pin can

be used in conjunction with the PLLIN/MODE pin.

Inductor Selection

Operatingfrequency,inductorselection,capacitorselection

and efficiency are interrelated. Higher operating frequen-

ciesallowtheuseofsmallerinductors,smallercapacitors,

but result in lower efficiency because of higher MOSFET

gate charge and transition losses. In addition to this basic

trade-off, the selection of inductor value is also influenced

by other factors.

Small inductor values result in large inductor ripple cur-

rents, large output voltage ripples and low efficiency due

to higher core and conduction loss. Large inductor ripple

currents result in high inductor peak currents, which re-

quire physically large inductors with large magnetic cross

sections and higher saturation current ratings.

Table 1

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

OV

Floating

DC Voltage

535kHz

Resistor to GND

Either of the Above

DC Voltage

50kHz to 850kHz

The value of the inductor can also impact the stability of

the feedback loop. In continuous mode, the buck-boost

converter transfer function has a right-half plane zero at

a frequency that is inversely proportional to the value of

the inductor. As a result, large inductor values can move

this zero to a frequency that is low enough to degrade the

phase margin of the feedback loop. Large inductor values

also tend to degrade stability due to low noise margin

caused from low ripple current. Additionally, large value

inductors can lead to slow transient response due to slow

inductor current ramping time.

External Clock

Phase Locked to

External Clock

Thefree-runningswitchingfrequencycanbeprogrammed

from50kHzto850kHzbyconnectingaresistorfromFREQ

to signal ground. The resulting switching frequency as a

functionofresistanceontheFREQpinisshowninFigure2.

Set the free-running frequency to the desired synchroni-

zation frequency using the FREQ pin so that the internal

oscillatorisprebiasedapproximatelytothesynchronization

frequency. While it is not required that the free-running

frequency be near the external clock frequency, doing so

will minimize synchronization time.

For an inverting buck-boost converter operating in con-

tinuous conduction mode (CCM), given the desired input,

outputvoltagesandswitchingfrequency,thepeak-to-peak

inductorripplecurrentisdeterminedbytheinductorvalue:

1000

900

800

700

600

500

400

300

200

100

V • |V |+V_D

V •D

(

)

IN

OUT

IN

∆I_L(CCM)

=

L•f L•f• V + |V |+V_D

(

)

IN

OUT

whereV isthediodeforwardconductionvoltage.Incases

D

where V

>> V , V can be ignored. D is the duty factor

OUT

D D

and is given as:

|V_OUT|+V_D

D=

0< D< 1

(

)

V + |V |+V_D

IN

OUT

0

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

3863 F02

Figure 2. Switching Frequency vs Resistor on FREQ

3863f

14

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

The duty factor increases with increasing V

and de-

Current Sensing and Current Limit Programming

The LTC3863 senses the inductor current through a cur-

rent sense resistor, R

, placed across the V and

OUT

creasing V . For a given V , the maximum duty factor

IN

OUT

occurs at minimum V .

IN

SENSE

IN

Atypicalstartingpointforselectinganinductoristochoose

the inductance such that the maximum peak-to-peak in-

SENSE pins. The voltage across the resistor, V

, is

SENSE

proportionaltoinductorcurrentandinnormaloperationis

ductor ripple current, ∆I

, is set to 40% ~ 50% of the

,atmaximumloadcurrent.

comparedtothepeakinductorcurrentsetpoint.Aninductor

L(MAX)

inductoraveragecurrent,I

current limit condition is detected when V

exceeds

L(AVG)

SENSE

Since∆I

occursatmaximumV incontinuousmode,

95mV. When the current limit threshold is exceeded, the

P-channel MOSFET is immediately turned off by pulling

L(MAX)

IN

the inductance is calculated at maximum V :

IN

the GATE voltage to V regardless of the controller input.

IN

2

V

• |V |+V_D

(

)

IN(MAX)

OUT

L =

The peak inductor current limit is equal to:

2

0.4•I_OUT(MAX)•f• V_IN(MAX)+ |V |+V_D

(

)

OUT







95mV

I_L(PEAK)

≅



The inductance can be further adjusted to achieve specific

designoptimizationofefficiency,outputripple,component

size and loop response.

R



_SENSE

This inductor current limit would translate to an output

current limit based on the inductor ripple and duty factor:

Once the inductance value has been determined, the type

of inductor must be selected. Core loss is independent of

core size for a given inductor value, but it is very depen-

dent on the inductance selected. As inductance increases,

corelossesdecrease.Unfortunately,increasedinductance

requires more turns of wire and therefore, copper losses

will increase.





95mV ∆I_L

I_OUT(LIMIT)

=

–

• 1–D

(

)





R

2





SENSE

The SENSE pin is a high impedance input with a maximum

leakage of 2µA. Since the LTC3863 is a peak current

mode controller, noise on the SENSE pin can create pulse

width jitter. Careful attention must be paid to the layout of

High efficiency converters generally cannot tolerate the

core loss of low cost powdered iron cores, forcing the use

of more expensive ferrite materials. Ferrite designs have

very low core loss and are preferred at high switching

frequencies, so design goals can concentrate on cop-

per loss and preventing saturation. Ferrite core material

saturates hard, which means that inductance collapses

abruptly when the peak design current is exceeded. This

will result in an abrupt increase in inductor ripple current

andoutputvoltageripple.Donotallowthecoretosaturate!

R

SENSE

. Toensuretheintegrityofthecurrentsensesignal,

SENSE

V

, the traces from V and SENSE pins should be

IN

short and run together as a differential pair and Kelvin

(4-wire) connected across R

(Figure 3).

SENSE

V

IN

V

IN

OPTIONAL

FILTERING

R

SENSE

LTC3863

C

F

R

F

A variety of inductors are available from manufacturers

such as Sumida, Panasonic, Coiltronics, Coilcraft, Toko,

Vishay, Pulse and Würth.

SENSE

MP

3863 F03

Figure 3. Inductor Current Sensing

3863f

15

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

The LTC3863 has internal filtering of the current sense

voltage which should be adequate in most applications.

However, adding a provision for an external filter offers

added flexibility and noise immunity, should it be neces-

sary.Thefiltercanbecreatedbyplacingaresistorfromthe

The power dissipated by the P-channel MOSFET when the

LTC3863 is in continuous conduction mode is given by:

I



 ²

OUT

P

≈ D•

•ρ_T•R_DS(ON)









PMOS

1–D

R

resistor to the SENSE pin and a capacitor across

2

SENSE

f•C_MILLER• V + |V |+V_D

(

)

I_OUT

1–D

IN

OUT

the V and SENSE pins.

IN

+

•

2

Power MOSFET Selection









R_DN

R_UP

•

+





The LTC3863 drives a P-channel power MOSFET that

serves as the main switch for the nonsynchronous

inverting converter. Important P-channel power MOSFET

parameters include drain-to-source breakdown voltage

V – V – V_MILLERV_MILLER

(

)

IN

CAP

where D is duty factor, R

is on-resistance of

DS(ON)

P-channel MOSFET, ρ is temperature coefficient of on-

T

BV , threshold voltage V

, on-resistance R

,

DSS

GS(TH)

DS(ON)

resistance,R isthepull-downdriverresistancespecified

DN

gate-to-drainreversetransfercapacitanceC ,maximum

RSS

at 0.9Ω typical and R is the pull-up driver resistance

UP

draincurrentI

,andtheMOSFET’sthermalresistance

D(MAX)

and θ

specified at 2Ω typical. V

is the Miller effective V

MILLER

GS

θ

.

JC(MOSFET)

JA(MOSFET)

voltage and is taken graphically from the power MOSFET

data sheet.

The drain-to-source breakdown voltage must meet the

following condition:

ThepowerMOSFETinputcapacitance,C

,isthemost

MILLER

important selection criteria for determining the transition

BV

> V + |V | + V

IN(MAX) OUT D

DSS

losstermintheP-channelMOSFETbutisnotdirectlyspeci-

The gate driver bias voltage V -V

is set by an internal

IN CAP

fied on MOSFET data sheets. C

is a combination of

MILLER

LDO regulator. In normal operation, the CAP pin will be

several components, but it can be derived from the typical

gatechargecurveincludedonmostdatasheets(Figure4).

The curve is generated by forcing a constant current out

of the gate of a common-source connected P-channel

MOSFET that is loaded with a resistor, and then plotting

the gate voltage versus time. The initial slope is the effect

of the gate-to-source and gate-to-drain capacitances. The

flat portion of the curve is the result of the Miller multipli-

cation effect of the drain-to-gate capacitance as the drain

regulated to 8V below V . A minimum 0.1µF capacitor

IN

is required across the V and CAP pins to ensure LDO

IN

stability. If required, additional capacitance can be added

to accommodate higher gate currents without voltage

droop. In shutdown and Burst Mode operation, the CAP

LDO is turned off. In the event of CAP leakage to ground,

the CAP voltage is limited to 9V by a weak internal clamp

from V to CAP. As a result, a minimum 10V V rated

IN

GS

MOSFET is required.

S

D

G

MILLER EFFECT

V

SG

+

–

V

SD(TEST)

a

b

I

R

LOAD

GATE

3863 F04

Q

IN

C

= (Q – Q )/V

MILLER

B

A

SD(TEST)

(4a)

(4b)

Figure 4. (4a) Typical P-Channel MOSFET Gate Charge

Characteristics and (4b) Test Set-Up to Generate Gate

Charge Curve

3863f

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LTC3863

APPLICATIONS INFORMATION

voltage rises across the resistor load. The Miller charge

Once the average forward diode current is calculated, the

powerdissipationcanbedetermined.RefertotheSchottky

(the increase in coulombs on the horizontal axis from a to

b while the curve is flat) is specified for a given V test

diode data sheet for the power dissipation, P

, as a

SD

DIODE

voltage, but can be adjusted for different V voltages by

function of average forward current, I

. P

can

SD

F(AVG) DIODE

multiplying by the ratio of the adjusted V to the curve

also be iteratively determined by the two equations below,

where V is a function of both I and junction

SD

specified V value. A way to estimate the C

term

,

J

SD

MILLER

F(IOUT TJ)

F(AVG)

is to take the change in gate charge from points a and b

temperatureT .Notethatthethermalresistance,θ

,

JA(DIODE)

(or the parameter Q on a manufacturer’s data sheet)

given in the data sheet is typical and can be highly layout

dependent. It is therefore important to make sure that the

Schottky diode has adequate heat sinking.

GD

and dividing it by the specified V test voltage, V

.

SD

SD(TEST)

Q_GD

V_SD(TEST)

C_MILLER

≅

T

J

≅ P

• θ

DIODE

JA(DIODE)

P

≅ I

• V

DIODE

F(AVG) D(IOUT,TJ)

The term with C

accounts for transition loss, which

MILLER

The Schottky diode forward voltage is a function of both

and T , so several iterations may be required to

is highest at high input voltages. For V < 20V, the high

IN

I

F(AVG)

J

currentefficiencygenerallyimproveswithlargerMOSFETs,

satisfy both equations. The Schottky forward voltage,

while for V > 20V, the transition losses rapidly increase

IN

V , should be taken from the Schottky diode data sheet

D

to the point that the use of a higher R

device with

DS(ON)

curveshowinginstantaneousforwardvoltage.Theforward

lower C

actually provides higher efficiency.

MILLER

voltage will change as a function of both T and I

.

J

F(AVG)

The nominal forward voltage will also tend to increase as

the reverse breakdown voltage increases. It is therefore

advantageoustoselectaSchottkydiodeappropriatetothe

input voltage requirements. The diode reverse breakdown

voltage must meet the following condition:

Schottky Diode Selection

When the P-channel MOSFET is turned off, a power

Schottky diode is required to function as a commutating

diode to carry the inductor current. The average forward

diode current is independent of duty factor and is de-

scribed as:

V > V

+ |V

|

OUT

R

IN(MAX)

I

= I

OUT

F(AVG)

C and C

IN

Selection

OUT

The worst-case condition for diode conduction is a short-

circuit condition where the Schottky must handle the

maximumcurrentasitsdutyfactorapproaches100%(and

the P-channel MOSFET’s duty factor approaches 0%). The

diode therefore must be chosen carefully to meet worst-

case voltage and current requirements. A good practice

is to choose a diode that has a forward current rating two

The input and output capacitance, C /C , are required

IN OUT

to filter the square wave current through the P-channel

MOSFET and diode respectively. Use a low ESR capacitor

sized to handle the maximum RMS current:

|V_OUT|+V_D

I_CIN(RMS)= I_COUT(RMS)= I_OUT

•

V

IN

times higher than I

.

OUT(MAX)

3863f

17

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

The formula shows that the RMS current is greater than

characteristics but can have a high voltage coefficient and

audible piezoelectric effects.

the maximum I

when V

is greater than V . Choose

OUT IN

OUT

capacitors with higher RMS rating with sufficient margin.

Note that ripple current ratings from capacitor manufac-

turers are often based on only 2000 hours of life, which

makes it advisable to derate the capacitor.

The high Q of ceramic capacitors with trace inductance

can also lead to significant ringing. When used as input

capacitors, care must be taken to ensure that ringing from

inrush currents and switching does not pose an overvolt-

age hazard to the power switch and controller. To dampen

inputvoltagetransients,addasmall5μFto40μFaluminum

electrolytic capacitor with an ESR in the range of 0.5Ω to

2Ω. High performance through-hole capacitors may also

be used, but an additional ceramic capacitor in parallel

is recommended to reduce the effect of lead inductance.

The selection of C

is primarily determined by the ESR

OUT

requiredtominimizevoltagerippleandloadsteptransients.

The ∆V

is approximately bounded by:

OUT

I_OUT•D

f•C_OUT

∆V_OUT≤ I_L(PEAK)•ESR+

whereI

isthepeakinductorcurrentandit’sgivenas:

L(PEAK)

Discontinuous and Continuous Operation

I_OUTV + |V |+V_D

(

)

IN

OUT

TheLTC3863operatesindiscontinuousconduction(DCM)

until the load current is high enough for the inductor

current to be positive at the end of the switching cycle.

The output load current at the continuous/discontinuous

I_L(PEAK)

=

V

IN

V • |V |+V_D

(

)

IN

OUT

+

2•L•f• V + |V |+V_D

(

)

IN

OUT

boundary, I

, is given by the following equation:

OUT(CDB)

V

²• |V |+V_D

Since I

and D reach their maximum values at mini-

(

)

IN(MAX)

L(PEAK)

OUT

I_OUT(CDB)

=

2

mum V , the output voltage ripple is highest at minimum

IN

2•L•f• V_IN(MAX)+ |V |+V_D

(

)

OUT

V and maximum I . Typically, once the ESR require-

IN

OUT

ment is satisfied, the capacitance is adequate for filtering

The continuous/discontinuous boundary is inversely

proportional to the inductor value. Therefore, if required,

and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, specialty polymer, aluminum electrolytic

and ceramic capacitors are all available in surface mount

packages. Specialty polymer capacitors offer very low

ESR but have lower specific capacitance than other types.

Tantalumcapacitorshavethehighestspecificcapacitance,

but it is important to only use types that have been surge

tested for use in switching power supplies. Aluminum

electrolytic capacitors have significantly higher ESR, but

can be used in cost-sensitive applications provided that

consideration is given to ripple current ratings and long-

termreliability.CeramiccapacitorshaveexcellentlowESR

I

can be reduced by increasing the inductor value.

OUT(CDB)

External Soft-Start and Output Tracking

Start-up characteristics are controlled by the voltage on

the SS pin. When the voltage on the SS pin is less than

the internal 0.8V reference, the LTC3863 regulates the V

FB

pin voltage to the voltage on the SS pin. When the SS pin

is greater than the internal 0.8V reference, the V pin

FB

voltage regulates to the 0.8V internal reference. The SS

pin can be used to program an external soft-start function

or to allow V

to track another supply during start-up.

OUT

3863f

18

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

Soft-start is enabled by connecting a capacitor from

the SS pin to ground. An internal 10µA current source

charges the capacitor, providing a linear ramping voltage

Short-Circuit Faults: Current Limit and Foldback

Theinductorcurrentlimitisinherentlysetinacurrentmode

controller by the maximum sense voltage and R

. In

SENSE

at the SS pin that causes V

to rise smoothly from 0V

OUT

the LTC3863, the maximum sense voltage is 95mV, mea-

to its final regulated value. The total soft-start time will

sured across the inductor sense resistor, R

, placed

SENSE

be approximately:

across the V and SENSE pins. The output current limit

IN

0.8V

10µA

is approximately:

t_SS= C_SS

•

V





95mV ∆I

IN(MIN)

L

I

=

–

•

LIMIT(MIN)





R

2





V

+ | V

|+ V

D

OUT

When the LTC3863 is configured to track another supply,

a voltage divider can be used from the tracking supply to

the SS pin to scale the ramp rate appropriately. Two com-

mon implementations of tracking as shown in Figure 5a

are coincident and ratiometric. For coincident tracking,

choose the divider ratio for the external supply as shown

in Figure 5b. Ratiometric tracking could be achieved by

using a different ratio than the feedback (Figure 5b).

SENSE

(

)

IN(MIN)

The current limit must be chosen to ensure that I

LIMIT(MIN)

> I

under all operating conditions. The inductor

OUT(MAX)

current limit should be greater than the inductor current

requiredtoproducemaximumoutputpoweratworst-case

efficiency. For the LTC3863, both minimum and maximum

V cases should be checked to determine the worst-case

IN

efficiency.

Notethatthesoft-startcapacitorchargingcurrentisalways

flowing, producing a small offset error. To minimize this

error,selectthetrackingresistivedividervaluestobesmall

enough to make this offset error negligible.

Short-circuitfaultprotectionisassuredbythecombination

of current limit and frequency foldback. When the output

feedback voltage, V , drops below 0.4V, the operating

FB

EXTERNAL

SUPPLY

EXTERNAL

SUPPLY

–V

OUT

–V

OUT

(V < 0V)

OUT

(V < 0V)

3863 F05a

TIME

Ratiometric Tracking

Coincident Tracking

Figure 5a. Two Different Modes of Output Tracking

|V | > 0.8V

OUT

EXT. V

TO SS

V

EXT. V

TO SS

V

OUT

R1 = R

– R

FB2

R

R1

R

FB1

R2

R1+ R2 EXT. V

R2

0.8V

≥

TO V

FBN

R2 = R

FB2

TO FB

3863 F05b

Coincident Tracking Setup

Ratiometric Tracking Setup

Figure 5b. Setup for Ratiometric and Coincident Tracking

3863f

19

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LTC3863

APPLICATIONS INFORMATION

frequency, f, will fold back to a minimum value of 0.18 • f

V

IN

when V reaches 0V. Both current limit and frequency

FB

foldback are active in all modes of operation. In a short-

circuit fault condition, the output current is first limited

by current limit and then further reduced by folding back

the operating frequency as the short becomes more se-

––V

OUT

INTERNAL SOFT-START INDUCED START-UP

(NO EXTERNAL SOFT-START CAPACITOR)

vere. The worst-case fault condition occurs when V

is shorted to ground.

OUT

~650µs

TIME

(6a)

Short-Circuit Recovery and Internal Soft-Start

–V

OUT

An internal soft-start feature guarantees a maximum posi-

tive output voltage slew rate in all operational cases. In a

short-circuit recovery condition for example, the output

recovery rate is limited by the internal soft-start so that

output voltage overshoot and excessive inductor current

buildup is prevented.

SHORT-CIRCUIT

INTERNAL SOFT-START

INDUCED RECOVERY

3863 F06

TIME

(6b)

Figure 6. Internal Soft-Start (6a) Allows Soft-Start without an

External Soft-Start Capacitor and Allows Soft Recovery from

(6b) a Short-Circuit

The internal soft-start voltage and the external SS pin

operate independently. The output will track the lower of

the two voltages. The slew rate of the internal soft-start

voltage is roughly 1.2V/ms, which translates to a total

soft-start time of 650µs. If the slew rate of the SS pin is

greaterthan1.2V/mstheoutputwilltracktheinternalsoft-

start ramp. To assure robust fault recovery, the internal

soft-start feature is active in all operational cases. If a

short-circuit condition occurs which causes the output to

drop significantly, the internal soft-start will assure a soft

recovery when the fault condition is removed.

The implications of both the UVLO rising and UVLO falling

specifications must be carefully considered for low V

IN

operation. The UVLO threshold with V rising is typi-

IN

cally 3.5V (with a maximum of 3.8V) and UVLO falling is

typically 3.25V (with a maximum of 3.5V). The operating

input voltage range of the LTC3863 is guaranteed to be

3.5V to 60V over temperature, but the initial V ramp

IN

must exceed 3.8V to guarantee start-up.

The internal soft-start assures a clean soft ramp-up from

any fault condition that causes the output to droop, guar-

anteeing a maximum ramp rate in soft-start, short-circuit

fault release. Figure 6 illustrates how internal soft-start

controlstheoutputramp-uprateundervaryingscenarios.

Minimum On-Time Considerations

The minimum on-time, t

, is the smallest time

ON(MIN)

duration that the LTC3863 is capable of turning on the

power MOSFET, and is typically 220ns. It is determined

by internal timing delays and the gate charge required

to turn on the MOSFET. Low duty cycle applications may

approach this minimum on-time limit, so care should be

taken to ensure that:

V Undervoltage Lockout (UVLO)

IN

The LTC3863 is designed to accommodate applications

requiring widely varying power input voltages from 3.5V

to 60V. To accommodate the cases where V drops sig-

IN

nificantly once in regulation, the LTC3863 is guaranteed

| V

|+ V

D

(

)

OUT

t

<

ON(MIN)

to operate down to a V of 3.5V over the full temperature

IN

f • V

+ | V

|+ V

D

OUT

(

)

IN(MAX)

range.

3863f

20

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will skip cycles.

However, the output voltage will continue to regulate.

2. Transition Loss: Transition loss of the P-channel

MOSFET becomes significant only when operating

at high input voltages (typically 20V or greater.) The

P-channel transition losses (P

) can be deter-

MOSTRL

Efficiency Considerations

mined from the following equation:

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

the dominant contributors and therefore where efficiency

improvements can be made. Percent efficiency can be

expressed as:

2

f•C_MILLER• V + |V |+V_D

(

)

IN

OUT

P

=

PMOSTRL

2









I_OUT

1–D

R_DN

– V

R_UP

V_MILLER

•

+





V – V

(

)

IN

MILLER

CAP

3. Gate Charging Loss: Charging and discharging the gate

of the MOSFET will result in an effective gate charg-

ing current. Each time the P-channel MOSFET gate is

switched from low to high and low again, a packet of

% Efficiency = 100% - (L1+L2+L3+…)

where L1, L2, L3, etc., are the individual losses as a per-

centage of input power.

Although all dissipative elements in the circuit produce

losses, four main sources account for most of the losses

in LTC3863 application circuits.

charge,dQ,movesfromthecapacitoracrossV –V

IN

CAP

andisthenreplenishedfromgroundbytheinternalV

CAP

regulator. The resulting dQ/dt current is a current out

of V flowing to ground. The total power loss in the

IN

1. Conduction Loss: Conduction losses result from the

controller including gate charging loss is determined

P-channel MOSFET R

, inductor resistance DCR,

SENSE

DS(ON)

by the following equation:

the current sense resistor R

, and input and output

capacitor ESR. The current through DCR is continuous.

The currents through both the P-channel MOSFET and

Schottky diode are discontinuous. The following equa-

tion may be used to determine the total conduction loss

P

= V • (I + f • Q

)

CNTRL

IN

Q

G(PMOSFET)

4. Schottky Loss: The Schottky loss is independent of

duty factors. The critical component is the Schottky

forward voltage as a function of junction temperature

and current. The Schottky power loss is given by the

equation:

(P

) in continuous conduction mode:

COND



₂



2

I_OUT

∆I_L

12

P_COND

≈

+

2



P

= I

• V

DIODE

OUT D(IOUT,TJ)

1–D

(

)





When making adjustments to improve efficiency, the in-

put current is the best indicator of changes in efficiency.

If changes cause the input current to decrease, then the

efficiency has increased. If there is no change in input

current, there is no change in efficiency.









R_DCR+ D• R_DS(ON)+ R_SENSE+ R_ESR(CIN)

(

)

•









+ 1–D •R

(

)

ESR(COUT)

3863f

21

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LTC3863

APPLICATIONS INFORMATION

OPTI-LOOP^®Compensation

ConnectingaresistiveloadinserieswithapowerMOSFET,

then placing the two directly across the output capacitor

and driving the gate with an appropriate signal generator

is a practical way to produce a realistic load-step condi-

tion. The initial output voltage step resulting from the step

change in output current may not be within the bandwidth

of the feedback loop, so this signal cannot be used to

determine phase margin. This is why it is better to look

at the ITH pin signal which is in the feedback loop and

is the filtered and compensated feedback loop response.

OPTI-LOOP compensation, through the availability of the

ITHpin,allowsthetransientresponsetobeoptimizedfora

wide range of loads and output capacitors. The ITH pin not

only allows optimization of the control loop behavior but

also provides a test point for the regulator’s DC-coupled

and AC-filtered closed-loop response. The DC step, rise

time and settling at this test point truly reflects the closed-

loop response. Assuming a predominantly second order

system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at this pin.

ThegainoftheloopincreaseswithR andthebandwidth

ITH

of the loop increases with decreasing C

. If R is

ITH1

ITH

increased by the same factor that C

is decreased, the

ITH1

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

TheITHseriesR -C

filtersetsthedominantpole-zero

ITH ITH1

loop compensation. Additionally, a small capacitor placed

fromtheITHpintosignalground,C ,mayberequiredto

feedback loop. In addition, a feedforward capacitor, C ,

FF

ITH2

can be added to improve the high frequency response, as

attenuatehighfrequencynoise.Thevaluescanbemodified

to optimize transient response once the final PCB layout

is done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selectedbecausetheirvarioustypesandvaluesdetermine

theloopfeedbackfactorgainandphase. Anoutputcurrent

pulse of 20% to 100% of full load current having a rise

time of 1μs to 10μs will produce output voltage and ITH

pin waveforms that will give a sense of the overall loop

stability without breaking the feedback loop. The general

goal of OPTI-LOOP compensation is to realize a fast but

stable ITH response with minimal output droop due to

the load step. For a detailed explanation of OPTI-LOOP

compensation, refer to Application Note 76.

shown in Figure 1. Capacitor C provides phase lead by

FF

creating a high frequency zero with R which improves

B1

the phase margin. The output voltage settling behavior is

related to the stability of the closed-loop system and will

demonstrate overall performance of the regulator.

Insomeapplications,amoreseveretransientcanbecaused

by switching in loads with large (>10μF) input capacitors.

If the switch connecting the load has low resistance and

is driven quickly, then the discharged input capacitors are

effectivelyputinparallelwithC , causingarapiddropin

OUT

V

OUT

. No regulator can deliver enough current to prevent

this problem. The solution is to limit the turn-on speed of

the load switch driver. A Hot Swap™ controller is designed

specifically for this purpose and usually incorporates cur-

rent limiting, short-circuit protection and soft-start.

Switching regulators take several cycles to respond to a

step in load current. When a load step occurs, V

im-

OUT

•ESR,where

mediatelyshiftsbyanamountequalto∆I

LOAD

Large-Signal Effects on ITH

ESR is the effective series resistance of C . ∆I

also

OUT

LOAD

Inverting controllers have a wide range of applications

and operating conditions which affect compensation.

Low switching frequencies and the inverting buck-boost

right-half-plane zero can result in very low gain crossover

frequencyrequirements.Lowcrossoverfrequenciesoften

beginstochargeordischargeC ,generatingafeedback

OUT

error signal used by the regulator to return V

to its

can

OUT

steady-state value. During this recovery time, V

OUT

be monitored for overshoot or ringing that would indicate

a stability problem.

requireacompensationR andC thataretoosmallfor

ITH

3863f

22

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

the error amplifier output drive current on ITH of 100µA.

The effect causes ITH to appear clamped in response

to a transient load current step which causes excessive

output droop.

If R is chosen to be 188k, then R needs to be 30.1k.

FB2 FB1

The FREQ pin is tied to signal ground in order to program

the switching frequency to 350kHz. The on-time required

to generate –5V output from 55V V in continuous mode

IN

An R greater than 20k allows ITH to swing 1.5V with

can be calculated as:

ITH

margin for temperature and part to part variation and

5V+ 0.5V

t_ON(CCM)

=

= 260ns

should never have this issue. In applications with less

320kHz • 55V+ 5V+ 0.5V

(

)

severe transient load step requirements, R can safely

ITH

be set as low as 10k. We do not recommend less than

This on-time, t , is larger than LTC3863’s minimum on-

ON

10k in any application. If R is too small then either

ITH

time with sufficient margin to prevent cycle skipping. Use

a lower frequency if a larger on-time margin is needed to

accountforvariationsfromminimumon-timeandswitch-

ing frequency. As load current decreases, the converter

will eventually start cycle skipping.

the operating frequency will need to be increased or the

output capacitor increased to increase the R required

ITH

to stabilize the system. We strongly recommend that any

system with an R less than 20k be experimentally veri-

ITH

fied with worst-case load steps.

Next, set the inductor value such that the inductor ripple

currentis60%oftheaverageinductorcurrentatmaximum

V = 55V and full load = 1.8A:

IN

Design Example

Consider an inverting converter with the following speci-

fications:

55V²• 5V+ 0.5V

(

)

L =

≈ 13.1µH

V

= 4.5V to 55V, V

= –5V, I

= 1.8A, and

OUT(MAX)

IN

OUT

2

0.6•1.8A •320kHz • 55V+ 5V+ 0.5V

(

)

f = 320kHz (Figure 7).

The output voltage is programmed according to:

Select a standard value of 12μH.

R_FB2

V_OUT= –0.8V •

R_FB1

The resulting ripple current at minimum V of 4.5V is:

IN

5V • 5V+ 0.5V

(

)

∆I_L=

= 0.644A

12µH•320kHz • 5V+ 5V+ 0.5V

(

)

V

IN

4.5V TO 55V

C

+

C

68µF

63V

IN2

IN1

0.47µF

4.7µF

100V

×2

CAP

RUN

V

IN

320kHz

16mΩ

D1

PLLIN/MODE

SENSE

GATE

SS

220pF

0.1µF

15nF

Q1

V

OUT

–5V

C

LTC3863

OUT1

OUT3 1.8A

10k

L1

12µH

33µF

16V

×2

100µF

+

ITH

187k

20V

52.3k

FREQ

C

: CDE AFK686M63G24T-F

: TDK CGA6M3X7S2A475K

SGND

V

IN1

IN2

FBN

30.1k

12pF

: TDK C4532X7R1C336M

OUT1

: PANASONIC 20SVP100M

OUT3

V

FB

PGND

3863 F07

D1: VISHAY SS8PH9-M3/87A

L1: MSS1278-123ML

Q1: VISHAY Si7469DP

Figure 7. Design Example (4.5V to 55V Input, –5V, 1.8A at 320kHz)

3863f

23

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LTC3863

APPLICATIONS INFORMATION

Theboundaryoutputcurrentforcontinuous/discontinuous

mode is calculated:

Next choose a P-channel MOSFET with the appropriate

BV and I rating. The BV rating should be greater

DSS

D

DSS

than (55V + 5V + V ) with sufficient margin. In this ex-

D

55V²•5V

ample, a good choice is the Vishay Si7469DP (BV

=

DSS

I_OUT(CDB)

=

= 0.55A

2

80V, I = 10A, R

= 30mΩ, ρ

JA

= 1.8, V

2•12µH•320kHz • 55V+ 5V

(

)

D

DS(ON)

100°C MILLER

3.2V, C

= 235pF, θ = 24°C/W). The highest power

MILLER

The maximum inductor peak current occurs at minimum

dissipation and the resulting junction temperature for the

V of 4.5V and full load of 1.8A where LTC3863 operates

P-channel MOSFET occurs at the minimum V of 5V and

IN

in continuous mode is:

maximum output current of 1.8A. They can be calculated

at T = 70°C as follows:

A

1.8A • 4.5V+ 5V+ 0.5V

∆I_L

2

(

)

+

I_{L(PEAK _MAX)}

=

5V+ 0.5V

D=

5V

≈ 0.55

4.5V+ 5V+ 0.5V

0.644A

= 3.6A+

≈ 4.25A

2

1.8A



 ²

P

= 0.55•

•1.8•30mΩ







PMOS



1–0.55

Next, set the R

resistor value to ensure that the

SENSE

2

converter can deliver the maximum peak inductor current

of 4.25A with sufficient margin to account for component

variations and worst-case operating conditions. Using a

30% margin factor:

320kHz •235pF • 4.5V+ |–5V|+0.5V

(

)

+

2

1.8A

1–0.55

0.9Ω

4.5V –3.2V 3.2V

2Ω





•

+









(

)

95mV

1.3•4.25A

R_SENSE

=

= 17.2mΩ

≈ 0.475W+ 0.020W ≈ 0.495W

T = 70°C + 0.495W • 24°C/W = 82°C

J

Use a more readily available 16mΩ sense resistor. This

results in peak inductor current limit:

The same calculations can be repeated for V

= 55V:

IN(MAX)

95mV

16mΩ

5V+ 0.5V

55V+ 5V+ 0.5V

I_L(PEAK)

=

= 5.94A

D=

≈ 0.091

 ²



Chooseaninductorthathasratedsaturationcurrenthigher

than 5.94A with sufficient margin.

1.8A

1–0.091



P

≈ 0.091•

•1.8•30mΩ



PMOS





2

The output current limit can be calculated from the peak

inductorcurrentlimitanditsminimumoccursatminimum

IN

320kHz •235pF • 55V+ |–5V|+0.5V

(

)

+

2

V of 5V:

1.8A

0.9Ω

2Ω







•

+

95mV 0.644A

5V











1–0.091 5V –3.2V 3.2V

I_LIMIT(MIN)

=

–

•

(

)









16mΩ

2

4.5V+ 5V+ 0.5V

(

)

≈ 0.019W+ 0.39W ≈ 0.411W

= 2.8A

T = 70°C + 0.411W • 24°C/W = 80°C

J

In this example, 2.8A is the maximum output current the

NextchooseanappropriateSchottkydiodethatwillhandle

the power requirements. The reverse voltage of the diode,

V , should be greater than (55V + 5V). The Fairchild

S38 Schottky diode is selected (V (3A,125°C) = 0.45V,

switching regulator can support at V = 4.5V. It is larger

IN

than the full load of 1.8A by a margin of 1A. If a larger

R

margin is needed, use a smaller R

.

SENSE

F

3863f

24

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

V = 80V, θ = 55°C/W) for this application. The power

Gate Driver Component Placement,

Layout and Routing

R

JA

dissipation and junction temperature at T = 70° and full

A

load = 1.8A can be calculated as:

It is important to follow recommended power supply PC

board layout practices such as placing external power ele-

ments to minimize loop area and inductance in switching

paths. Be careful to pay particular attention to gate driver

component placement, layout and routing.

P

DIODE

= 1.8A • 0.45V = 0.81W

T = 70°C + 0.81W • 55°C/W = 114°C

J

These power dissipation calculations show that careful

attention to heat sinking will be necessary.

TheeffectiveC capacitanceshouldbegreaterthan0.1µF

CAP

For the input bypass capacitors, choose low ESR ceramic

capacitors that can handle the maximum RMS current at

minimum in all operating conditions. Operating voltage

and temperature both decrease the rated capacitance to

varyingdegreesdependingondielectrictype.TheLTC3863

is a PMOS controller with an internal gate driver and boot-

strapped LDO that regulates the differential CAP voltage

the minimum V of 4.5V:

IN

|–5V|

4.5V

I_CIN(RMS)≈ 1.8A •

= 1.9A

(V – V ) to 8V nominal. The C capacitance needs

IN

CAP

to be large enough to assure stability and provide cycle-

to-cycle current to the PMOS switch with minimum series

inductance.Werecommendaceramic0.47µF16Vcapacitor

with a high quality dielectric such as X5R or X7R. Some

high current applications with large Qg PMOS switches

C

will be selected based on the ESR that is required

OUT

to satisfy the output voltage ripple requirement. For this

design, two 47μF ceramic capacitors are chosen to offer

low ripple in both normal operation and in Burst Mode

operation.

may benefit from an even larger C

capacitance.

CAP

The selected C

operating current at a minimum V of 4.5V:

must support the maximum RMS

OUT

Figure 8 shows the LTC3863 Generic Application Sche-

matic which includes an optional current sense filter and

series gate resistor. Figure 9 illustrates the recommended

gate driver component placement, layout and routing of

IN

|–5V|

4.5V

I_CIN(RMS)≈ 1.8A •

= 1.9A

the GATE, V , SENSE and CAP pins and key gate driver

IN

A soft-start time of 8ms can be programmed through a

0.1μF capacitor on the SS pin:

components.Itisrecommendedthatthegatedriverlayout

follow the example shown in Figure 9 to assure proper

operation and long term reliability.

8ms•10µA

C_SS=

= 0.1µF

The LTC3863 gate driver should connect to the external

power elements in the following manner. First route the

0.8V

LoopcompensationcomponentsontheITHpinarechosen

based on load step transient behavior (as described under

OPTI-LOOPCompensation)andisoptimizedforstability.A

pull-up resistor is used on the RUN pin for FMEA compli-

ance (see Failure Modes and Effects Analysis).

V

pin using a single low impedance isolated trace to

IN

the positive R

resistor PAD without connection to

SENSE

the V plane. The reason for this precaution is that the

IN

V pin is internally Kelvin connected to the current sense

IN

comparator, internal V power and the PMOS gate driver.

IN

Connecting the V pin to the V power plane adds noise

An application with complementary dual outputs of 5V

can be designed by using two LTC3863 parts with one

configured into an inverting regulator and the other into

a step-down buck regulator as shown in Figure 11. Refer

to LTC3864 data sheet for the actual design of a buck

output of 5V.

IN

andcanresultinjitterorinstability.Figure9showsasingle

V trace from the positive R

pad connected to C ,

IN

SENSE

SF

C

, V pad and C . The total trace length to R

CAP IN

INB SENSE

should be minimized and the capacitors C , C

and

CF CAP

C

should be placed near the V pin of the LTC3863.

INB

IN

3863f

25

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

C

R

resistor pads can be added with a 0Ω resistor to

INB

GATE

V

allow the damping resistor to be added later. The total

length of the gate drive trace to the PMOS gate should

be minimized and ideally be less than 1cm. In most cases

IN

C

CAP

C

IN

CAP

RUN

V

IN

+

R

–

C

SF

C

SENSE

PLLIN/MODE

SS

with a good layout the R

resistor is not needed. The

R

GATE

SF

SENSE

GATE

R

resistor should be located near the gate pin to re-

C

GATE

R

PITH

GATE

D1

Q1

duce peak current through GATE and minimize reflected

V

OUT

C

noise on the gate pin.

ITH

LTC3863

C

R

OUT

ITH

L1

ITH

The R and C pads can be added with a zero ohm resis-

SF

R

FREQ

R

FREQ

FB1

FB2

tor for R and C not populated. In most applications,

SF

SGND

V

FBN

external filtering is not needed. The current sense filter

C

FB2

GROUND

PLANE

TO PGND

R

and C can be added later if noise if demonstrated

SF

V

FB

PGND

3863 F08

to be a problem.

The bypass capacitor C

is used to locally filter the

INB

Figure 8: LTC3863 Generic Application Schematic with Optional

Current Sense Filter and Series Gate Resistor

V

supply. C should be tied to the V pin trace and

IN

INB IN

to the PGND exposed pad. The C positive pad should

INB

connect to R

INB

pad connection.

positive though the V pin trace. The

SENSE

IN

C

ground trace should connect to the PGND exposed

C

INB

TO Q1 GATE

+

R

GATE

PC Board Layout Checklist

TO R

SENSE

GATE

C

R

SF

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3863.

V

IN

C

CAP

SENSE

CAP

SF

1. Multilayer boards with dedicated ground layers are

preferable for reduced noise and for heat sinking pur-

–

TO R

SENSE

3863 F09

poses. Use wide rails and/or entire planes for V , V

IN OUT

Figure 9: LTC3863 Recommended Gate Driver PC Board

Placement, Layout and Routing

and GND for good filtering and minimal copper loss. If

a ground layer is used, then it should be immediately

below (and/or above) the routing layer for the power

C

should be placed near the V and CAP pins. Figure 9

IN

CAP

shows C

train components which consist of C , sense resistor,

P-channelMOSFET,Schottkydiode,inductor,andC

Flood unused areas of all layers with copper for better

heat sinking.

IN

placed adjacent to the V and CAP pins with

CAP

IN

.

OUT

SENSEroutedbetweenthepads.Thisistherecommended

layout and results in the minimum parasitic inductance.

The gate driver is capable of providing high peak current.

Parasitic inductance in the gate drive and the series in-

2. Keep signal and power grounds separate except at the

point where they are shorted together. Short the signal

and power ground together only at a single point with a

narrow PCB trace (or single via in a multilayer board).

All power train components should be referenced to

power ground and all small-signal components (e.g.,

ductance between V to CAP can cause a voltage spike

IN

betweenV andCAPoneachswitchingcycle. Thevoltage

IN

spike can result in electrical over-stress to the gate driver

and can result in gate driver failures in extreme cases. It

is recommended to follow the example shown in Figure 9

C

, R

, C etc.) should be referenced to the

for the placement of C

as close as is practical.

ITH1

signal ground.

FREQ SS

CAP

3863f

26

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

3. Place C , sense resistor, P-channel MOSFET, induc-

and R

pins. Use sufficient isolation when routing a

IN

FREQ

tor, and primary C

capacitors close together in

clock signal into the PLLIN /MODE pin so that the clock

does not couple into sensitive small-signal pins.

OUT

one compact area. The junction connecting the drain

of the P-channel MOSFET, cathode of the Schottky,

and (+) terminal of the inductor (this junction is com-

monly referred to as switch or phase node) should be

compact but be large enough to handle the inductor

currents without large copper losses. Place the sense

resistor and source of P-channel MOSFET as close

Failure Mode and Effects Analysis (FMEA)

AFMEAstudyontheLTC3863hasbeenconductedthrough

adjacent pin opens and shorts. The device was tested in

a step-down application (Figure 15) from V = 12V to

IN

V

= –5V with a current load of 2A on the output. One

OUT

as possible to the (+) plate of the C capacitor(s)

IN

group of tests involved the application being monitored

while each pin was disconnected from the PC board

and left open while all other pins remained intact. The

other group of tests involved each pin being shorted to

its adjacent pins while all other pins were connected as

it would be normally in the application. The results are

shown in Table 2.

that provides the bulk of the AC current (these are

normally the ceramic capacitors), and connect the (–)

terminal of the inductor as close as possible to the

(–) terminal of the same C capacitor(s). The high

IN

dI/dt loop formed by C , the MOSFET, and the Schottky

IN

diode should have short leads and PCB trace lengths to

minimize high frequency EMI and voltage stress from

For FMEA compliance, the following design implementa-

tions are recommended:

inductive ringing. The (+) terminal of the primary C

OUT

capacitor(s) which filter the bulk of the inductor ripple

current (these are normally the ceramic capacitors)

• If the RUN pin is being pulled up to a voltage greater

shouldalsobeconnectedclosetothe(–)terminalofC .

than 6V, then it is done so through a pull-up resistor

IN

(100k to 1M) so that the V

case of a RUN to V

pin is not damaged in

FBN

short.

4. Place Pins 7 to 12 facing the power train components.

Keep high dV/dt signals on GATE and switch away from

sensitive small-signal traces and components.

FBN

• The gate of the external P-channel MOSFET should be

pulled through a resistor (20k to 100k) to the input

5. Place the sense resistor close to the (+) terminal of C

IN

supply,V sothattheP-channelMOSFETisguaranteed

IN

and source of P-channel MOSFET. Use a Kelvin (4-wire)

connectionacrossthesenseresistorandroutethetraces

to turn off in case of a GATE open.

together as a differential pair into the V and SENSE

• To protect against the V

open condition it is neces-

IN

FBN

pins. An optional RC filter could be placed near the V

sary to add an output shutdown clamp. The output

shutdown clamp is comprised of a Zener, V , NPN and

IN

and SENSE pins to filter the current sense signal.

Z

Zener bias resistor, R , to ground as found in Figure 10.

Z

6. Place the resistive feedback divider R

as close as

FB1/2

The clamp voltage will be the Zener forward voltage V

Z

possible to the V and V

pins. The (–) terminal

FB

FBN

plus a V . The clamp needs to be designed such that

BE

of the feedback divider should connect to the output

the worst-case minimum Zener voltage is less than

the maximum operating voltage. The worst-case Zener

leakagecurrenttimestheZenerbiasresistorshouldnot

exceed 200mV.

regulation point and the (+) terminal of the feedback

divider should connect to V .

FB

7. PlacetheceramicC capacitorascloseaspossibleto

CAP

the V and CAP pins. This capacitor provides the gate

IN

C

Z

discharging current for the power P-channel MOSFET.

V

Z

R

Z

8. Placesmallsignalcomponentsasclosetotheirrespective

pins as possible. This minimizes the possibility of PCB

–V

OUT

3863 F10

SS

2N3904

noise coupling into these pins. Give priority to V , ITH,

FB

Figure 10

3863f

27

For more information www.linear.com/3863

LTC3863

APPLICATIONS INFORMATION

Table 2

RECOVERY

WHEN

FAULT IS

FAILURE MODE

None

V

I

VIN

f

REMOVED? BEHAVIOR

OUT

–5V

1A

453mA

350kHz

N/A

Normal Operation.

Pin Open

Open Pin 1 (PLLIN/MODE)

Open Pin 2 (FREQ)

Open Pin 3 (GND)

Open Pin 4 (SS)

–5V

0V

1A

0A

453mA

0.7mA

350kHz

535kHz

350kHz

0kHz

OK

Pin already left open in normal application, so no difference.

Frequency jumps to default open value.

Exposed pad still provides GND connection to device.

External soft-start removed, but internal soft-start still available.

Open Pin 5 (V

)

FB

Controller stops switching. V internally self biases HI to prevent

FB

switching.

Open Pin 6 (ITH)

Open Pin 7 (V

–5V

1A

507mA

502mA

40kHz

OK

Output still regulating, but the switching is erratic. Loop not stable.

)

–6V pk

350kHz

Use a 5.1V Zener V , 10k R and 0.01µF C . Output Voltage is –6V

FBN

Z

peak and averages –4.9V.

Open Pin 8 (RUN)

Open Pin 9 (CAP)

Open Pin 10 (SENSE)

–5V

0V

1A

0A

453mA

0.7mA

350kHz

0kHz

OK

Controller does not start-up.

More jitter during switching, but regulates normally.

SENSE internally prebiases to 0.6V below V . This prevents

IN

controller from switching.

Open Pin 11 (V )

–5.4V

0V

1A

0A

597mA

0.7mA

453mA

20kHz

0kHz

OK

V

able to bias internally through SENSE. Regulates with high

OUT

IN

ripple.

Open Pin 12 (GATE)

Gate does not drive external power FET, preventing output

regulation.

Open Pin 13 (PGND)

–5V

350kHz

Pin 3 (GND) still provides GND connection to device.

Pins Shorted

Short Pins 1, 2

–5V

0V

1A

0A

453mA

0.7mA

9mA

350kHz

0kHz

OK

Burst Mode operation disabled, but runs normally as in pulse-

skipping mode.

(PLLIN/MODE and FREQ)

Short Pins 2, 3

(FREQ and GND)

FREQ already shorted to GND, so regulates normally.

Short Pins 3, 4

(GND and SS)

0kHz

SS short to GND prevents device from starting up.

Short Pins 4, 5

–1V(DC) 50mA

–3V

Erratic

350kHz

V

oscillates from 0V to 3V.

OUT

(SS and V

)

FB

P-P

Short Pins 5, 6

–3.15V 625mA 181mA

Controller loop does not regulate to proper output voltage.

Controller does not start-up.

(V and ITH)

FB

Short Pins 7, 8

5V

0A

860µA

(V

and RUN)

FBN

Short Pins 8, 9

(RUN and CAP)

–5V

0V

1A

0A

1A

0A

453mA

181mA

453mA

29mA

350kHz

0kHz

OK

Able to start-up and regulate normally.

Short Pins 9, 10

(CAP and SENSE)

CAP ~ V , which prevents turning on external P-MOSFET.

IN

Short Pins 10, 11

–5V

0V

50kHz

0kHz

Regulates with high V

ripple.

OUT

(SENSE and V )

IN

Short Pins 11, 12

Power MOSFET is always kept OFF, preventing regulation.

(V and GATE)

IN

3863f

28

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATIONS

V

*

IN

4.5V TO 55V

+

C

68µF

63V

0.1µF

316k

IN2

IN1

LTC6908-1

4.7µF

100V

×2

+

0.47µF

V

SYNC1

GND SYNC2

CAP

SET

MOD

RUN

V

IN

320kHz

25mΩ

16mΩ

D1

PLLIN/MODE

SS

0.1µF

SENSE

GATE

SENSE

GATE

SS

Q2

220pF

L2

10µH

Q1

V

*

V

OUT

5V

–5V

LTC3864

LTC3863

+

10nF

15nF

C

OUT1

C

1.8A

OUT4

OUT5

OUT3 1.8A

15k

10k

L1

100µF

6.3V

220µF

35V

33µF

100µF

D2

+

ITH

12µH

187k

16V

×2

20V

52.3k

PGOOD

FREQ

*V

OUT

WHEN 3.5V < V < 5.2V

IN

FOLLOWS V

IN

SGND

V

C

: CDE AFK686M63G24T-F

: TDK CGA6M3X7S2A475K

TDK C4532X7R1C336M

PANASONIC 20SVP100M

FBN

IN1

IN2

30.1k

422k

12pF

OUT1

OUT3

V

FB

D2: DIODES SBR3U100LP-7

L2: TOKO B1134AS-100M

Q2: FAIRCHILD FDMC5614P

FB

PGND

3863 F11a

D1: VISHAY SS8PH9-M3/87A

L1: MSS1278-123ML

80.6k

C

: TDK C4532X5R0J07M

: PANASONIC EEE-FK1V221P

Q1: VISHAY Si7469DP

OUT4

OUT5

NOTE: LTC3863 CAN BE USED IN PLACE

OF LTC3864 IF V IS TIED > 2V

FBN

Negative 5V Efficiency

Positive 5V Efficiency

100

10

9

90

9

8

7

6

5

4

3

2

1

0

V

= 12V

= 5V

V

= 12V

= –5V

IN

OUT

IN

OUT

90

80

70

80

70

60

50

40

30

20

10

0

8

7

EFFICIENCY

60

50

6

5

PULSE-SKIPPING MODE

Burst Mode OPERATION

40

30

20

10

0

4

3

2

1

0

PULSE-SKIPPING MODE

Burst Mode OPERATION

POWER LOSS

0.02 0.2

LOAD CURRENT (A)

0.002

2

0.002

0.02

0.2

2

LOAD CURRENT (A)

3863 F11b

3863 F11d

Negative 5V Gain/Phase

Positive 5V Gain/Phase

70

105

90

60

90

75

60

45

30

15

0

60

50

40

30

20

10

0

75

PHASE

GAIN

40

60

PHASE

30

45

20

30

10

15

GAIN

0

–10

–20

–30

–15

–30

–45

–10

–20

–30

–15

–30

–45

1

10

100

1

10

100

FREQUENCY (kHz)

3863 F11c

3863 F11e

Figure 11. Design Example, 4.5V to 55V Input, 5V, 1.8A at 320kHz

Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.

3863f

29

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATIONS

V

IN

5V TO 23V

+

C

IN2

IN1

0.47µF

100µF

50V

10µF

25V

×2

CAP

RUN

V

IN

750kHz

50pF

25mΩ

PLLIN/MODE

SS

SENSE

GATE

0.1µF

4.7nF

D1

Q1

V

OUT

–18V

C

OUT3

OUT1

LTC3863

700mA

36.5k

100k

100µF

10µF

L1

15µH

+

ITH

20V

25V

×2

191k

FREQ

C

: NICHICON UCJ1H101MCL1GS

: TDK C3225X7R1E108M

SGND

V

IN1

IN2

FBN

8.45k

47pF

: MURATA GRM32DR61E106KA12L

OUT1

: PANASONIC 20SVO100M

OUT3

V

FB

PGND

3863 F12a

D1: DIODES SBR8U60P5

L1: WURTH 744770115

Q1: VISHAY SI7469DP

Efficiency

Gain/Phase

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

60

50

90

75

60

45

30

15

0

PULSE-SKIPPING MODE

Burst Mode OPERATION

V

= 12V

IN

OUT

= –18V

V

= 12V

IN

OUT

40

= –18V

PHASE

GAIN

30

20

EFFICIENCY

10

0

–10

–20

–30

–15

–30

–45

POWER LOSS

0

1

10

100

0.001

0.01

0.1

FREQUENCY (kHz)

LOAD CURRENT (A)

3863 F12c

3863 F12b

Figure 12. 5V to 23V Input, –18V/700mA Output, 750kHz Inverting Converter

Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.

3863f

30

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATIONS

V

IN

3.5V TO 28V

+

C

IN1

100µF

50V

IN2

0.47µF

10µF

50V

×2

CAP

RUN

V

IN

80kHz

82pF

82mΩ

PLLIN/MODE

SS

SENSE

GATE

0.1µF

3.3nF

D1

Q1

V

OUT

–0.4V

C

OUT3

OUT1

LTC3863

200mA

5k

100µF

10µF

25V

×2

L1

+

ITH

20V

15µH

95.3k

191k

61.9k

FREQ

C

: NICHICON UCJ1H101MCL1GS

: MURATA GRM32ER71H108H

SGND

V

IN1

IN2

FBN

10pF

: TDK C4532X7R1C336M

OUT1

OUT3

V

: PANASONIC 16TQC150MYF

FB

PGND

3863 F13a

D1: DIODES B540C-13-F

L1: WURTH 7447779115

Q1: FAIRCHILD FDMC5614P

Efficiency

Gain/Phase

50

40

30

20

10

0

0.5

0.4

0.3

0.2

0.1

0

60

50

90

V

= 12V

OUT

PULSE-SKIPPING MODE

Burst Mode OPERATION

IN

= –0.4V

75

V

= 12V

IN

OUT

40

60

= –0.4V

PHASE

GAIN

30

45

20

30

EFFICIENCY

10

15

0

–10

–20

–30

–15

–30

–45

POWER LOSS

0.2

1

10

FREQUENCY (kHz)

100

0.002

0.02

LOAD CURRENT (A)

3863 F13c

3863 F13b

Figure 13. 3.5V to 28V Input, –0.4V/200mA Output, 80kHz Inverting Converter

Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.

3863f

31

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATIONS

V

IN

12V TO 42V

+

C

IN1

100µF

50V

IN2

0.47µF

10µF

50V

×2

CAP

RUN

V

IN

440kHz

27mΩ

D1

PLLIN/MODE

SENSE

GATE

0.1µF

18nF

SS

Q1

V

OUT

–48V

C

OUT3

OUT1

LTC3863

300mA

1M

100µF

4.7µF

100V

×2

L1

10µH

+

ITH

63V

196k

64.9k

FREQ

C

: NICHICON UCJ1H101MCL1GS

: MURATA GRM32ER71H106H

SGND

V

IN1

IN2

FBN

3.32k

100pF

: TDK CGA6M3X7S2A475K

OUT1

: UCC EMVH630ARA101MKE

OUT3

V

FB

PGND

3863 F14a

D1: DIODES PDS5100H

L1: WURTH 744314101

Q1: VISHAY SI7113DN

Efficiency

Gain/Phase

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

0

70

60

105

90

V

= 24V

PULSE-SKIPPING MODE

Burst Mode OPERATION

IN

OUT

= –48V

V

= 24V

IN

OUT

50

75

= –48V

40

60

PHASE

30

45

EFFICIENCY

20

30

10

GAIN

15

0

–10

–20

–30

–15

–30

–45

POWER LOSS

2

20

FREQUENCY (kHz)

200

0.001

0.01

0.1

LOAD CURRENT (A)

3863 F14c

3863 F14b

Figure 14. 12V to 42V Input, –48V/300mA Output, 440kHz Inverting Converter

Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.

3863f

32

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATIONS

V

IN

4.5V TO 16V

+

C

IN1

100µF

20V

IN2

0.47µF

10µF

25V

×2

CAP

RUN

V

IN

350kHz

16mΩ

PLLIN/MODE

SS

SENSE

GATE

390pF

0.1µF

27nF

D1

Q1

V

OUT

–5V 1.7A (SHORT R

–12V 1A

)

FBO

C

OUT3

OUT1

LTC3863

14.7k

61.9k

R

150µF

33µF

FBO

L1

+

ITH

698k

16V

10µH

16V

×2

511k

FREQ

C

: PANASONIC 20SVP100M

: TDK C3225X7R1E106M

SGND

V

IN1

IN2

FBN

80.6k

68pF

: TDK C4532X7R1C336M

OUT1

OUT3

V

: PANASONIC 16TQC150MYF

FB

PGND

3863 F15a

D1: DIODES B540C

L1: TOKO 919AS-100M

Q1: VISHAY SI7129DN-T1-GE3

–5V Efficiency

–12V Efficiency

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

V

= 12V

V

= 12V

IN

OUT

IN

OUT

= –5V

= –12V

EFFICIENCY

PULSE-SKIPPING MODE

Burst Mode OPERATION

PULSE-SKIPPING MODE

Burst Mode OPERATION

3

2

1

0

POWER LOSS

0

2

0.002

0.02

0.2

0.002

0.02

0.2

2

LOAD CURRENT (A)

3863 F15b

Figure 15. 4.5V to 16V Input, –5V/1.7A, –12V/1A Output, 350kHz Inverting Converter

3863f

33

For more information www.linear.com/3863

LTC3863

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DE/UE Package

12-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1695 Rev D)

0.70 ±0.05

3.30 ±0.05

3.60 ±0.05

2.20 ±0.05

1.70 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

2.50 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.40 ±0.10

4.00 ±0.10

(2 SIDES)

R = 0.115

TYP

7

12

R = 0.05

TYP

3.30 ±0.10

3.00 ±0.10

(2 SIDES)

1.70 ±0.10

PIN 1

TOP MARK

(NOTE 6)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

(UE12/DE12) DFN 0806 REV D

6

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.50 REF

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3863f

34

For more information www.linear.com/3863

LTC3863

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSE Package

12-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1666 Rev F)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 ±0.102

(.112 ±.004)

0.889 ±0.127

(.035 ±.005)

(.112 ±.004)

1

6

0.35

REF

1.651 ±0.102

(.065 ±.004)

5.23

(.206)

MIN

1.651 ±0.102

(.065 ±.004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

DETAIL “B”

12

7

0.65

(.0256)

BSC

0.42 ±0.038

4.039 ±0.102

(.159 ±.004)

(NOTE 3)

(.0165 ±.0015)

TYP

0.406 ±0.076

RECOMMENDED SOLDER PAD LAYOUT

(.016 ±.003)

12 11 10 9 8 7

REF

DETAIL “A”

0.254

(.010)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0° – 6° TYP

4.90 ±0.152

(.193 ±.006)

GAUGE PLANE

0.53 ±0.152

(.021 ±.006)

1

2 3 4 5 6

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 ±0.0508

(.004 ±.002)

MSOP (MSE12) 0911 REV F

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL

NOT EXCEED 0.254mm (.010") PER SIDE.

3863f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

35

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/3863

LTC3863

TYPICAL APPLICATION

Efficiency

90

80

70

60

50

40

30

20

10

0

9

8

7

6

5

4

3

2

1

0

V

= 24V

IN

OUT

= –150V

EFFICIENCY

V

IN

12V TO 40V

IN3

+

C

68µF

63V

IN2

0.47µF

CAP

PULSE-SKIPPING MODE

Burst Mode OPERATION

10µF

50V

×2

RUN

V

IN

320kHz

1.8pF

39mΩ

PLLIN/MODE

SS

POWER LOSS

SENSE

GATE

0.1µF

D1

Q1

V

0.001

0.01

0.1

OUT

–150V

40mA

LOAD CURRENT (A)

3863 F16b

C

180pF

C

OUT3

47µF

OUT1

LTC3863

845k

1M

1µF

L1

15µH

+

ITH

Gain/Phase

200V

250V

52.3k

×2

40

135

120

105

90

FREQ

V

= 24V

= –150V

IN

OUT

35

30

25

20

15

10

5

C

: CDE AFK686M63G24T-F

: MURATA GRM32ER71H106H

: TDK CGA8P3X7T2E105K/SOFT

: LELON VEJ-470M2DTR-1616

D1: ON SEMI MBRS3201T3G

L1: TOKO 1217AS-H-150M

Q1: VISHAY SI7119

SGND

V

IN1

IN2

OUT1

OUT3

FBN

10.7k

3.3pF

PHASE

V

FB

PGND

3863 F16a

75

60

45

30

0

15

GAIN

–5

–10

–15

–20

0

–15

–30

–45

0.1

1

10

100

FREQUENCY (Hz)

3963 F16c

Figure 16. 12V to 40V Input, –150V/40mA Output, 320kHz Inverting Converter

Gain/Phase Measurements Taken with OMICRON Lab Bode 100 Vector Network Analyzer.

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3864

Low I , High Voltage Step-Down DC/DC Controller Fixed Frequency 50kHz to 850kHz, 3.5V≤ V ≤ 60V, 0.8V ≤ V

≤ V ,

OUT IN

Q

IN

with 100% Duty Cycle

I = 40µA, MSOP-12E, 3mm × 4mm DFN-12

Q

LTC3891

60V, Low I , Synchronous Step-Down DC/DC

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 24V,

Q

IN

OUT

Controller

I = 50µA

Q

LTC3890/LTC3890-1

60V, Low I , Dual 2-Phase Synchronous

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 24V,

Q

IN

OUT

LTC3890-2/LTC3890-3 Step-Down DC/DC Controller

I = 50µA

Q

LTC3630

High Efficiency, 65V, 500mA Synchronous

Step-Down Regulator

4V ≤ V ≤ 65V, 0.8V ≤ V

≤ V , I = 12µA, 3mm × 5mm DFN-16 and

IN Q

IN

OUT

MSOP-16E

LTC3834/LTC3834-1

LTC3835/LTC3835-1

Low I , Single Output Synchronous Step-Down

PLL Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V,

Q

IN

OUT

DC/DC Controllers with 99% Duty Cycle

I = 30µA/80µA

Q

LT3758A

High Input Voltage, Boost, Flyback, SEPIC and

Inverting Controller

5.5V ≤ V ≤ 100V, Positive or Negative V , 3mm × 3mm DFN-10 and

IN

OUT

MSOP-10E

LTC3826/LTC3826-1

LTC3859AL

Low I , Dual Output 2-Phase Synchronous

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 36V, 0.8V ≤ V

Q

≤ 10V,

Q

IN

OUT

Step-Down DC/DC Controllers with 99% Duty Cycle I = 30µA

Low I , Triple Output Buck/Buck/Boost

All Outputs Remain in Regulation Through Cold Crank 2.5V ≤ V ≤ 38V,

IN

Q

Synchronous DC/DC Controller

V

Up to 24V, V Up to 60V, I = 28µA

OUT(BOOST) Q

OUT(BUCKS)

3863f

LT 0313 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

For more information www.linear.com/3863

(408)432-1900 FAX: (408) 434-0507 www.linear.com/3863

●

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC3835IFE#PBF
厂家：	Linear
描述：	LTC3835 - Low IQ Synchronous Step-Down Controller; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 控制器
文件：	总36页 (文件大小：541K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3835IFE#PBF [Linear]

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