LTC3835IGN-1#PBF [Linear]
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| 型号： | LTC3835IGN-1#PBF |
| 厂家： | 
Linear |
| 描述： | 暂无描述 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 光电二极管 |
| 文件： | 总28页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3835
Low I Synchronous
Q
Step-Down Controller
FEATURES
DESCRIPTION
TheLTC®3835isahighperformancestep-downswitching
regulator controller that drives an all N-channel synchro-
nous power MOSFET stage. A constant-frequency current
mode architecture allows a phase-lockable frequency of
up to 650kHz.
n
Wide Output Voltage Range: 0.8V ≤ V ≤ 10V
IN
n
Low Operating Quiescent Current: 80μA
OPTI-LOOP® Compensation Minimizes C
n
OUT
n
1ꢀ Output Voltage Accuracy
n
Wide V Range: 4V to 36V Operation
IN
n
Phase-Lockable Fixed Frequency 140kHz to 650kHz
The 80μA no-load quiescent current extends operating
life in battery powered systems. OPTI-LOOP compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3835 features a precision 0.8V reference and a power
good output indicator. The 4V to 36V input supply range
encompasses a wide range of battery chemistries.
n
Dual N-Channel MOSFET Synchronous Drive
n
Very Low Dropout Operation: 99% Duty Cycle
n
Adjustable Output Voltage Soft-Start or Tracking
n
Output Current Foldback Limiting
n
Power Good Output Voltage Monitor
Clock Output for PolyPhase® Applications
n
n
Output Overvoltage Protection
Low Shutdown I : 10μA
n
The TRACK/SS pin ramps the output voltage during start-
up.CurrentfoldbacklimitsMOSFETheatdissipationduring
short-circuit conditions.
Q
n
n
Internal LDO Powers Gate Drive from V or V
IN
OUT
Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
Comparison of LTC3835 and LTC3835-1
CLKOUT/
n
Small 20-Lead TSSOP or 4mm × 5mm QFN Package
PART #
PHASMD
EXTV
PGOOD
PACKAGES
FE20/4 × 5 QFN
GN16/3 × 5 DFN
CC
LTC3835
LTC3835-1
YES
YES
NO
YES
APPLICATIONS
NO
NO
n
Automotive Systems
n
Telecom Systems
L, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620,
6304066, 6498466, 6580258, 6611131.
n
Battery-Operated Digital Devices
Distributed DC Power Systems
n
TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
High Efficiency Synchronous Step-Down Converter
CLKOUT
V
IN
V
IN
4V TO
36V
100000
10000
1000
100
100
90
PLLLPF
RUN
EFFICIENCY
= 12V; V = 3.3V
10μF
TG
V
IN
OUT
0.01μF
0.22μF
PGOOD
TRACK/SS
80
BOOST
SW
70
3.3μH
V
0.012Ω
OUT
I
TH
3.3V
5A
330pF
33k
60
50
LTC3835
100pF
150μF
40
30
20
10
0
SGND
INTV
EXTV
CC
CC
POWER LOSS
10
4.7μF
20k
PLLIN/MODE
V
BG
FB
1
–
SENSE
62.5k
+
0.1
SENSE
PGND
0.001 0.01 0.1
1
10 100 1000 10000
LOAD CURRENT (mA)
3835 TA01b
3835 TA01
3835fc
1
LTC3835
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (V )......................... 36V to –0.3V
Peak Output Current <10μs (TG,BG)...........................3A
IN
Top Side Driver Voltage (BOOST)............... 42V to –0.3V
Switch Voltage (SW)..................................... 36V to –5V
INTV Peak Output Current ................................. 50mA
CC
Operating Temperature Range (Note 2).... –40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range
FE Package ........................................ –65°C to 150°C
Storage Temperature Range
UFD Package ..................................... –65°C to 125°C
Lead Temperature (FE Package, Soldering, 10 sec)... 300°C
INTV , (BOOST-SW), CLKOUT, PGOOD ... 8.5V to –0.3V
CC
RUN, TRACK/SS ......................................... 7V to –0.3V
+
–
SENSE , SENSE Voltages ........................ 11V to –0.3V
PLLIN/MODE, PHASMD, PLLLPF ......... INTV to –0.3V
CC
EXTV ...................................................... 10V to –0.3V
CC
I , V Voltages ...................................... 2.7V to –0.3V
TH FB
PIN CONFIGURATION
TOP VIEW
TOP VIEW
CLKOUT
PLLLPF
1
2
20
19
18
17
16
15
14
13
12
11
PHASMD
PLLIN/MODE
PGOOD
20 19 18 17
I
3
TH
I
1
2
3
4
5
6
16 PGOOD
TH
+
TRACKS/SS
4
SENSE
+
TRACK/SS
15 SENSE
14 SENSE
13 RUN
–
V
5
21
SENSE
FB
–
V
FB
21
SGND
PGND
BG
6
RUN
BOOST
TG
SGND
PGND
BG
7
12 BOOST
11 TG
8
INTV
CC
9
SW
7
8
9 10
EXTV
CC
10
V
IN
FE PACKAGE
20-LEAD PLASTIC TSSOP
UFD PACKAGE
20-PIN (4mm s 5mm) PLASTIC QFN
T
= 125°C, θ = 35°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS SGND MUST BE SOLDERED TO PCB
T
= 125°C, θ = 37°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS SGND MUST BE SOLDERED TO PCB
3835fc
2
LTC3835
(Note 2)
ORDER INFORMATION
LEAD FREE FINISH
LTC3835EFE#PBF
LTC3835IFE#PBF
LTC3835EUFD#PBF
LTC3835IUFD#PBF
LEAD BASED FINISH
LTC3835EFE
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3835EFE#TRPBF
LTC3835IFE#TRPBF
LTC3835EUFD#TRPBF
LTC3835IUFD#TRPBF
TAPE AND REEL
LTC3835EFE
LTC3835IFE
3835
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
–40°C to 85°C
–40°C to 85°C
20-Pin (4mm × 5mm) Plastic DFN
20-Pin (4mm × 5mm) Plastic DFN
PACKAGE DESCRIPTION
3835
–40°C to 85°C
PART MARKING*
LTC3835EFE
LTC3835IFE
3835
TEMPERATURE RANGE
–40°C to 85°C
LTC3835EFE#TR
20-Lead Plastic TSSOP
LTC3835IFE
LTC3835IFE#TR
20-Lead Plastic TSSOP
–40°C to 85°C
LTC3835EUFD
LTC3835EUFD#TR
LTC3835IUFD#TR
–40°C to 85°C
20-Pin (4mm × 5mm) Plastic DFN
20-Pin (4mm × 5mm) Plastic DFN
LTC3835IUFD
3835
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Main Control Loops
l
V
Regulated Feedback Voltage
Feedback Current
(Note 4); I Voltage = 1.2V
0.792
0.800
–5
0.808
–50
V
nA
FB
TH
I
(Note 4)
VFB
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 4V to 30V (Note 4)
0.002
0.02
%/V
REFLNREG
IN
(Note 4)
Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔI Voltage = 1.2V to 2V
LOADREG
l
l
0.1
–0.1
0.5
–0.5
%
%
TH
TH
g
m
Transconductance Amplifier g
I = 1.2V; Sink/Source 5μA (Note 4)
TH
1.55
mmho
m
I
Q
Input DC Supply Current
Sleep Mode
Shutdown
(Note 5)
RUN = 5V, V = 0.83V (No Load)
80
10
125
20
μA
μA
FB
V = 0V
RUN
l
UVLO
Undervoltage Lockout
V
Ramping Down
3.5
10
4
V
%
μA
%
μA
V
IN
V
OVL
Feedback Overvoltage Lockout
Sense Pins Total Source Current
Maximum Duty Factor
Measured at V Relative to Regulated V
FB
8
12
FB
I
V
SENSE
– = V + = 0V
SENSE
–660
99.4
1.0
SENSE
DF
MAX
In Dropout
98
0.75
0.5
I
Soft-Start Charge Current
V
TRACK
= 0V
1.35
0.9
TRACK/SS
V
V
ON
RUN
SENSE(MAX)
RUN Pin ON Threshold
V
RUN
Rising
0.7
Maximum Current Sense Threshold
V
FB
V
FB
= 0.7V, V
= 0.7V, V
– = 3.3V
SENSE
– = 3.3V
SENSE
90
80
100
100
110
115
mV
mV
l
TG Transition Time:
Rise Time
Fall Time
(Note 6)
TG t
TG t
C
C
= 3300pF
50
50
90
90
ns
ns
r
f
LOAD
LOAD
= 3300pF
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG t
BG t
C
C
= 3300pF
= 3300pF
40
40
90
80
ns
ns
r
f
3835fc
3
LTC3835
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
TG/BG t
Top Gate Off to Bottom Gate On Delay C
Synchronous Switch-On Delay Time
= 3300pF
70
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay C
Top Switch-On Delay Time
= 3300pF
70
ns
ns
2D
LOAD
t
Minimum On-Time
(Note 7)
180
ON(MIN)
CC
INTV Linear Regulator
V
V
V
V
V
V
Internal V Voltage
8.5V < V < 30V, V = 0V
EXTVCC
5
5.25
0.2
7.5
0.2
4.7
0.2
5.5
1.0
7.8
1.0
V
%
V
INTVCCVIN
LDOVIN
CC
IN
INTV Load Regulation
I
CC
= 0mA to 20mA, V
= 0V
CC
EXTVCC
Internal V Voltage
V = 8.5V
EXTVCC
7.2
4.5
INTVCCEXT
LDOEXT
CC
INTV Load Regulation
I
CC
= 0mA to 20mA, V
= 8.5V
%
V
CC
EXTVCC
EXTV Switchover Voltage
EXTV Ramping Positive
CC
EXTVCC
CC
EXTV Hysteresis
V
LDOHYS
CC
Oscillator and Phase-Locked Loop
f
f
f
f
f
I
Nominal Frequency
Lowest Frequency
Highest Frequency
V
V
V
= No Connect
= 0V
360
220
475
400
250
530
115
800
440
280
580
140
kHz
kHz
kHz
kHz
kHz
NOM
PLLLPF
PLLLPF
PLLLPF
LOW
= INTV
HIGH
CC
Minimum Synchronizable Frequency PLLIN/MODE = External Clock; V
Maximum Synchronizable Frequency PLLIN/MODE = External Clock; V
Phase Detector Output Current
Sinking Capability
Sourcing Capability
= 0V
= 2V
SYNCMIN
SYNCMAX
PLLLPF
PLLLPF
650
PLLLPF
f
f
< f
OSC
> f
OSC
–5
5
μA
μA
PLLIN/MODE
PLLIN/MODE
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.1
0.3
1
V
PGL
PGOOD
I
V
μA
PGOOD
PGOOD
V
PG
V
with Respect to Set Regulated Voltage
Ramping Negative
Ramping Positive
FB
V
FB
V
FB
-12
8
–10
10
–8
12
%
%
Note 4: The LTC3835 is tested in a feedback loop that servos V to a
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
ITH
specified voltage and measures the resultant V
.
FB
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 2: The LTC3835E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3835I is guaranteed to meet
performance specifications over the full –40°C to 85°C operating
temperature range.
Note 6: Rise and fall times are measured using 10% and 90% levels.
Delay times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
Considerations in the Applications Information section).
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LTC3835FE: T = T + (P • 35°C/W)
J
A
D
LTC3835UFD: T = T + (P • 37°C/W)
J
A
D
3835fc
4
LTC3835
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25ºC, unless otherwise noted.
Efficiency and Power Loss
vs Output Current
Efficiency vs Load Current
Efficiency vs Input Voltage
10000
1000
100
10
100
90
100
90
80
70
60
50
40
98
96
94
92
90
88
86
84
82
Burst Mode OPERATION
FORCED CONTINUOUS MODE
PULSE SKIPPING MODE
V
V
V
= 12V
= 5V
OUT
IN
IN
= 3.3V
80
70
60
50
40
30
20
10
0
V
V
= 12V
IN
OUT
= 3.3V
1
V
= 3.3V
OUT
5
0.1
0.001 0.01 0.1
1
10 100 1000 10000
0.001 0.01 0.1
1
10 100 1000 10000
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3835 G01
3835 G02
3835 G03
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
V
V
OUT
OUT
V
OUT
100mV/
DIV AC
100mV/DIV
AC
100mV/DIV
AC
COUPLED
COUPLED
COUPLED
I
I
I
L
2A/DIV
L
L
2A/DIV
2A/DIV
3835 G04
3835 G06
3835 G05
20μs/DIV
20μs/DIV
20μs/DIV
FIGURE 11 CIRCUIT
OUT
FIGURE 11 CIRCUIT
OUT
FIGURE 11 CIRCUIT
OUT
V
= 3.3V
V
= 3.3V
V
= 3.3V
Inductor Current at Light Load
Soft Start-Up
Tracking Start-Up
V
OUT2
FORCED
CONTIN-
UOUS
2V/DIV (MASTER)
V
OUT
1V/DIV
V
OUT1
MODE
2V/DIV
(SLAVE)
2A/DIV
BURST
MODE
PULSE-
SKIPPING
MODE
3835 G07
3835 G09
3835 G08
4μs/DIV
20ms/DIV
FIGURE 11 CIRCUIT
20ms/DIV
FIGURE 11 CIRCUIT
FIGURE 11 CIRCUIT
V
= 3.3V
OUT
I
= 300μA
LOAD
3835fc
5
LTC3835
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25ºC, unless otherwise noted.
Total Input Supply Current
vs Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.10
5.05
5.00
350
300
250
200
150
100
50
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
INTV
CC
300μA LOAD
NO LOAD
EXTV RISING
CC
EXTV FALLING
CC
0
25
INPUT VOLTAGE (V)
35
35
5
10
15
20
30
35
TEMPERATURE (°C)
0
20
INPUT VOLTAGE (V)
30
–45
–5
15
55
75
95
5
10 15
25
40
–25
3835 G12
3835 G10
3835 G11
Maximum Current Sense Voltage
vs ITH Voltage
Sense Pins Total Input
Bias Current
Maximum Current Sense
Threshold vs Duty Cycle
100
80
200
100
120
100
PULSE SKIPPING
FORCED CONTINUOUS
BURST MODE (RISING)
BURST MODE (FALLING)
0
60
40
20
0
–100
–200
–300
–400
–500
–600
–700
80
60
40
20
0
–20
10% Duty Cycle
–40
0.8
PIN VOLTAGE (V)
1.2
1.4
0
0.2
0.4 0.6
1.0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
0
1
2
3
4
5
10
6
7
8
9
I
V
COMMON MODE VOLTAGE (V)
TH
SENSE
3835 G13
3835 G15
3835 G14
Quiescent Current
vs Temperature
SENSE Pins Total Input
Bias Current vs ITH
Foldback Current Limit
120
100
12
10
8
100
95
90
85
80
75
70
65
60
V
= 3.3V
TRACK/SS = 1V
SENSE
PLLIN/MODE = 0V
80
60
40
6
4
20
0
2
0
0
0.4
0.6 0.8 1.0 1.2
VOLTAGE (V)
1.4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FEEDBACK VOLTAGE (V)
15 30
0
TEMPERATURE (°C)
0.2
–45 –30 –15
45 60 75 90
I
TH
3835 G18
3835 G16
3835 G17
3835fc
6
LTC3835
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25ºC, unless otherwise noted.
TRACK/SS Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
808
806
804
802
800
798
796
794
792
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
3835 G20
3835 G21
3835 G19
Sense Pins Total Input Current
vs Temperature
Shutdown Current
vs Input Voltage
Oscillator Frequency
vs Temperature
25
20
15
10
5
800
700
600
500
200
100
V
V
= 10V
OUT
= 3.3V
OUT
0
V
V
= INTV
CC
–100
–200
–300
–400
–500
–600
–700
–800
PLLLPF
PLLLPF
= FLOAT
400
300
200
100
V
= GND
PLLLPF
V
= OV
OUT
0
0
5
10
15
20
25
30
35
–45
–5
15
35
55
75
95
–45 –30 –15
0
15 30 45 60 75 90
–25
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3835 G23
3835 G24
3835 G22
Undervoltage Lockout Threshold
vs Temperature
Oscillator Frequency
vs Input Voltage
Shutdown Current
vs Temperature
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
404
402
12
10
400
8
RISING
398
396
6
4
FALLING
394
392
2
0
–45
–15
0
15 30 45 60 75 90
–30
5
10
15
20
25
30
35
15 30
–45 –30 –15
0
45 60 75 90
TEMPERATURE (°C)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3835 G25
3835 G26
3835 G27
3835fc
7
LTC3835
PIN FUNCTIONS (FE Package/UFD Package)
CLKOUT (Pin 1/Pin 19): Open-Drain Output Clock Signal
available to daisychain other controller ICs for additional
MOSFET driver stages/phases.
V (Pin11/Pin9):MainSupplyPin.Abypasscapacitorshould
IN
be tied between this pin and the signal ground pin.
SW(Pin12/Pin10):SwitchNodeConnectionstoInductor.
PLLLPF (Pin 2/Pin 20): The phase-locked loop’s lowpass
VoltageswingatthispinisfromaSchottkydiode(external)
filter is tied to this pin when synchronizing to an external
voltage drop below ground to V .
IN
clock. Alternatively, tie this pin to GND, V or leave floating
IN
TG (Pin 13/Pin 11): High Current Gate Drive for Top
to select 250kHz, 530kHz or 400kHz switching frequency.
N-ChannelMOSFET.Thesearetheoutputsoffloatingdrivers
I
(Pin 3/Pin 1): Error Amplifier Outputs and Switching
withavoltageswingequaltoINTV –0.5Vsuperimposed
TH
CC
Regulator Compensation Points. The current comparator
on the switch node voltage SW.
trip point increases with this control voltage.
BOOST (Pin 14/Pin 12): Bootstrapped Supply to the Top
Side Floating Driver. A capacitor is connected between the
BOOST and SW pins and a Schottky diode is tied between
TRACK/SS (Pin 4/Pin 2): External Tracking and Soft-Start
Input.TheLTC3835regulatestheV voltagetothesmaller
FB
of 0.8V or the voltage on the TRACK/SS pin. A internal 1μA
pull-upcurrentsourceisconnectedtothispin. Acapacitor
to ground at this pin sets the ramp time to final regulated
output voltage. Alternatively, a resistor divider on another
voltage supply connected to this pin allows the LTC3835
output to track the other supply during startup.
the BOOST and INTV pins. Voltage swing at the BOOST
CC
pin is from INTV to (V + INTV ).
CC
IN
CC
RUN (Pin 15/Pin 13): Digital Run Control Input for
Controller. Forcing this pin below 0.7V shuts down all
controller functions, reducing the quiescent current that
the LTC3835 draws to approximately 10μA.
V (Pin5/Pin3):Receivestheremotelysensedfeedbackvolt-
FB
SENSE– (Pin 16/Pin 14): The (–) Input to the Differential
Current Comparator.
age from an external resistive divider across the output.
SGND (Pin 6/Pin 4): Small Signal Ground. Must be routed
separately from high current grounds to the common (–)
terminals of the input capacitor.
SENSE+ (Pin 17/Pin 15): The (+) Input to the Differential
Current Comparator. The I pin voltage and controlled
TH
offsets between the SENSE– and SENSE+ pins in conjunc-
PGND(Pin7/Pin5):DriverPowerGround.Connectstothe
tion with R
set the current trip threshold.
SENSE
sourceofbottom(synchronous)N-channelMOSFET,anode
PGOOD(Pin18/Pin16):Open-DrainLogicOutput.PGOOD
of the Schottky rectifier and the (–) terminal of C .
IN
is pulled to ground when the voltage on the V pin is not
FB
BG (Pin 8/Pin 6): High Current Gate Drive for Bottom
within 10% of its set point.
(Synchronous) N-Channel MOSFET. Voltage swing at this
PLLIN/MODE (Pin 19/Pin 17): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3835 operates at light loads.
Pulling this pin below 0.7V selects Burst Mode operation.
pin is from ground to INTV .
CC
INTV (Pin 9/Pin 7): Output of the Internal Linear Low
CC
Dropout Regulator. The driver and control circuit are
powered from this voltage source. Must be decoupled to
power ground with a minimum of 4.7μF tantalum or other
low ESR capacitor.
EXTV (Pin10/Pin8):ExternalPowerInputtoanInternalLDO
CC
Connected to INTV . This LDO supplies V power, bypass-
CC
CC
TyingthispintoINTV forcescontinuousinductorcurrent
CC
ing the internal LDO powered from V whenever EXTV is
IN
CC
operation. Tying this pin to a voltage greater than 0.9V and
higher than 4.7V. See EXTV Connection in the Applications
CC
less than INTV selects pulse-skipping operation.
CC
Information section. Do not exceed 10V on this pin.
3835fc
8
LTC3835
PIN FUNCTIONS (FE Package/UFD Package)
PHASMD(Pin20/Pin18):ControlInputtoPhaseSelector
whichdeterminesthephaserelationshipsbetweenTGand
the CLKOUT signal.
Exposed Pad (Pin 21/Pin 21): SGND. Must be soldered
to the PCB.
FUNCTIONAL DIAGRAM
PLLIN/
MODE
F
IN
PHASE DET
INTV
CC
V
IN
PHASMD
PLLLPF
D
C
B
BOOST
TG
R
LP
C
B
LP
DROP
OUT
DET
CLK
TOP
BOT
C
IN
D
OSCILLATOR
INTV
CC
BOT
TOP ON
FC
SW
S
R
Q
Q
10k
CLKOUT
PGOOD
–
+
SWITCH
LOGIC
0.88V
INTV
CC
BG
V
FB1
–
+
BURSTEN
SLEEP
C
OUT
PGND
B
0.72V
+
–
0.4V
V
OUT
SHDN
R
SENSE
L
–
+
INTV -0.5V
CC
FC
ICMP
IR
+
–
–
+ +
–
–
+
PLLIN/MODE
0.8V
+
–
+
SENSE
BURSTEN
6mV
0.45V
2(V
–
)
SENSE
FB
SLOPE
COMP
V
FB
R
B
V
FB
–
+
TRACK/SS
0.80V
EA
OV
V
IN
R
A
V
IN
+
–
+
4.7V
5.25V/
7.5V
LDO
0.88V
–
C
C
I
0.5μA
TH
EXTV
INTV
CC
R
C
C
C
C2
6V
1μA
TRACK/SS
CC
+
RUN
INTERNAL
SUPPLY
SS
SGND
SHDN
3835 FD
3835fc
9
LTC3835
(Refer to Functional Diagram)
OPERATION
Main Control Loop
close to V , the loop may enter dropout and attempt
OUT
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one twelfth of the clock period every tenth cycle to
The LTC3835 uses a constant-frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock sets the
RSlatch,andisturnedoffwhenthemaincurrentcompara-
tor, ICMP, resets the RS latch. The peak inductor current
at which ICMP trips and resets the latch is controlled by
allow C to recharge.
B
Shutdown and Start-Up (RUN and TRACK/SS Pins)
The LTC3835 can be shut down using the RUN pin. Pulling
thispinbelow0.7Vshutsdownthemaincontrolloopofthe
controller. A low disables the controller and most internal
the voltage on the I pin, which is the output of the error
TH
amplifierEA.Theerroramplifiercomparestheoutputvolt-
agefeedbacksignalattheV pin,(whichisgeneratedwith
FB
circuits, including the INTV regulator, at which time the
an external resistor divider connected across the output
CC
LTC3835 draws only 10μA of quiescent current.
voltage, V , to ground) to the internal 0.800V reference
OUT
voltage.Whentheloadcurrentincreases,itcausesaslight
Releasing the RUN pin allows an internal 0.5μA current
to pull up the pin and enable that controller. Alternatively,
the RUN pin may be externally pulled up or driven directly
by logic. Be careful not to exceed the Absolute Maximum
rating of 7V on this pin.
decrease in V relative to the reference, which cause the
FB
EA to increase the I voltage until the average inductor
TH
current matches the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFETisturnedonuntileithertheinductorcurrentstarts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
The start-up of the output voltage V
is controlled by
OUT
the voltage on the TRACK/SS pin. When the voltage on
the TRACK/SS pin is less than the 0.8V internal reference,
the LTC3835 regulates the V voltage to the TRACK/SS
FB
INTV /EXTV Power
CC
CC
pin voltage instead of the 0.8V reference. This allows
the TRACK/SS pin to be used to program a soft start by
connecting an external capacitor from the TRACK/SS pin
to SGND. An internal 1μA pull-up current charges this
capacitor creating a voltage ramp on the TRACK/SS pin.
As the TRACK/SS voltage rises linearly from 0V to 0.8V
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin.
CC
When the EXTV pin is left open or tied to a voltage less
CC
than 4.7V, an internal 5.25V low dropout linear regulator
supplies INTV power from V . If EXTV is taken above
CC
IN
CC
4.7V, the 5.25V regulator is turned off and a 7.5V low
(and beyond), the output voltage V
rises smoothly
OUT
dropout linear regulator is enabled that supplies INTV
from zero to its final value.
CC
power from EXTV . If EXTV is less than 7.5V (but
CC
CC
Alternatively the TRACK/SS pin can be used to cause the
start-upofV to“track”thatofanothersupply.Typically,
greater than 4.7V), the 7.5V regulator is in dropout and
INTV is approximately equal to EXTV . When EXTV
OUT
CC
CC
CC
this requires connecting to the TRACK/SS pin an external
resistor divider from the other supply to ground (see
Applications Information section).
is greater than 7.5V (up to an absolute maximum rating
of 10V), INTV is regulated to 7.5V. Using the EXTV
CC
CC
pin allows the INTV power to be derived from a high
CC
When the RUN pin is pulled low to disable the LTC3835, or
efficiency external source such as one of the LTC3835
when V drops below its undervoltage lockout threshold
switching regulator outputs.
IN
of 3.5V, the TRACK/SS pin is pulled low by an internal
MOSFET. When in undervoltage lockout, the controller is
disabled and the external MOSFETs are held off.
ThetopMOSFETdriverisbiasedfromthefloatingbootstrap
capacitor C , which normally recharges during each off
B
cycle through an external diode when the top MOSFET
turns off. If the input voltage V decreases to a voltage
IN
3835fc
10
LTC3835
(Refer to Functional Diagram)
OPERATION
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
(PLLIN/MODE Pin)
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
The LTC3835 can be enabled to enter high efficiency Burst
Modeoperation, constant-frequencypulse-skippingmode,
orforcedcontinuousconductionmodeatlowloadcurrents.
To select Burst Mode operation, tie the PLLIN/MODE pin
to a DC voltage below 0.8V (e.g., SGND). To select forced
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
modeorclockedbyanexternalclocksourcetousethephase-
locked loop (see Frequency Selection and Phase-Locked
Loopsection),theLTC3835operatesinPWMpulse-skipping
modeatlightloads.Inthismode,constant-frequencyopera-
tion is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
continuousoperation,tiethePLLIN/MODEpintoINTV .To
CC
selectpulse-skippingmode,tiethePLLIN/MODEpintoaDC
voltage greater than 0.8V and less than INTV – 0.5V.
comparator I
may remain tripped for several cycles and
CC
CMP
forcetheexternaltopMOSFETtostayoffforthesamenumber
of cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference as
compared to Burst Mode operation. It provides higher low
current efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation.
When the LTC3835 is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-tenth of the maximum sense voltage even though the
voltage on the I pin indicates a lower value. If the aver-
TH
age inductor current is lower than the load current, the
error amplifier EA will decrease the voltage on the I pin.
TH
When the I voltage drops below 0.4V, the internal sleep
TH
signalgoeshigh(enabling“sleep”mode)andbothexternal
MOSFETs are turned off. The I pin is then disconnected
TH
Frequency Selection and Phase-Locked Loop
(PLLLPF and PLLIN/MODE Pins)
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3835 draws to
only 80μA. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
enough, the I pin is reconnected to the output of the
TH
The switching frequency of the LTC3835’s controllers can
be selected using the PLLLPF pin.
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
If the PLLIN/MODE pin is not being driven by an external
clocksource,thePLLLPFpincanbefloated,tiedtoINTV ,
When the LTC3835 is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
CC
or tied to SGND to select 400kHz, 530kHz, or 250kHz,
respectively.
current comparator (RI
) turns off the bottom external
CMP
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative, thus
operating in discontinuous operation.
A phase-locked loop (PLL) is available on the LTC3835
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case,aseriesR-CshouldbeconnectedbetweenthePLLLPF
pinandSGNDtoserveasthePLL’sloopfilter. TheLTC3835
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of the external top MOSFET to the rising
edge of the synchronizing signal.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions.Thepeakinductorcurrentisdeterminedbythe
voltage on the I pin, just as in normal operation. In this
TH
mode, the efficiency at light loads is lower than in Burst
Mode operation. However, continuous operation has the
3835fc
11
LTC3835
(Refer to Functional Diagram)
OPERATION
Table 1
The typical capture range of the LTC3835’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee to be between 140kHz and 650kHz. In other
words, the LTC3835’s PLL is guaranteed to lock to an
externalclocksourcewhosefrequencyisbetween140kHz
and 650kHz.
V
CLKOUT PHASE
PHASMD
GND
90°
Floating
INTV
120°
180°
CC
Output Overvoltage Protection
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the V pin rises to more
than10%higherthanitsregulationpointof0.800V,thetop
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
FB
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3835 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3835 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal, as summarized in Table 1.
The phases are calculated relative to the zero degrees
phase being defined as the rising edge of the top gate
driver output (TG).
Power Good (PGOOD) Pin
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the V pin voltage is not within
FB
10%ofthe0.8Vreferencevoltage.ThePGOODpinisalso
pulled low when the RUN pin is low (shut down). When
the V pin voltage is within the 10% requirement, the
FB
MOSFET is turned off and the pin is allowed to be pulled
TheCLKOUTpinhasanopen-drainoutputdevice.Normally,
a 10k to 100k resistor can be connected from this pin to a
voltage supply that is less than or equal to 8.5V.
up by an external resistor to a source of up to 8.5V.
3835fc
12
LTC3835
APPLICATIONS INFORMATION
SENSE
R
Selection For Output Current
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
R
is chosen based on the required output current.
SENSE
The current comparator has a maximum threshold of
100mV/R
and an input common mode range of
SENSE
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current I
equal to the peak value less half the
The inductor value has a direct effect on ripple current.
MAX
peak-to-peak ripple current, ΔI .
The inductor ripple current ΔI decreases with higher
L
L
inductance or frequency and increases with higher V :
IN
Allowing a margin for variations in the IC and external
component values yields:
⎛
⎞
1
VOUT
V
IN
ΔIL =
VOUT 1–
⎜
⎟
80mV
IMAX
(f)(L)
⎝
⎠
RSENSE
=
Accepting larger values of ΔI allows the use of low in-
L
When using the controller in very low dropout conditions,
themaximumoutputcurrentlevelwillbereducedduetothe
internalcompensationrequiredtomeetstabilitycriterionfor
buckregulatorsoperatingatgreaterthan50%dutyfactor. A
curve is provided to estimate this reduction in peak output
current level depending upon the operating duty factor.
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔI =0.3(I
). The maximum ΔI occurs
L
L
MAX
at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
Operating Frequency and Synchronization
10% of the current limit determined by R
. Lower
SENSE
The choice of operating frequency, is a trade-off between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
inductor values (higher ΔI ) will cause this to occur at
L
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
The internal oscillator of the LTC3835 runs at a nominal
400kHz frequency when the PLLLPF pin is left floating
and the PLLIN/MODE pin is a DC low or high. Pulling the
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
PLLLPF to INTV selects 530kHz operation; pulling the
CC
PLLLPF to SGND selects 250kHz operation.
Alternatively, the LTC3835 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
Inductor Value Calculation
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
3835fc
13
LTC3835
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
current are given by:
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
VOUT
2
PMAIN
=
(
I
1+δ R
+
)
(
)
)
(
MAX
DS(ON)
V
IN
Power MOSFET and Schottky Diode (Optional)
Selection
I
⎛
⎝
⎞
2
MAX
2
V
R
DR )(
C
•
)
(
IN ⎜
⎟
MILLER
⎠
Two external power MOSFETs must be selected for the
LTC3835: One N-channel MOSFET for the top (main)
switch, and one N-channel MOSFET for the bottom (syn-
chronous) switch.
⎡
⎤
⎥
⎦
1
1
+
f
( )
⎢
⎣
V
INTVCC – VTHMIN VTHMIN
V – VOUT
2
IN
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
MAX
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
CC
V
IN
Thisvoltageistypically5Vduringstart-up(seeEXTV Pin
CC
Connection).Consequently,logic-levelthresholdMOSFETs
where δ is the temperature dependency of R
DR
and
DS(ON)
must be used in most applications. The only exception
R
(approximately 2Ω) is the effective driver resistance
is if low input voltage is expected (V < 5V); then, sub-
at the MOSFET’s Miller threshold voltage. V
is the
IN
GS(TH)
THMIN
logic level threshold MOSFETs (V
< 3V) should be
specification for
typical MOSFET minimum threshold voltage.
used. Pay close attention to the BV
DSS
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
the MOSFETs as well; most of the logic level MOSFETs are
limited to 30V or less.
which are highest at high input voltages. For V < 20V
IN
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
the high current efficiency generally improves with larger
resistance R
, Miller capacitance C
, input
MOSFETs, while for V > 20V the transition losses rapidly
DS(ON)
MILLER
IN
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
increasetothepointthattheuseofahigherR
device
DS(ON)
C
withlowerC
actuallyprovideshigherefficiency.The
MILLER
MILLER
usually provided on the MOSFET manufacturers’ data
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
sheet. C
is equal to the increase in gate charge
MILLER
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
DS
The term (1+δ) is generally given for a MOSFET in the
to the Gate charge curve specified V . When the IC is
DS
form of a normalized R
vs Temperature curve, but
DS(ON)
operating in continuous mode the duty cycles for the top
δ = 0.005/°C can be used as an approximation for low
and bottom MOSFETs are given by:
voltage MOSFETs.
VOUT
TheoptionalSchottkydiodeD1showninFigure6conducts
during the dead-time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
Main Switch Duty Cycle =
V
IN
V – VOUT
IN
Synchronous Switch Duty Cycle =
V
IN
could cost as much as 3% in efficiency at high V . A 1A
IN
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current.Largerdiodesresultinadditionaltransitionlosses
due to their larger junction capacitance.
3835fc
14
LTC3835
APPLICATIONS INFORMATION
C and C
Selection
To improve the frequency response, a feed-forward ca-
IN
OUT
pacitor, C , may be used. Great care should be taken to
FF
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
route the V line away from noise sources, such as the
FB
OUT
IN
inductor and the SW line.
large voltage transients, a low ESR capacitor sized for the
maximumRMScurrentmustbeused.ThemaximumRMS
capacitor current is given by:
V
OUT
R
C
FF
LTC3835
B
A
1/2
IMAX
V
FB
CIN Required IRMS
≈
V
V – V
IN OUT
(
[
OUT)(
)
]
V
R
IN
3835 F01
This formula has a maximum at V = 2V , where I
= I /2. This simple worst-case condition is commonly
IN
OUT
RMS
OUT
Figure 1. Setting Output Voltage
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3835, ceramic capacitors
canalsobeusedforCIN. Alwaysconsultthemanufacturer
if there is any question.
200
100
0
–100
–200
–300
–400
–500
–600
–700
0
1
2
3
4
5
10
6
7
8
9
The selection of C
is driven by the effective series
OUT
V
COMMON MODE VOLTAGE (V)
SENSE
resistance (ESR). Typically, once the ESR requirement
3835 F02
is satisfied, the capacitance is adequate for filtering. The
Figure 2. SENSE Pins Input Bias Current
vs Common Mode Voltage
output ripple (ΔV ) is approximated by:
OUT
⎛
⎞
1
+
–
ΔVOUT ≈IRIPPLE ESR +
SENSE and SENSE Pins
⎜
⎟
8fCOUT
⎝
⎠
The common mode input range of the current comparator
is from 0V to 10V. Continuous linear operation is provided
throughout this range allowing output voltages from 0.8V
to 10V. The input stage of the current comparator requires
thatcurrenteitherbesourcedorsunkfromtheSENSEpins
depending on the output voltage, as shown in the curve in
Figure 2. If the output voltage is below 1.5V, current will
flow out of both SENSE pins to the main output. In these
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
RIPPLE
Setting Output Voltage
The LTC3835 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 1. The regulated output voltage is
determined by:
cases, the output can be easily pre-loaded by the V
OUT
resistordividertocompensateforthecurrentcomparator’s
negative input bias current. Since V is servoed to the
FB
0.8V reference voltage, R in Figure 1 should be chosen
A
⎛
⎝
RB ⎞
RA ⎠
to be less than 0.8V/I
, with I
determined from
VOUT = 0.8V • 1+
SENSE
SENSE
⎜
⎟
Figure 2 at the specified output voltage.
3835fc
15
LTC3835
APPLICATIONS INFORMATION
Tracking and Soft-Start (TRACK/SS Pin)
according to the voltage on the TRACK/SS pin, allowing
OUT
The total soft-start time will be approximately:
V
to rise smoothly from 0V to its final regulated value.
The start-up of V
is controlled by the voltage on the
OUT
TRACK/SS pin. When the voltage on the TRACK/SS pin is
0.8V
1μA
lessthantheinternal0.8Vreference,theLTC3835regulates
tSS = CSS
•
the V pin voltage to the voltage on the TRACK/SS pin
FB
insteadof0.8V. TheTRACK/SSpincanbeusedtoprogram
Alternatively, the TRACK/SS pin can be used to track two
(or more) supplies during start-up, as shown qualitatively
in Figures 4a and 4b. To do this, a resistor divider should
an external soft-start function or to allow V
another supply during start-up.
to “track”
OUT
LTC3835
be connected from the master supply (V ) to the TRACK/
X
TRACK/SS
SS pin of the slave supply (V ), as shown in Figure 5.
OUT
C
SS
During start-up V
will track V according to the ratio
OUT
X
SGND
set by the resistor divider:
3835 F03
VX
RA
RTRACKA +RTRACKB
RA +RB
Figure 3. Using the TRACK/SS Pin to Program Soft-Start
=
•
VOUT RTRACKA
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 3.
An internal 1μA current source charges up the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
For coincident tracking (V
= V during start-up),
OUT
X
R = R
A
TRACKA
TRACKB
R = R
B
The LTC3835 will regulate the V pin (and hence V
)
FB
OUT
V (MASTER)
X
V (MASTER)
X
V
(SLAVE)
V
(SLAVE)
OUT
OUT
3835 F04B
TIME
TIME
3835 F04A
(4a) Coincident Tracking
(4b) Ratiometric Tracking
Figure 4. Two Different Modes of Output Voltage Tracking
V
V
OUT
x
LTC3835
R
B
A
V
FB
R
R
R
TRACKB
TRACK/SS
3835 F05
TRACKA
Figure 5. Using the TRACK/SS Pin for Tracking
3835fc
16
LTC3835
APPLICATIONS INFORMATION
INTVCC Regulators
EXTV remains above 4.5V. The EXTV LDO attempts
CC CC
to regulate the INTV voltage to 7.5V, so while EXTV
CC
CC
CC
CC
TheLTC3835featurestwoseparateinternalP-channellow
dropout linear regulators (LDO) that supply power at the
is less than 7.5V, the LDO is in dropout and the INTV
voltage is approximately equal to EXTV . When EXTV
CC
INTV pin from either the V supply pin or the EXTV
CC
IN
CC
is greater than 7.5V up to an absolute maximum of 10V,
INTV is regulated to 7.5V.
pin, respectively, depending on the connection of the
CC
EXTV pin. INTV powers the gate drivers and much of
CC
CC
the LTC3835’s internal circuitry. The V LDO regulates
Using the EXTV LDO allows the MOSFET driver and
IN
CC
the voltage at the INTV pin to 5.25V and the EXTV
control power to be derived from the LTC3835 switching
CC
CC
LDO regulates it to 7.5V. Each of these can supply a peak
current of 50mA and must be bypassed to ground with
a minimum of 4.7μF tantalum, 10μF special polymer, or
low ESR electrolytic capacitor. A ceramic capacitor with a
minimum value of 4.7μF can also be used if a 1Ω resistor
isaddedinserieswiththecapacitor.Nomatterwhattypeof
bulkcapacitorisused, anadditional1μFceramiccapacitor
regulator output (4.7V ≤ V
≤ 10V) during normal
OUT
operation and from the V LDO when the output is out
IN
of regulation (e.g., startup, short-circuit). If more cur-rent
is required through the EXTV LDO than is specified, an
CC
external Schottky diode can be added between the EXTV
CC
CC
andINTV pins.Donotapplymorethan10VtotheEXTV
CC
pin and make sure than EXTV ≤ V .
CC
IN
placed directly adjacent to the INTV and PGND IC pins is
CC
Significant efficiency and thermal gains can be realized
by powering INTV from the output, since the V cur-
highlyrecommended.Goodbypassingisneededtosupply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
CC
IN
rent resulting from the driver and control currents will be
scaledbyafactorof(DutyCycle)/(SwitcherEfficiency).For
4.7V to 10V regulator outputs, this means connecting the
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junctiontemperatureratingfortheLTC3835tobeexceeded.
EXTV pin directly to V . Tying the EXTV pin to a 5V
CC
OUT
CC
supply reduces the junction temperature in the previous
The INTV current, which is dominated by the gate charge
example from 125°C to:
CC
current, may be supplied by either the 5V V LDO or the
IN
T = 70°C + (24mA)(5V)(95°C/W) = 81°C
J
7.5V EXTV LDO. When the voltage on the EXTV pin is
CC
CC
However, for 3.3V and other low voltage outputs, addi-
less than 4.7V, the V LDO is enabled. Power dissipation
IN
tional circuitry is required to derive INTV power from
for the IC in this case is highest and is equal to V • I
.
CC
IN INTVCC
the output.
Thegatechargecurrentisdependentonoperatingfrequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
The following list summarizes the four possible connec-
tions for EXTV :
CC
1. EXTV Left Open (or Grounded). This will cause
CC
For example, the LTC3835 INTV current is limited to less
CC
INTV to be powered from the internal 5.25V regulator
CC
than 41mA from a 24V supply when in the G package and
resulting in an efficiency penalty of up to 10% at high
not using the EXTV supply:
CC
input voltages.
T = 70°C + (41mA)(36V)(95°C/W) = 125°C
J
2. EXTV Connected Directly to V . This is the normal
CC
OUT
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
connection for a 5V regulator and provides the highest
efficiency.
3. EXTV Connected to an External supply. If an external
CC
= INTV ) at maximum V .
CC
IN
supply is available in the 5V to 7V range, it may be used
When the voltage applied to EXTV rises above 4.7V, the
CC
to power EXTV providing it is compatible with the
CC
V LDO is turned off and the EXTV LDO is enabled. The
IN
CC
MOSFET gate drive requirements.
EXTV LDO remains on as long as the voltage applied to
CC
3835fc
17
LTC3835
APPLICATIONS INFORMATION
4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.
Fault Conditions: Current Limit and Current Foldback
CC
For 3.3V and other low voltage regulators, efficiency
The LTC3835 includes current foldback to help limit load
current when the output is shorted to ground. If the output
falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
100mV to 30mV. Under short-circuit conditions with very
low duty cycles, the LTC3835 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple cur-
gains can still be realized by connecting EXTV to an
CC
output-derivedvoltagethathasbeenboostedtogreater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 6.
V
IN
1μF
+
C
IN
0.22μF
BAT85
BAT85
BAT85
V
rent is determined by the minimum on-time t
of the
IN
ON(MIN)
LTC3835
LTC3835 (≈180ns), the input voltage and inductor value:
VN2222LL
TG1
SW
R
ΔI = t (V /L)
SENSE
L(SC)
ON(MIN) IN
N-CH
V
OUT
L1
EXTV
CC
The resulting short-circuit current is:
+
10mV
RSENSE
1
2
C
BG1
OUT
ISC
=
– ΔIL(SC)
N-CH
PGND
Fault Conditions: Overvoltage Protection (Crowbar)
3835 F06
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
muchhigherthannominallevels.Thecrowbarcauseshuge
currents to flow, that blow the fuse to protect against a
shortedtopMOSFETiftheshortoccurswhilethecontroller
is operating.
Figure 6. Capacitive Charge Pump for EXTVCC
Topside MOSFET Driver Supply (C , D )
B
B
External bootstrap capacitors C connected to the BOOST
B
pinssupplythegatedrivevoltagesforthetopsideMOSFET.
Capacitor C in the Functional Diagram is charged
B
A comparator monitors the output for overvoltage
conditions.Thecomparator(OV)detectsovervoltagefaults
greaterthan10%abovethenominaloutputvoltage. When
this condition is sensed, the top MOSFET is turned off and
the bottom MOSFET is turned on until the overvoltage
condition is cleared. The bottom MOSFET remains on
continuously for as long as the overvoltage condition
though external diode D from INTV when the SW pin
B
CC
is low. When the topside MOSFET is to be turned on,
the driver places the C voltage across the gate-source
B
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to V and the BOOST pin follows. With the topside
IN
MOSFET on, the boost voltage is above the input supply:
persists; if V
returns to a safe level, normal operation
OUT
V
= V + V
. The value of the boost capacitor
BOOST
B
IN
INTVCC
automaticallyresumes.AshortedtopMOSFETwillresultin
a high current condition which will open the system fuse.
The switching regulator will regulate properly with a leaky
top MOSFET by altering the duty cycle to accommodate
the leakage.
C needstobe100timesthatofthetotalinputcapacitance
of the topside MOSFET. The reverse breakdown of the
external Schottky diode must be greater than V
.
IN(MAX)
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
3835fc
18
LTC3835
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
than f , current is sunk continuously, pulling down
OSC
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
The LTC3835 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the top MOSFET (TG)
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
the filter capacitor C holds the voltage.
LP
The loop filter components, C and R , smooth out the
LP
LP
current pulses from the phase detector and provide a stable
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
external filter network connected to the PLLLPF pin. The
relationship between the voltage on the PLLLPF pin and
operating frequency, when there is a clock signal applied
to PLLIN/MODE, is shown in Figure 7 and specified in the
Electrical Characteristics table. Note that the LTC3835 can
onlybesynchronizedtoanexternalclockwhosefrequency
is within range of the LTC3835’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 8.
input to the voltage-controlled oscillator. The filter compo-
nents C and R determine how fast the loop acquires
LP
LP
lock. Typically R = 10k and C is 2200pF to 0.01μF.
LP
LP
Typically,theexternalclock(onPLLIN/MODEpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
PLLIN/MODE PIN
DC Voltage
FREQUENCY
250kHz
400kHz
Floating
DC Voltage
If the external clock frequency is greater than the internal
INTV
DC Voltage
530kHz
CC
oscillator’s frequency, f , then current is sourced con-
OSC
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
2.4V
900
800
700
600
500
400
300
200
100
0
R
LP
C
LP
PLLLPF
PLLIN/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
OSCILLATOR
3835 F08
0
0.5
1
1.5
2
2.5
PLLLPF PIN VOLTAGE (V)
Figure 8. Phase-Locked Loop Block Diagram
3835 F07
Figure 7. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
3835fc
19
LTC3835
APPLICATIONS INFORMATION
Minimum On-Time Considerations
1. The V current has two components: the first is the
IN
DCsupplycurrentgivenintheElectricalCharacteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
Minimum on-time t
is the smallest time duration
ON(MIN)
that the LTC3835 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
linear regulator output. V current typically results in
IN
a small (< 0.1%) loss.
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ
VOUT
tON(MIN)
<
V (f)
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
moves from INTV to ground. The resulting dQ/dt is
CC
a current out of INTV that is typically much larger
CC
than the control circuit current. In continuous mode,
I
= f(Q +Q ), where Q and Q are the gate
GATECHG
T B T B
The minimum on-time for the LTC3835 is approximately
180ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
200ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
charges of the topside and bottom side MOSFETs.
Supplying INTV power through the EXTV switch
CC
CC
input from an output-derived source will scale the VIN
current required for the driver and control circuits by
a factor of (Duty Cycle)/(Efficiency). For example, in a
20V to 5V application, 10mA of INTV current results
CC
inapproximately2.5mAofV current.Thisreducesthe
IN
mid-current loss from 10% or more (if the driver was
powered directly from V ) to only a few percent.
Efficiency Considerations
IN
2
3. I R losses are predicted from the DC resistances of the
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
fuse(ifused), MOSFET, inductor, currentsenseresistor,
and input and output capacitor ESR. In continuous
mode the average output current flows through L and
R
, but is “chopped” between the topside MOSFET
SENSE
andthesynchronousMOSFET.IfthetwoMOSFETshave
approximately the same R
, then the resistance
DS(ON)
%Efficiency = 100% – (L1 + L2 + L3 + ...)
of one MOSFET can simply be summed with the
2
where L1, L2, etc. are the individual losses as a percent-
age of input power.
resistances of L, R
and ESR to obtain I R losses.
SENSE
For example, if each R
= 30mΩ, R = 50mΩ,
= 40mΩ (sum of both input
DS(ON)
L
R
SENSE
= 10mΩ and R
ESR
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
andoutputcapacitancelosses),thenthetotalresistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
losses in LTC3835 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
3835fc
20
LTC3835
APPLICATIONS INFORMATION
a 5V output, or a 4% to 20% loss for a 3.3V output.
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
capacitance and ESR values. The availability of the I pin
TH
not only allows optimization of control loop behavior but
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
4. TransitionlossesapplyonlytothetopsideMOSFET, and
become significant only when operating at high input
voltages (typically 15V or greater). Transition losses
can be estimated from:
pin. The I external components shown in the Typical
TH
Transition Loss = (1.7) V 2 I
C
f
Application circuit will provide an adequate starting point
IN O(MAX) RSS
for most applications.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
The I series RC-CC filter sets the dominant pole-zero
TH
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
C
IN
has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance hav-
ing a maximum of 20mΩ to 50mΩ of ESR. Other losses
including Schottky conduction losses during dead-time
and inductor core losses generally account for less than
2% total additional loss.
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by
OUT
why it is better to look at the I pin signal which is in the
an amount equal to ΔI
(ESR), where ESR is the ef-
TH
LOAD
feedback loop and is the filtered and compensated control
fective series resistance of C . ΔI
also begins to
OUT
LOAD
loop response. The gain of the loop will be increased
charge or discharge C
generating the feedback error
OUT
by increasing R and the bandwidth of the loop will be
signal that forces the regulator to adapt to the current
C
increased by decreasing C . If R is increased by the same
change and return V
this recovery time V
to its steady-state value. During
can be monitored for excessive
C
C
OUT
OUT
factor that C is decreased, the zero frequency will be kept
C
the same, thereby keeping the phase shift the same in the
overshoot or ringing, which would indicate a stability
3835fc
21
LTC3835
APPLICATIONS INFORMATION
The R
resistor value can be calculated by using the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
SENSE
maximum current sense voltage specification with some
accommodation for tolerances:
80mV
RSENSE
≤
≈ 0.012Ω
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
5.84A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
= 0.035Ω/0.022Ω, C
= 215pF. At
DS(ON)
MILLER
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
maximum input voltage with T(estimated) = 50°C:
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10μF capacitor would
1.8V
22V
2
LOAD
PMAIN
=
5
( )
1+ (0.005)(50°C – 25°C) •
[
]
require a 250μs rise time, limiting the charging current
to about 200mA.
5A
2
⎛
⎞
2
0.035Ω + 22V
) (
4Ω 215pF •
)(
(
)
(
)
⎜
⎝
⎟
⎠
Design Example
1
1
⎡
⎤
+
300kHz = 332mW
(
)
As a design example, assume V = 12V(nominal), V =
⎢
⎣
⎥
⎦
IN
IN
5 – 2.3 2.3
22V(max), V
= 1.8V, I
= 5A, and f = 250kHz.
OUT
MAX
A short-circuit to ground will result in a folded back
current of:
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
⎛
⎞
25mV 1 120ns(22V)
ISC
=
–
= 2.1A
⎜
⎟
⎠
0.01Ω 2⎝ 3.3μH
with a typical value of R
and δ = (0.005/°C)(20) = 0.1.
DS(ON)
⎛
⎞
VOUT
(f)(L)
VOUT
The resulting power dissipated in the bottom MOSFET is:
ΔIL =
1–
⎜
⎝
⎟
⎠
V
IN
22V – 1.8V
2
PSYNC
=
2.1A 1.125 0.022Ω
(
) (
)(
)
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3μH value. Increasing the ripple current will
also help ensure that the minimum on-time of 180ns is not
22V
= 100mW
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
IN
violated. The minimum on-time occurs at maxi-mum V :
IN
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VOUT
1.8V
tON(MIN)
=
=
= 327ns
VIN(MAX)f 22V(250kHz)
V
= R (ΔI ) = 0.02Ω(1.67A) = 33mV
ESR L P–P
ORIPPLE
3835fc
22
LTC3835
APPLICATIONS INFORMATION
PC Board Layout Checklist
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 9. The Figure 10 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
thecurrentintheinductorwhiletestingthecircuit.Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance
over the operating voltage and current range expected
in the application. The frequency of operation should be
maintained over the input voltage range down to dropout
and until the output load drops below the low current
operation threshold—typically 10% of the maximum
designed current level in Burst Mode operation.
1. Is the top N-channel MOSFET M1 located within 1cm
of C ?
IN
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
must return to the combined C
(–) ter-
INTVCC
OUT
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the C capacitor should have short
IN
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
3. Does the LTC3835 V pin resistive divider connect to the
FB
(+) terminals of C ? The resistive divider must be con-
OUT
nectedbetweenthe(+)terminalofC andsignalground.
OUT
Thefeedbackresistorconnectionsshouldnotbealongthe
high current input feeds from the input capacitor(s).
–
+
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
5. Is the INTV decoupling capacitor connected close to
CC
theIC, betweentheINTV andthepowergroundpins?
CC
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1μFceramiccapacitorplacedimmediately
next to the INTV and PGND pins can help improve
CC
noise performance substantially.
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes.Allofthesenodeshaveverylargeandfastmoving
signalsandthereforeshouldbekeptonthe“outputside”
of the LTC3835 and occupy minimum PC trace area.
for inductive coupling between C , Schottky and the top
IN
3835fc
23
LTC3835
APPLICATIONS INFORMATION
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
V
IN
C1
1nF
C
B
C
IN
M1
M2
L1
V
OUT
D1
OPTIONAL
C
OUT
D
B
3835 F09
Figure 9. LTC3835 Recommended Printed Circuit Layout Diagram
L1
R
SENSE
SW
V
V
IN
OUT
R
IN
C
IN
D1
C
R
L1
OUT
3835 F10
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
Figure 10. Branch Current Waveforms
3835fc
24
LTC3835
TYPICAL APPLICATIONS
High Efficiency 9.5V, 3A Step-Down Converter
INTV
CC
100k
100k
V
IN
CLKOUT
PLLLPF
RUN
V
IN
4V TO 36V
C
10μF
IN
M1
TG
C
B
0.01μF
0.22μF
PGOOD
TRACK/SS
BOOST
SW
7.2μH
V
0.012Ω
OUT
I
TH
9.5V
3A
560pF
LTC3835
D
B
100pF
35k
CMDSH-3
C
OUT
150μF
SGND
PLLIN/MODE
INTV
EXTV
CC
CC
4.7μF
39.2k
432k
M2
V
BG
FB
–
+
SENSE
SENSE
PGND
3835 TA02
High Efficiency 12V to 1.8V, 2A Step-Down Converter
V
12V
IN
CLKOUT
PLLLPF
RUN
V
IN
C
10μF
IN
M1
TG
C
B
0.01μF
0.22μF
PGOOD
TRACK/SS
L1
BOOST
SW
V
3.3μH
20mΩ
OUT
I
TH
1.8V
2A
3300pF
LTC3835
D
B
100pF
2.49k
CMDSH-3
C
OUT
100μF
CERAMIC
SGND
PLLIN/MODE
INTV
EXTV
CC
CC
4.7μF
169k
M2
V
BG
FB
–
+
SENSE
SENSE
215k
PGND
100pF
3835 TA03
M1, M2: Si4840DY
L1: TOKO DS3LC A915AY-3R3M
3835fc
25
LTC3835
TYPICAL APPLICATIONS
High Efficiency 5V, 5A Step-Down Converter
V
IN
CLKOUT
PLLLPF
RUN
V
4V TO
36V
IN
C
10μF
IN
M1
TG
C
B
0.01μF
0.22μF
PGOOD
TRACK/SS
BOOST
SW
V
3.3μH
0.012Ω
OUT
I
TH
5V
5A
470pF
LTC3835
D
B
100pF
10k
CMDSH-3
C
OUT
150μF
SGND
PLLIN/MODE
INTV
EXTV
CC
CC
4.7μF
69.8k
M2
V
BG
FB
–
+
SENSE
SENSE
365k
PGND
High Efficiency 1.2V, 5A Step-Down Converter
INTV
V
IN
CC
CLKOUT
PLLLPF
RUN
V
IN
4V TO
36V
GND
C
10μF
IN
10k
M1
TG
C
B
0.01μF
0.22μF
PGOOD
TRACK/SS
BOOST
SW
V
2.2μH
0.012Ω
OUT
I
TH
1.2V
5A
2.2nF
LTC3835
D
B
100pF
10k
CMDSH-3
C
OUT
150μF
SGND
PLLIN/MODE
INTV
EXTV
CC
CC
4.7μF
118k
M2
V
BG
FB
–
+
SENSE
SENSE
59k
PGND
3835 TA05
3835fc
26
LTC3835
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 p 0.10
2.74
(.108)
4.50 p 0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 p 0.05
1.05 p 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
UFD Package
20-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
0.75 p 0.05
1.50 REF
19
4.00 p 0.10
(2 SIDES)
R = 0.05 TYP
20
0.70 p0.05
0.40 p 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2.65 p 0.05
3.65 p 0.05
2
4.50 p 0.05
3.10 p 0.05
1.50 REF
5.00 p 0.10
(2 SIDES)
2.50 REF
3.65 p 0.10
2.65 p 0.10
PACKAGE
OUTLINE
0.25 p0.05
0.50 BSC
2.50 REF
(UFD20) QFN 0506 REV
B
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.200 REF
0.00 – 0.05
R = 0.115
TYP
4.10 p 0.05
5.50 p 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3835fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3835
TYPICAL APPLICATION
V
IN
CLKOUT
PLLLPF
RUN
V
IN
4V TO
36V
C
10μF
IN
M1
TG
C
B
0.01μF
0.22μF
PGOOD
TRACK/SS
L1
3.3μH
BOOST
SW
V
0.012Ω
OUT
I
TH
3.3V
5A
1200pF
LTC3835
D
B
100pF
10k
CMDSH-3
C
OUT
SGND
PLLIN/MODE
INTV
CC
150μF
4.7μF
68.1k
EXTV
CC
M2
V
BG
FB
–
+
SENSE
SENSE
215k
PGND
39pF
3835 TA06
M1, M2: Si7848DP
L1: CDEP105-3R2M
C
: SANYO 10TPD150M
Figure 11. High Efficiency Step-Down Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1628/
LTC1628-PG/
LTC1628-SYNC
2-Phase, Dual Output Synchronous Step-Down
DC/DC Controller
Reduces C and C , Power Good Output Signal, Synchronizable,
IN
OUT
OUT
3.5V ≤ V ≤ 36V, I
Up to 20A, 0.8V ≤ V
≤ 5
OUT
IN
LTC1629/
LTC1629-PG
20A to 200A PolyPhase Synchronous Controllers
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, No Heatsink, V Up to 36V
IN
LTC1708-PG
2-Phase, Dual Synchronous Controller with Mobile VID
3.5V ≤ V ≤ 36V, VID Sets V
, PGOOD
OUT1
IN
LT1709/
LT1709-8
High Efficiency, 2-Phase Synchronous Step-Down Switching
Regulators with 5-Bit VID
1.3V ≤ V
≤ 3.5V, Current Mode Ensures Accurate Current
OUT
Sharing, 3.5V ≤ V ≤ 36V
IN
LTC1735
LTC1736
High Efficiency Synchronous Step-Down Switching Regulator
Output Fault Protection, 16-Pin SSOP
High Efficiency Synchronous Controller with 5-Bit Mobile
VID Control
Output Fault Protection, 24-Pin SSOP, 3.5V ≤ V ≤ 36V
IN
LTC1778/
LTC1778-1
No R
Current Mode Synchronous Step-Down Controllers Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
I
Up to 20A
OUT
LTC3708
LTC3711
Dual, 2-Phase, DC/DC Controller with Output Tracking
Current Mode, No R
, Up/Down Tracking, Synchronizable
SENSE
®
No R
Current Mode Synchronous Step-Down Controller
Up to 97% Efficiency, Ideal for Pentium III Processors,
SENSE
with Digital 5-Bit Interface
0.925V ≤ V
≤ 2V, 4V ≤ V ≤ 36V, I
Up to 20A
OUT
OUT
IN
LTC3728
LTC3729
LTC3731
Dual, 550kHz, 2-Phase Synchronous Step-Down Controller
Dual 180° Phased Controllers, V 3.5V to 35V, 99% Duty Cycle,
IN
5x5QFN, SSOP-28
20A to 200A, 550kHz PolyPhase Synchronous Controller
3- to 12-Phase Step-Down Synchronous Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, V Up to 36V
IN
60A to 240A Output Current, 0.6V ≤ V
≤ 6V, 4.5V ≤ V ≤ 32V
IN
OUT
LTC3827/
LTC3827-1
Low I Dual Synchronous Controller
2-Phase Operation; 115μA Total No Load IQ, 4V ≤ V ≤ 36V
IN
80μA No Load I with One Channel On
Q
Q
No R
is a trademark of Linear Technology Corporation.
SENSE
3835fc
LT 0508 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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