LTC3855EUJ#TRPBF [Linear]
LTC3855 - Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C;
| 型号： | LTC3855EUJ#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3855 - Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C 控制器 |
| 文件： | 总36页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3866
Current Mode Synchronous
Controller for Sub Milliohm
DCR Sensing
FeaTures
DescripTion
n
Sub Milliohm DCR Current Sensing
TheLTC®3866isasinglephasecurrentmodesynchronous
step-down switching regulator controller that drives all
N-channel power MOSFET switches. It employs a unique
architecture which enhances the signal-to-noise ratio of
the current sense signal, allowing the use of a very low
DC resistance power inductor to maximize the efficiency
in high current applications. This feature also reduces the
switching jitter commonly found in low DCR applications.
TheLTC3866alsoincludesahighspeedremotesensedif-
ferentialamplifier,aprogrammablecurrentsense limitthat
can be selected to 10mV, 15mV, 20mV, 25mV or 30mV,
andDCRtemperaturecompensationtolimitthemaximum
output current precisely over temperature.
n
High Efficiency: Up to 95%
n
Selectable Current Sensing Limit
n
Programmable DCR Temperature Compensation
n
Die Overtemperature Thermal Shutdown
n
ꢀ05% ꢀ0.6 Output 6oltage Accuracy
n
Programmable Fixed Frequency 25ꢀkHz to 77ꢀkHz
n
High Speed Differential Remote Sense Amplifier
n
Wide Input Voltage Range: 4.5V to 38V
n
Output Voltage Range: 0.6V to 3.5V with Diffamp
n
Adjustable Soft-Start or Output Voltage Tracking
n
Foldback Output Current Limit
n
Short-Circuit Soft Recovery
n
Output Overvoltage Protection
The LTC3866 also features a precise 0.6V reference with a
guaranteedlimitof 0.5%thatprovidesanaccurateoutput
voltage from 0.6V to 3.5V. A 4.5V to 38V input voltage
range allows it to support a wide variety of bus voltages
and various types of batteries.
n
24-Lead (4mm × 4mm) QFN and 24-Lead FE Packages
applicaTions
n
Computer Systems
The LTC3866 is offered in a low profile 24-lead 4mm ×
4mm QFN and 24-lead exposed pad FE packages.
n
Telecom Systems
n
Industrial and Medical Instruments
DC Power Distribution Systems
n
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
registered trademarks and No R
is a trademark of Linear Technology Corporation. All other
SENSE
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending.
Typical applicaTion
High Efficiency, 1056/3ꢀA Step-Down Converter with 6ery Low DCR Sensing
Efficiency vs Load Current
and Mode
100k
V
IN
4.5V TO 20V
FREQ MODE/PLLIN
100
90
80
70
60
50
40
30
20
10
0
220µF
0.1µF
RUN
TK/SS
ITH
PGOOD
ITEMP
4.7µF
0.1µF
EXTV
CC
LTC3866
V
V
IN
FB
INTV
DIFFOUT
DIFFP
CC
BOOST
TG
0.33µH
DCR = 0.32mΩ
V
V
= 12V
IN
OUT
30.1k
20k
DIFFN
= 1.5V
V
1.5V
30A
OUT
+
L = 0.33µH
SW
SNSD
C1
(DCR = 0.32mΩ TYP)
–
C
BG
OUT
220pF
SNS
220nF
CCM
470µF
R1
4.64k
R2
931Ω
+
10k
PGND
SNSA
ILIM
PULSE SKIPPING
Burst Mode
OPERATION
×2
C2
220nF
CLKOUT
1.5nF
SGND
0.01
0.1
1
10
100
LOAD CURRENT (A)
3866 TA01b
3866 TA01a
3866fa
1
LTC3866
absoluTe MaxiMuM raTings (Note 1)
Input Supply Voltage.................................. –0.3V to 40V
Topside Driver Voltage (BOOST)................ –0.3V to 46V
Switch Voltage(SW) ..................................... –5V to 40V
DIFFP, DIFFN .........................................–0.3V to INTV
CC
CC
ITEMP, ITH, V Voltages ....................–0.3V to INTV
FB
INTV Peak Output Current ..............................100mA
Operating Junction Temperature Range
(Notes 2, 4)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
CC
INTV , EXTV , RUN, PGOOD,
CC
CC
BOOST-SW Voltages .................................... –0.3V to 6V
+
+
–
SNSD , SNSA , SNS Voltages.............–0.3V to INTV
MODE/PLLIN, ILIM, TK/SS, FREQ,
CC
DIFFOUT Voltages.................................–0.3V to INTV
FE Package .......................................................300°C
CC
pin conFiguraTion
TOP VIEW
TOP VIEW
1
2
MODE/PLLIN
PGOOD
24
23
22
21
20
19
18
17
16
15
14
13
FREQ
RUN
3
ITEMP
TK/SS
ITH
24 23 22 21 20 19
4
EXTV
CC
ITH
1
2
3
4
5
6
18 EXTV
CC
5
V
V
FB
IN
V
FB
V
IN
17
16
6
INTV
CC
DIFFOUT
DIFFN
25
SGND
DIFFOUT
DIFFN
INTV
CC
25
SGND
7
BOOST
TG
15 BOOST
TG
8
DIFFP
DIFFP
14
13 SW
+
9
SW
SNSD
+
SNSD
–
10
11
12
BG
SNS
7
8
9 10 11 12
+
PGND
CLKOUT
SNSA
ILIM
FE PACKAGE
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
= 47°C/W, θ = 4.5°C/W
24-LEAD PLASTIC TSSOP
θ
= 33°C/W, θ = 10°C/W
JA
JC
θ
JA
JC
EXPOSED PAD (PIN 25) IS SGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 25) IS SGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3866EFE#PBF
LTC3866IFE#PBF
LTC3866EUF#PBF
LTC3866IUF#PBF
TAPE AND REEL
PART MARKING*
LTC3866FE
LTC3866FE
3866
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3866EFE#TRPBF
LTC3866IFE#TRPBF
LTC3866EUF#TRPBF
LTC3866IUF#TRPBF
24-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
24-Lead Plastic TSSOP
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
3866
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3866fa
2
LTC3866
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2)0 6IN = 156, 6RUN = 56 unless otherwise specified0
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
V
V
V
Input Voltage Range
4.5
0.6
38
V
V
IN
Output Voltage Range
Regulated Feedback Voltage
with Diffamp in Loop
3.5
OUT
FB
Current ITH Voltage = 1.2V (Note 5)
–40°C to 85°C
l
l
0.597
0.5955
0.6
0.6
0.603
0.6045
V
V
–40°C to 125°C
I
Feedback Current
(Note 5)
–15
–50
nA
%
FB
V
Reference Voltage Line
Regulation
V
IN
= 4.5V to 38V (Note 5)
0.002
0.02
REFLNREG
V
Output Voltage Load
Regulation
(Note 5)
LOADREG
l
l
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V
0.01
0.01
0.1
0.1
%
%
g
Error Amplifier (EA)
Transconductance
ITH =1.2V, Sink/Source 5µA (Note 5)
2
mmho
m
I
Input DC Supply Current
Normal Mode
Shutdown
(Note 6)
Q
V
V
= 15V
3.2
30
mA
µA
IN
IN
= 15V, V
= 0V
50
RUN
UVLO
UVLO
Undervoltage Lockout
V
Ramping Down
3.4
3.75
0.5
0.66
30
4.1
V
V
INTVCC
UVLO Hysteresis Voltage
HYS
l
l
l
V
Feedback Overvoltage Lockout Measured at V
0.64
0.68
100
2
V
FBOVL
FB
+
I
I
+
SNSD Pin Bias Current
V
V
+ = 3.3V
nA
µA
V/V
SNSD
SNSD
+
+
SNSA Pin Bias Current
+ = 3.3V
+ + V
1
SNSA
SNSA
A
Total Sense Signal Gain to
Current Comparator
(V
+)/V +
SNSD
5
VT_SNS
SNSD
SNSA
V
Maximum Current Sense
Threshold
–40°C to 85°C
– = 1.8V, ILIM = 0V
SENSE(MAX)
l
l
l
l
l
V
9.2
10
15
20
25
30
10.8
15.8
20.8
26.5
31.5
mV
mV
mV
mV
mV
SNS
ILIM = 1/4 V
ILIM = 1/2 V
ILIM = 3/4 V
14.2
19.2
23.5
28.5
INTVCC
INTVCC
INTVCC
or Float
ILIM = V
INTVCC
–40°C to 125°C
– = 1.8V, ILIM = 0V
l
l
l
l
l
V
9
10
15
20
25
30
11
16
21
26.5
31.5
mV
mV
mV
mV
mV
SNS
ILIM = 1/4V
ILIM = 1/2V
ILIM = 3/4V
14
INTVCC
INTVCC
INTVCC
or Float
19
23.5
28.5
ILIM = V
INTVCC
l
I
I
DCR Temperature
V
= 0.3V
ITEMP
9
10
11
µA
TEMP
TK/SS
Compensation Current
l
l
Soft-Start Charge Current
V
TK/SS
= 0V
1.0
1.1
1.25
1.22
80
1.5
µA
V
V
V
RUN Pin On Threshold Voltage V
Rising
1.35
RUN
RUN
RUN Pin On Hysteresis
Voltage
mV
RUN(HYS)
TG
BG
Top Gate (TG) Transition Time
t
t
Rise Time
Fall Time
(Note 7)
r
f
C
C
= 3300pF
= 3300pF
25
25
ns
ns
LOAD
LOAD
Bottom Gate (BG) Transition
t
r
t
f
Time
(Note 7)
Rise Time
Fall Time
C
LOAD
C
LOAD
= 3300pF
= 3300pF
25
25
ns
ns
3866fa
3
LTC3866
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2)0 6IN = 156, 6RUN = 56 unless otherwise specified0
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TG/BG t
Top Gate Off to Bottom Gate
On Delay, Synchronous
Switch-On Delay Time
C
= 3300pF
= 3300pF
30
ns
D
D
LOAD
LOAD
BG/TG t
Bottom Gate Off to Top Gate
On Delay, Top Switch-On
Delay Time
C
30
90
ns
ns
t
Minimum On-Time
(Note 8)
ON(MIN)
INT6 Linear Regulator
CC
V
Internal V Voltage
6V < V < 38V
5.25
4.5
5.5
0.5
4.7
5.75
2
V
%
V
INTVCC
CC
IN
Load Regulation
I
= 0mA to 20mA
INTVCC
V
External V Switchover
EXTV Ramping Positive
CC
EXTVCC
CC
Voltage
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
50
100
mV
mV
CC
EXTVCC
EXTV Hysteresis
200
CC
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
V
FREQ
V
FREQ
V
FREQ
= 1.2V
= 0.4V
> 2.4V
450
225
700
500
250
770
250
10
550
275
850
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
Lowest Frequency
Highest Frequency
R
MODE/PLLIN Input Resistance
Frequency Setting Current
MODE/PLLIN
FREQ
I
9
11
µA
CLKOUT
Phase Relative to the
Oscillator Clock
180
Deg
CLKOUT
CLKOUT
Clock Output High Voltage
Clock Output Low Voltage
V
= 5.5V
4.5
5.5
0
V
V
HI
INTVCC
0.2
LO
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip
I
= 2mA
= 5.5V
0.1
0.3
2
V
PGDLO
PGD
PGOOD
I
V
V
µA
PGOOD
V
PGD
with Respect to Set Output Voltage
FB
V
V
Going Negative
Going Positive
–10
10
%
%
FB
FB
Differential Amplifier
l
l
A
Gain
–40°C to 85°C
–40°C to 125°C
0.999
0.998
1
1
1.001
1.002
V/V
V/V
V
R
Input Resistance
Measured at DIFFP Input
80
kΩ
mV
dB
IN
V
Input Offset Voltage
V
DIFFP
= 1.5V, V
DIFFOUT
= 100µA
2
OS
PSRR
Power Supply Rejection Ratio 5V < V < 38V
90
3
IN
I
Maximum Sourcing Output
Current
1.5
mA
OUT
V
Maximum Output Voltage
Gain-Bandwidth Product
Slew Rate
V
= 5.5V, I
= 300µA
V
– 1.4 V – 1.1
INTVCC
V
MHz
V/µs
OUT
INTVCC
DIFFOUT
INTVCC
GBW
SR
(Note 9)
(Note 9)
3
2
3866fa
4
LTC3866
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C (Note 2)0 6IN = 156, 6RUN = 56 unless otherwise specified0
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
On-Chip Driver
TG R
TG R
BG R
BG R
TG Pull-Up R
TG High
TG Low
BG High
BG Low
2.6
1.5
2.4
1.1
Ω
Ω
Ω
Ω
UP
DS(ON)
TG Pull-Down R
DOWN
UP
DS(ON)
BG Pull-Up R
DS(ON)
BG Pull-Down R
DOWN
DS(ON)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the absolute maximum operating junction
temperature may impair device reliability or permanently damage the
device.
Note 2: The LTC3866 is tested under pulsed load conditions such that
T ≈ T . The LTC3866E is guaranteed to meet performance specifications
J
A
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3866I is guaranteed to meet performance specifications over the
full –40°C to 125°C operating junction temperature range. The maximum
ambient temperature consistent with these specifications is determined
by specific operating conditions in conjunction with board layout, the
package thermal impedance and other environmental factors.
Note 5: The LTC3866 is tested in a feedback loop that servos V to a
ITH
specified voltage and measures the resultant V
.
FB
Note .: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 8: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
Note 3: The junction temperature, T , is calculated from the ambient
J
Considerations in the Applications Information section).
Note 9: Guaranteed by design.
temperature, T , and power dissipation, P , according to the following
A
D
formula:
LTC3866FE: T = T + (P • 33°C/W)
J
A
D
LTC3866UF: T = T + (P • 47°C/W)
J
A
D
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted0
Efficiency vs Load Current
and Mode
Efficiency vs Load Current
and Mode
Efficiency and Power Loss
vs Load Current
100
90
80
70
60
50
40
30
20
10
0
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
15
10
5
100
90
80
70
60
50
40
30
20
10
0
V
V
= 20V
IN
OUT
= 1.5V
FRONT PAGE CIRCUIT
EFFICIENCY
V
V
= 12V
V
V
= 4.5V
IN
OUT
IN
OUT
= 1.5V
= 1.5V
L = 0.33µH
L = 0.33µH
(DCR = 0.32mΩ TYP)
FRONT PAGE CIRCUIT
(DCR = 0.32mΩ TYP)
FRONT PAGE CIRCUIT
CCM
POWER LOSS
CCM
PULSE SKIPPING
Burst Mode
OPERATION
PULSE SKIPPING
Burst Mode
OPERATION
0
20
LOAD CURRENT (A)
0
5
10
15
25
30
35
0.01
0.1
1
10
100
0.01
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
3866 G01
3866 G02
3866 G03
3866fa
5
LTC3866
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted0
Load Step
Load Step
(Continuous Conduction Mode)
Load Step
(Pulse-Skipping Mode)
(Burst Mode® Operation)
I
I
I
LOAD
LOAD
LOAD
10A/DIV
10A/DIV
10A/DIV
1.5A TO 15A
1.5A TO 15A
1.5A TO 15A
0A
0A
0A
I
I
I
L
L
L
10A/DIV
0A
10A/DIV
0A
10A/DIV
0A
V
V
V
OUT
OUT
OUT
100mV/DIV
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
AC-COUPLED
3866 G04
3866 G05
3866 G06
V
V
= 12V
20µs/DIV
V
V
= 12V
20µs/DIV
V
V
= 12V
20µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.5V
= 1.5V
= 1.5V
FRONT PAGE CIRCUIT
FRONT PAGE CIRCUIT
FRONT PAGE CIRCUIT
Tracking Up and Down with
TK/SS External Ramp
Inductor Current at Light Load
Prebiased Output at 1026
V
TK/SS
V
OUT
CONTINUOUS
V
TK/SS
500mV/DIV
CONDUCTION
MODE 5A/DIV
0A
0.2V/DIV
V
OUT
Burst Mode
OPERATION
5A/DIV
V
OUT
0V
0.5V/DIV
TRACK/SS 500mV/DIV
0A
0A
V
FB
0V
500mV/DIV
0V
PULSE-SKIPPING
MODE
5A/DIV
3866 G08
3866 G09
3866 G07
V
V
= 12V
500µs/DIV
V
V
= 12V
2.5ms/DIV
V
V
LOAD
= 12V
10µs/DIV
IN
OUT
IN
OUT
IN
= 1.5V
= 1.5V
= 1.5V
OUT
1Ω LOAD
I
= 300mA
Current Sense Threshold
vs ITH 6oltage
Maximum Current Sense Threshold
vs Common Mode 6oltage
INT6CC Line Regulation
40
35
30
25
20
15
10
5
6
5
4
3
2
1
0
40
35
30
25
20
15
10
5
I
I
I
I
I
= 0V
LIM
LIM
LIM
LIM
LIM
= 1/4 INTV
= 1/2 INTV
= 3/4 INTV
CC
CC
CC
I
= INTV
CC
LIM
= INTV
CC
I
I
I
= 3/4 INTV
= 1/2 INTV
= 1/4 INTV
LIM
LIM
LIM
CC
CC
CC
I
= 0V
LIM
0
–5
–10
0
25 30
INPUT VOLTAGE (V)
0
5
10 15 20
35 40
1.75
2.0
2.0 2.5
COMMON MODE VOLTAGE (V)
0
1.0
1.5
0
0.5 1.0 1.5
3.0 3.5 4.0
0.25 0.5 0.75
1.25
V
(V)
V
ITH
SENSE
3866 G10
3866 G11
3866 G12
3866fa
6
LTC3866
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted0
Maximum Current Sense
Threshold 6oltage vs Feedback
6oltage (Current Foldback)
Shutdown (RUN) Threshold
vs Temperature
TK/SS Pull-Up Current
vs Temperature
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
40
35
30
25
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I
= INTV
CC
LIM
I
I
= 3/4 INTV
= 1/2 INTV
= 1/4 INTV
LIM
CC
CC
CC
ON
LIM
20
15
OFF
I
LIM
I
= 0V
LIM
10
5
0
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
0.1
0.2
0.4
50 75
TEMPERATURE (°C)
0
0.5
0.6
–50 –25
0.3
0
25
100 125
150
FEEDBACK VOLTAGE (V)
3866 G16
3866 G14
3866 G15
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Input 6oltage
Regulated Feedback 6oltage
vs Temperature
601.5
601.0
600.5
600.0
599.5
599.0
598.5
600
575
550
525
500
475
450
425
400
900
800
700
600
500
400
300
200
100
0
V
= 1.2V
FREQ
V
= 2.5V
FREQ
V
= 1.2V
= 0V
FREQ
V
FREQ
75 100
–50 –25
0
25 50
125 150
50 75
25
TEMPERATURE (°C)
20 25
–50 –25
0
100 125 150
0
5
10 15
30 35 40
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3866 G17
3866 G18
3866 G19
Undervoltage Lockout Threshold
(INT6CC) vs Temperature
Shutdown Current
vs Input 6oltage
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
100
90
80
70
60
50
40
30
20
10
0
RISE
FALL
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
35
0
30
5
10 15
20
INPUT VOLTAGE (V)
25
40
3866 G20
3866 G21
3866fa
7
LTC3866
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted0
Input Quiescent Current
vs Input 6oltage without EXT6CC
Quiescent Current vs Temperature
without EXT6CC
Shutdown Current vs Temperature
4.00
3.75
3.50
3.25
50
45
40
35
30
25
20
15
10
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
3.00
2.75
2.50
25
INPUT VOLTAGE (V)
35
40
50 75
TEMPERATURE (°C)
5
10
15
20
30
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
–50 –25
0
25
100 125 150
3866 G23
3866 G22
3866 G24
pin FuncTions
(FE/UF)
FREQ (Pin 1/Pin 22): Oscillator Frequency Control Input.
A 10µA current source flows out of this pin. Connecting
a resistor between this pin and ground sets a DC voltage
which in turn programs the oscillator frequency. Alterna-
tively, this pin can be driven with a DC voltage to vary the
frequency of the internal oscillator.
DIFFN (Pin 7/Pin 4): Negative Input of Remote Sensing
Differential Amplifier. Connect this pin close to the ground
of the output load.
DIFFP (Pin 8/Pin 5): Positive Input of Remote Sensing
Differential Amplifier. Connect this pin close to the output
load.
RUN (Pin 2/Pin 23): Run Control Input. A voltage above
1.22V turns on the IC. Pulling this pin below 1.14V causes
the IC to shut down. There is a 1μA pull-up current for the
pin. Once the RUN pin rises above 1.22V, an additional
4.5μA pull-up current is added to the pin.
+
SNSD (Pin 9/Pin .): First Positive Current Sense Input.
This pin is connected to sense the signal of the output
inductor’s DCR, it is to be used with a filter that matches
the bandwidth, L/DCR, of the inductor.
–
SNS (Pin 1ꢀ/Pin 7): Negative Current Sense Input. This
negativeinputofthecurrentcomparatoristobeconnected
to the output.
TK/SS (Pin 3/Pin 24): Output Voltage Tracking and Soft-
StartInput.Aninternalsoft-startcurrentof1.25μAcharges
the external soft-start capacitor connected to this pin.
+
SNSA (Pin 11/Pin 8): Second Positive Current Sense
ITH (Pin 4/Pin 1): Current Control Threshold and Error
AmplifierCompensationPin. Thecurrentcomparatortrip-
ping threshold is proportional with this voltage.
Input. This input is to be connected to sense the signal of
the output’s inductor DCR with a filter bandwidth of five
times larger than L/DCR.
6
FB
(Pin 5/Pin 2): Error Amplifier Feedback Input. This
ILIM (Pin 12/Pin 9): Current Comparator Sense Voltage
Limit. Apply a DC voltage to set the maximum current
sense threshold for the current comparator.
pin receives the remotely sensed feedback voltage to set
the output voltage through an external resistive divider
connected to the DIFFOUT pin or the output.
CLKOUT (Pin 13/Pin 1ꢀ): Clock Output Pin. The CLKOUT
signal is 180° out of phase to the rising edge of the IC
internal clock.
DIFFOUT (Pin ./Pin 3): Output of Remote Sensing Differ-
entialAmplifier. ConnectthispintoV througharesistive
FB
divider to set the desired output voltage.
3866fa
8
LTC3866
pin FuncTions (FE/UF)
PGND (Pin 14/Pin 11): Power Ground. Connect to the
EXT6 (Pin 21/Pin 18): External Supply Voltage Input.
CC
source of the bottom N-channel MOSFET and the negative
Whenever an external voltage supply greater than 4.7V
is connected to this pin, an internal switch will close and
bypasstheinternallowdropoutregulator,andtheexternal
supply will power the IC. Do not exceed 6V on this pin and
terminals of the V and INTV decoupling capacitors
IN
CC
close to this pin.
BG (Pin 15/Pin 12): Bottom Gate Driver Output. This pin
ensure V > V
at all times.
IN
EXTVCC
drives the gate of the bottom N-channel MOSFET and
swings between INTV or EXTV and PGND.
ITEMP (Pin 22/Pin 19): Temperature DCR Compensation
Input. Connect to a NTC (negative tempco) resistor placed
neartheoutputinductortocompensateforitsDCRchange
CC
CC
SW (Pin 1./Pin 13): Switch Node Connection. Connect
this pin to the output filter inductor, bottom N-channel
MOSFETdrainandtopN-channelMOSFETsource.Voltage
swing at these pins is from a Schottky diode (external)
over temperature. Floating this pin or tying it to INTV
CC
disables the DCR temperature compensation function.
voltage drop below ground to V .
PGOOD (Pin 23/Pin 2ꢀ): Power Good Indicator Output.
Open-drain logic out that is pulled to ground when the
output exceeds the 10% regulation window, after the
internal 20μs power bad mask timer expires.
IN
TG (Pin 17/Pin 14): Top Gate Driver Output. This is a float-
ing driver to be connected to the gate of the top N-channel
MOSFET. The voltage swing of this pin equals to INTV
superimposed over the switch node (SW) voltage.
CC
MODE/PLLIN (Pin24/Pin 21): Mode Operation or External
Clock Synchronization. Connect this pin to SGND to set
BOOST (Pin 18/Pin 15): Boosted Top Gate Driver Supply.
The (+) terminal of the booststrap capacitor connects to
this pin. This pins swings from a diode voltage drop below
the continuous mode of operation. Connect to INTV to
CC
enable pulse-skipping mode of operation. Leaving the pin
floating will enable Burst Mode operation. A clock signal
applied to the pin will force the controller into continuous
modeofoperationandsynchronizestheinternaloscillator.
INTV up to V + INTV .
CC
IN
CC
INT6 (Pin 19/Pin 1.): Internal 5.5V Regulator Output.
CC
Theinternalcontrolcircuitsarepoweredfromthisvoltage.
Decouple this pin to PGND with a 4.7μF low ESR tantalum
or ceramic capacitor.
SGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Sig-
nal Ground. This is the ground of the controller. Connect
compensation components and output setting resistors
to this ground. The exposed pad must be soldered to the
PCB ground plane.
6 (Pin 2ꢀ/Pin 17): Main Input Supply. Decouple this pin
IN
to PGND with a capacitor (0.1μF to 1μF). For applications
where the main input power is 5V, tie the V and INTV
IN
CC
pins together.
3866fa
9
LTC3866
FuncTional block DiagraM
EXTV
CC
ITEMP
MODE/PLLIN
4.7V
FREQ
+
–
TEMPSNS
F
V
IN
0.6V
MODE/SYNC
DETECT
V
IN
+
5.5V
REG
C
+
IN
–
INTV
CC
F
PLL-SYNC
BOOST
TG
BURST EN
C
B
CLKOUT
FCNT
OSC
M1
SW
S
R
ON
Q
V
OUT
+
SNSA
D
B
SWITCH
LOGIC
AND
ANTISHOOT-
THROUGH
–
+
–
SNS
I
I
REV
COMP
+
–
+
BG
RUN
OV
C
OUT
M2
C
PGND
PGOOD
VCC
ILIM
SLOPE
COMPENSATION
+
–
0.54V
INTV
CC
UVLO
UV
OV
R2
R1
V
FB
1
+
SNSD
R
ACTIVE CLAMP
I
+
–
THB
AMP
V
OUT
+
–
SLEEP
40k
40k
0.66V
SGND
+
–
DIFFOUT
V
IN
– SS
– RUN
+
+
DIFFP
DIFFAMP
1.25µA
EA
0.6V
REF
–
–
+ +
+
0.5V
1.22V
DIFFN
40k
40k
0.55V
1µA/5.5µA
3866 BD
C
C1
C
TK/SS
ITH
RUN
SS
R
C
3866fa
10
LTC3866
operaTion
Main Control Loop
+
constant, R1C1, of the SNSD should match the L/DCR
+
of the output inductor, while the filter at SNSA should
have a bandwidth of five times larger than SNSD , R2C2
TheLTC3866usesLTC proprietarycurrentsensing,current
modestep-downarchitecture.Duringnormaloperation,the
top MOSFET is turned on every cycle when the oscillator
sets the RS latch, and turned off when the main current
+
equals R1C1/5.
INT6 /EXT6 Power
CC
CC
comparator, I
, resets the RS latch. The peak inductor
CMP
CMP
Power for the top and bottom MOSFET drivers and most
current at which I
resets the RS latch is controlled
other internal circuitry is derived from the INTV pin.
by the voltage on the ITH pin, which is the output of the
error amplifier, EA. The remote sense amplifier (diffamp)
produces a signal equal to the differential voltage sensed
across the output capacitor divided down by the feedback
dividerandre-referencesittothelocalICgroundreference.
CC
When the EXTV pin is left open or tied to a voltage
CC
less than 4.7V, an internal 5.5V linear regulator supplies
INTV power from V . If EXTV is taken above 4.7V,
CC
IN
CC
the 5.5V regulator is turned off and an internal switch is
turnedonconnectingEXTV toINTV .UsingtheEXTV
CC
The V pin receives this feedback signal and compares
CC
CC
FB
pin allows the INTV power to be derived from a high
it to the internal 0.6V reference. When the load current
CC
efficiency external source such as a switching regulator
increases, itcausesaslightdecreaseintheV pinvoltage
FB
output. The top MOSFET driver is biased from the floating
relative to the 0.6V reference, which in turn causes the
ITHvoltagetoincreaseuntiltheinductor’saveragecurrent
equals the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
bootstrap capacitor, C , which normally recharges dur-
B
ing the off cycle through an external diode when the top
MOSFET turns off. If the input voltage, V , decreases to
IN
a voltage close to V , the loop may enter dropout and
OUT
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period plus 100ns
reverse current comparator, I , or the beginning of the
next cycle.
REV
The main control loop is shut down by pulling the RUN
pin low. Releasing RUN allows an internal 1.0µA current
source to pull up the RUN pin. When the RUN pin reaches
1.22V, the main control loop is enabled and the IC is
powered up. When the RUN pin is low, all functions are
kept in a controlled state.
every third cycle to allow C to recharge. However, it is
B
recommended that a load be present or the IC operates
at low frequency during the dropout transition to ensure
C is recharged.
B
Internal Soft-Start
By default, the start-up of the output voltage is normally
controlled by an internal soft-start ramp. The internal
soft-start ramp connects to the noninverting input of the
error amplifier. The FB pin is regulated to the lower of the
error amplifier’s three noninverting inputs (the internal
soft-start ramp, the TK/SS pin or the internal 600mV ref-
erence). As the ramp voltage rises from 0V to 0.6V over
approximately 600µs, the output voltage rises smoothly
from its prebiased value to its final set value.
Sensing Signal of 6ery Low DCR
The LTC3866 employs a unique architecture to enhance
the signal-to-noise ratio that enables it to operate with a
small sense signal of a very low value inductor DCR, 1mΩ
or less, to improve power efficiency, and reduce jitter due
to the switching noise which could corrupt the signal. The
LTC3866 can sense a DCR value as low as 0.2mΩ with
careful PCB layout.The LTC3866 comprises two positive
+
+
sense pins, SNSD and SNSA , to acquire signals and
processes them internally to provide the response as
with a DCR sense signal that has a 14dB signal-to-noise
ratio improvement. In the meantime, the current limit
threshold is still a function of the inductor peak current
and its DCR value, and can be accurately set from 10mV
to 30mV in a 5mV steps with the ILIM pin. The filter time
Certain applications can result in the start-up of the con-
verter into a non-zero load voltage, where residual charge
is stored on the output capacitor at the onset of converter
switching. Inordertopreventtheoutputfromdischarging
under these conditions, the bottom MOSFET is disabled
until soft-start is greater than V .
FB
3866fa
11
LTC3866
operaTion
Shutdown and Start-Up (RUN and TK/SS Pins)
the load current, the error amplifier, EA, will decrease the
voltage on the ITH pin. When the ITH voltage drops below
0.5V, the internal sleep signal goes high (enabling “sleep”
mode) and both external MOSFETs are turned off.
TheLTC3866canbeshutdownusingtheRUNpin. Pulling
theRUNpinbelow1.14Vshutsdownthemaincontrolloop
for the controller and most internal circuits, including the
In sleep mode, the load current is supplied by the output
capacitor.Astheoutputvoltagedecreases,theEA’soutput
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller
is enabled for Burst Mode operation, the inductor current
is not allowed to reverse. The reverse current comparator
INTV regulator.ReleasingtheRUNpinallowsaninternal
CC
1.0µA current to pull up the pin and enable the controller.
Alternatively, the RUN pin may be externally pulled up
or driven directly by logic. Be careful not to exceed the
absolute maximum rating of 6V on this pin. The start-up
of the controller’s output voltage, V , is controlled by
OUT
the voltage on the TK/SS pin, if the internal soft-start
has expired. When the voltage on the TK/SS pin is less
than the 0.6V internal reference, the LTC3866 regulates
(I ) turns off the bottom external MOSFET just before
REV
the inductor current reaches zero, preventing it from re-
versing and going negative. Thus, the controller operates
in discontinuous operation.
the V voltage to the TK/SS pin voltage instead of the
FB
0.6V reference. This allows the TK/SS pin to be used to
program a soft-start by connecting an external capacitor
from the TK/SS pin to SGND. An internal 1.25µA pull-up
current charges this capacitor, creating a voltage ramp on
the TK/SS pin. As the TK/SS voltage rises linearly from
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
BurstModeoperation.However,continuousmodehasthe
advantages of lower output ripple and less interference
with audio circuitry.
0V to 0.6V (and beyond), the output voltage, V , rises
OUT
smoothly from zero to its final value. Alternatively, the
TK/SSpincanbeusedtocausethestart-upofV totrack
OUT
that of another supply. Typically, this requires connect-
ing to the TK/SS pin an external resistor divider from the
other supply to ground (see the Applications Information
section). When the RUN pin is pulled low to disable the
When the MODE/PLLIN pin is connected to INTV , the
CC
LTC3866 operates in PWM pulse skipping mode at light
controller, or when INTV drops below its undervoltage
CC
loads. At very light loads, the current comparator, I
,
CMP
lockout threshold of 3.75V, the TK/SS pin is pulled low by
an internal MOSFET. When in undervoltage lockout, the
controllerisdisabledandtheexternalMOSFETsareheldoff.
mayremaintrippedforseveralcyclesandforcetheexternal
topMOSFETtostayoffforthesamenumberofcycles(i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuousoperation, exhibitslowoutputrippleaswellas
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
efficiency than forced continuous mode, but not nearly as
high as Burst Mode operation.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Continuous Conduction)
The LTC3866 can be enabled to enter high efficiency Burst
Modeoperation,constant-frequencypulse-skippingmode
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to SGND.
To select pulse-skipping mode of operation, tie the MODE/
Frequency Selection and Phase-Locked Loop
(FREQ and MODE/PLLIN Pins)
PLLIN pin to INTV . To select Burst Mode operation, float
CC
the MODE/PLLIN pin. When the controller is enabled for
Burst Mode operation, the peak current in the inductor
is set to approximately one-third of the maximum sense
voltage even though the voltage on the ITH pin indicates a
lower value. If the average inductor current is higher than
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
3866fa
12
LTC3866
operaTion
If the MODE/PLLIN pin is not being driven by an external
clock source, the FREQ pin can be used to program the
controller’s operating frequency from 250kHz to 770kHz.
There is a precision 10µA current flowing out of the FREQ
pin so that the user can program the controller’s switch-
ing frequency with a single resistor to SGND. A curve
is provided later in the Applications Information section
showing the relationship between the voltage on the FREQ
pin and switching frequency.
TheLTC3866differentialamplifierhasatypicaloutputslew
rate of 2V/µs. The amplifier is configured for unity gain,
meaning that the difference between DIFFP and DIFFN is
translated to DIFFOUT, relative to SGND.
Care should be taken to route the DIFFP and DIFFN PCB
tracesparalleltoeachotherallthewaytotheremotesens-
ing points on the board. In addition, avoid routing these
sensitive traces near any high speed switching nodes in
the circuit. Ideally, the DIFFP and DIFFN traces should be
shielded by a low impedance ground plane to maintain
signal integrity.
A phase-locked loop (PLL) is available on the LTC3866
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The PLL
loop filter network is integrated inside the LTC3866. The
phase-locked loop is capable of locking any frequency
withintherangeof250kHzto770kHz.Thefrequencysetting
resistor should always be present to set the controller’s
initial switching frequency before locking to the external
clock. The controller operates in forced continuous mode
when it is synchronized.
Power Good (PGOOD Pin)
The PGOOD pin is connected to the open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the V pin voltage is not
FB
within 10% of the 0.6V reference voltage. The PGOOD
pin is also pulled low when the RUN pin is below 1.14V or
whentheLTC3866isinthesoft-startortrackingupphase.
When the V pin voltage is within the 10% regulation
FB
Sensing the Output 6oltage with a
Differential Amplifier
window, the MOSFET is turned off and the pin is allowed
to be pulled up by an external resistor to a source of up
to 6V. The PGOOD pin will flag power good immediately
The LTC3866 includes a low offset, high input impedance,
unity-gain, high bandwidth differential amplifier for ap-
plications that require true remote sensing. Sensing the
load across the load capacitors directly greatly benefits
regulation in high current, low voltage applications, where
board interconnection losses can be a significant portion
ofthetotalerrorbudget. ConnectDIFFPtotheoutputload,
and DIFFN to the load ground. See Figure 1.
whentheV piniswithintheregulationwindow.However,
FB
there is an internal 20µs power-bad mask when the V
FB
goes out of the window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
topMOSFETisturnedoffandthebottomMOSFETisturned
on until the overvoltage condition is cleared.
V
LTC3866
DIFFOUT
OUT
DIFFP
DIFFN
8
7
+
C
OUT
6
5
DIFFAMP
Undervoltage Lockout
–
V
FB
The LTC3866 has two functions that help protect the
controller in case of undervoltage conditions. A precision
3866 F01
Figure 10 Differential Amplifier Connection
UVLOcomparatorconstantlymonitorstheINTV voltage
CC
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV is below
CC
3.75V. To prevent oscillation when there is a disturbance
on the INTV , the UVLO comparator has 600mV of preci-
CC
sion hysteresis.
3866fa
13
LTC3866
operaTion
Another way to detect an undervoltage condition is to
the RUN pin voltage passes 1.22V. The RUN comparator
itself has about 80mV of hysteresis. One can program
additional hysteresis for the RUN comparator by adjust-
monitor the V supply. Because the RUN pin has a preci-
IN
sion turn-on reference of 1.22V, one can use a resistor
divider to V to turn on the IC when V is high enough.
ing the values of the resistive divider. For accurate V
IN
IN
IN
An extra 4.5µA of current flows out of the RUN pin once
undervoltagedetection,V needstobehigherthan4.75V.
IN
applicaTions inForMaTion
The Typical Application on the first page of this data sheet
is a basic LTC3866 application circuit. The LTC3866 is
designed and optimized for use with a very low DCR
value by utilizing a novel approach to reduce the noise
sensitivity of the sensing signal by a factor of 14dB. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, as the
DCR value drops below 1mΩ, the signal-to-noise ratio
is low and current sensing is difficult. LTC3866 uses an
LTC proprietary technique to solve this issue. In general,
externalcomponentselectionisdrivenbytheloadrequire-
ment, and begins with the DCR and inductor value. Next,
power MOSFETs are selected. Finally, input and output
capacitors are selected.
isforSNSA+, SNS– andSNSD+ whentheinternaldifferen-
tial amplifier is used to remotely sense the output. All the
positivesensepinsthatareconnectedtothecurrentcom-
paratorortheamplifierarehighimpedancewithinputbias
currents of less than 1µA, but there is also a resistance of
about300kfromtheSNS– pintoground.TheSNS– should
be connected directly to VOUT. The SNSD+ pin connects
to the filter that has a R1C1 time constant matched to
L/DCR of the inductor. The SNSA+ pin is connected to the
secondfilterwiththetimeconstantone-fifththatofR1C1.
Care must be taken not to float these pins during normal
operation. Filtercomponents, especiallycapacitors, must
beplacedclosetotheLTC3866,andthesenselinesshould
run close together to a Kelvin connection underneath the
current sense element (Figure 2). Because the LTC3866
is designed to be used with a very low DCR value to
sense inductor current, without proper care, the parasitic
resistance, capacitance and inductance will degrade the
current sense signal integrity, making the programmed
currentlimitunpredictable.AsshowninFigure3,resistors
R1 and R2 are placed close to the output inductor and
capacitors C1 and C2 are close to the IC pins to prevent
noise coupling to the sense signal.
Current Limit Programming
The ILIM pin is a 5-level logic input which sets the maxi-
mum current limit of the controller. When ILIM is either
grounded, floated or tied to INTV , the typical value for
CC
the maximum current sense threshold will be 10mV,
20mV or 30mV, respectively. Setting ILIM to one-fourth
INTV and three-fourths INTV for maximum current
CC
CC
sense thresholds of 15mV and 25mV.
Which setting should be used? For the best current limit
accuracy, use the highest setting that is applicable to the
output requirements.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
3866 F02
+
+
–
SNSD , SNSA and SNS Pins
INDUCTOR
+
–
The SNSA and SNS pins are the inputs to the current
comparators,whiletheSNSD+pinistheinputofaninternal
amplifier. The operating input voltage range of 0V to 3.5V
Figure 20 Sense Lines Placement with Inductor DCR
3866fa
14
LTC3866
applicaTions inForMaTion
V
V
IN
IN
INTV
CC
INDUCTOR
BOOST
TG
LTC3866
L
DCR
V
SW
OUT
R
ITEMP
R
ITEMP
BG
PGND
R1 R2
S
22.6k
+
SNSD
C1
C2
–
SNS
R
R
+
NTC
P
SNSA
100k
90.9k
SGND
PLACE C1, C2 NEXT TO IC
3866 F03
PLACE R1, R2 NEXT TO INDUCTOR
R1C1 = 5 • R2C2
Figure 30 Inductor DCR Current Sensing
The LTC3866 could also be used like any typical current
of the sense pin filters to output inductor characteristics
as depicted below.
+
mode controller by disabling the SNSD pin, shorting it
to ground. An R
resistor or a RC filter can be used
SENSE
V
SENSE(MAX)
to sense the output inductor signal and connects to the
DCR =
∆I
+
L
SNSA pin. If the RC filter is used, its time constant,
I
+
MAX
2
R • C, is equaled to L/DCR of the output inductor. In these
applications, the current limit, V
, will be five
SENSE (MAX)
L/DCR = R1• C1 = 5 • R2 • C2
where:
times larger for the specified ILIM, and the operating
+
–
voltage range of SNSA and SNS is from 0V to 5.25V.
Withoutusingtheinternaldifferentialamplifier, theoutput
voltage of 5V can be generated as shown in the Typical
Applications section.
V
: Maximum sense voltage for a given ILIM
SENSE(MAX)
threshold
I
: Maximum load current
MAX
Inductor DCR Sensing
∆I : Inductor ripple current
L
The LTC3866 is specifically designed for high load current
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
sub milliohm range (Figure 3). The DCR is the DC winding
resistanceoftheinductor’scopper,whichisoftenlessthan
1mΩ for high current inductors. In high current and low
output voltage applications, a conduction loss of a high
DCR or a sense resistor will cause a significant reduction
in power efficiency. For a specific output requirement,
chose the inductor with the DCR that satisfies the maxi-
mum desirable sense voltage, and uses the relationship
L, DCR: Output inductor characteristics
+
R1, C1: Filter time constant of the SNSD pin
+
R2, C2: Filter time constant of the SNSA pin
To ensurethattheloadcurrentwillbedeliveredoverthefull
operatingtemperaturerange,thetemperaturecoefficientof
DCR resistance, approximately 0.4%/°C, should be taken
into account. The LTC3866 features a DCR temperature
compensationcircuitthatusesanNTCtemperaturesensing
resistor for this purpose. See the Inductor DCR Sensing
Temperature Compensation section for details.
3866fa
15
LTC3866
applicaTions inForMaTion
The following guideline will help to choose components
for temperature correction. The initial compensation is for
25°C ambient temperature:
Typically, C1 and C2 are selected in the range of 0.047µF
to 0.47µF. If C1 and C2 are chosen to be 220nF, and an
inductor of 330nH with 0.32mΩ DCR is selected, R1 and
R2 will be 4.7k and 942Ω respectively. The bias current at
ITEMP • R
= 0.7V for 25°C
ITEMP
+
+
SNSD and SNSA is about 30nA and 500nA respectively,
and it causes some small error to the sense signal.
R
is a thermistor resistance network connected to
ITEMP
ITEMP pin.
There will be some power loss in R1 and R2 that relates to
the duty cycle, and will be the most in continuous mode
at the maximum input voltage:
Since ITEMP = 10µA, choose R
25°C
network = 70kΩ at
ITEMP
TC
= –(1.5/0.7) • TC
DCR
RITEMP
V
IN(MAX) – VOUT • V
(
)
OUT
P
R =
LOSS ( )
Typically TC
= 4000ppm/°C, tempco of DCR which is
DCR
R
usually Copper. For ideal compensation, the tempco of
EnsurethatR1andR2haveapowerratinghigherthanthis
value. However, DCR sensing eliminates the conduction
loss of a sense resistor; it will provide a better efficiency
at heavy loads. To maintain a good signal-to-noise ratio
for the current sense signal, using a minimum ∆V
2mV for duty cycles less than 40% is desirable. The actual
ripplevoltagewillbedeterminedbythefollowingequation:
the R
should be:
ITEMP
TC
= –(1.5/0.7) • 4000 ppm/°C = –8570 ppm/°C
RITEMP
For example, a Murata NTC thermistor of 100k with B =
4334 that has a nonlinear temperature characteristic as
described in R[T] = R[T0] • EXP B (1/T – 1/T0) where T0
is the temperature at 300°K. Resistors R and R of 22.6k
of
SENSE
S
P
and 90.9k respectively are used to linearize the network
as shown in Figure 4.The current limit threshold will be
compensated from 25°C to over 100°C of the inductor
temperature,Figure5.Oncethetemperaturecompensation
is done, it will remain valid for all programmable current
sense limit scales.
VOUT V – V
IN
OUT
∆VSENSE
=
•
V
R1C1• fOSC
IN
Inductor DCR Sensing Temperature Compensation
with NTC Thermistor
For DCR sensing applications, the temperature coefficient
of the inductor winding resistance should be taken into
account when the accuracy of the current limit is critical
over a wide range of temperature. The main element used
in inductors is Copper; that has a positive tempco of ap-
proximately4000ppm/°C.TheLTC3866providesafeature
to correct for this variation through the use of the ITEMP
pin. There is a 10µA precision current source flowing out
of the ITEMP pin. A thermistor with a NTC (negative tem-
perature coefficient) resistance can be used in a network,
10000
THERMISTOR RESISTANCE
R
= 100k
= 25°C
O
O
1000
100
10
T
B = 4334 FOR 25°C TO 100°C
R
S
P
ITEMP
R
R
= 22.6k
= 90.9k
100k NTC
R
(Figure 3) connected to maintain the current limit
ITEMP
1
threshold constant over a wide operating temperature.
The ITEMP voltage range that activates the correction is
from 0.7V or less. If floating this pin, its voltage will be at
–50 –25
0
25 50 75 100 125 150
INDUCTOR TEMPERATURE (°C)
3866 F04
INTV potential, about 5.5V. When the ITEMP voltage is
CC
Figure 40 Resistance 6ersus Temperature for the ITEMP Pin
Network and the 1ꢀꢀk NTC
higherthan0.7V,thetemperaturecompensationisinactive.
3866fa
16
LTC3866
applicaTions inForMaTion
50
than TK/SS or the internal soft-start voltage, the error amp
output is railed low. The control loop would like to turn
BG on, which would discharge the output. Disabling BG
and TG prevents the pre-biased output voltage from being
discharged. When TK/SS and the internal soft-start both
45
40
CORRECTED
35
30
25
20
15
10
5
I
MAX
R
:
ITEMP
S
P
cross 500mV or V , whichever is lower, TG and BG are
FB
R
= 22.6k
= 90.9k
UNCORRECTED
R
enabled. If the pre-bias is higher than the OV threshold,
thebottomgateisturnedonimmediatelytopulltheoutput
back into the regulation window.
I
MAX
NTC THERMISTOR:
R
T
= 100k
= 25°C
O
O
B = 4334
NOMINAL I
= 30A
MAX
0
50
INDUCTOR TEMPERATURE (°C)
–50 –25
0
25
75 100 125 150
Overcurrent Fault Recovery
3866 F05
When the output of the power supply is loaded beyond
its preset current limit, the regulated output voltage
will collapse depending on the load. The output may be
shorted to ground through a very low impedance path or
it may be a resistive short, in which case the output will
collapse partially, until the load current equals the preset
currentlimit. Thecontrollerwillcontinuetosourcecurrent
into the short. The amount of current sourced depends
Figure 50 Worst-Case IMAX 6ersus Inductor Temperature Curve
with and without NTC Temperature Compensation
V
OUT
R
NTC
on the ILIM pin setting and the V voltage as shown in
FB
the Current Foldback graph in the Typical Performance
Characteristics section.
L1
Upon removal of the short, the output soft starts using
the internal soft-start, thus reducing output overshoot. In
the absence of this feature, the output capacitors would
have been charged at current limit, and in applications
with minimal output capacitance this may have resulted
in output overshoot. Current limit foldback is not disabled
during an overcurrent recovery. The load must step below
the folded back current limit threshold in order to restart
from a hard short.
SW1
3867 F08
Figure .0 Thermistor Location0 Place the Thermistor Next to
the Inductor for Accurate Sensing of the Inductor Temperature,
But Keep the ITEMP Pin Away from the Switch Nodes and Gate
Drive Traces
For the most accurate temperature detection, place the
thermistornexttotheoutputinductorasshowninFigure6.
Care should be taken to keep the ITEMP sense line away
from switch nodes.
Thermal Protection
Excessive ambient temperatures, loads and inadequate
airflow or heat sinking can subject the chip, inductor,
FETs etc. to high temperatures. This thermal stress re-
duces component life and if severe enough, can result
in immediate catastrophic failure (Note 4). To protect the
power supply from undue thermal stress, the LTC3866
has a fixed chip temperature-based thermal shutdown.
The internal thermal shutdown is set for approximately
160°C with 10°C of hysteresis. When the chip reaches
160°C, both TG and BG are disabled until the chip cools
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTC3866 can safely power up into a
pre-biased output without discharging it.
The LTC3866 accomplishes this by disabling both TG and
BG until the TK/SS pin voltage and the internal soft-start
voltage are above the V pin voltage. When V is higher
down below 150°C.
FB
FB
3866fa
17
LTC3866
applicaTions inForMaTion
Inductor 6alue Calculation
Power MOSFET and Schottky Diode
(Optional) Selection
Given the desired input and output voltages, the inductor
value and operating frequency, f , directly determine
At least two external power MOSFETs need to be selected:
One N-channel MOSFET for the top (main) switch and one
or more N-channel MOSFET(s) for the bottom (synchro-
nous) switch. The number, type and on-resistance of all
MOSFETsselectedtakeintoaccountthevoltagestep-down
ratio as well as the actual position (main or synchronous)
in which the MOSFET will be used. A much smaller and
much lower input capacitance MOSFET should be used
for the top MOSFET in applications that have an output
voltage that is less than one-third of the input voltage. In
OSC
the inductor’s peak-to-peak ripple current:
⎛
⎞
⎟
⎠
VOUT V – V
IN
OUT
IRIPPLE
=
⎜
⎝
V
fOSC •L
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
applications where V >> V , the top MOSFETs’ on-
IN
OUT
resistance is normally less important for overall efficiency
than its input capacitance at operating frequencies above
300kHz. MOSFET manufacturers have designed special
purposedevicesthatprovidereasonablylowon-resistance
with significantly reduced input capacitance for the main
switch application in switching regulators.
A reasonable starting point is to choose a ripple current
that is about 40% of I
. Note that the largest ripple
OUT(MAX)
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
V – V
fOSC •IRIPPLE
VOUT
IN
OUT
L ≥
•
The peak-to-peak MOSFET gate drive levels are set by the
V
IN
internal regulator voltage, V
, requiring the use of
INTVCC
logic-level threshold MOSFETs in most applications. Pay
closeattentiontotheBV specificationfortheMOSFETs
Inductor Core Selection
DSS
as well; many of the logic-level MOSFETs are limited to
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductanceselected. Asinductanceincreases, corelosses
go down. Unfortunately, increased inductance requires
moreturnsofwireandthereforecopperlosseswillincrease.
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, R , input capacitance,
DS(ON)
inputvoltageandmaximumoutputcurrent.MOSFETinput
capacitance is a combination of several components but
can be taken from the typical gate charge curve included
on most data sheets (Figure 7). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
3866fa
18
LTC3866
applicaTions inForMaTion
V
IN
where δ is the temperature dependency of R
, R
DS(ON) DR
is the effective top driver resistance (approximately 2Ω at
= V ), V is the drain potential and the change
MILLER EFFECT
V
V
GS
V
GS
MILLER
IN
a
b
in drain potential in the particular application. V
TH(MIN)
+
–
V
DS
+
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
Q
IN
V
GS
–
C
= (Q – Q )/V
B A DS
MILLER
3766 F07
drain current. C
is the calculated capacitance using
MILLER
the gate charge curve from the MOSFET data sheet and
Figure 70 Gate Charge Characteristic
the technique described above.
2
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V < 20V,
IN
while the curve is flat) is specified for a given V drain
the high current efficiency generally improves with larger
DS
voltage, but can be adjusted for different V voltages by
MOSFETs, whileforV >20V, thetransitionlossesrapidly
DS
IN
multiplying the ratio of the application V to the curve
increasetothepointthattheuseofahigherR
device
DS
DS(ON)
specified V values. A way to estimate the C
term
withlowerC
actuallyprovideshigherefficiency.The
DS
MILLER
MILLER
is to take the change in gate charge from points a and b
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
on a manufacturer’s data sheet and divide by the stated
V
DS
voltage specified. C
is the most important se-
MILLER
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
The term (1 + δ ) is generally given for a MOSFET in the
data sheets. C
and C are specified sometimes but
OS
RSS
form of a normalized R
vs temperature curve, but
DS(ON)
definitionsoftheseparametersarenotincluded.Whenthe
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
An optional Schottky diode across the synchronous
MOSFET conducts during the dead time between the con-
ductionofthetwolargepowerMOSFETs.Thispreventsthe
bodydiodeofthebottomMOSFETfromturningon,storing
chargeduringthedeadtimeandrequiringareverse-recov-
ery period which could cost as much as several percent in
efficiency. A 2A to 8A Schottky is generally a good com-
promise for both regions of operation due to the relatively
small average current. Larger diodes result in additional
transition loss due to their larger junction capacitance.
VOUT
MainSwitchDuty Cycle =
V
IN
⎛
⎜
⎝
⎞
⎟
⎠
V – V
IN
OUT
Synchronous SwitchDuty Cycle =
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
VOUT
PMAIN
=
I
(
1+δ R
+
(
)
)
MAX
DS(ON)
V
IN
C and C
IN
Selection
OUT
⎛
⎜
⎝
⎞
⎟
⎠
IMAX
2
V
R
(
C
(
•
(
)
)
)
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
IN
DR
MILLER
2
OUT
IN
⎡
⎢
⎤
⎥
⎦
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
1
1
+
• f
V
– VTH(MIN) VTH(MIN)
⎢
⎥
⎣ INTVCC
2
V – V
IN
OUT
IMAX
1/2
P
=
I
(
1+δ R
(
DS(ON)
)
)
MAX
⎡
⎤
OUT
SYNC
CIN Required IRMS
≈
V
OUT )(
V – V
IN
(
)
⎦
⎣
V
V
IN
3866fa
19
LTC3866
applicaTions inForMaTion
This formula has a maximum at V = 2V , where I
where f = operating frequency, C
= output capacitance
OUT
IN
OUT
RMS
= I /2. This simple worst-case condition is commonly
and ∆I
= ripple current in the inductor. The output
OUT
RIPPLE
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3866, ceramic capacitors
ripple is highest at maximum input voltage since ∆I
RIPPLE
increases with input voltage. The output ripple will be less
than 50mV at maximum V with ∆I
= 0.4I
IN
RIPPLE
OUT(MAX)
assuming:
C
OUT
required ESR < N • R
SENSE
and
1
COUT
>
can also be used for C . Always consult the manufacturer
IN
8f R
( )
(
)
SENSE
if there is any question.
TheemergenceofverylowESRcapacitorsinsmall,surface
mount packages makes very small physical implementa-
tions possible. The ability to externally compensate the
switching regulator loop using the ITH pin allows a much
wider selection of output capacitor types. The impedance
characteristic of each capacitor type is significantly differ-
ent than an ideal capacitor and therefore requires accurate
modelingorbenchevaluationduringdesign.Manufacturers
suchasNichicon,NipponChemi-ConandSanyoshouldbe
consideredforhighperformancethrough-holecapacitors.
TheOS-CONsemiconductordielectriccapacitorsavailable
from Sanyo and the Panasonic SP surface mount types
have a good (ESR)(size) product.
Ceramic capacitors are becoming very popular for small
designsbutseveralcautionsshouldbeobserved.X7R,X5R
and Y5V are examples of a few of the ceramic materials
used as the dielectric layer, and these different dielectrics
have very different effect on the capacitance value due to
thevoltageandtemperatureconditionsapplied.Physically,
if the capacitance value changes due to applied voltage
change, there is a concomitant piezo effect which results
in radiating sound! A load that draws varying current at
an audible rate may cause an attendant varying input volt-
age on a ceramic capacitor, resulting in an audible signal.
A secondary issue relates to the energy flowing back into
a ceramic capacitor whose capacitance value is being
reducedbytheincreasingcharge.Thevoltagecanincrease
ataconsiderablyhigherratethantheconstantcurrentbeing
supplied because the capacitance value is decreasing as
thevoltageisincreasing!Nevertheless,ceramiccapacitors,
when properly selected and used, can provide the lowest
overall loss due to their extremely low ESR.
OncetheESRrequirementforC hasbeenmet,theRMS
OUT
currentratinggenerallyfarexceedstheI
require-
RIPPLE(P-P)
ment. Ceramic capacitors from AVX, Taiyo Yuden, Murata
and TDK offer high capacitance value and very low ESR,
especially applicable for low output voltage applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surface mount capacitors offer very low ESR also but
have much lower capacitive density per unit volume. In
the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent choices are the AVX TPS, AVX TPSV, the KEMET
T510 series of surface mount tantalums or the Panasonic
SP series of surface mount special polymer capacitors
A small (0.1µF to 1µF) bypass capacitor, C , between the
IN
chip V pin and ground, placed close to the LTC3866, is
IN
also suggested. A 2.2Ω to 10Ω resistor placed between
C and V pin provides further isolation.
IN
IN
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V ) is determined by:
OUT
⎛
⎞
⎟
⎠
1
∆VOUT ≈ ∆IRIPPLE ESR+
⎜
8fCOUT
⎝
3866fa
20
LTC3866
applicaTions inForMaTion
availableincaseheightsrangingfrom2mmto4mm.Other
capacitor types include Sanyo POSCAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturers for other specific recommendations.
operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.54V. The output ripple
is minimized during the 40mV forced continuous mode
window, ensuring a clean PGOOD signal. When the chan-
nel is configured to track another supply, the feedback
voltage of the other supply is duplicated by a resistor
divider and applied to the TK/SS pin. Therefore, the volt-
age ramp rate on this pin is determined by the ramp rate
of the other supply’s voltage. It is only possible to track
another supply that is slower than the internal soft-start
ramp. Note that the small soft-start capacitor charging
current is always flowing, producing a small offset error.
To minimize this error, select the tracking resistive divider
value to be small enough to make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3866 is forced into
Differential Amplifier
The LTC3866 has true remote voltage sense capability.
The sense connections should be returned from the load,
back to the differential amplifier’s inputs through a com-
mon, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well
as ground loop disturbances. The LTC3866 diffamp has
80kΩ input impedance on DIFFP. It is designed to be con-
nected directly to the output. The output of the diffamp
connects to the V pin through a voltage divider, setting
FB
continuous mode of operation as soon as V is below the
FB
the output voltage.
undervoltage threshold of 0.54V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3866 should
always be set in forced continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, the
controller operates in discontinuous mode.
External Soft-Start and Tracking
The LTC3866 has the ability to either soft-start by itself
or track the output of another channel or external supply.
When the controller is configured to soft-start by itself, a
capacitormaybeconnectedtoitsTK/SSpinortheinternal
soft-start may be used. The controller is in the shutdown
state if its RUN pin voltage is below 1.14V and its TK/SS
pin is actively pulled to ground in this shutdown state. If
the RUN pin voltage is above 1.22V, the controller powers
up. A soft-start current of 1.25µA then starts to charge the
TK/SS soft-start capacitor. Note that soft-start or tracking
is achieved not by limiting the maximum output current
of the controller but by controlling the output ramp volt-
age according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TK/SS pin. The total soft-start time can be calculated as:
The LTC3866 allows the user to program how its output
ramps up and down by means of the TK/SS pin. Through
thesepins, theoutputcanbesetuptoeithercoincidentally
or ratiometrically track another supply’s output, as shown
inFigure8.Inthefollowingdiscussions,V
referstothe
OUT2
refers to another
LTC3866’s output as a slave and V
OUT1
supply output as a master. To implement the coincident
tracking in Figure 8a, connect an additional resistive di-
vider to V
and connect its mid-point to the TK/SS pin
OUT1
of the slave controller. The ratio of this divider should be
the same as that of the slave controller’s feedback divider
shown in Figure 9a. In this tracking mode, V
must
OUT1
be set higher than V
. To implement the ratiometric
OUT2
tracking in Figure 8b, the ratio of the V
divider should
OUT2
be exactly the same as the master controller’s feedback
divider shown in Figure 9b . By selecting different resis-
tors, the LTC3866 can achieve different modes of tracking
including the two in Figure 8.
CSS
1.25µA
tSOFTSTART = 0.6 •
Regardless of the mode selected by the MODE/PLLIN pin,
the controller always starts in discontinuous mode up to
TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will
So which mode should be programmed? While either
mode in Figure 8 satisfies most practical applications,
3866fa
21
LTC3866
applicaTions inForMaTion
V
V
V
OUT1
OUT1
OUT2
V
OUT2
TIME
3866 F08
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 80 Two Different Modes of Output 6oltage Tracking
V
OUT1
V
OUT1
V
OUT2
V
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
R4
TO
TK/SS2
PIN
TO
V
TO
TK/SS2
PIN
TO
V
TO
FB2
PIN
TO
FB2
PIN
V
V
FB1
FB1
PIN
PIN
3866 F09
(9a) Coincident Tracking Setup
(9b) Ratiometric Tracking Setup
Figure 90 Setup and Coincident and Ratiometric Tracking
some trade-offs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. Under ratiometric tracking, when the master
controller’soutputexperiencesdynamicexcursion(under
load transient, for example), the slave controller output
will be affected as well. For better output regulation, use
the coincident tracking mode instead of ratiometric.
placed directly adjacent to the INTV and PGND pins is
CC
highly recommended. Good bypassing is needed to sup-
ply the high transient currents required by the MOSFET
gate drivers. High input voltage applications in which
large MOSFETs are being driven at high frequencies may
cause the maximum junction temperature rating for the
LTC3866 to be exceeded. The INTV current, which is
CC
dominated by the gate charge current, may be supplied by
INT6 (LDO) and EXT6
either the 5.5V LDO or EXTV . When the voltage on the
CC
CC
CC
EXTV pin is less than 4.5V, the LDO is enabled. Power
CC
The LTC3866 features a true PMOS LDO that supplies
power to INTV from the V supply. INTV powers the
dissipation for the IC in this case is highest and is equal
CC
IN
CC
to V • I
. The gate charge current is dependent
IN
INTVCC
gate drivers and much of the LTC3866’s internal circuitry.
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 2 of the
ElectricalCharacteristicstables.Forexample,theLTC3866
The LDO regulates the voltage at the INTV pin to 5.5V
CC
when V is greater than 6V. EXTV connects to INTV
IN
CC
CC
through a P-channel MOSFET and can supply the needed
power when its voltage is higher than 4.7V. Either of these
cansupplyapeakcurrentof100mAandmustbebypassed
to ground with a minimum of 4.7µF ceramic capacitor or
lowESRelectrolyticcapacitor. Nomatterwhattypeofbulk
capacitor is used, an additional 0.1µF ceramic capacitor
INTV current is limited to less than 39mA from a 38V
CC
supply in the UF package and not using the EXTV supply
CC
with a 70°C ambient temperature:
T = 70°C + (39mA)(38V)(37°C/W) ≅ 125°C
J
3866fa
22
LTC3866
applicaTions inForMaTion
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 10 to minimize the voltage drop caused by the
gate charge current. This will override the INTV linear
CC
= SGND) at maximum V . When the voltage applied to
regulator and will prevent INTV from dropping too low
IN
CC
EXTV rises above 4.7V, the INTV LDO is turned off
due to the dropout voltage. Make sure the INTV voltage
CC
CC
CC
and the EXTV is connected to the INTV . The EXTV
is at or exceeds the R
test voltage for the MOSFET
CC
CC
CC
DS(ON)
remains on as long as the voltage applied to EXTV re-
which is typically 4.5V for logic-level devices.
CC
mains above 4.5V. Using the EXTV allows the MOSFET
CC
driver and control power to be derived from an efficient
LTC3866
switchingregulatoroutputduringnormaloperation.Ifmore
V
R
IN
VIN
current is required through the EXTV than is specified,
CC
1Ω
INTV
5V
CC
an external Schottky diode can be added between the
+
C
INTVCC
C
IN
EXTV and INTV pins. Do not apply more than 6V to
4.7µF
CC
CC
3866 F10
the EXTV pin and make sure that EXTV < V .
CC
CC
IN
Figure 1ꢀ0 Setup for a 56 Input
Significant efficiency and thermal gains can be realized
by powering INTV from EXTV , since the V current
CC
CC
IN
resultingfromthedriverandcontrolcurrentswillbescaled
Topside MOSFET Driver Supply (C , D )
B
B
by a factor of (duty cycle)/(switcher efficiency). Tying the
External bootstrap capacitor, C , connected to the BOOST
B
EXTV pintoa5Vsupplyreducesthejunctiontemperature
CC
pin supplies the gate drive voltages for the topside MOS-
in the previous example from 125°C to:
FET. Capacitor C in the Functional Diagram is charged
B
T = 70°C + (39mA)(5V)(37°C/W) = 77°C
J
though external diode D from INTV when the SW pin
B
CC
is low. When the topside MOSFET is to be turned on, the
However, for low voltage outputs, additional circuitry is
driver places the C voltage across the gate source of the
required to derive INTV power from the output.
B
CC
MOSFET. This enhances the MOSFET and turns on the
The following list summarizes the three possible connec-
topside switch. The switch node voltage, SW, rises to V
IN
tions for EXTV :
CC
and the BOOST pin follows. With the topside MOSFET on,
1. EXTV left open (or grounded). This will cause
the boost voltage is above the input supply:
CC
INTV to be powered from the internal LDO resulting
CC
V
= V + V
– V
INTVCC DB
BOOST
IN
in an efficiency penalty of up to 10% at high input
Thevalueoftheboostcapacitor, C , needstobe100times
voltages.
B
thatofthetotalinputcapacitanceofthetopsideMOSFET(s).
2. EXTV connectedtoanexternalsupply.Ifa5Vexternal
CC
The reverse breakdown of the external Schottky diode
supply is available, it may be used to power EXTV
CC
must be greater than V . When adjusting the gate
IN(MAX)
providing it is compatible with the MOSFET gate drive
drive level, the final arbiter is the total input current for
the regulator. If a change is made and the input current
decreases, then the efficiency has improved. If there is
no change in input current, then there is no change in
efficiency.
requirements.
3. EXTV connectedtoan output-derived boostnetwork.
CC
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV to an
CC
output-derivedvoltagethathasbeenboostedtogreater
Setting Output 6oltage
than 4.7V.
The LTC3866 output voltage is set by an external feedback
resistive divider carefully placed across the DIFFOUT pin,
For applications where the main input power is 5V, tie
the V and INTV pins together and tie the combined
IN
CC
3866fa
23
LTC3866
applicaTions inForMaTion
as shown in Figure 11. The regulated output voltage is
determined by:
The resulting short-circuit current is:
⎛
⎜
⎝
⎞
⎟
⎠
1/3VSENSE(MAX)
1
2
ISC
=
– ∆IL SC
⎛
⎞
⎟
⎠
(
)
RB
RA
RSENSE
VOUT = 0.6V • 1+
⎜
⎝
Afterashort,orwhilestartingwithinternalsoft-start,make
sure that the load current takes the folded-back current
limit into account.
To improve the frequency response, a feedforward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
Phase-Locked Loop and Frequency Synchronization
inductor or the SW line.
The LTC3866 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phasedetector. Thisallowstheturn-onofthetopMOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
To minimize the effect of the voltage drop caused by high
currentflowingthroughboardconductance;connectDIFFN
and DIFFP sense lines close to the ground and the load
output respectively.
DIFFOUT
R
R
C
FF
B
LTC3866
V
FB
A
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. There is a precision 10µA current flowing
out of the FREQ pin. This allows the user to use a single
resistor to SGND to set the switching frequency when
no external clock is applied to the MODE/PLLIN pin. The
internal switch between the FREQ pin and the integrated
PLL filter network is on, allowing the filter network to be
pre-charged to the same voltage as the FREQ pin. The
relationship between the voltage on the FREQ pin and
operating frequency is shown in Figure 12 and specified
in the Electrical Characteristics table. If an external clock
is detected on the MODE/PLLIN pin, the internal switch
mentionedaboveturnsoffandisolatestheinfluenceofthe
FREQpin.NotethattheLTC3866canonlybesynchronized
to an external clock whose frequency is within range of
the LTC3866’s internal VCO. This is guaranteed to be
between 250kHz and 770kHz. A simplified block diagram
is shown in Figure 13.
3866 F11
Figure 110 Setting Output 6oltage
Fault Conditions: Current Limit and Current Foldback
The LTC3866 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from
its maximum programmed value to one-third of the maxi-
mum value. Foldback current limiting is disabled during
the soft-start or tracking up using the TK/SS pin. It is not
disabled for internal soft-start. Under short-circuit condi-
tions with very low duty cycles, the LTC3866 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short circuit ripple current is determined by the minimum
on-timet
oftheLTC3866(≈90ns),theinputvoltage
ON(MIN)
and inductor value:
V
L
IN
∆IL(SC) = tON(MIN)
•
3866fa
24
LTC3866
applicaTions inForMaTion
900
800
700
600
500
400
300
200
100
0
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
thattheLTC3866iscapableofturningonthetopMOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
ON(MIN)
VOUT
V f
IN ( )
tON(MIN)
<
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
3866 F12
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the voltage ripple and current ripple will increase. The
minimumon-timefortheLTC3866isapproximately90ns,
with good PCB layout, minimum 30% inductor current
ripple and at least 2mV ripple on the current sense signal.
The minimum on-time can be affected by PCB switch-
ing noise in the voltage and current loop. As the peak
sense voltage decreases the minimum on-time gradually
increases to about 110ns. This is of particular concern in
forced continuous applications with low ripple current at
light loads. If the duty cycle drops below the minimum
on-timelimitinthissituation, asignificantamountofcycle
skipping can occur with correspondingly larger current
and voltage ripple.
Figure 120 Relationship Between Oscillator
Frequency and 6oltage at the FREQ Pin
2.4V 5.5V
R
SET
10µA
FREQ
DIGITAL
PHASE/
MODE/PLLIN
SYNC
EXTERNAL
OSCILLATOR
FREQUENCY
DETECTOR
VCO
3866 F13
Figure 130 Phase-Locked Loop Block Diagram
Efficiency Considerations
If the external clock frequency is greater than the inter-
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f , current is sunk continuously, pulling down
OSC
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the filter capacitor C holds the voltage.
LP
the losses in LTC3866 circuits: 1) IC V current, 2)
IN
2
Typically,theexternalclock(ontheMODE/PLLINpin)input
high threshold is 1.6V, while the input low threshold is 1V.
INTV regulatorcurrent,3)I Rlosses,4)topsideMOSFET
CC
transition losses.
3866fa
25
LTC3866
applicaTions inForMaTion
1. The V current is the DC supply current given in the
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
IN
ElectricalCharacteristicstable,whichexcludesMOSFET
driverandcontrolcurrents. V currenttypicallyresults
IN
in a small (<0.1%) loss.
2
2. INTV current is the sum of the MOSFET driver and
Transition Loss = (1.7) V • I
• C
• f
CC
IN
O(MAX)
RSS
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
fromINTV toground.TheresultingdQ/dtisacurrent
CC
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
C has adequate charge storage and very low ESR at
IN
= f(Q + Q ), where Q and Q are the gate charges
T
B
T
B
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses, including Schottky conduction losses during
dead time and inductor core losses, generally account
for less than 2% total additional loss.
of the topside and bottom side MOSFETs. Supplying
INTV powerthroughEXTV fromanoutput-derived
CC
CC
source will scale the V current required for the driver
IN
and control circuits by a factor of (duty cycle)/(effi-
ciency). Forexample, ina20Vto5Vapplication, 10mA
of INTV current results in approximately 2.5mA of
CC
V current. This reduces the mid-current loss from
IN
Checking Transient Response
10% or more (if the driver was powered directly from
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor and current sense re-
sistor(ifused).Incontinuousmode,theaverageoutput
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ∆I
• ESR, where ESR is the effective
LOAD
current flows through L and R
, but is chopped
SENSE
series resistance of C . ∆I
also begins to charge or
OUT
LOAD
betweenthetopsideMOSFETandthesynchronousMOS-
discharge C , generating the feedback error signal that
OUT
FET. If the two MOSFETs have approximately the same
forces the regulator to adapt to the current change and
R
, thentheresistance ofone MOSFET can simply
DS(ON)
return V
to its steady-state value. During this recovery
can be monitored for excessive overshoot or
OUT
be summed with the resistances of L and R
to
SENSE
=10mΩ,
time V
OUT
2
obtainI Rlosses.Forexample,ifeachR
R = 10mΩ, R
DS(ON)
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can
be estimated using the percentage of overshoot seen at
this pin. The bandwidth can also be estimated by examin-
ing the rise time at the pin. The ITH external components
shown in the Typical Application circuit will provide an
= 5mΩ, then the total resistance is
L
SENSE
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for a 5V
output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
3866fa
26
LTC3866
applicaTions inForMaTion
adequatestartingpointformostapplications.TheITHseries
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
R -C filtersetsthedominantpole-zeroloopcompensation.
C
C
The values can be modified slightly (from 0.5 to 2 times
their suggested values) to optimize transient response
once the final PC layout is done and the particular output
capacitortypeandvaluehavebeendetermined.Theoutput
capacitors need to be selected because the various types
and values determine the loop gain and phase. An output
current pulse of 20% to 80% of full-load current having a
rise time of 1µs to 10µs will produce output voltage and
ITH pin waveforms that will give a sense of the overall
loop stability without breaking the feedback loop. Placing
a power MOSFET directly across the output capacitor and
driving the gate with an appropriate signal generator is a
practicalwaytoproducearealisticloadstepcondition.The
initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10µF capacitor would
LOAD
require a 250µs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 14. Check the following in the
PC layout:
1. The INTV decoupling capacitor should be placed
CC
immediately adjacent to the IC between the INTV pin
CC
loop will be increased by increasing R and the bandwidth
C
and PGND plane. A 1µF ceramic capacitor of the X7R
or X5R type is small enough to fit very close to the IC
to minimize the ill effects of the large current pulses
drawn to drive the bottom MOSFETs. An additional
4.7µF to 10µF of ceramic, tantalum or other very low
ESR capacitance is recommended in order to keep the
internal IC supply quiet.
of the loop will be increased by decreasing C . If R is
C
C
increased by the same factor that C is decreased, the
C
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
L1
V
OUT
V
IN
SW2
DCR
R
IN
+
+
R
L
D1
C
OUT
C
SW1
IN
3866 F14
BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH
Figure 140 Branch Current Waveforms
3866fa
27
LTC3866
applicaTions inForMaTion
8. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
2. Place the feedback divider between the + and – termi-
nals of C . Route DIFFP and DIFFN with minimum
OUT
of C
must return to the combined C
(–) ter-
PC trace spacing from the IC to the feedback divider.
INTVCC
OUT
minals. The V and ITH traces should be as short as
+
+
–
FB
3. Are the SNSD , SNSA and SNS printed circuit traces
routed together with minimum PC trace spacing? The
possible. The path formed by the top N-channel MOS-
FET, Schottky diode and the C capacitor should have
+
+
–
IN
filter capacitors between SNSD , SNSA and SNS
should be as close as possible to the pins of the IC.
ConnecttheSNSD andSNSA pinstothefilterresistors
as illustrated in Figure 3.
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
+
+
4. Do the (+) plates of C connect to the drain of the
IN
topside MOSFET as closely as possible? This capacitor
9. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
provides the pulsed current to the MOSFET.
5. Keep the switching nodes, SW, BOOST and TG away
+
+
from sensitive small-signal nodes (SNSD , SNSA ,
capacitors with tie-ins for the bottom of the INTV
CC
–
SNS , DIFFP, DIFFN, V ). Ideally the SW, BOOST and
decouplingcapacitor,thebottomofthevoltagefeedback
FB
TG printed circuit traces should be routed away and
separated from the IC and especially the quiet side of
the IC. Separate the high dv/dt traces from sensitive
small-signalnodeswithgroundtracesorgroundplanes.
resistive divider and the SGND pin of the IC.
Design Example
As a design example of the front page circuit for a single
channelhighcurrentregulator,assumeV =12V(nominal),
6. Use a low impedance source such as a logic gate to
drive the MODE/PLLIN pin and keep the lead as short
as possible.
IN
V
IN
= 20V(maximum), V
= 1.5V, I
= 30A, and
OUT
MAX
f = 400kHz (see front page schematic).
The regulated output voltage is determined by:
7. The 47pF to 330pF ceramic capacitor between the I
TH
pin and signal ground should be placed as close as
possible to the IC. Figure 14 illustrates all branch cur-
rents in a switching regulator. It becomes very clear
afterstudyingthecurrentwaveformswhyitiscriticalto
keepthehighswitchingcurrentpathstoasmallphysical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a com-
mon ground path with any switched current paths. The
left half of the circuit gives rise to the noise generated
by a switching regulator. The ground terminations of
the synchronous MOSFET and Schottky diode should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP® compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
⎛
⎞
⎟
⎠
RB
RA
VOUT = 0.6V • 1+
⎜
⎝
Using a 20k 1% resistor from the V node to ground,
FB
the top feedback resistor is (to the nearest 1% standard
value) 30.1k.
The frequency is set by biasing the FREQ pin to 1V (see
Figure 12).
The inductance value is based on a 35% maximum ripple
current assumption (10.5A). The highest value of ripple
current occurs at the maximum input voltage:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
f • ∆IL(MAX)
VOUT
V
IN(MAX)
L =
1−
3866fa
28
LTC3866
applicaTions inForMaTion
This design will require 0.33µH. The Würth 744301033,
0.32µH inductor is chosen. At the nominal input voltage
(12V), the ripple current will be:
MOSFET results in: R
MILLER
(estimated) = 75°C:
= 7.1mΩ (max), V
=
DS(ON)
MILLER
2.8V, C
≅ 35pF. At maximum input voltage with T
J
1.5V
⎛
⎞
2
VOUT
f • L
VOUT
V
IN(NOM)
PMAIN
=
30A 1+(0.005)(75°C – 25°C) •
(
)
[
]
⎜
⎟
∆IL(NOM)
=
1−
20V
0.0071Ω + 20V
⎜
⎟
⎝
⎠
⎛
⎞
⎟
⎠
30A
2
2
2Ω 35pF •
)(
(
) (
)
⎜
(
)
⎝
It will have 10A (33%) ripple. The peak inductor current
will be the maximum DC value plus one-half the ripple
current, or 35A.
⎡
⎤
1
1
+
400kHz
(
⎥
)
⎢
⎣
⎦
5.5V – 2.8V 2.8V
The minimum on-time occurs at the maximum V , and
IN
= 599mW+122mW
= 721mW
should not be less than 90ns:
VOUT
1.5V
tON(MIN)
=
=
= 187ns
For a 0.32mΩ DCR, a short-circuit to ground will result
in a folded back current of:
VIN(MAX)f 20V(400kHz)
DCRsensingisusedinthiscircuit. IfC1andC2arechosen
to be 220nF, based on the chosen 0.33µH inductor with
0.32mΩ DCR, R1 and R2 can be calculated as:
⎛
⎞
⎟
⎠
1/ 3 15mV
0.0032Ω
1 90ns(20V)
(
)
ISC
=
–
= 12.9A
⎜
2
0.33µH
⎝
L
An Infineon BSC010NE2LS, R
= 1.1mΩ, is chosen
DS(ON)
R1=
R2 =
= 4.69k
for the bottom FET. The resulting power loss is:
DCR •C1
L
20V – 1.5V
20V
2
= 937Ω
P
=
30A •
(
)
SYNC
DCR •C2 • 5
⎡
⎤
1+ 0.005 • 75°C – 25°C • 0.0011Ω
(
)
(
)
⎣
⎦
Choose R1 = 4.64k and R2 = 931Ω.
P
= 1.14W
The maximum DCR of the inductor is 0.34Ω. The
SENSE(MAX)
SYNC
V
is calculated as:
C is chosen for an equivalent RMS current rating of at
IN
least 13.7A. C
is chosen with an equivalent ESR of
V
= I
• DCR
= 12mV
OUT
SENSE(MAX)
PEAK
MAX
4.5mΩ for low output ripple. The output ripple in continu-
ous mode will be highest at the maximum input voltage.
The output voltage ripple due to ESR is approximately:
The current limit is chosen to be 15mV. If temperature
variation is considered, please refer to Inductor DCR
SensingTemperatureCompensationwithNTCThermistor.
V
= R (∆I ) = 0.0045Ω • 10A = 45mV
ESR L P-P
ORIPPLE
The power dissipation on the topside MOSFET can be
easily estimated. Choosing an Infineon BSC050NE2LS
Further reductions in output voltage ripple can be made
by placing a 100µF ceramic capacitor across C
.
OUT
3866fa
29
LTC3866
Typical applicaTions
6ery Low Output Ripple Converter
The schematic as shown Figure 15 is similar to that of the
front page circuit, except that three times the inductance
and double the output capacitance are used. The com-
pensation components are changed to maintain the same
crossover frequency and phase margin. Figure 16 shows
the transient response of 15A load step, and Figure 17
demonstrates that the output voltage ripple is a factor of
six smaller than that of typical current mode converters.
The LTC3866 can work with very low DCR inductors be-
cause it can operate with only a small peak-to-peak sense
voltage. Two inductor characteristics can diminish this
signal: lower DC resistance and higher inductance. While
lowerDCRimprovesefficiency,higherinductancereduces
output ripple. Because the LTC3866 only requires a ripple
signal about a quarter of the sense signal of the next best
current mode converters, output ripple can be drastically
reduced by increasing the inductance and capacitance of
the output filter. The very small output voltage ripple is
critical for low noise applications such as audio systems
and noise sensitive systems.
Increasing the inductance, while maintaining the same
physical size inductor, will invariably increase conduction
lossesduetohigherDCresistance.However,reducedripple
current will decrease the core loss and the AC resistance
loss often enough to negate the extra DC conduction
losses. Figure 18 shows a high efficiency converter with
the benefit of low output ripple current.
100k
V
IN
FREQ MODE/PLLIN
4.5V TO 20V
0.1µF
220µF
RUN
TK/SS
ITH
PGOOD
ITEMP
4.7µF
EXTV
CC
CMDSH-3
0.1µF
LTC3866
V
V
IN
FB
INTV
DIFFOUT
DIFFP
CC
L1
1µH
DCR = 1mΩ
BOOST
TG
R
B
BSC050NE2LS
BSC010NE2LS
DIFFN
30.1k
V
OUT
+
1.5V
25A
SW
SNSD
C1
R
A
C
OUT
–
BG
SNS
75pF
220nF
20k
470µF
+
PGND
R1
4.53k
R2
909Ω
SNSA
ILIM
×4
10k
C2
220nF
CLKOUT
SGND
680pF
3866 F15
Figure 150 High Efficiency, 1056/25A Step-Down Converter with 6ery Low Output Ripple
3866fa
30
LTC3866
Typical applicaTions
V
OUT
TYPICAL
FRONT PAGE
10mV/DIV
I
L
AC-COUPLED
10A/DIV
0A
V
OUT
V
OUT
LOW RIPPLE
FIGURE 15
100mV/DIV
AC-COUPLED
10mV/DIV
AC-COUPLED
3866 F16
V
V
= 12V
50µs/DIV
IN
OUT
3866 F17
= 1.5V
2µs/DIV
V
V
= 12V
IN
OUT
= 1.5V
Figure 1.0 Load Step Transient Response
Figure 170 6ery Low Output 6oltage Ripple
100
V
IN
V
OUT
= 12V
90
80
70
60
50
40
30
20
10
0
= 1.5V
0.01
0.1
1
10
100
LOAD CURRENT (A)
3866 F18
Figure 180 Power Efficiency vs Load Current
56/25A Step-Down Converter
2.2Ω
V
IN
12V
10µF
×2
180µF
×2
1µF
FREQ MODE/PLLIN
120k
4.7µF
20k
RUN
TK/SS
ITH
PGOOD
ITEMP
EXTV
CC
V
OUT
0.1µF
LTC3866
V
V
IN
FB
CMDSH-3
INTV
DIFFOUT
DIFFP
CC
L1
1µH
BOOST
TG
BSC024NE2LS
BSC010NE2LS
DIFFN
DCR = 1.3mΩ
V
OUT
+
5V
SW
SNSD
100µF
R1
25A
–
BG
SNS
×2
3.48k
C1
220nF
R2
147k
28.7k
+
PGND
330µF
×2
SNSA
ILIM
CLKOUT
100pF
R3
20k
SGND
2.2nF
3866 TA04
3866fa
31
LTC3866
Typical applicaTions
High Efficiency, Dual Phase 6ery Low DCR Sensing 1056/.ꢀA Step-Down Supply
100k
V
IN
7V TO 20V
FREQ MODE/PLLIN
120k
PGOOD
ITEMP
RUN
TK/SS
ITH
0.1µF
10µF
×2
2.2Ω
CMDSH-3
EXTV
CC
V
V
FB
IN
30.1k
DIFFOUT
DIFFP
INTV
CC
LTC3866
3.57k
20k
BOOST
0.1µF
BSC050NE2LS
BSC010NE2LS
DIFFN
TG
202nF
0.33µH
DCR = 0.32mΩ
V
1.5V
60A
OUT
+
SNSD
SW
220nF
220nF
330µF
–
SNS
BG
931Ω 4.64k
×2
+
SNSA
PGND
CLKOUT
100µF
×2
1µF
4.7µF
I
GND
LIM
SGND
30.1k
330pF
10k
FREQ MODE/PLLIN
120k
PGOOD
ITEMP
RUN
TK/SS
ITH
CMDSH-3
EXTV
CC
V
V
FB
IN
10µF
×2
DIFFOUT
DIFFP
INTV
CC
LTC3866
BOOST
0.1µF
BSC050NE2LS
BSC010NE2LS
DIFFN
TG
0.33µH
DCR = 0.32mΩ
+
SNSD
SW
220nF
220nF
330µF
–
931Ω
×2
SNS
BG
4.64k
100k
+
SNSA
PGND
CLKOUT
100µF
×2
1µF
4.7µF
I
LIM
3866 TA02
SGND
3866fa
32
LTC3866
package DescripTion
Please refer to http://www0linear0com/designtools/packaging/ for the most recent package drawings0
FE Package
24-Lead Plastic TSSOP (404mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad 6ariation AA
7.70 – 7.90*
3.25
(.128)
(.303 – .311)
3.25
(.128)
24 23 22 21 20 19 18 17 16 15 14 13
6.60 ±0.10
4.50 ±0.10
2.74
(.108)
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE24 (AA) TSSOP REV B 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3866fa
33
LTC3866
package DescripTion
Please refer to http://www0linear0com/designtools/packaging/ for the most recent package drawings0
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45 CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05
0.200 REF
0.25 0.05
0.00 – 0.05
0.50 BSC
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3866fa
34
LTC3866
revision hisTory
RE6
DATE
DESCRIPTION
PAGE NUMBER
A
08/12 Clarified operating temperatures.
2-5
5
Modified the P equation thermal resistance value.
D
Modified the Block Diagram sense amplifier.
Clarified the SNS section values.
10
14
Modified the ripple value in the Soft-Start section.
21
Modified values in the INTV and EXTV section.
22-23
31
CC
CC
Modified the 5V/25A Step-Down Converter circuit schematic.
3866fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3866
Typical applicaTion
High Efficiency Step-Down Converter with Power Block
100k
INTV
CC
1µF
V
IN
100k
470µF
10µF
0.1µF
24 23 22 21 20 19
2.2Ω
V
V
IN
OUT
V
1.5V
40A
OUT
1
7
11
12
INTV
CC
V
V
V
V
IN1
IN2
OUT1
OUT2
1
18
17
16
15
14
13
12
+
+
4.7µF
ITH
EXTV
CC
100µF
10Ω
330µF
330µF
2
3
4
5
6
5
1500pF
220pF
10k
V
V
PWMH
PWML
FB
IN
4
15
14
GND
+
CMDSH-3
0.1µF
DIFFOUT
DIFFN
INTV
TEMP
TEMP
CC
LTC3866EUF
3
–
10Ω
30.1k
BOOST
TG
V
GATE
2
DIFFP
GND
GND
GND
GND
6
+
20k
SNSD
SW
9
10
8
–
+
BG
CS
CS
13
4.75k
25
7
8
9
10 11
ACBEL POWER BLOCK
VRA001-4C1G
INTV
CC
47nF
47nF
3866 TA03
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
Very Fast Transient Response, t
LTC3833
Fast Accurate Step-Down DC/DC Controller with
Differential Output Sensing
= 20ns, 4.5V ≤ V ≤ 38V,
ON(MIN) IN
0.6V ≤ V
≤ 5.5V, TSSOP-20E, 3mm × 4mm QFN-20
OUT
LTC3878/LTC3879
LTC3775
No R
™ Constant On-Time Synchronous Step-Down Very Fast Transient Response, t
= 43ns, 4V ≤ V ≤ 38V,
SENSE
ON(MIN) IN
DC/DC Controllers
0.6V ≤ V
≤ 0.9V , SSOP-16, MSOP-16E, 3mm × 3mm QFN-16
OUT IN
High Frequency Synchronous Voltage Mode Step-Down
DC/DC Controller
Very Fast Transient Response, t
= 30ns, 4V ≤ V ≤ 38V,
ON(MIN) IN
0.6V ≤ V
≤ 0.8V , MSOP-16E, 3mm × 3mm QFN-16
IN
OUT
LTC3854
Small Footprint Synchronous Step-Down DC/DC
Controller
Fixed 400kHz Operating Frequency, 4.5V ≤ V ≤ 38V,
IN
0.8V ≤ V
≤ 5.25V, 2mm × 3mm QFN-12
OUT
LTC3851A/LTC3851A-1 No R
Wide V Range Synchronous Step-Down
PLL Fixed Frequency 250kHz to 750kHz, 4V ≤ V ≤ 38V,
IN
SENSE
IN
DC/DC Controllers
0.8V ≤ V
≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16
OUT
LTC3891
60V, Low I Synchronous Step-Down DC/DC Controller
PLL Capable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,
IN
Q
0.8V ≤ V
≤ 24V, I = 50µA
Q
OUT
LTC3856
2-Phase, Single Output Synchronous Step-Down DC/DC
Controller with Diff Amp and DCR Temp Compensation
PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,
IN
0.6V ≤ V
≤ 5.25V
OUT
LTC3829
3-Phase, Single Output Synchronous Step-Down DC/DC
Controller with Diff Amp and DCR Temp Compensation
PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,
IN
0.6V ≤ V
≤ 5.25V
OUT
LTC3855
2-Phase, Dual Output Synchronous Step-Down DC/DC
Controller with Differential Remote Sense
PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V,
IN
0.6V ≤ V
≤ 12.5V
OUT
LTC3860
Dual, Multiphase, Synchronous Step-Down DC/DC
Controller with Diff Amp and Three-State Output Drive
Operates with Power Blocks, DRMOS Devices or External Drivers/
MOSFETs, 3V ≤ V ≤ 24V, t = 20ns
IN
ON(MIN)
LTC3869/LTC3869-2
LTC3867
2-Phase, Dual Output Synchronous Step-Down DC/DC
Controllers, with Accurate Multiphase Current Matching
PLL Fixed Frequency 250kHz to 780kHz, 4V ≤ V ≤ 30V,
IN
0.6V ≤ V
≤ 12.5V, 4mm × 5mm QFN-28, SSOP-28
OUT
Synchronous Step-Down DC/DC Controller with Nonlinear Fast Transient Response, t
Control and Remote Sense
= 65ns, 4V ≤ V ≤ 38V,
IN
ON(MIN)
0.6V ≤ V
≤ 14V, 4mm × 4mm QFN-24
OUT
3866fa
LT 0812 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC3855IUJ#PBF
LTC3855 - Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
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