LTC3858IGN-1#TRPBF_技术文档

LTC3858-1

Low I , Dual

Q

2-Phase Synchronous

Step-Down Controller

FEATURES

DESCRIPTION

The LTC^®3858-1 is a high performance dual step-down

switching regulator controller that drives all N-channel

synchronouspowerMOSFETstages.Aconstantfrequency

current mode architecture allows a phase-lockable fre-

quency of up to 850kHz. Power loss and noise due to the

input capacitor ESR are minimized by operating the two

controller outputs out of phase.

n

Low Operating I : 170μA (One Channel On)

Q

n

Wide Output Voltage Range: 0.8V ≤ V

≤ 24V

OUT

Wide V Range: 4V to 38V

IN

R

or DCR Current Sensing

SENSE

Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C

n

OUT

Phase-Lockable Frequency (75kHz-850kHz)

Programmable Fixed Frequency (50kHz-900kHz)

Selectable Continuous, Pulse-Skipping or

Burst Mode^®Operation at Light Loads

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start

The 170ꢀA no-load quiescent current extends operating

life in battery powered systems. OPTI-LOOP compensa-

tion allows the transient response to be optimized over

a wide range of output capacitance and ESR values. The

LTC3858-1featuresaprecision0.8Vreferenceandapower

goodoutputindicator. Awide4Vto38Vinputsupplyrange

encompasses a wide range of intermediate bus voltages

and battery chemistries.

n

Power Good Output Voltage Monitor

Output Overvoltage Protection

Output Latchoff Protection During Short Circuit

Independent soft-start pins for each controller ramp the

outputvoltagesduringstart-up.Theoutput Latchofffeature

protects the circuit in short-circuit conditions.

Low Shutdown I : 8μA

Q

Internal LDO Powers Gate Drive from V or EXTV

IN

CC

No Current Foldback During Start-Up

Tiny 4mm × 5mm QFN and Narrow SSOP Packages

For a leadless 32-pin QFN package with the additional fea-

tures of adjustable current limit, clock out, phase modula-

tionandtwoPGOODoutputs,seetheLTC3858datasheet.

L,LT,LTC,LTM,BurstMode,OPTI-LOOP,μModule,LinearTechnologyandtheLinearlogo

APPLICATIONS

n

Automotive Systems

areregisteredtrademarksandNoR

andUltraFastaretrademarksofLinearTechnology

SENSE

n

Battery Operated Digital Devices

Corporation.Allothertrademarksarethepropertyoftheirrespectiveowners.ProtectedbyU.S.

Patents,including5481178,5705919,5929620,6100678,6144194,6177787,6304066,6580258.

n

Distributed DC Power Systems

TYPICAL APPLICATION

High Efﬁciency Dual 8.5V/3.3V Step-Down Converter

V

Efﬁciency and Power Loss

IN

9V TO 38V

22μF

50V

vs Load Current

4.7μF

V

INTV

CC

100

90

10000

1000

100

10

IN

TG1

TG2

0.1μF

BOOST1

SW1

BOOST2

SW2

3.3μH

7.2μH

80

70

EFFICIENCY

BG1

BG2

60

50

LTC3858-1

PGND

POWER LOSS

= 12V

+

40

30

20

10

0

SENSE1

SENSE2

0.01Ω

193k

0.007Ω

–

1

–

V

8.5V

3.5A

SENSE2

OUT2

V

OUT1

3.3V

5A

IN

OUT

V

= 3.3V

FB1

FB2

I

TH2

62.5k

FIGURE 12 CIRCUIT

0.1 10

OUTPUT CURRENT (A)

I

TH1

SS1

0.1

150μF

680pF

15k

680pF

15k

150μF

SGND

SS2

0.0001 0.001

0.01

1

20k

0.1μF

38581 TA01b

38581 TA01

38581fd

1

LTC3858-1

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

EXTV ...................................................... –0.3V to 14V

Input Supply Voltage (V )......................... –0.3V to 40V

CC

IN

I

, I ,V , V Voltages ...................... –0.3V to 6V

TH1 TH2 FB1 FB2

Topside Driver Voltages

PGOOD1 Voltage ......................................... –0.3V to 6V

BOOST1, BOOST2 ................................. –0.3V to 46V

Switch Voltage (SW1, SW2) ........................ –5V to 40V

(BOOST1-SW1), (BOOST2-SW2) ................ –0.3V to 6V

RUN1, RUN2 ............................................... –0.3V to 8V

Maximum Current Sourced Into Pin

SS1, SS2, INTV Voltages ......................... –0.3V to 6V

CC

Operating Junction Temperature Range

(Note 2).................................................. –40°C to 125°C

Maximum Junction Temperature (Note 3) ............ 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

from Source >8V...............................................100μA

+

–

+

–

SENSE1 , SENSE2 , SENSE1

SSOP ................................................................ 300°C

SENSE2 Voltages...................................... –0.3V to 28V

PLLIN/MODE, FREQ Voltages .............. –0.3V to INTV

CC

PIN CONFIGURATION

TOP VIEW

1

2

SS1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I

TH1

PGOOD1

TG1

V

FB1

+

3

SENSE1

28 27 26 25 24 23

+

–

SENSE1

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

BOOST1

BG1

4

SW1

–

5

BOOST1

BG1

FREQ

PLLIN/MODE

SGND

FREQ

PLLIN/MODE

SGND

V

IN

6

PGND

29

SGND

7

V

IN

EXTV

CC

8

PGND

RUN1

INTV

BG2

9

EXTV

CC

RUN2

–

10

11

12

13

14

INTV

CC

SENSE2

–

SENSE2

BOOST2

+

BG2

SENSE2

9

10 11 12 13 14

UFD PACKAGE

BOOST2

SW2

V

FB2

TH2

I

TG2

SS2

28-LEAD (4mm s 5mm) PLASTIC QFN

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θ = 43°C/W

JMAX

JA

EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB

T

= 125°C, θ = 90°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LTC3858EUFD-1#PBF

LTC3858IUFD-1#PBF

LTC3858EGN-1#PBF

LTC3858IGN-1#PBF

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3858EUFD-1#TRPBF 38581

28-Lead (4mm × 5mm) Plastic QFN

28-Lead Plastic SSOP

LTC3858IUFD-1#TRPBF

LTC3858EGN-1#TRPBF

LTC3858IGN-1#TRPBF

38581

LTC3858GN-1

28-Lead Plastic SSOP

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

38581fd

2

LTC3858-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Supply Operating Voltage Range

Regulated Feedback Voltage

4

38

V

IN

(Note 4) I

= 1.2V

TH1,2

FB1,2

l

–40°C to 125°C

–40°C to 85°C

0.788

0.792

0.800

0.812

0.808

V

I

Feedback Current

(Note 4)

5

50

nA

FB1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

(Note 4) V = 4.5V to 38V

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note4)

l

Measured in Servo Loop,

0.01

0.1

%

∆I Voltage = 1.2V to 0.7V

TH

(Note4)

Measured in Servo Loop,

–0.01

2

–0.1

%

∆I Voltage = 1.2V to 2V

TH

g

Transconductance Ampliﬁer g

Input DC Supply Current

(Note 4) I = 1.2V, Sink/Source = 5μA

TH1,2

mmho

m1,2

m

I

(Note 5)

Q

Pulse Skip or Forced Continuous Mode

(One Channel On)

Pulse Skip or Forced Continuous Mode

(Both Channels On)

RUN1 = 5V and RUN2 = 0V, V = 0.83V (No Load) or

1.3

2

mA

μA

FB1

RUN1 = 0V and RUN2 = 5V, V = 0.83V (No Load)

FB2

RUN1,2 = 5V, V

= 0.83V (No Load)

FB1,2

Sleep Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V, V = 0.83V (No Load) or

170

250

FB1

RUN1 = 0V and RUN2 = 5V, V = 0.83V (No Load)

FB2

Sleep Mode (Both Channels On)

Shutdown

RUN1,2 = 5V, V

RUN1,2 = 0V

= 0.83V (No Load)

300

8

450

20

μA

FB1,2

l

UVLO

Undervoltage Lockout

INTV Ramping Up

4.0

3.8

10

4.2

4.0

13

1

V

%

CC

INTV Ramping Down

3.6

7

CC

V

Feedback Overvoltage Protection

Measured at V

Each Channel

, Relative to Regulated V

FB1,2

OVL

FB1,2

+

–

+

I

SENSE Pin Current

μA

SENSE

–

SENSE Pin Current

V

< INTV – 0.5V

1

950

μA

%

μA

V

mV

V

OUT1,2

CC

> INTVCC + 0.5V

550

99.4

1.0

1.28

50

DF

Maximum Duty Factor

Soft-Start Charge Current

RUN Pin On Threshold Voltage

In Dropout, FREQ = 0V

98

0.7

1.23

MAX

I

V = 0V

SS1,2

1.4

1.33

SS1,2

l

V

On

V

, V Rising

RUN1 RUN2

RUN1,2

SS1,2

Hyst RUN Pin Hysteresis Voltage

LA

SS Pin Latchoff Arming Threshold

Voltage

SS Pin Latchoff Threshold Voltage

SS Discharge Current

V

, V

Rising from 1V

, V Rising from 2V

SS1 SS2

1.9

2

2.1

SS1 SS2

V

LT

V

1.3

7

1.5

10

1.7

13

V

μA

SS1,2

I

LT

Short-Circuit Condition V

= 0V

DSC1,2

FB1,2

V

= 5V

= 0.7V, V

SS1,2

l

V

Maximum Current Sense Threshold

Voltage

–, – = 3.3V

43

50

57

mV

SENSE(MAX)

FB1,2

SENSE1 2

Gate Driver

TG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.5

1.5

ꢁ

BG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.4

1.1

ꢁ

TG Transistion Time:

Rise Time

Fall Time

(Note 6)

TG1,2 t

C

= 3300pF

25

16

ns

r

f

LOAD

= 3300pF

38581fd

3

LTC3858-1

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_A= 25°C (Note 2). V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless

otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

BG Transistion Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1,2 t

C

= 3300pF

28

13

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

30

95

ns

1D

LOAD

BG/TG t

C

LOAD

= 3300pF Each Driver

1D

t

Minimum On-Time

(Note 7)

6V < V < 38V, V = 0V

EXTVCC

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

4.85

4.5

5.1

0.7

5.1

0.6

4.7

250

5.35

1.1

5.35

1.1

V

%

V

%

V

INTVCCVIN

LDOVIN

CC

IN

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 0V

CC

EXTVCC

Internal V Voltage

6V < V < 13V

EXTVCC

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 8.5V

CC

EXTVCC

EXTV Switchover Voltage

EXTV Ramping Positive

4.9

EXTVCC

CC

EXTV Hysteresis Voltage

mV

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Programmable Frequency

Low Fixed Frequency

High Fixed Frequency

Synchronizable Frequency

R

V

= 25k, PLLIN/MODE = DC Voltage

= 65k, PLLIN/MODE = DC Voltage

= 105k, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kꢁ

65kꢁ

105kꢁ

LOW

FREQ

375

505

320

485

75

380

585

850

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

PLLIN/MODE = External Clock

PGOOD1 Output

V

PGOOD1 Voltage Low

PGOOD1 Leakage Current

PGOOD1 Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

μA

PGL

PGOOD

I

V

PGOOD

V

with Respect to Set Regulated Voltage

Ramping Negative

PG

FB

–13

7

–10

2.5

–7

13

%

Hysteresis

V

with Respect to Set Regulated Voltage

Ramping Positive

FB

10

2.5

%

Hysteresis

t

Delay for Reporting a Fault (PGOOD Low)

25

μs

PG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability and

lifetime.

where θ = 43°C/W for the QFN package and θ = 90°C/W for the SSOP

JA

package.

Note 4: The LTC3858-1 is tested in a feedback loop that servos V

to

ITH1,2

a speciﬁed voltage and measures the resultant V . The speciﬁcation at

FB1,2

Note 2: The LTC3858-1 is tested under pulsed conditions such that

85°C is not tested in production. This speciﬁcation is assured by design,

characterization and correlation to production testing at 125°C.

T ≈ T . The LTC3858E-1 is guaranteed to meet performance speciﬁcations

J

A

from 0°C to 85°C. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3858I-1 is guaranteed

over the full –40°C to 125°C operating junction temperature range.

Note that the maximum ambient temperature is determined by speciﬁc

operating conditions in conjunction with board layout, the rated package

thermal resistance and other environmental factors.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels

Note 7: The minimum on-time condition is speciﬁed for an inductor peak-

to-peak ripple current ≥ of I

(See Minimum On-Time Considerations in

MAX

the Applications Information section).

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

D

T = T + (P • θ )

JA

J

A

D

38581fd

4

LTC3858-1

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency and Power Loss

vs Output Current

Efﬁciency vs Load Current

100

90

100

90

10000

1000

100

10

FIGURE 12 CIRCUIT

V

= 12V

IN

OUT

V

= 5V

IN

= 3.3V

80

70

V

= 12V

IN

60

50

60

50

Burst Mode

OPERATION

PULSE-

SKIPPING

MODE

FORCED

40

30

20

10

0

40

30

20

10

0

1

V

= 3.3V

CONTINUOUS

MODE

OUT

FIGURE 12 CIRCUIT

0.1

0.0001 0.001

0.01

0.1 10

1

0.0001 0.001

0.01

0.1

1

10

OUTPUT CURRENT (A)

3858 G02

3858 G01

Load Step

(Forced Continuous Mode)

Load Step (Burst Mode Operation)

Efﬁciency vs Input Voltage

98

96

94

92

90

88

86

84

82

80

FIGURE 12 CIRCUIT

V

I

= 3.3V

= 4A

OUT

V

OUT

100mV/DIV

AC-

100mV/DIV

AC-

COUPLED

I

L

I

L

2A/DIV

3858 G04

3858 G05

20 25

V

= 3.3V

20μs/DIV

V

= 3.3V

20μs/DIV

0

5

10 15

30 35 40

OUT

FIGURE 12 CIRCUIT

INPUT VOLTAGE (V)

3858 G03

Inductor Current at Light Load

Load Step (Pulse-Skipping Mode)

Soft-Start

V

OUT

FORCED

CONTINUOUS

MODE

V

OUT2

100mV/DIV

AC-

2V/DIV

COUPLED

Burst Mode

OPERATION

2A/DIV

V

OUT1

2V/DIV

I

L

2A/DIV

PULSE-

SKIPPING

MODE

3858 G06

3858 G07

3858 G08

V

= 3.3V

20μs/DIV

V

LOAD

FIGURE 12 CIRCUIT

= 3.3V

2μs/DIV

20ms/DIV

FIGURE 12 CIRCUIT

OUT

FIGURE 12 CIRCUIT

I

= 200μA

38581fd

5

LTC3858-1

TYPICAL PERFORMANCE CHARACTERISTICS

Total Input Supply Current

vs Input Voltage

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

400

5.6

5.2

5.1

FIGURE 12 CIRCUIT

= 3.3V

V

OUT

350

300

5.4

5.2

ONE CHANNEL ON

INTV

CC

300μA LOAD

250

200

150

100

50

5.0

4.8

4.6

4.4

4.2

EXTV RISING

CC

NO LOAD

EXTV FALLING

CC

0

5.0

4.0

10

15

25

30

35

40

5

20

0

5

10 15 20 25 30 35 40

INPUT VOLTAGE (V)

–20

5

55

80 105 130

–45

30

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3858 G10

3858 G12

3858 G11

Maximum Current Sense Voltage

vs I_THVoltage

Maximum Current Sense

Threshold vs Duty Cycle

SENSE^–Pin Input Bias Current

80

60

40

20

80

60

40

20

0

PULSE-SKIPPING MODE

FORCED CONTINUOUS MODE

Burst Mode OPERATION

(FALLING)

Burst Mode OPERATION

(RISING)

–50

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

0

–20

–40

5% DUTY CYCLE

0.8

PIN VOLTAGE

1.2 1.4

0

10

15

20

25

10 20

50

60 70 80 90 100

0

0.2 0.4 0.6

1.0

5

0

30 40

V

COMMON MODE VOLTAGE (V)

I

DUTY CYCLE (%)

SENSE

TH

3858 G14

3858 G13

3858 G15

Shutdown Current vs Temperature

Foldback Current Limit

Quiescent Current vs Temperature

230

210

190

170

150

130

110

10

9

90

80

70

60

50

40

30

20

10

PLLIN/MODE = 0

V

= 12V

IN

OUT

= 3.3V

ONE CHANNEL ON

8

7

6

5

4

0

55

TEMPERATURE (°C)

105 130

–45 –20

5

30

80

–45 –20

5

30

55

80 105 130

0

0.1 0.2 0.3 0.4 0.5

0.9

0.6 0.7 0.8

TEMPERATURE (°C)

FEEDBACK VOLTAGE (V)

3858 G17

3858 G18

3858 G16

38581fd

6

LTC3858-1

TYPICAL PERFORMANCE CHARACTERISTICS

Regulated Feedback Voltage

vs Temperature

Soft-Start Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

1.20

808

1.15

1.10

806

804

1.05

1.00

0.95

0.90

0.85

802

800

798

796

794

0.80

792

–45

5

30

55

80 105 130

–20

5

55

80 105 130

–45

30

–20

5

55

80 105 130

–45

30

TEMPERATURE (°C)

3858 G20

3858 G19

22554 G21

SENSE– Pin Input Current

vs Temperature

Shutdown Input Current

vs Input Voltage

Oscillator Frequency

vs Temperature

50

0

–50

14

12

800

700

600

V

= 3.3V

OUT

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

FREQ = INTV

CC

10

8

500

400

300

200

100

FREQ = GND

6

4

2

V

= 28V

55

OUT

0

25

INPUT VOLTAGE (V)

35

40

5

10

15

20

30

–45 –20

5

30

80 105 130

–45

–20

5

30

55

80 105 130

TEMPERATURE (°C)

3858 G22

3858 G23

3858 G24

Oscillator Frequency

vs Input Voltage

Undervoltage Lockout Threshold

vs Temperature

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

356

354

352

350

FREQ = GND

348

346

344

25

35

40

–45

5

30

55

80

130

5

10

15

20

30

–20

105

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3858 G28

3858 G25

38581fd

7

LTC3858-1

TYPICAL PERFORMANCE CHARACTERISTICS

Latchoff Threshold Voltage

vs Temperature

INTV_CCvs Load Current

5.20

5.15

5.10

2.3

V

= 12V

IN

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

ARMING THRESHOLD

EXTV = 0V

CC

5.05

5.00

4.95

LATCHOFF THRESHOLD

EXTV = 8V

CC

0

20 40 60 80 100 120 140 160 180 200

–45

5

30

55

80 105 130

–20

TEMPERATURE (°C)

LOAD CURRENT (mA)

3858 G26

3858 G27

PIN FUNCTIONS ^(QFN/SSOP)

–

LTC3858-1 operates at light loads. Pulling this pin to

ground selects Burst Mode operation. An internal 100k

resistor to ground also invokes Burst Mode operation

SENSE1 , SENSE2 (Pin 2, Pin 8/Pin 4, Pin 10): The (–)

InputtotheDifferentialCurrentComparators.Whengreater

–

than INTV – 0.5V, the SENSE pin supplies current to

CC

when the pin is ﬂoated. Tying this pin to INTV forces

the current comparator.

CC

continuous inductor current operation. Tying this pin to

FREQ (Pin 3/Pin 5): The Frequency Control Pin for the

Internal Voltage-Contolled Oscillator (VCO). Connecting

this pin to GND forces the VCO to a ﬁxed low frequency

a voltage greater than 1.2V and less than INTV – 1.3V

CC

selects pulse-skipping operation.

SGND (Pin 5, Exposed Pad Pin 29/Pin 7): Small-signal

ground common to both controllers, must be routed

separately from high current grounds to the common (–)

of 350kHz. Connecting this pin to INTV forces the VCO

CC

to a ﬁxed high frequency of 535kHz. Other frequencies

between 50kHz and 900kHz can be programmed using a

resistor between FREQ and GND. An internal 20μA pull-

up current develops the voltage to be used by the VCO to

control the frequency

terminals of the C capacitors. The exposed pad (QFN

IN

only) must be soldered to the PCB for rated thermal

performance.

RUN1, RUN2 (Pin 6, Pin 7/Pin 8, Pin 9): Digital Run

Control Inputs for Each Controller. Forcing either of these

pinsbelow1.2Vshutsdownthatcontroller.Forcingbothof

these pins below 0.7V shuts down the entire LTC3858-1,

reducing quiescent current to approximately 8μA. Do NOT

ﬂoat these pins.

PLLIN/MODE (Pin 4/Pin 6): External Synchronization

Input to Phase Detector and Forced Continuous Mode

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG1 signal to be

synchronized with the rising edge of the external clock.

When not synchronizing to an external clock, this input,

which acts on both controllers, determines how the

38581fd

8

LTC3858-1

PIN FUNCTIONS ^(QFN/SSOP)

INTV (Pin 17/Pin 19): Output of the Internal Linear Low

TG1, TG2 (Pin 24, Pin 13/Pin 26, Pin 15): High Current

Gate Drives for Top N-Channel MOSFETs. These are the

outputs of ﬂoating drivers with a voltage swing equal to

CC

Dropout Regulator. The driver and control circuits are

powered from this voltage source. Must be decoupled to

power ground with a minimum of 4.7μF ceramic or other

INTV – 0.5V superimposed on the switch node voltage

CC

low ESR capacitor. Do not use the INTV pin for any

SW.

CC

other purpose.

PGOOD1 (Pin 25/Pin 27): Open-Drain Logic Output.

EXTV (Pin 18/Pin 20): External Power Input to an

PGOOD1 is pulled to ground when the voltage on the V

pin is not within 10% of its set point.

CC

FB1

Internal LDO Connected to INTV . This LDO supplies

CC

INTV power, bypassing the internal LDO powered from

CC

SS1, SS2 (Pin 26, Pin 12/Pin 28, Pin 14): External Soft-

V

whenever EXTV is higher than 4.7V. See EXTV

IN

CC CC

Start Input. The LTC3858-1 regulates the V

voltage

FB1,2

Connection in the Applications Information section. Do

to the smaller of 0.8V or the voltage on the SS1,2 pin. An

internal 1μA pull-up current source is connected to this

pin. A capacitor to ground at this pin sets the ramp time

to ﬁnal regulated output voltage. This pin is also used as

the short-circuit latchoff timer.

not exceed 14V on this pin.

PGND (Pin 19/Pin 21): Driver Power Ground. Connects to

thesourcesofbottom(synchronous)N-channelMOSFETs

and the (–) terminal(s) of C .

IN

V

(Pin 20/Pin 22): Main Input Supply Pin. A bypass

I

, I

(Pin 27, Pin 11/Pin 1, Pin 13): Error Ampliﬁer

IN

TH1 TH2

capacitor should be tied between this pin and the signal

Outputs and Switching Regulator Compensation Points.

Each associated channel’s current comparator trip point

increases with this control voltage.

ground pin.

BG1, BG2 (Pin 21, Pin 16/Pin 23, Pin 18): High Current

Gate Drives for Bottom (Synchronous) N-Channel

MOSFETs. Voltage swing at these pins is from ground

V

, V

FB1 FB2

(Pin 28, Pin 10/Pin 2, Pin 12): Receives the

remotelysensedfeedbackvoltageforeachcontrollerfrom

an external resistive divider across the output.

to INTV .

CC

+

BOOST1, BOOST2 (Pin 22, Pin 15/Pin 24, Pin 17):

Bootstrapped Supplies to the Topside Floating Drivers.

CapacitorsareconnectedbetweentheBOOSTandSWpins

SENSE1 , SENSE2 (Pin 1, Pin 9/Pin 3, Pin 11): The

(+) input to the differential current comparators that are

normally connected to inductor DCR sensing networks

andSchottkydiodesaretiedbetweentheBOOSTandINTV

or current sensing resistors. The I pin voltage and

CC

TH

–

+

pins. Voltage swing at the BOOST pins is from INTV to

controlledoffsetsbetweentheSENSE andSENSE pinsin

CC

(V + INTV ).

conjunction with R

set the current trip threshold.

IN

CC

SENSE

SW1, SW2 (Pin 23, Pin 14/Pin 25, Pin 16): Switch Node

Connections to Inductors.

38581fd

9

LTC3858-1

FUNCTIONAL DIAGRAM

INTV

V

IN

CC

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

BOOST

D

B

C

B

TG

DROP

OUT

DET

TOP

BOT

+

C

IN

PGOOD1

0.88V

D

BOT

–

SW

TOP ON

V

S

R

Q

FB1

+

INTV

CC

Q

–

SWITCH

LOGIC

0.72V

BG

SHDN

C

OUT

PGND

20μA

FREQ

V

OUT

VCO

CLK2

CLK1

+

–

R

SENSE

0.425V

SLEEP

L

ICMP

IR

+

–

+

–

PFD

+

–

+

3mV

SENSE

SYNC

DET

2(V

)

FB

0.45V

PLLIN/MODE

–

100k

SLOPE COMP

V

FB

R

B

+

V

IN

0.80V

TRACK/SS

EA

–

R

A

EXTV

CC

+

–

OV

C

0.88V

I

TH

5.1V

LDO

EN

5.1V

LDO

EN

0.5μA

11V

SHDN

RST

FB

C

C2

R

C

FOLDBACK

+

–

2(V

)

1μA

4.7V

SS

SGND

INTV

RUN

CC

SHORT CKT

LATCHOFF

C

SS

SHDN

10μA

38581 FD

OPERATION

Main Control Loop

the V pin (which is generated with an external resistor

FB

divider connected across the output voltage, V , to

OUT

The LTC3858-1 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating 180 degrees out of phase. During normal op-

eration, each external top MOSFET is turned on when the

clock for that channel sets the RS latch, and is turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP trips and

ground)totheinternal0.800Vreferencevoltage.Whenthe

load current increases, it causes a slight decrease in V

FB

relative to the reference, which causes the EA to increase

the I voltage until the average inductor current matches

TH

the new load current.

After the top MOSFET is turned off each cycle, the bottom

MOSFETisturnedonuntileithertheinductorcurrentstarts

to reverse, as indicated by the current comparator IR, or

the beginning of the next clock cycle.

resets the latch is controlled by the voltage on the I pin,

TH

which is the output of the error ampliﬁer, EA. The error

ampliﬁer compares the output voltage feedback signal at

38581fd

10

LTC3858-1

OPERATION ^{(Refer to the Functional Diagram)}

INTV /EXTV Power

internal reference, the LTC3858-1 regulates the V volt-

CC

FB

age to the SS pin voltage instead of the 0.8V reference.

This allows the SS pin to be used to program a soft-start

by connecting an external capacitor from the SS pin to

SGND. An internal 1μA pull-up current charges this ca-

pacitor creating a voltage ramp on the SS pin. As the SS

voltage rises linearly from 0V to 0.8V (and beyond up to

the absolute maximum rating of 6V), the output voltage

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.When

CC

the EXTV pin is left open or tied to a voltage less than

CC

4.7V, the V LDO (low dropout linear regulator) supplies

IN

5.1V from V to INTV . If EXTV is taken above 4.7V,

IN

CC

theV LDOisturnedoffandtheEXTV LDOisturnedon.

IN

CC

Onceenabled,theEXTV LDOsupplies5.1VfromEXTV

CC

V

rises smoothly from zero to its ﬁnal value.

OUT

to INTV . Using the EXTV pin allows the INTV power

CC

to be derived from a high efﬁciency external source such

as one of the LTC3858-1 switching regulator outputs.

Short-Circuit Latch-Off

After the controller has been started and been given

adequate time to ramp up the output voltage, the SS

capacitor is used in a short-circuit time-out circuit. Spe-

ciﬁcally, once the voltage on the SS pin rises above 2V

(the arming threshold), the short-circuit timeout circuit is

enabled (see Figure 1). If the output voltage falls below

70% of its nominal regulated voltage, the SS capacitor

begins discharging with a net 9μA pull-down current on

the assumption that the output is in an overcurrent and/or

short-circuit condition. If the condition lasts long enough

to allow the SS pin voltage to fall below 1.5V (the latchoff

threshold) , the controller will shut down (latch off) until

Each top MOSFET driver is biased from the ﬂoating boot-

strap capacitor, C , which normally recharges during each

B

switching cycle through an external diode when the top

MOSFET turns off. If the input voltage V decreases to

IN

a voltage close to V , the loop may enter dropout and

OUT

attempt to turn on the top MOSFET continuously. The

dropout detector detects this and forces the top MOSFET

off for about one-twelfth of the clock period every tenth

cycle to allow C to recharge.

B

Shutdown and Start-Up (RUN1, RUN2 and

SS1, SS2 Pins)

the RUN pin voltage or the V voltage is recycled.

IN

The two channels of the LTC3858-1 can be independently

shutdownusingtheRUN1andRUN2pins.Pullingeitherof

these pins below 1.26V shuts down the main control loop

for that controller. Pulling both pins below 0.7V disables

both controllers and most internal circuits, including the

The delay time from when an short-circuit occurs until

the controller latches off can be calculated using the fol-

lowing equation:

V_SS– 1.5V

t_LATCH≈ C_SS

9μA

INTV LDOs. In this state, the LTC3858-1 draws only 8μA

CC

of quiescent current.

where V is the initial voltage (must be greater than 2V)

SS

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V on this pin. The RUN pin has an internal 11V voltage

clamp that allows the RUN pin to be connected through a

ontheSSpinatthetimetheshort-circuitoccurs. Normally

the SS pin voltage will have been pulled up to the INTV

voltage (5.1V) by the internal 1μA pull-up current.

CC

Note that the two controllers on the LTC3858-1 have

separate, independent short-circuit latchoff circuits.

Latchoff can be overridden/defeated by connecting a

resistor to a higher voltage (for example, V ), so long as

IN

the maximum current into the RUN pin does not exceed

100μA.

resistor 150k or less from the SS pin to INTV . This

CC

resistor provides enough pull-up current to overcome the

9μApull-downcurrentpresentduringashort-circuit.Note

that this resistor also shortens the soft-start period.

The start-up of each controller’s output voltage V

controlled by the voltage on the SS pin for that channel.

When the voltage on the SS pin is less than the 0.8V

is

OUT

38581fd

11

LTC3858-1

OPERATION ^{(Refer to the Functional Diagram)}

INTV

CC

WhenacontrollerisenabledforBurstModeoperation, the

minimum peak current in the inductor is set to approxi-

mately 30% of the maximum sense voltage even though

SS VOLTAGE

2V

1.5V

the voltage on the I pin indicates a lower value. If the

0.8V

TH

average inductor current is higher than the load current,

LATCHOFF

COMMAND

the error ampliﬁer, EA, will decrease the voltage on the I

TH

pin. When the I voltage drops below 0.425V, the internal

TH

0V

SS PIN

CURRENT

sleep signal goes high (enabling “sleep” mode) and both

external MOSFETs are turned off.

1μA

–9μA

OUTPUT

VOLTAGE

In sleep mode, much of the internal circuitry is turned off,

reducingthequiescentcurrent.Ifonechannelisshutdown

and the other channel is in sleep mode, the LTC3858-1

draws only 170μA of quiescent current. If both channels

areinsleepmode,theLTC3858-1drawsonly300μAofqui-

escent current. In sleep mode, the load current is supplied

by the output capacitor. As the output voltage decreases,

the EA’s output begins to rise. When the output voltage

38581 F01

LATCHOFF

ENABLE

ARMING

SOFT-START INTERVAL

t

LATCH

Figure 1. Latchoff Timing Diagram

Foldback Current

drops enough, the I pin is reconnected to the output

TH

of the EA, the sleep signal goes low, and the controller

resumes normal operation by turning on the top external

MOSFET on the next cycle of the internal oscillator.

On the other hand, when the output voltage falls to less

than 70% of its nominal level, foldback current limiting

is also activated, progressively lowering the peak current

limit in proportion to the severity of the overcurrent or

short-circuit condition. Even if a short-circuit is present

and the short-circuit latchoff is not yet enabled (when

SS voltage has not yet reached 2V), a safe, low output

current is provided due to internal current foldback and

actual power wasted is low due to the efﬁcient nature of

the current mode switching regulator. Foldback current

limiting is disabled during the soft-start interval (as long

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator, IR, turns off the bottom external

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative. Thus,

the controller is in discontinuous operation.

In forced continuous operation or when clocked by an

external clock source to use the phase-locked loop (see

Frequency Selection and Phase-Locked Loop section),

the inductor current is allowed to reverse at light loads

or under large transient conditions. The peak inductor

as the V voltage is keeping up with the SS voltage).

FB

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Forced Continuous Conduction)

(PLLIN/MODE Pin)

current is determined by the voltage on the I pin, just

TH

as in normal operation. In this mode, the efﬁciency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantages of lower output

voltage ripple and less interference to audio circuitry. In

forced continuous mode, the output ripple is independent

of load current.

The LTC3858-1 can be enabled to enter high efﬁciency

Burst Mode operation, constant frequency pulse-skipping

mode, or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to ground. To select forced continuous opera-

tion, tie the PLLIN/MODE pin to INTV . To select pulse-

CC

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3858-1 operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

skipping mode, tie the PLLIN/MODE pin to a DC voltage

greater than 1.2V and less than INTV – 1.3V.

CC

38581fd

12

LTC3858-1

OPERATION ^{(Refer to the Functional Diagram)}

operation is maintained down to approximately 1% of

designedmaximumoutputcurrent. Atverylightloads, the

current comparator, ICMP, may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference when compared to Burst Mode

operation. It provides higher light load efﬁciency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

is applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

pre-bias the loop ﬁlter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

The typical capture range of the phase-locked loop is

from approximately 55kHz to 1MHz, with a guarantee

over all manufacturing variations to be between 75kHz

and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling).

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Output Overvoltage Protection

An overvoltage comparator guards against transient over-

shoots as well as other more serious conditions that may

The selection of switching frequency is a tradeoff between

efﬁciency and component size. Low frequency opera-

tion increases efﬁciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

overvoltage the output. When the V pin rises by more

FB

than 10% above its regulation point of 0.800V, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

The switching frequency of the LTC3858-1’s controllers

can be selected using the FREQ pin.

Power Good (PGOOD) Pin

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

The PGOOD1 pin is connected to an open drain of an

internal N-channel MOSFET. The MOSFET turns on and

INTV orprogrammedthroughanexternalresistor. Tying

CC

pullsthePGOOD1pinlowwhenthecorrespondingV pin

FB1

FREQ to SGND selects 350kHz while tying FREQ to INTV

CC

voltage is not within 10% of the 0.8V reference voltage.

selects 535kHz. Placing a resistor between FREQ and

SGND allows the frequency to be programmed between

50kHz and 900kHz.

The PGOOD1 pin is also pulled low when the RUN1 pin

is low (shut down). When the V pin voltage is within

FB1

the 10% requirement, the MOSFET is turned off and the

pin is allowed to be pulled up by an external resistor to a

source no greater than 6V.

A phase-locked loop (PLL) is available on the LTC3858-1

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

phase detector adjusts the voltage (through an internal

lowpass ﬁlter) of the VCO input to align the turn-on of

controller 1’s external top MOSFET to the rising edge of

the synchronizing signal. Thus, the turn-on of controller

2’s external top MOSFET is 180 degrees out of phase to

the rising edge of the external clock source.

Theory and Beneﬁts of 2-Phase Operation

Why the need for 2-phase operation? Up until the

2-phasefamily, constantfrequencydualswitchingregula-

tors operated both channels in phase (i.e., single phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

The VCO input voltage is pre-biased to the operating

frequency set by the FREQ pin before the external clock

38581fd

13

LTC3858-1

OPERATION ^{(Refer to the Functional Diagram)}

pulses increased the total RMS current ﬂowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V (Duty Cycle = V /V ). Figure 3 shows how

IN

OUT IN

theRMSinputcurrentvariesforsingle-phaseand2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

With 2-phase operation, the two channels of the dual

switchingregulatorareoperated180degreesoutofphase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

together. The result is a signiﬁcant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁciency.

It can readily be seen that the advantages of 2-phase op-

eration are not just limited to a narrow operating range,

for most applications is that 2-phase operation will reduce

theinputcapacitorrequirementtothatforjustonechannel

operating at maximum current and 50% duty cycle.

Figure2comparestheinputwaveformsforarepresentative

single phase dual switching regulator to the LTC3858-1

2-phase dual switching regulator. An actual measure-

ment of the RMS input current under these conditions

shows that 2-phase operation dropped the input current

3.0

SINGLE PHASE

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

from 2.53A

to 1.55A

. While this is an impressive

RMS

2-PHASE

DUAL CONTROLLER

reduction in itself, remember that the power losses are

2

proportionaltoI

,meaningthattheactualpowerwasted

RMS

is reduced by a factor of 2.66. The reduced input ripple

voltage also means less power is lost in the input power

path, which could include batteries, switches, trace/con-

nectorresistancesandprotectioncircuitry.Improvements

inbothconductedandradiatedEMIalsodirectlyaccrueas

a result of the reduced RMS input current and voltage.

V

= 5V/3A

O1

O2

= 3.3V/3A

0

10

20

30

40

INPUT VOLTAGE (V)

3858 F03

Figure 3. RMS Input Current Comparison

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

38581 F01

I

= 2.53A

I = 1.55A

IN(MEAS) RMS

IN(MEAS)

RMS

Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efﬁciency

38581fd

14

LTC3858-1

APPLICATIONS INFORMATION

The Typical Application on the ﬁrst page is a basic

LTC3858-1applicationcircuit.LTC3858-1canbeconﬁgured

to use either DCR (inductor resistance) sensing or low

value resistor sensing. The choice between the two cur-

rent sensing schemes is largely a design tradeoff between

cost, power consumption and accuracy. DCR sensing is

becoming popular because it saves expensive current

sensing resistors and is more power efﬁcient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

programmed current limit unpredictable. If inductor DCR

sensing is used (Figure 5b), resistor R1 should be placed

closetotheswitchingnode,topreventnoisefromcoupling

into sensitive small-signal nodes.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

38581 F04

INDUCTOR OR R

SENSE

Figure 4. Sense Lines Placement with Inductor or Sense Resistor

R

(if R

is used) and inductor value. Next, the

SENSE

V

IN

powerMOSFETsandSchottkydiodesareselected. Finally,

input and output capacitors are selected.

INTV

CC

BOOST

TG

+

–

SENSE and SENSE Pins

SW

V

OUT

+

–

LTC3858-1

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode voltage range on these

pins is 0V to 28V (Abs Max), enabling the LTC3858-1 to

regulate output voltages up to a nominal 24V (allowing

margin for tolerances and transients).

BG

+

SENSE

PLACE CAPACITOR NEAR

SENSE PINS

–

SENSE

SGND

+

38581 F05a

The SENSE pin is high impedance over the full common

mode range, drawing at most 1μA. This high impedance

allows the current comparators to be used in inductor

DCR sensing.

(5a) Using a Resistor to Sense Current

V

INTV

V

IN

–

The impedance of the SENSE pin changes depending on

CC

–

the common mode voltage. When SENSE is less than

INDUCTOR

DCR

BOOST

TG

INTV – 0.5V, a small current of less than 1μA ﬂows out

CC

L

–

of the pin. When SENSE is above INTV + 0.5V, a higher

CC

SW

V

OUT

LTC3858-1

current(~550μA)ﬂowsintothepin.BetweenINTV –0.5V

CC

BG

andINTV +0.5V, thecurrenttransitionsfromthesmaller

CC

R1

C1* R2

current to the higher current.

+

SENSE

Filter components mutual to the sense lines should be

placed close to the LTC3858-1, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 4). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

–

SENSE

SGND

38581 F05b

R2

R1 + R2

L

DCR

||

(R1 R2) • C1 =

*PLACE C1 NEAR

SENSE PINS

R

= DCR

SENSE(EQ)

(5b) Using the Inductor DCR to Sense Current

Figure 5. Current Sensing Methods

38581fd

15

LTC3858-1

APPLICATIONS INFORMATION

Low Value Resistors Current Sensing

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult the

manufacturers’ data sheets for detailed information.

A typical sensing circuit using a discrete resistor is shown

in Figure 5a. R

output current.

is chosen based on the required

SENSE

Using the inductor ripple current value from the Inductor

Value Calculation section, the target sense resistor value

is:

The current comparator has a maximum threshold

of 50mV (typ). The current comparator

V

SENSE(MAX)

threshold voltage sets the peak of the inductor current,

yielding a maximum average output current, I , equal

V_SENSE(MAX)

R_SENSE(EQUIV)

=

MAX

ΔI_L

to the peak value less half the peak-to-peak ripple current,

I_MAX+

2

∆I .Tocalculatethesenseresistorvalue,usetheequation:

L

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimum value for the Maximum Current Sense Thresh-

V_SENSE(MAX)

R_SENSE

=

ΔI_L

2

I_MAX

+

old Voltage (V

table.

) in the Electrical Characteristics

SENSE(MAX)

When using the controller in very low dropout conditions,

themaximumoutputcurrentlevelwillbereducedduetothe

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor.AcurveisprovidedintheTypicalPerformanceChar-

acteristicssectiontoestimatethisreductioninpeakoutput

current depending upon the operating duty factor.

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefﬁcient of copper, which is approximately 0.4%/°C.

A conservative value for T

is 100°C.

L(MAX)

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

Inductor DCR Sensing

R_SENSE(EQUIV)

For applications requiring the highest possible efﬁciency

at high load currents, the LTC3850 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 5b. The DCR of the inductor represents the small

amount of DC resistance of the copper wire, which can be

lessthan1mꢁfortoday’slowvalue,highcurrentinductors.

In a high current application requiring such an inductor,

power loss through a sense resistor would cost several

points of efﬁciency compared to inductor DCR sensing.

R_D=

DCR_MAXatT

L(MAX)

C1 is usually selected to be in the range of 0.1μF to 0.47μF.

This forces R1||R2 to around 2k, reducing error that might

have been caused by the SENSE pin’s 1μA current.

+

The equivalent resistance R1||R2 is scaled to the room

temperature inductance and maximum DCR:

L

R1|| R2 =

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external ﬁlter components, the

DCR of the inductor must be known. It can be measured

DCR at 20°C • C1

(

)

The sense resistor values are:

R1|| R2

R_D

R1• R_D

1– R_D

R1=

; R2 =

38581fd

16

LTC3858-1

APPLICATIONS INFORMATION

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

30% of the current limit determined by R

. Lower

SENSE

inductor values (higher ∆I ) will cause this to occur at

L

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

V

_IN(MAX)– V_OUT• V

(

)

OUT

P

LOSS

R1=

R1

Ensure that R1 has a power rating higher than this value.

If high efﬁciency is necessary at light loads, consider

this power loss when deciding to use inductor DCR

sensing or sense resistors. Light load power loss can be

modestly higher with a DCR network than with a sense

resistor,duetotheextraswitchinglossesincurredthrough

R1. However, DCR sensing eliminates a sense resistor,

reduces conduction losses and provides higher efﬁciency

at heavy loads. Peak efﬁciency is about the same with

either method.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

ﬁxedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Inductor Value Calculation

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁciency. A higher

frequency generally results in lower efﬁciency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Power MOSFET and Schottky Diode

(Optional) Selection

Theinductorvaluehasadirecteffectonripplecurrent.The

Two external power MOSFETs must be selected for each

controller in the LTC3858-1: one N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

inductor ripple current ∆I decreases with higher induc-

L

tance or higher frequency and increases with higher V :

IN

⎛

⎞

⎟

⎠

V_OUT

V

1

ΔI_L=

V_OUT1–

⎜

f L

( )( )

⎝

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

IN

CC

This voltage is typically 5.1V during start-up (see EXTV

CC

Accepting larger values of ∆I allows the use of low

Pin Connection). Consequently, logic-level threshold

L

inductances, but results in higher output voltage ripple

MOSFETs must be used in most applications. The only

and greater core losses. A reasonable starting point for

exception is if low input voltage is expected (V < 4V);

IN

GS(TH)

DSS

setting ripple current is ∆I = 0.3(I

). The maximum

MAX

then, sub-logic level threshold MOSFETs (V

< 3V)

speci-

L

∆I occurs at the maximum input voltage.

should be used. Pay close attention to the BV

L

ﬁcation for the MOSFETs as well; many of the logic-level

MOSFETs are limited to 30V or less.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

38581fd

17

LTC3858-1

APPLICATIONS INFORMATION

Selection criteria for the power MOSFETs include the on-

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

resistance, R

, Miller capacitance, C , input

DS(ON) MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

C

MILLER

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

The term (1+ δ) is generally given for a MOSFET in the

MILLER

form of a normalized R

vs Temperature curve, but

DS(ON)

along the horizontal axis while the curve is approximately

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

ﬂat divided by the speciﬁed change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

TheoptionalSchottkydiodesD1andD2showninFigure 10

conduct during the dead-time between the conduction of

the two power MOSFETs. This prevents the body diode of

thebottomMOSFETfromturningon,storingchargeduring

the dead-time and requiring a reverse recovery period that

to the gate charge curve speciﬁed V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

V

IN

Main Switch Duty Cycle =

could cost as much as 3% in efﬁciency at high V . A 1A

IN

V − V

to 3A Schottky is generally a good compromise for both

regions of operation due to the relatively small average

current.Largerdiodesresultinadditionaltransitionlosses

due to their larger junction capacitance.

IN

OUT

Synchronous Switch Duty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

C and C

Selection

IN

OUT

V_OUT

2

The selection of C is simpliﬁed by the 2-phase architec-

P_MAIN

=

I

1+ δ R

+

IN

(

_MAX) (

)

DS(ON)

V

ture and its impact on the worst-case RMS current drawn

throughtheinputnetwork(battery/fuse/capacitor).Itcanbe

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with

IN

⎛

⎞

⎟

⎠

2

I_MAX

2

V

R

C

•

⎜

(

)

(

_DR)(

)

IN

MILLER

⎝

⎡

⎢

⎣

⎤

1

the highest (V )(I ) product needs to be used in the

OUT OUT

+

f

( )

⎥

⎦

formula shown in Equation 1 to determine the maximum

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The out-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

V

_INTVCC– V_THMINV_THMIN

V – V_OUT

2

IN

P

=

I

1+ δ R

(

_MAX) (

)

SYNC

DS(ON)

V

IN

where δ is the temperature dependency of R

and

DS(ON)

R

(approximately 2ꢁ) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

is the

THMIN

typical MOSFET minimum threshold voltage.

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

OUT

IN

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

which are highest at high input voltages. For V < 20V

IN

the high current efﬁciency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

1/2

⎦

I_MAX

⎡

⎤

increasetothepointthattheuseofahigherR

device

C_INRequired I_RMS

≈

V

V – V

(1)

DS(ON)

(

_OUT)(

)

IN

OUT

⎣

V

IN

withlowerC

actuallyprovideshigherefﬁciency.The

MILLER

38581fd

18

LTC3858-1

APPLICATIONS INFORMATION

Equation 1 has a maximum at V = 2V , where I

where f is the operating frequency, C

is the output

IN

OUT

RMS

OUT

= I /2. This simple worst-case condition is commonly

capacitance and ∆I is the ripple current in the inductor.

OUT

L

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operatingfrequencyoftheLTC3858-1, ceramiccapacitors

The output ripple is highest at maximum input voltage

since ∆I increases with input voltage.

L

Setting Output Voltage

The LTC3858-1 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, as shown in Figure 6. The regulated output voltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

⎛

⎞

⎟

⎠

if there is any question.

R_B

R_A

V_OUT= 0.8V 1+

⎜

⎝

The beneﬁt of the 2-phase operation can be calculated

by using Equation 1 for the higher power controller and

then calculating the loss that would have resulted if both

controller channels switched on at the same time. The

total RMS power lost is lower when both controllers are

operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall beneﬁt of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efﬁciency testing.

The sources of the top MOSFETs should be placed within

To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

B

C

FF

1/2 LTC3858-1

V

FB

R

A

38581 F05

Figure 6. Setting Output Voltage

Soft-Start (SS Pins)

The start-up of each V

is controlled by the voltage on

OUT

1cmofeachotherandshareacommonC (s). Separating

IN

the respective SS pin. When the voltage on the SS pin

is less than the internal 0.8V reference, the LTC3858-1

the sources and C may produce undesirable voltage and

IN

current resonances at V .

IN

regulates the V pin voltage to the voltage on the SS pin

FB

A small (0.1μF to 1μF) bypass capacitor between the chip

instead of 0.8V. The SS pin can be used to program an

V

pin and ground, placed close to the LTC3858-1, is

IN

external soft-start function.

also suggested. A 10ꢁ resistor placed between C (C1)

IN

Soft-startisenabledbysimplyconnectingacapacitorfrom

the SS pin to ground, as shown in Figure 7. An internal

1μA current source charges the capacitor, providing a

and the V pin provides further isolation between the

two channels.

IN

The selection of C

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement

1/2 LTC3858-1

SS

is satisﬁed, the capacitance is adequate for ﬁltering. The

C

SS

output ripple (∆V ) is approximated by:

OUT

SGND

⎛

⎞

⎟

⎠

38581 F06

1

ΔV_OUT≈ ΔI ESR+

⎜

L

8 • f • C_OUT

⎝

Figure 7. Using the SS Pin to Program Soft-Start

38581fd

19

LTC3858-1

APPLICATIONS INFORMATION

linear ramping voltage at the SS pin. The LTC3858-1 will

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current must be checked

while operating in forced continuous mode (PLLIN/MODE

regulate the V pin (and hence V ) according to the

FB

OUT

voltageontheSSpin, allowingV

torisesmoothlyfrom

OUT

0V to its ﬁnal regulated value. The total soft-start time will

= INTV ) at maximum V .

CC

IN

be approximately:

When the voltage applied to EXTV rises above 4.7V, the

CC

0.8V

1μA

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

t_SS= C_SS

•

EXTV LDO remains on as long as the voltage applied to

CC

EXTV remains above 4.5V. The EXTV LDO attempts

CC

INTV Regulators

to regulate the INTV voltage to 5.1V, so while EXTV

CC

is less than 5.1V, the LDO is in dropout and the INTV

The LTC3858-1 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power

voltage is approximately equal to EXTV . When EXTV

CC

is greater than 5.1V, up to an absolute maximum of 14V,

at the INTV pin from either the V supply pin or the

CC

IN

INTV is regulated to 5.1V.

CC

EXTV pin depending on the connection of the EXTV

CC

pin. INTV powers the gate drivers and much of the

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from one of the switching

regulator outputs (4.7V ≤ V_OUT≤ 14V) during normal

operation and from the V_INLDO when the output is out

ofregulation(e.g.,start-up,short-circuit).Ifmorecurrent

is required through the EXTV_CCLDO than is speciﬁed, an

externalSchottkydiodecanbeaddedbetweentheEXTV_CC

and INTV_CCpins. In this case, do not apply more than 6V

to the EXTV_CCpin and make sure that EXTV_CC≤ V_IN.

CC

internalcircuitry.TheV LDOandtheEXTV LDOregulate

IN

CC

INTV to 5.1V. Each of these can supply a peak current of

CC

50mA and must be bypassed to ground with a minimum

of 4.7μF low ESR capacitor. Regardless of what type of

bulkcapacitorisused, anadditional1μFceramiccapacitor

placed directly adjacent to the INTV and PGND IC pins is

CC

highlyrecommended.Goodbypassingisneededtosupply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between the channels.

Signiﬁcant efﬁciency and thermal gains can be realized

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the

maximum junction temperature rating for the LTC3858-1

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efﬁciency).

For 5V to 14V regulator outputs, this means connecting

to be exceeded. The INTV current, which is dominated

CC

by the gate charge current, may be supplied by either the

the EXTV pin directly to V . Tying the EXTV pin to

CC

OUT

CC

V

LDO or the EXTV LDO. When the voltage on the

a 8.5V supply reduces the junction temperature in the

IN

CC

EXTV pinislessthan4.7V,theV LDOisenabled.Power

previous example from 125°C to:

CC

IN

dissipation for the IC in this case is highest and is equal to

• I . The gate charge current is dependent on

T = 70°C + (15mA)(8.5V)(90°C/W) = 82°C

J

V

IN

INTVCC

However, for 3.3V and other low voltage outputs, addi-

operating frequency as discussed in the Efﬁciency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 2 of the

Electrical Characteristics. For example, the LTC3858-1

tional circuitry is required to derive INTV power from

CC

the output.

The following list summarizes the four possible connec-

INTV current is limited to less than 15mA from a 40V

CC

tions for EXTV :

CC

supplywhennotusingtheEXTV supplyat70°Cambient

CC

temperature in the SSOP package:

T = 70°C + (15mA)(40V)(90°C/W) = 125°C

J

38581fd

20

LTC3858-1

APPLICATIONS INFORMATION

1. EXTV LeftOpen(orGrounded).ThiswillcauseINTV

on, the boost voltage is above the input supply: V

=

CC

BOOST

to be powered from the internal 5.1V regulator result-

ing in an efﬁciency penalty of up to 10% at high input

voltages.

V + V

. The value of the boost capacitor, C , needs

IN

INTVCC

B

to be 100 times that of the total input capacitance of the

topsideMOSFET(s).Thereversebreakdownoftheexternal

Schottky diode must be greater than V

.

IN(MAX)

2. EXTV Connected Directly to V . This is the normal

CC

OUT

connection for a 5V to 14V regulator and provides the

When adjusting the gate drive level, the ﬁnal arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efﬁciency has

improved. If there is no change in input current, then there

is no change in efﬁciency.

highest efﬁciency.

3. EXTV_CCConnected to an External Supply. If an external

supply is available in the 5V to 14V range, it may be

used to power EXTV_CC. Ensure that EXTV_CC< V_IN.

4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.

Fault Conditions: Current Limit and Current Foldback

CC

For 3.3V and other low voltage regulators, efﬁciency

When the output current hits the current limit, the output

voltage begins to drop. If the output falls below 70% of its

nominal output level, then the maximum sense voltage is

progressively lowered to about one-half of its maximum

selected value. Under short-circuit conditions with very

low duty cycles, the LTC3858-1 will begin cycle skipping

in order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

gains can still be realized by connecting EXTV to an

CC

output-derivedvoltagethathasbeenboostedtogreater

than 4.7V. This can be done with the capacitive charge

pump shown in Figure 8. Ensure that EXTV < V .

CC

IN

V

IN

C

IN

BAT85

V

IN

current is determined by the minimum on-time, t

,

ON(MIN)

MTOP

MBOT

of the LTC3858-1 (≈90ns), the input voltage and inductor

value:

VN2222LL

TG1

1/2 LTC3858-1

L

R

SENSE

⎛

⎜

⎝

⎞

⎟

⎠

V

EXTV

SW

OUT

CC

V

L

IN

ΔI_L(SC)= t_ON(MIN)

C

D

BG1

OUT

The resulting average short-circuit current is:

38581 F08

PGND

50% •I

1

2

I_SC

=

^LIM(MAX)– ΔI_L(SC)

Figure 8. Capacitive Charge Pump for EXTV_CC

R_SENSE

Fault Conditions: Overvoltage Protection (Crowbar)

Topside MOSFET Driver Supply (C , D )

B

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to ﬂow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C in the Functional Diagram is charged though

B

external diode D from INTV when the SW pin is low.

B

CC

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate-source of the

B

desired MOSFET. This enhances the MOSFET and turns on

A comparator monitors the output for overvoltage condi-

tions. The comparator detects faults greater than 10%

the topside switch. The switch node voltage, SW, rises to

V and the BOOST pin follows. With the topside MOSFET

above the nominal output voltage. When this condition

IN

38581fd

21

LTC3858-1

APPLICATIONS INFORMATION

1000

900

800

700

600

500

400

300

200

100

0

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. The bottom MOSFET remains on continuously

for as long as the overvoltage condition persists; if V

OUT

returns to a safe level, normal operation automatically

resumes.

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kꢁ)

38581 F09

Phase-Locked Loop and Frequency Synchronization

Figure 9. Relationship Between Oscillator Frequency

and Resistor Value at the FREQ Pin

The LTC3858-1 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass ﬁlter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET

is thus 180 degrees out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

Typically, the external clock (on the PLLIN/MODE pin)

input high threshold is 1.6V, while the input low threshold

is 1.1V.

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired

synchronization frequency. The VCO’s input voltage is

prebiased at a frequency corresponding to the frequency

set by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock

and synchronization. Although it is not required that the

free-running frequency be near external clock frequency,

doingsowillpreventtheoperatingfrequencyfrompassing

through a large range of frequencies as the PLL locks.

If the external clock frequency is greater than the internal

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than f

,

OSC

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal ﬁlter capacitor,

Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor

DC Voltage

50kHz–900kHz

C , holds the voltage at the VCO input.

LP

Any of the Above

External Clock

Phase–Locked to

External Clock

Note that the LTC3858-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3858-1’s internal VCO, which is nominally 55kHz

to 1MHz. This is guaranteed to be between 75kHz and

850kHz.

38581fd

22

LTC3858-1

APPLICATIONS INFORMATION

Minimum On-Time Considerations

1. The V current is the DC input supply current given

IN

in the Electrical Characteristics table, which excludes

Minimum on-time, t

, is the smallest time dura-

ON(MIN)

MOSFET driver and control currents. V current typi-

IN

tion that the LTC3858-1 is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

cally results in a small (<0.1%) loss.

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

V_OUT

t_ON(MIN)

<

V

f

_IN( )

from INTV to ground. The resulting dQ/dt is a current

CC

out of INTV that is typically much larger than the

CC

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

the topside and bottom side MOSFETs.

SupplyingINTV fromanoutput-derivedpowersource

CC

Theminimumon-timefortheLTC3858-1isapproximately

95ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 130ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a signiﬁcant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

through EXTV will scale the V current required

CC

IN

for the driver and control circuits by a factor of (Duty

Cycle)/(Efﬁciency). Forexample, ina20Vto5Vapplica-

tion, 10mA of INTV current results in approximately

CC

2.5mA of V current. This reduces the midcurrent loss

IN

from 10% or more (if the driver was powered directly

from V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

R

, but is “chopped” between the topside MOSFET

SENSE

andthesynchronousMOSFET.IfthetwoMOSFETshave

approximately the same R

, then the resistance

DS(ON)

of one MOSFET can simply be summed with the resis-

2

tances of L, R

and ESR to obtain I R losses. For

= 30mꢁ, R = 50mꢁ, R

SENSE

example, if each R

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

DS(ON)

L

SENSE

= 10mꢁ and R

= 40mꢁ (sum of both input and

ESR

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

output capacitance losses), then the total resistance

is 130mꢁ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC3858-1 circuits: 1) IC V current, 2)

Efﬁciency varies as the inverse square of V

for the

IN

OUT

2

INTV regulatorcurrent,3)I Rlosses,4)topsideMOSFET

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

CC

transition losses.

38581fd

23

LTC3858-1

APPLICATIONS INFORMATION

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

be estimated by examining the rise time at the pin. The

I_THexternal components shown in Figure 12 circuit will

provide an adequate starting point for most applications.

The I series R -C ﬁlter sets the dominant pole-zero

TH

C

Transition Loss = (1.7) • V • 2 • I

• C • f

RSS

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

IN

O(MAX)

Other“hidden”lossessuchascoppertraceandinternal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

C has adequate charge storage and very low ESR at

IN

produce output voltage and I pin waveforms that will

TH

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mꢁ to 50mꢁ of ESR. The

LTC3858-1 2-phase architecture typically halves this

input capacitance requirement over competing solu-

tions.OtherlossesincludingSchottkyconductionlosses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a resistive load and a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

Checking Transient Response

is why it is better to look at the I pin signal which is in

TH

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

seriesresistanceofC_OUT. ∆I_LOADalsobeginstochargeor

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the I_THpin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC ﬁltered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reﬂects the closed-loop response. Assuming

apredominantlysecondordersystem,phasemarginand/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also

the feedback loop and is the ﬁltered and compensated

control loop response.

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

creasing C . If R is increased by the same factor that C

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

38581fd

24

LTC3858-1

APPLICATIONS INFORMATION

should be controlled so that the load rise time is limited

estimated. Choosing a Fairchild FDS6982S dual MOSFET

to approximately 25 • C

. Thus a 10μF capacitor would

results in: R

= 0.035ꢁ/0.022ꢁ, C

= 215pF. At

LOAD

DS(ON)

MILLER

require a 250μs rise time, limiting the charging current

to about 200mA.

maximum input voltage with T(estimated) = 50°C:

3.3V

22V

2

⎡

⎤

P_MAIN

=

6A 1+ 0.005 50°C – 25°C

(

)

(

)(

)

⎣

⎦

Design Example

²6A

As a design example for one channel, assume V

=

0.035Ω + 22V

2.5Ω 215pF •

(

) (

)

1

(

)(

)

IN

= 6A,

2

12V(nominal), V = 22V (max), V

= 3.3V, I

IN

OUT

MAX

⎡

⎤

1

V

= 50mV and f = 350kHz.

SENSE(MAX)

+

350kHz = 433mW

(

)

⎢

⎣

⎥

5V – 2.3V 2.3V

⎦

Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

A short-circuit to ground will result in a folded back cur-

rent of:

⎛

⎞

95ns 22V

(

)

25mV

0.006Ω 2

1

I_SC

=

–

= 3.9A

⎜

⎟

3.9μH

⎛

⎜

⎝

⎞

⎟

⎠

⎝

⎠

V_OUT

f L

( )( )

V_OUT

ΔI_L=

1–

V

IN

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

A 3.9μH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 6.88A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

MOSFET is:

2

P

= 3.9A 1.125 0.022Ω = 376mW

(

) (

)(

)

SYNC

which is less than full-load conditions.

maximum V :

IN

C is chosen for an RMS current rating of at least 3A at

IN

V_OUT

3.3V

temperature assuming only this channel is on. C

is

t_ON(MIN)

=

= 429ns

OUT

V

f

22V 350kHz

_IN( )

(

)

chosen with an ESR of 0.02ꢁ for low output ripple volt-

age. The output ripple in continuous mode will be highest

at the maximum input voltage. The output voltage ripple

due to ESR is approximately:

The equivalent R

resistor value can be calculated by

SENSE

using the minimum value for the maximum current sense

threshold (43mV):

V

= R (∆I ) = 0.02ꢁ(1.75A) = 35mV

ESR L P-P

ORIPPLE

43mV

6.88A

R_SENSE

≤

= 0.006Ω

PC Board Layout Checklist

Choosing0.5%resistors:R =24.9kandR =77.7kyields

A

B

an output voltage of 3.296V.

ThepowerdissipationonthetopsideMOSFETcanbeeasily

38581fd

25

LTC3858-1

APPLICATIONS INFORMATION

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layoutdiagramofFigure10.Figure11illustratesthecurrent

waveforms present in the various branches of the 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

from sensitive small-signal nodes, especially from the

opposites channel’s voltage and current sensing feed-

back pins. All of these nodes have very large and fast

moving signals and therefore should be kept on the

“output side” of the LTC3858-1 and occupy minimum

PC trace area.

7. Use a modiﬁed “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

connection at C ? Do not attempt to split the input

capacitors with tie-ins for the bottom of the INTV

IN

CC

decoupling for the two channels as it can cause a large

decouplingcapacitor,thebottomofthevoltagefeedback

resistive divider and the SGND pin of the IC.

resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequencyofoperationshouldbemaintainedovertheinput

voltage range down to dropout and until the output load

drops below the low current operation threshold—typi-

cally 10% of the maximum designed current level in Burst

Mode operation.

of C

must return to the combined C

(–) ter-

INTVCC

OUT

minals. The path formed by the top N-channel MOSFET,

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

3. Do the LTC3858-1 V pins’ resistive dividers connect

FB

to the (+) terminals of C ? The resistive divider

OUT

must be connected between the (+) terminal of C

OUT

and signal ground. The feedback resistor connections

should not be along the high current input feeds from

the input capacitor(s).

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regula-

tor bandwidth optimization is not required. Only after

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difﬁcult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Theﬁltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1μF ceramic capacitor placed

immediatelynexttotheINTV andPGNDpinscanhelp

CC

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), andboostnodes(BOOST1, BOOST2)away

38581fd

26

LTC3858-1

APPLICATIONS INFORMATION

SS1

LTC3858-1

I

R

TH1

PU1

V

PULL-UP

(<6V)

V

PGOOD1

TG1

PGOOD1

FB1

L1

R

SENSE

D1

+

–

V

SENSE1

FREQ

OUT1

SW1

C

B1

M1

M2

BOOST1

BG1

C

OUT1

V

f

IN

1μF

IN

PLLIN/MODE

RUN1

R

C

IN

VIN

CERAMIC

PGND

GND

RUN2

EXTV

CC

V

OUT1

C

IN

C

SGND

INTVCC

V

IN

–

INTV

CC

SENSE2

OUT2

D2

1μF

CERAMIC

+

BG2

SENSE2

M4

M3

BOOST2

V

FB2

TH2

C

B2

SW2

TG2

I

R

SENSE

V

OUT2

SS2

L2

38581 F10

Figure 10. Recommended Printed Circuit Layout Diagram

Reduce V from its nominal level to verify operation

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

IN

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

38581fd

27

LTC3858-1

APPLICATIONS INFORMATION

SW1

L1

R

SENSE1

V

OUT1

D1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38581 F11

Figure 11. Branch Current Waveforms

path voltage pickup between these components and the

SGND pin of the IC.

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

38581fd

28

LTC3858-1

TYPICAL APPLICATIONS

R

B1

215k

LTC3858-1

+

C

SENSE1

F1

INTV

CC

C1

1nF

15pF

100k

–

R

A1

68.1k

SENSE1

PGOOD1

BG1

L1

MBOT1

MTOP1

V

FB1

3.3μH

V

3.3V

5A

OUT1

C

ITH1A

150pF

SW1

R

C

SENSE1

7mꢁ

OUT1

B1

0.47μF

BOOST1

TG1

150μF

R

15k

SS1

ITH1

I

TH1

D1

D2

C

820pF

ITH1

C

0.1μF

V

IN

V

IN

9V TO 38V

C

IN

22μF

SS1

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

C

B2

0.47μF

BOOST2

L2

7.2μH

R

SENSE2

10mꢁ

C

0.1μF

SS2

V

8.5V

3A

OUT2

SW2

BG2

SS2

C

ITH2

680pF

OUT2

R

27k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

R

A2

44.2k

–

+

SENSE2

C

1nF

F2

39pF

SENSE2

R

B2

442k

38581 F12

C

, C : SANYO 10TPD150M

OUT1 OUT2

L1: SUMIDA CDEP105-3R2M

L2: SUMIDA CDEP105-7R2M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

Start-Up

SW Node Waveforms

Efﬁciency vs Output Current

100

90

V

80

OUT2

V

= 8.5V

V

= 3.3V

OUT

2V/DIV

OUT

70

SW1

5V/DIV

60

50

V

OUT1

2V/DIV

40

30

20

10

0

SW2

5V/DIV

V

= 12V

IN

Burst Mode OPERATION

0.1 10

OUTPUT CURRENT (A)

3858 F12c

3858 F12d

20ms/DIV

1μs/DIV

0.000010.0001 0.001 0.01

1

38581 F12b

Figure 12. High Efﬁciency Dual 8.5V/3.3V Step-Down Converter

38581fd

29

LTC3858-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 2.5V/3.3V Step-Down Converter

R

B1

143k

LTC3858-1

+

C

SENSE1

INTV

CC

F1

C1

1nF

22pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

68.1k

L1

2.4μH

MBOT1

MTOP1

V

FB1

V

2.5V

5A

OUT1

C

100pF

ITH1A

SW1

R

C

SENSE1

7mꢁ

OUT1

B1

BOOST1

TG1

150μF

0.47μF

R

ITH1

22k

I

TH1

D1

D2

C

820pF

ITH1

C

0.01μF

SS1

V

IN

V

IN

4V TO 38V

C

IN

SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

C

B2

BOOST2

0.47μF

L2

3.2μH

R

SENSE2

7mꢁ

C

0.01μF

SS2

V

3.3V

5A

OUT2

SW2

BG2

SS2

C

820pF

OUT2

ITH2

R

15k

150μF

ITH2

I

TH2

C

150pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

68.1k

C

1nF

F2

15pF

SENSE2

R

B2

215k

38581 F13

C

, C

: SANYO 10TPD150M

OUT1 OUT2

L1: SUMIDA CDEP105-2R5

L2: SUMIDA CDEP105-3R2M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

38581fd

30

LTC3858-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 12V/5V Step-Down Converter

R

B1

422k

+

C

SENSE1

INTV

F1

CC

C1

1nF

33pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

30.1k

L1

8.8μH

MBOT1

MTOP1

V

FB1

V

12V

3A

OUT1

C

100pF

ITH1A

SW1

R

C

SENSE1

OUT1

B1

BOOST1

TG1

10mꢁ

47μF

0.47μF

R

33k

ITH1

I

TH1

D1

D2

C

0.01μF

SS1

LTC3858-1

C

680pF

ITH1

V

IN

V

SS1

IN

12.5V TO 38V

C

IN

INTV

CC

C

22μF

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

4.3μH

R

SENSE2

7mꢁ

C

0.01μF

SS2

V

OUT2

5V

SW2

BG2

SS2

5.5A

C

680pF

OUT2

ITH2

R

17k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

C

: KEMET T525D476M016E035

: SANYO 10TPD150M

R

OUT1

OUT2

A2

–

+

SENSE2

C

75k

L1: SUMIDA CDEP105-8R8M

L2: SUMIDA CDEP105-4R3M

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

C

1nF

F2

15pF

SENSE2

R

B2

393k

38581 TA02a

38581fd

31

LTC3858-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 24V/5V Step-Down Converter

R

B1

487k

+

C

SENSE1

INTV

F1

CC

C1

1nF

18pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

16.9k

L1

22μH

MBOT1

MTOP1

V

FB1

V

24V

1A

OUT1

C

100pF

ITH1A

SW1

R

C

SENSE1

OUT1

B1

BOOST1

TG1

25mꢁ

22μF

25V

×2

0.47μF

R

46k

ITH1

I

TH1

D1

D2

C

0.01μF

SS1

CERAMIC

LTC3858-1

C

680pF

ITH1

V

IN

V

SS1

IN

24.5V TO 38V

C

IN

INTV

CC

C

4.7μF

22μF

INT

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

4.3μH

R

SENSE2

7mꢁ

C

0.01μF

SS2

V

5V

5A

OUT2

SW2

BG2

SS2

C

680pF

OUT2

ITH2

R

17k

150μF

ITH2

I

TH2

C

100pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

75k

C

: SANYO 10TPD150M

OUT2

L1: SUMIDA CDRH105R-220M

L2: SUMIDA CDEP105-4R3M

C

1nF

F2

15pF

SENSE2

MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP

R

B2

392k

38581 TA04

38581fd

32

LTC3858-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 1V/1.2V Step-Down Converter

R

B1

28.7k

+

C

SENSE1

F1

INTV

CC

C1

1nF

56pF

100k

–

R

A1

SENSE1

PGOOD1

BG1

115k

L1

0.47μH

MBOT1

MTOP1

V

FB1

V

OUT1

C

220pF

ITH1A

1V

SW1

C

R

OUT1 8A

C

SENSE1

4mꢁ

B1

BOOST1

TG1

220μF

0.47μF

R

ITH1

3.93k

×2

I

TH1

D1

D2

LTC3858-1

C

1000pF

ITH1

C

0.01μF

SS1

V

IN

V

IN

12V

C

IN

SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

60k

0.47μF

L2

0.47μH

R

SENSE2

4mꢁ

C

0.01μF

SS2

V

OUT2

1.2V

SW2

BG2

SS2

C

OUT2 8A

C

1000pF

ITH2

220μF

R

3.43k

ITH2

×2

I

TH2

C

220pF

C2

ITH2A

V

FB2

R

C

, C

: SANYO 2RSTPE220M

A2

OUT1 OUT2

–

+

SENSE2

115k

L1: SUMIDA CDEP105-3R2M

L2: SUMIDA CDEP105-7R2M

MTOP1, MTOP2: RENESAS RJK0305

MBOT1, MBOT2: RENESAS RJK0328

C

1nF

F2

56pF

SENSE2

R

B2

38581 TA03a

57.6k

38581fd

33

LTC3858-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 1V/1.2V Step-Down Converter with Inductor DCR Current Sensing

R

1.18k

B1

S1

28.7k

+

C

SENSE1

F1

INTV

CC

C1

0.1μF

56pF

100k

–

R

A1

PGOOD1

115k

L1

0.47μH

MBOT1

MTOP1

V

BG1

SW1

FB1

V

OUT1

C

200pF

ITH1A

1V

C

OUT1 8A

C

B1

BOOST1

TG1

220μF

0.47μF

R

3.93k

ITH1

×2

I

TH1

D1

D2

LTC3858-1

C

1000pF

ITH1

C

SS1

0.01μF

V

IN

V

IN

12V

C

IN

SS1

22μF

INTV

CC

C

INT

4.7μF

PGND

PLLIN/MODE

SGND

MTOP2

MBOT2

EXTV

TG2

CC

RUN1

RUN2

FREQ

R

C

FREQ

B2

BOOST2

65k

0.47μF

L2

0.47μH

C

0.01μF

SS2

V

OUT2

1.2V

SW2

BG2

SS2

C

OUT2 8A

C

1000pF

ITH2

220μF

R

3.93k

ITH2

×2

I

TH2

C

220pF

C2

ITH2A

V

FB2

R

A2

–

+

SENSE2

115k

C

, C

: SANYO 2R5TPE220M

OUT1 OUT2

L1, L2: SUMIDA IHL P2525CZERR47M06

MTOP1, MTOP2: RENESAS RJK0305

MBOT1, MBOT2: RENESAS RJK0328

C

0.1μF

F2

56pF

SENSE2

R

1.18k

S2

R

B2

57.6k

38581 TA05

38581fd

34

LTC3858-1

PACKAGE DESCRIPTION

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 p0.05

4.50 p 0.05

3.10 p 0.05

2.50 REF

2.65 p 0.05

3.65 p 0.05

PACKAGE

OUTLINE

0.25 p0.05

0.50 BSC

3.50 REF

4.10 p 0.05

5.50 p 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

s 45o CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 p 0.05

4.00 p 0.10

(2 SIDES)

27

28

0.40 p 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 p 0.10

(2 SIDES)

3.50 REF

3.65 p 0.10

2.65 p 0.10

(UFD28) QFN 0506 REV B

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

38581fd

35

LTC3858-1

PACKAGE DESCRIPTION

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 p.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 p .004

(0.38 p 0.10)

.0532 – .0688

(1.35 – 1.75)

s 45o

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0o – 8o TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

38581fd

36

LTC3858-1

REVISION HISTORY ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

11/09 Change to Absolute Maximum Ratings

Change to Electrical Characteristics

Change to Typical Performance Characteristics

Change to Pin Functions

2

3, 4

6

8, 9

Text Changes to Operation Section

Text Changes to Applications Information Section

Change to Table 2

11, 12, 13

20, 21, 22, 23, 25

22

Change to Figure 10

27

Changes to Related Parts

38

C

D

08/10 Changes to Electrical Characteristics

Added Typical Application to Back Page and Updated Related Parts

12/10 Changes to Electrical Characteristics

Changes to Pin Functions

3, 4

38

3

8, 9

Changes to Functional Diagram

10

Changes to Typical Applications

29 to 34, 38

38581fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

LTC3858-1

TYPICAL APPLICATION

High Efﬁciency 2-Phase 12V/150W Step-Down Converter

R

B1

698k

+

–

C

SENSE1

F1

INTV

CC

C1

1nF

10pF

100k

R

A1

PGOOD1

BG1

49.9k

L1

6μH

10μF

16V

MBOT1

MTOP1

V

FB1

V

OUT1

C

68pF

ITH1A

12V

SW1

C

R

OUT1

12.5A

C

SENSE1

5mꢁ

B1

BOOST1

TG1

22μF

16V

0.47μF

R

2.94k

ITH1

I

TH1

D1

D2

LTC3858-1

C

3300pF

ITH1

C

0.1μF

SS1

V

IN

V

IN

19V TO 28V

C

10μF

50V

IN

SS1

10μF

50V

INTV

CC

C

INT

4.7μF

PGND

TG2

PLLIN/MODE

SGND

MTOP2

MBOT2

V

EXTV

OUT

SS1

CC

RUN1

RUN2

FREQ

SS2

C

B2

L2

6μH

BOOST2

SW2

R

SENSE2

5mꢁ

0.47μF

C

OUT2

10μF

16V

22μF

16V

I

BG2

I

TH2

TH1

V

FB1

FB2

–

+

SENSE2

C

, C

: SANYO 16TQC22M

OUT1 OUT2

C2

1nF

L1, L2: SUMIDA CDEP106-6ROM

MTOP1, MTOP2: INFINEON BSZ097N04LS

MBOT1, MBOT2: INFINEON BSZ097N04LS

SENSE2

38581 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3859

Low I , Triple Output Buck/Buck/Boost Synchronous Outputs (≥5V) Remain in Regulation Through Cold Crank 2.5V ≤ V ≤ 38V,

Q

IN

DC/DC Controller

V

Up to 24V, V

Up to 60V, I = 55μA,

OUT(BUCKS)

OUT(BOOST) Q

LTC3868/LTC3868-1 Low I , Dual Output 2-Phase Synchronous Step-

Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ V ≤ 24V, 0.8V ≤ V ≤ 14V, I = 170μA

Q

Down DC/DC Controllers with 99% Duty Cycle

IN

OUT

Q

LTC3857/LTC3857-1 Low I , Dual Output 2-Phase Synchronous Step-

Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

4V≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50μA,

Q

Down DC/DC Controllers with 99% Duty Cycle

IN

OUT

Q

LTC3890/LTC3890-1 60V, Low I , Dual 2-Phase Synchronous Step-Down Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

Q

DC/DC Controller with 99% Duty Cycle

4V ≤ V ≤ 60V, 0.8V ≤ V

≤ 24V, I = 50μA,

OUT Q

IN

LTC3834/LTC3834-1 Low I , Synchronous Step-Down DC/DC Controllers Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,

Q

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, I = 30μA,

Q

IN

OUT

LTC3835/LTC3835-1 Low I , Synchronous Step-Down DC/DC Controllers Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,

Q

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, I = 80μA,

Q

IN

OUT

LT3845A

LTC3824

Low I , High Voltage Synchronous Step-Down

Adjustable Fixed Operating Frequency 100kHz to 500kHz, 4V ≤ V ≤ 60V,

IN

Q

DC/DC Controller

1.23V ≤ V

≤ 36V, I = 120μA, TSSOP-16

OUT Q

Low I , High Voltage DC/DC Controller, 100% Duty

Selectable Fixed 200kHz to 600kHz Operating Frequency 4V ≤ V ≤ 60V,

IN

Q

Cycle

0.8V ≤ V

≤ V , I = 40μA, MSOP-10E

OUT IN Q

38581fd

LT 1210 REV D • PRINTED IN USA

38 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3858IGN-1#TRPBF
厂家：	Linear
描述：	LTC3858-1 - Low IQ, Dual 2-Phase Synchronous Step-Down Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总38页 (文件大小：439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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