LTC3870 [Linear]
PolyPhase Step-Down Slave Controller for Digital Power System Management;
| 型号： | LTC3870 |
| 厂家： | 
Linear |
| 描述： | PolyPhase Step-Down Slave Controller for Digital Power System Management |
| 文件： | 总22页 (文件大小：911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3870
PolyPhase Step-Down
Slave Controller for Digital
Power System Management
DescripTion
FeaTures
The LTC®3870 is a PolyPhase® step-down slave control-
ler specially designed for multiphase operation with the
LTC3880familydigitalpowersystemmanagementDC/DC
controllers. It provides a small and cost effective solution
for supplying very large currents by cascading it with a
master controller. A peak current mode architecture pro-
vides the LTC3870 with excellent current sharing from
phase to phase and from chip to chip.
n
LTC3880 Family Phase Extender Supporting
LTC3880/3880-1, LTC3883/3883-1, LTC3886,
LTC3887 Master Controllers
n
Cascade with Multiple Chips for Very Large Current
Applications
n
Accurate PolyPhase Current Sharing
n
EXTV Capable of 5V to 14V Input
CC
n
n
n
n
n
n
n
Wide V Range: 4.5V to 60V
IN
Wide Output Voltage Range : 0.5V to 14V
CoherentlyworkingwiththeLTC3880family,theLTC3870
Wide SYNC Frequency Range: 100kHz to 1MHz
Pin Programmable of CCM/DCM Operation
Pin Programmable of Phase-Shift Control
2
doesnotrequireadditionalI Caddresses, anditsupports
all programmable features as well as fault protection.
The constant switching frequency can be synchronized
to an external clock from the master controller from
100kHz to 1MHz.
Integrated Powerful N-Channel MOSFET Gate Drivers
Available in a 28-Pin (4mm × 5mm) QFN Package
L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787,
6580258, 5408150
applicaTions
n
High Power Distributed Power Systems
Telecom Systems
n
n
Industrial Applications
Typical applicaTion
Load Transient Response of a
2-Phase Master (3880)/Slave
(3870) Converter
V
IN
4.7µF
V
IN
TG0
INTV
CC
TG1
I
LOAD
V
V
OUT0
30A
OUT1
40A
10A/DIV
BOOST0 BOOST1
1.0µH
0.56µH
0A TO 10A TO 0A
0.1µF
0.1µF
SW0
BG0
SW1
BG1
530µF
530µF
+
+
I
L_3880(CH1)
10A/DIV
2.15k
0.2µF
1.74k
0.2µF
PGND
EXTV
CC
LTC3870
I
L_3870(CH1)
10A/DIV
+
–
+
–
I
I
I
I
SENSE0
SENSE0
SENSE1
SENSE1
V
OUT1
100mV/DIV
AC-COUPLED
LTC3880*
RUN0
RUN0
RUN1
3.3V
RUN1
GPIO0
GPIO1
+
V
V
SENSE0
FAULT0
FAULT1
100k
3870 TA01b
FREQ
50µs/DIV
I
PHASMD
I
V
V
= 12V
1.8V
TH0
I
TH0
IN
OUT1
SENSE1
I
= 1.8V
LIM
TH1
I
TH1
SYNC
MODE0
MODE1
SGND
SYNC
* REFER TO LTC3880 DATA SHEET
FOR MASTER SETUP
3870 TA01a
3870fb
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For more information www.linear.com/LTC3870
LTC3870
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V ............................................................. –0.3V to 65V
IN
BOOST0, BOOST1.......................................–0.3V to 71V
SW0, SW1 .................................................... –5V to 65V
SENSE0 SENSE0 SENSE1 SENSE1
28 27 26 25 24 23
+
−
+
–
I
, I
, I
, I
..........–0.3V to 15V
MODE0
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
BOOST0
BG0
+
(BOOST0-SW0), (BOOST1-SW1) ................. –0.3V to 6V
I
I
SENSE0
–
INTV , RUN0/RUN1 ................................... –0.3V to 6V
V
SENSE0
CC
IN
29
SGND
RUN0
PGND
EXTV ...................................................... –0.3V to 14V
CC
RUN1
EXTV
INTV
CC
MODE0/MODE1, FREQ, PHASMD, I ...–0.3V to INTV
LIM
CC
–
I
I
SENSE1
CC
FAULT0/FAULT1, I /I , SYNC .............. –0.3V to 3.6V
TH0 TH1
+
BG1
BOOST1
SENSE1
INTV , EXTV Peak Current (Note 9) ...............100mA
CC
CC
MODE1
Operating Junction Temperature Range
9
10 11 12 13 14
UFD PACKAGE
.......................................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
28-LEAD (4mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 43°C/W, θ = 3.4°C/W
JMAX
JA
JC_BOT
EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3870EUFD#PBF
LTC3870IUFD#PBF
TAPE AND REEL
PART MARKING*
3870
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3870EUFD#TRPBF
LTC3870IUFD#TRPBF
–40°C to 125°C
–40°C to 125°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
3870
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, VRUN0, RUN1 = 3.3V, fSYNC = 350kHz
V
(externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
(Note 3)
MIN
4.5
TYP
MAX
60
UNITS
V
V
Input Voltage Range
Output Voltage Range
V
V
IN
(Note 4)
0.5
14
OUT
I
Q
Input Voltage Supply Current
Normal Operation
V
V = 0V (Note 5)
RUN0, RUN1
1.1
2.6
mA
mA
V
V
= 3.3V, No Caps on TG and BG
RUN0, RUN1
V
UVLO
Undervoltage Lockout Threshold
V
V
Falling
Rising
3.7
4.0
V
V
INTVCC
INTVCC
When V > 4.2V
IN
3870fb
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For more information www.linear.com/LTC3870
LTC3870
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, VRUN0, RUN1 = 3.3V, fSYNC = 350kHz
V
(externally driven) unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Control Loop
+
+
+
l
l
l
l
I
I
Current Sense + Pin Current
Current Sense − Pin Current
V
V
V
V
= 3.3V
= 3.3V
0.1
0.1
75
1
1
µA
µA
ISENSE0 ,
ISENSE1
ISENSE0,1
–
ISENSE0 ,
–
–
I
I
ISENSE0,1
ISENSE1
V
Maximum Current Sense threshold
(High Range)
= 2.22V, I = INTV
CC
70
45
80
55
mV
mV
IILIMIT
ITH
ITH
LIM
Maximum Current Sense threshold
(Low Range)
= 2.22V, I = GND
50
LIM
Gate Drivers
TG R
TG R
BG R
BG R
Pull-Up On-Resistance
Pull-down On-Resistance
Pull-Up On-Resistance
Pull-down On-Resistance
TG High
TG Low
BG High
BG Low
(Note 6)
2.5
1.5
2.4
1.1
Ω
Ω
Ω
Ω
UP
DOWN
UP
DOWN
TG0, TG1
TG Transition Time:
Rise Time
Fall Time
t
r
t
f
C
C
= 3300pF
= 3300pF
30
30
ns
ns
LOAD
LOAD
BG0, BG1
r
f
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
t
t
C
C
= 3300pF
= 3300pF
30
30
ns
ns
TG/BG t
Top Gate Off to Bottom Gate On Delay Time
Bottom Gate Off to Top Gate On Delay Time
Minimum On-Time
(Note 6)
= 3300pF Each Driver
30
30
90
ns
ns
ns
1D
2D
C
LOAD
BG/TG t
(Note 6)
= 3300pF Each Driver
C
LOAD
t
(Note 7)
ON(MIN)
INTV Regulator
CC
V
V
V
V
V
V
Internal V Voltage No Load
6.0V <V <60V, V = 0 V
EXTVCC
4.85
4.85
4.7
5.1
0.8
5.1
0.5
4.8
200
5.35
2
V
%
V
INTVCC_VIN
CC
IN
INT
INTV Load Regulation
I
= 0mA to 50mA, V
= 0V
LDO
CC
CC
EXTVCC
Internal V Voltage No Load
V
= 8.5V (Note 8)
5.35
2
INTVCC_EXT
CC
EXTVCC
EXT
INTV Load Regulation with EXTV
I
= 0 to 20mA, V
= 8.5V
%
V
LDO
CC
CC
CC
EXTVCC
EXTV Switchover Voltage
V
Ramping Positive (Note 8)
4.9
EXTVCC
CC
EXTVCC
EXTV HYSTERESIS
mV
HYS_EXTVCC
CC
Oscillator and Phase-Locked Loop
l
f
Oscillator SYNC Range
SYNC Input Threshold
100
9
1000
11
kHz
SNYC
V
V
V
Falling (Note 9)
Rising
0.4
2.0
V
V
TH,SYNC
TH,sync
TH,sync
f
I
Nominal Frequency
FREQ setting current
V
FREQ
= 1.0V
500
10
kHz
µA
NOM
FREQ
SYNC to Ch0 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG0
PHASMD = 0
180
60
Deg
Deg
Deg
Deg
θ
-θ
-θ
SYNC
0
PHASMD = 1/3 INTV
PHASMD = 2/3 INTV
CC
CC
120
90
PHASMD = INTV
CC
SYNC to Ch1 Phase Relationship Based on
the Falling Edge of Sync and Rising Edge of
TG1
PHASMD = 0
0
Deg
Deg
Deg
Deg
θ
SYNC
1
PHASMD = 1/3 INTV
PHASMD = 2/3 INTV
300
240
270
CC
CC
PHASMD = INTV
CC
3870fb
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For more information www.linear.com/LTC3870
LTC3870
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, VRUN0, RUN1 = 3.3V, fSYNC = 350kHz
V
(externally driven) unless otherwise specified.
SYMBOL PARAMETER
Digital Inputs RUN0/RUN1, MODE0/MODE1, FAULT0/FAULT1
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
IH
V
IL
Input High Threshold Voltage
Input Low Threshold Voltage
2.0
V
V
1.4
Note 1: Stresses beyond those listed in under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: When V >15V, EXTV is recommended to reduce IC
IN CC
Temperature.
Note 4: Output voltage is set and controlled by the master controller in
multiphase operations.
Note 2: The LTC3870 is tested under pulsed load conditions such that
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Application Information.
T ≈ T . The LTC3870E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3870I is guaranteed over the full –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the related package thermal
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
Considerations in the Applications Information section.
Note 8: EXTV is enabled only if V is higher than 6.5V.
CC
IN
Note 9: Guaranteed by design.
impedance and other environmental factors. The junction temperature T
J
is calculated from the ambient temperature T and power dissipation P
A
D
according to the following formula:
T = T + (P • 43°C/W)
J
A
D
Typical perForMance characTerisTics
Full Load Efficiency and Power
Loss vs Input Voltage
Efficiency vs Load Current
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
94
93
92
91
90
89
88
87
3
DCM
CCM
DCM
CCM
POWER LOSS
EFFICIENCY
2.5
2
1.5
1
V
V
SW
L = 0.56µH
DCR = 1.8mΩ
= 12V
= 1.8V
= 400kHz
V
V
= 12V
= 3.3V
= 400kHz
IN
OUT
IN
OUT
0.5
0
f
f
SW
V
V
= 12V
IN
OUT
L = 0.56µH
DCR = 1.8mΩ
= 1.8V
0.1
1
10
100
0.1
1
10
100
5
7
9
11
13
15
17
19
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3870 G01
3870 G02
3870 G03
3870fb
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For more information www.linear.com/LTC3870
LTC3870
Typical perForMance characTerisTics
Load Step (Discontinuous
Conduction Mode) 4-Phase
Operation LTC3880 and LTC3870
Load Step (Forced Continuous
Mode) 4-Phase Operation
LTC3880 and LTC3870
Inductor Current at Light Load
I
I
LOAD
LOAD
20A/DIV
20A/DIV
0A TO 20A TO 0A
0A TO 20A TO 0A
I
L_3870(CH0)
FORCED CONTINUOUS
MODE
I
I
L_3880(CH0)
10A/DIV
L_3880(CH0)
10A/DIV
5A/DIV
I
I
L_3870(CH0)
10A/DIV
L_3870(CH0)
10A/DIV
I
V
V
L_3870(CH0)
OUT
OUT
DISCONTINUOUS
CONDUCTION MODE
5A/DIV
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
3870 G06
3870 G04
3870 G05
1µs/DIV
50µs/DIV
50µs/DIV
V
V
LOAD
= 12V
V
V
= 12V
V
V
= 12V
IN
IN
OUT
IN
OUT
= 1.8V
= 1A
= 1.8V
= 1.8V
OUT
I
Start-Up Into a Pre-Biased
Output 4-Phase Operation
LTC3880 and LTC3870
Current Sense Threshold
vs ITH Voltage
INTVCC Line Regulation
80
60
6
5
4
3
2
1
0
RUN
ALL RUN PINS
TIED TOGETHER
2V/DIV
RANGE HIGH
RANGE LOW
40
V
OUT
LTC3870 IN DCM
500mV/DIV
20
0
3870 G07
–20
–40
2ms/DIV
V
V
= 12V
IN
OUT
= 1.8V
0
0.5
1
V
1.5
(V)
2
2.5
0
10
20
30
40
50
60
INPUT VOLTAGE (V)
ITH
3870 G08
3870 G09
Dynamic Current Sharing During
a Load Transient in a 4-Phase
Operation LTC3880 and LTC3870
DC Output Current Matching
Quiescent Current vs Input
Voltage Without EXTVCC
Between LTC3880 and LTC3870
25
20
15
10
5
3.5
3
I
2.5
2
L_3880(CH0)
I
I
I
L_3880(CH1)
L_3870(CH0)
L_3870(CH1)
5A/DIV
1.5
1
LTC3880 CH0
LTC3880 CH1
LTC3870 CH0
LTC3870 CH1
3870 G11
0.5
0
50µs/DIV
I
0A TO 32A TO 0A
LOAD
0
0
10 20 30 40 50 60 70 80 90
TOTAL OUTPUT CURRENT (A)
0
10
20
30
40
50
60
INPUT VOLTAGE (V)
3870 G10
3870 G12
3870fb
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LTC3870
pin FuncTions
MODE0/MODE1 (Pin 1/Pin 8): DCM/CCM Mode Control
Pins. Channel0/Channel1 operates in forced continuous
modeifMODE0/MODE1pinislogichigh.Thereisa500kΩ
pull down resistor on MODE0/MODE1 internally. The
default operation mode in each channel is discontinuous
mode operation unless these pins are actively driven high.
PHASMD (Pin 12): Phase Set Pin. This pin can be tied to
SGND, INTV or a resistor divider from INTV to SGND.
This pin determines the relative phases between the ext-
ernal clock on the SYNC pin and the internal controllers.
See Table 1 in the Operation Section for details.
CC
CC
TG0/TG1 (Pin 24/Pin 13): Top Gate Driver Outputs. These
+
+
I
/I
(Pin2/Pin7):CurrentSenseComparator
are the outputs of floating drivers with a voltage swing
SENSE0 SENSE1
positive inputs, normally connected to the positive node
of the DCR sensing networks or current sensing resistors.
equaltoINTV superimposedontheswitchnodevoltages.
CC
SW0/SW1 (Pin 23/Pin 14): Switch Node Connections to
−
−
I
/I
(Pin3/Pin6):CurrentSenseComparator
Inductors. Voltage swings at the pins are from a Schottky
SENSE0 SENSE1
negative inputs, normally connected to the negative node
of the DCR sensing network or current sensing resistors.
diode (external) voltage drop below ground to V .
IN
BOOST0/BOOST1(Pin22/Pin15):BoostedFloatingDriver
Supplies.The(+)terminalofthebootstrapcapacitorscon-
nect to these pins. These pins swing from a diode voltage
RUN0/RUN1 (Pin 4/Pin 5): Enable RUN Input Pins. Logic
high on these pins enables the corresponding channel. In
multiphase operation, these pins are connected to master
RUN pins.
drop below INTV up to V + INTV .
CC
IN
CC
BG0/BG1 (Pin 21/Pin 16): Bottom Gate Driver Outputs.
I
/I (Pin 28/Pin 9): Current Control Threshold. Each
These pins drive the gates of the bottom N-Channel MOS-
TH0 TH1
associatedchannel’scurrentcomparatortrippingthreshold
FETs between PGND and INTV .
CC
increases with its I voltage. In multiphase operation,
TH
INTV (Pin 17): Internal Regulator 5V Output. The
CC
these pins are connected to the master controller’s I
TH
internal control circuits are powered from this voltage.
pins for current sharing.
Bypass this pin to PGND with a minimum of 4.7µF low
I
(Pin 10): Program Current Comparators’ Sense
ESR tantalum or ceramic capacitor. INTV is enabled as
CC
LIM
Voltage Range. This pin can be tied to SGND or INTV
soon as V is powered.
CC
IN
to select the maximum current sense threshold for each
currentcomparator.SGNDsetsbothchannels’currentlow
EXTV (Pin 18): External power input to an internal LDO
CC
connected to INTV . This LDO supplies INTV power
CC
CC
range with maximum 50mV sensing voltage. INTV sets
CC
bypassing the internal LDO powered from V whenever
IN
both channels’ current high range with maximum 75mV
EXTV is higher than 4.8V. See EXTV connection in the
CC
CC
sensing voltage. For equal current sharing, the setup on
Applications Information Section. Do not exceed 14V on
this pin. Bypass this pin to PGND with a minimum of 4.7µF
the I
pin has to be same as the setup on the bit 7 of
LIM
MFR_PWM_MODE_3880/3883/3886/3887registerinthe
master controller. See Table 2 in the Operation Section
for details.
low ESR tantalum or ceramic capacitor. If the EXTV pin
CC
is not used, leave it open or tie it to ground. EXTV can
CC
be present before V . However, EXTV is enabled only
IN
CC
SYNC(Pin11):ExternalClockSynchronizationInput.Ifan
externalclockispresentatthispin,theswitchingfrequency
will be synchronized to the falling edge of the external
clock. In multiphase operation, this pin is connected to
the master's SYNC pin for frequency synchronization. Do
not float the SYNC pin.
if V is higher than 6.5V.
IN
PGND(Pin19):PowerGroundPin.Connectthispinclosely
to the sources of the bottom N-Channel MOSFETs and the
(–) terminals of C .
IN
V (Pin 20): Main Input Supply. Bypass this pin to PGND
IN
with a capacitor (0.1µF to 1µF).
3870fb
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LTC3870
pin FuncTions
pin sets the default switching frequency when there is no
external clock on the SYNC pin. Set the frequency close
to the external clock to help the internal PLL sync to the
SYNC pin clock quickly and smoothly. See the application
section for the detailed information.
FAULT0/FAULT1 (Pin 26/Pin 25): Fault Input Pins. Con-
nect these pins to the master chip GPIO pins to respond
to fault signals from the master controller. If this pin is
low, both TG and BG pins are pulled down at the corre-
sponding channel. There is a 500k pull down resistor on
FAULT0/FAULT1 internally. These pins have to be driven
high externally for normal operation.
SGND (Exposed Pad Pin 29): Signal Ground. All small-
signal and compensation components should connect to
this ground, which in turn connects to PGND at one point.
The exposed pad must be soldered to the PCB, providing
a local ground for the control components of the IC, and
be tied to PGND under the IC.
FREQ (Pin 27): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which in turn programs the frequency. This
3870fb
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LTC3870
block DiagraM
(CH0 Shown)
SYNC
11
PHASMD
12
EXTV
18
CC
10µA
SYNC
DET
4.8V
PHASE
PROGRAM
V
IN
PFD
VCO
27
FREQ
V
IN
20
+
C
IN
OSC
5.0V
LDO
EN
5.0V
LDO
EN
S
R
Q
INTV
17
CC
I
I
REV
–
+
3K
CMP
+
–
BOOST0
22
C
B
TG0
24
SW0
23
ON
M1
R
SWITCH
LOGIC
AND
REV
L
UVLO
C
V
C
C
OUT0
OUT0
I
LIM
10
ANTI-
SHOOT-
THROUGH
FAULTB
FCNT
RUN
D
B
I
RANGE SELECT
HI: 1:1
LO: 1:1.5
C
LIM
+
UVLO
INTV
BG0
21
CC
M2
C
VCC
PGND
19
SENSE0
2
+
SLOPE
COMPENSATION
I
I
–
SENSE0
3
1
INTV
71.1k
CC
1.7V
REF
I
28
1
4
26
29
TH0
SGND
MODE0
RUN0
FAULT0
3870 BD
3870fb
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Main Control Loop
off for about one-twelfth of the clock period plus 100ns
every three cycles to allow C to recharge. However, it is
B
The LTC3870 is a constant frequency, current mode
step-down slave controller for parallel operation with the
LTC3880 family master controllers. During normal opera-
tion, each top MOSFET is turned on when the clock for
that channel sets the RS latch, and turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP resets the RS latch
recommended that a load be present or the IC operates
at low frequency during the drop-out transition to ensure
C is recharged.
B
Start-Up and Shutdown (RUN0, RUN1)
The two channels of the LTC3870 can independently
start up and shut down using the RUN0 and RUN1 pins.
Pulling either of these pins below 1.4V shuts down the
control circuits for that channel. During shutdown, both
TG and BG are pulled down to turn off the external power
MOSFETs. Pulling either of these pins above 2V enables
the corresponding channel and internal circuits. During
startup, the RUN0/RUN1 pins are actively pulled down
is controlled by the voltage on the I pin, which is tied
TH
directlytothecorrespondingI pinofthemastercontrol-
TH
lers. When the load current increases, master controllers
drive and increase the I voltage, which in turn cause
TH
the peak current in the corresponding slave channels to
increase, until the average inductor current matches the
new load current. After the top MOSFET has been turned
off, the bottom MOSFET is turned on until the beginning
of the next cycle in Continuous Conduction Mode (CCM)
or until the inductor current starts to reverse, as indicated
until the INTV voltage passes the under-voltage lockout
CC
threshold of 4V. For multiphase parallel operation, the
RUN0/RUN1 pins have to be connected and driven by
the RUN pins of the master controller. Do not exceed the
Absolute Maximum Rating of 6V on these pins.
by the reverse current comparator I , in Discontinuous
REV
Conduction Mode (DCM). The LTC3870 slave controllers
DONOTregulatetheoutputvoltagebutregulatethecurrent
ineachchannelforcurrentsharingwithmastercontrollers.
Output voltage regulation is achieved through the voltage
feedback loops in master controllers.
The start-up of each channel’s output voltage V
is
OUT
controlledandprogrammedbythemastercontroller.After
theRUNpinsarereleased, themastercontrollerdrivesthe
outputbasedontheprogrammeddelaytimeandrisetime,
and the slave controller LTC3870 just follows the master
to supply equivalent current to the output during startup.
INTV /EXTV Power
CC
CC
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin.
Light Load Current Operation (Discontinuous
Conduction Mode, Continuous Conduction Mode)
CC
Normally an internal 5.0V linear regulator supplies INTV
CC
power from V . In high V applications, if a high effi-
IN
IN
TheLTC3870canbesettooperateeitherinDiscontinuous
Conduction Mode (DCM) or forced Continuous Conduc-
tion Mode (CCM). To select forced Continuous Mode of
operation, tie the MODE pin to a DC voltage above 2V
ciency external voltage source is available for the EXTV
CC
pin, another internal 5.0V linear regulator is enabled and
supplies INTV power from EXTV . To enable the linear
CC
CC
regulator driven by the EXTV pin, V has to be higher
CC
IN
(e.g., INTV ). To select discontinuous conduction mode
CC
than 6.5V and EXTV pin voltage has to be higher than
CC
of operation, tie the MODE pin to a DC voltage below 1.4V
(e.g., SGND). In forced continuous operation, the induc-
tor current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current is
4.8V. Do not exceed 14V on the EXTV pin.
CC
Each top MOSFET driver is biased from the floating
bootstrap capacitor C , which normally recharges during
B
determined by the voltage on the I pin. In this mode,
each off cycle through an external diode when the top
TH
the efficiency at light loads is lower than in discontinu-
ous Mode operation. However, continuous mode has the
advantages of lower output ripple and less interference
with audio circuitry. When the MODE pin is connected to
MOSFET turns off. If the input voltage V decreases to
IN
a voltage close to V , the loop may enter dropout and
OUT
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
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SGND, the LTC3870 operates in discontinuous mode at
light loads. At very light loads, the current comparator
ICMP may remain tripped for several cycles and force the
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). This mode provides higher
light load efficiency than forced continuous mode and the
inductor current is not allowed to reverse. There are 500k
pull down resistors internally connected to the MODE0/
MODE1 pins. If MODE0/MODE1 pins are floating, both
channels default to discontinuous conduction mode.
Single Output Multiphase Operation
The LTC3870 is designed for multiphase converters with
the master controller by making these connections:
Tie all the I pins of paralleled channels together for
TH
current sharing between masters and slaves. Note that
I
setup on slaves has to match MFR_PWM_MODE
LIM
current range setup in masters.
Tie all SYNC pins together between master and slaves for
sameswitchingfrequencysynchronization;oneandonly
one of the master controllers has to be programmed
as master to generate clock signal on the SYNC pin.
Multichip Operation (PHASMD and SYNC Pins)
The PHASMD pin determines the relative phases between
theinternalchannelsaswellastheexternalclocksignalon
the SYNC pin, as shown in Table 1. The phases tabulated
are relative to zero degree phase being defined as the
falling edge of the clock on SYNC.
TiealltheRUNpinsofparalleledchannelstogetherbetween
masterandslavesforstartupandshutdownsequences.
Tie the GPIO pin of the master controller to the FAULT pin
of slave controllers and program the master GPIO as
fault sharing for fault protections.
Table 1.
PHASMD
Channel 0 Phase
Channel 1 Phase
Examples of single output multiphase converters are
shown in Figure 1.
GND
180°
60°
0°
1/3 INTV
300°
240°
270°
CC
Inductor Current Sensing
2/3 INTV or Float
120°
90°
CC
INTV
CC
LiketheLTC3880/LTC3883,LTC3870canuseeitherinduc-
tor DCR or R
to sense the inductor current. Inductor
SENSE
The SYNC pin is used to synchronize switching frequency
between master and slave controllers. Input capacitance
ESR requirements and efficiency losses are substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A two-phase, single output voltage implementa-
tion can reduce input path power loss by 75% and radi-
cally reduce the required RMS current rating of the input
capacitor(s).
DCR current sensing provides a lossless method of sens-
ing the instantaneous current. Therefore, it can provide
higherefficiencyforapplicationswithhighoutputcurrents.
However, the DCR of a copper inductor typically has 10%
tolerance.Forprecisecurrentsensing,aprecisionsensing
resistor R
can be used to sense the inductor current.
SENSE
Itisimportanttomatchthecurrentsensingcircuitbetween
master controllers and slave controllers to guarantee bal-
anced load sharing and overcurrent protection.
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2 + 2
1 + 3
CH0 CH1
CH0
120°
CH1
240°
CH0
0°
CH1
180°
0°
180°
LTC3870
PHASMD = 2/3 INTV OR FLOAT
LTC3880
LTC3880
CC
CH0 CH1
180° 0°
LTC3870
PHASMD = GND
4 PHASE OPERATION
6 PHASE OPERATION
CH0
90°
CH1
270°
CH0
0°
CH1
180°
CH0
CH1
180°
CH0
60°
CH1
300°
CH0
120°
CH1
240°
0°
LTC3870
PHASMD = INTV
LTC3880
LTC3880
LTC3870
PHASMD = 1/3 INTV
LTC3870
PHASMD = 2/3 INTV
CC
CC
CC
3870 F01
Figure 1. Examples of Single/Dual Output Multiphase Converters
Frequency Selection and Phase-Locked Loop (FREQ
and SYNC Pins)
LTC3870. The phase-locked loop is capable of locking to
any frequency within the range of 100kHz to 1MHz.
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency of
theLTC3870controllerscanbesynchronizedtothefalling
edge of the external clock on the SYNC pin or selected us-
ing the FREQ pin. A phase-locked loop (PLL) is integrated
in the LTC3870 to synchronize the internal oscillator to an
external clock source that is connected to the SYNC pin;
this source is normally provided by the master control-
lers. The PLL loop filter network is integrated inside the
If the SYNC pin is not being driven by an external clock
source,theFREQpincanbeusedtoprogramtheLTC3870’s
operating frequency from 100kHz to 1MHz. There is a
precision 10µA current flowing out of the FREQ pin, so
the user can program the controller’s switching frequency
with a single resistor to SGND. A curve is provided later in
the application section showing the relationship between
the voltage on the FREQ pin and switching frequency. The
frequency setting resistor should always be present to set
the controller’s initial switching frequency before locking
to the external clock.
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TheTypicalApplicationonthefirstpageofthisdatasheetis
a basic LTC3870 application circuit featuring the LTC3880
as a slave controller. In paralleled operation, the current
sensing scheme as well as the power stage parameters
in LTC3870 must be the same as the master controller to
achieve balanced current sharing between masters and
slaves. Finally, input and output capacitors are selected
based on RMS current rating, ripple, and transient specs.
INTV Regulators and EXTV
CC CC
The LTC3870 features a PMOS LDO that supplies power
to INTV from the V supply. INTV powers the gate
CC
IN
CC
drivers and most of the LTC3870’s internal circuitry. The
linear regulator regulates the voltage at the INTV pin
CC
to 5.0V when V is greater than 6V. EXTV connects to
IN
CC
INTV through another PMOS LDO and can supply the
CC
needed power when its voltage is higher than 4.8V and
V is higher than 6.5V. Each of these LDOs can supply a
IN
Current Limit Programming
peak current of 100mA and must be bypassed to ground
with a minimum of 4.7µF ceramic capacitor or low ESR
electrolytic capacitor. No matter what type of bulk capaci-
tor is used, an additional 0.1µF ceramic capacitor placed
To match the master controller current limit, each chan-
nel of LTC3870 can be programmed separately with two
current ranges. The I pin of LTC3870 is a 4-level logic
LIM
input which sets the current limit of LTC3870. When I
directly adjacent to the INTV and PGND pins is highly
LIM
CC
is grounded, both channel0 and channel1 are set to be low
current range. When I is tied to INTV , both channel0
recommended. Good bypassing is needed to supply the
high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
LIM
CC
and channel1 are set to be high current range. Here, low
current range means the current sense threshold linearly
HighinputvoltageapplicationsinwhichlargeMOSFETsare
being driven at high frequencies may cause the maximum
junctiontemperatureratingfortheLTC3870tobeexceeded.
increases from 0mV to 50mV as I voltage is increased
TH
from0.5Vto2.22Vwithoutslopecompensation.Highcur-
rentrangemeansthecurrentsensethresholdincreasesto
TheINTV current,whichisdominatedbythegatecharge
CC
75mV as I voltage is increased to 2.22V without slope
TH
current, may be supplied by either the 5.0V linear regula-
compensation. Set I to one-third INTV for channel0
LIM
CC
tor from V or the linear regulator from EXTV . When
IN
CC
high current range and channel1 low current range. Set
to two-thirds INTV or float for channel0 low current
the voltage on the EXTV pin is less than 4.8V, the linear
CC
I
LIM
CC
regulator from V is enabled. Power dissipation for the
IN
range and channel1 high current range. The summary of
pin setups is shown in Table 2. For balanced load
IC in this case is highest and is equal to V • I
. The
IN INTVCC
I
LIM
gate charge current is dependent on operating frequency.
The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
current sharing, use the same current range setting as
in the master controller. Note that the LTC3870 does not
have active clamping circuit on I pin for peak current
TH
Forexample,theLTC3870INTV currentislimitedtoless
CC
limit and over current protection. Over current protection
than 34mA from a 38V supply in the UFD package and not
relies on the master controller to drive and clamp the I
TH
using the EXTV supply:
CC
pinvoltagenottoexceedtheprogrammedvoltagethrough
the PMBus command.
T = 70°C + (34mA)(38V)(43°C/W) = 125°C
J
Table 2.
whereambienttemperatureis70°Candthermalresistance
from junction to ambient is 43°C/W.
Channel 0
Current limit
Channel 1
Current limit
I
LIM
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
GND
Range Low
Range High
Range Low
Range High
Range Low
Range Low
Range High
Range High
1/3 INTV
CC
2/3 INTV or Float
CC
= INTV ) at maximum V . When the voltage applied to
CC
IN
INTV
CC
EXTV rises above 4.8V and V above 6.5V, the INTV
CC
IN
CC
linearregulatoristurnedoffandtheEXTV linearregulator
CC
is turned on. Using the EXTV allows the MOSFET driver
CC
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and control power to be derived from other high efficiency
the final arbiter is the total input current for the regulator.
If a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
sources such as +5V or +12V rails in the system. Using
EXTV can significantly reduce the IC temperature in
CC
high V applications. Tying the EXTV pin to a 5V supply
IN
CC
reduces the junction temperature in the previous example
Undervoltage Lockout
from 125°C to: T = 70°C + (34mA) (5V) (43°C/W) = 77°C.
J
Do not apply more than 14V to the EXTV pin.
CC
TheLTC3870hasaprecisionUVLOcomparatorconstantly
monitoring the INTV voltage to ensure that an adequate
For applications where the main input power is 5V, tie
CC
gate-drive voltage is present. It locks out the switching
the V and INTV pins together and tie the combined
IN
CC
action and pulls down RUN pins when INTV is below
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
CC
3.7V. To prevent oscillationwhen there is a disturbance on
in Figure 2 to minimize the voltage drop caused by the
theINTV , theUVLOcomparatorhas300mVofprecision
CC
gate charge current. This will override the INTV linear
CC
hysteresis. In multiphase operation, when LTC3870 is in
undervoltage lockout, the RUN0 and RUN1 pins are pulled
down to disable the master’s switching action.
regulator and will prevent INTV from dropping too low
CC
due to the dropout voltage. Make sure the INTV voltage
CC
is at or exceeds the R
test voltage for the MOSFET
DS(ON)
which is typically 4.5V for logic-level devices.
Phase-Locked Loop and Frequency Synchronization
The LTC3870 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the internal clock to be locked
to the falling edge of an external clock signal applied to
the SYNC pin. The turn-on of channel 0/channel 1’s top
MOSFET is synchronized or out-of-phase with the falling
edge of the external clock. The phase detector is an edge
sensitive digital type that provides zero degree phase shift
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics
of the external clock.
V
IN
R
VIN
LTC3870
1Ω
INTV
5V
CC
+
C
INTVCC
4.7µF
C
IN
3870 F04
Figure 2. Setup for a 5V Input
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitor C , connected to the BOOST
B
Theoutputofthephasedetectorisapairofcomplementary
current sources that charge or discharge the internal filter
network.Thereisaprecision10µAofcurrentflowingoutof
the FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the SYNC pin. The voltage on the FREQ
pin is equal to the resistance multiplied by 10µA current
(e.g. the voltage is 1V with a 100k resistor from the FREQ
pin to SGND). The internal switch between FREQ pin and
the integrated PLL filter network is ON, allowing the filter
network to be pre-charged to the same voltage potential
as the FREQ pin. The relationship between the voltage
on the FREQ pin and the operating frequency is shown
in Figure 3 and specified in the Electrical Characteristic
table. If an external clock is detected on the SYNC pin, the
pin, supplies the gate drive voltages for the topside MOS-
FET. Capacitor C in the Functional Diagram is charged
B
though external diode DB from INTV when the SW pin
CC
is low. When the topside MOSFET is to be turned on, the
driver places the C voltage across the gate source of the
B
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to V
IN
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
V
= V + V
– V
INTVCC DB
BOOST
IN
The value of the boost capacitor, C , needs to be 100 times
thatofthetotalinputcapacitanceofthetopsideMOSFET(s).
B
ThereversebreakdownoftheexternalSchottkydiodemust
begreaterthanV
.Whenadjustingthegatedrivelevel,
IN(MAX)
internal switch mentioned above will turn off and isolate
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the influence of FREQ pin. Note that the LTC3870 can only
be synchronized to an external clock whose frequency is
within the range of the LTC3870’s internal VCO. This is
guaranteed to be between 100kHz and 1MHz. A simplified
block diagram is shown in Figure 4.
1400
1200
1000
800
600
400
200
0
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f , current is sunk continuously, pulling down
OSC
0
0.5
1
1.5
2
2.5
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
FREQ PIN VOLTAGE (V)
3870 F02
Figure 3. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
2.4V 5V
10µA
R
SET
FREQ
Typically, the external clock (on SYNC pin) input high
threshold is 2V, while the input low threshold is 0.4V.
SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC
EXTERNAL
OSCILLATOR
VCO
Fault Protection and Responses
LTC3880familymastercontrollersmonitorsystemvoltage,
current, and temperature and provide many protection
features during fault conditions. LTC3870 slave control-
lers do not provide as many fault monitors as master
controllers and have to respond to fault signals from the
master controller. FAULT0 and FAULT1 pins are designed
to share fault signals between masters and slaves. In a
typical parallel application, connect the FAULT pins on
LTC3870 to the master GPIO pins of the corresponding
paralleled channels and program the master GPIO as
fault sharing, so that the slave controller can respond to
all fault protections from the master. When the FAULT pin
is pulled below 1.4V, both TG and BG in the correspond-
ing channel are pulled down and external MOSFETs are
turned off. When the FAULT pin voltage is above 2V, the
corresponding channel is back to the normal operation.
Duringfaultconditions, allinternalcircuitsinLTC3870are
still running so the slave controllers can immediately go
back to normal operation when the FAULT pin is released.
3870 F03
Figure 4. Phase-Locked Loop Block Diagram
is higher than 160°C. In thermal shutdown, FAULT0 and
FAULT1 pinsarealsopulledlow.Thereisa500kpulldown
resistor on each FAULT pin which sets the default voltage
on Fault pins low if FAULT pins are floating.
Transient Response and Loop Stability
In a typical parallel operation, LTC3870 cooperates with
master controllers to supply more current. To achieve
balanced current sharing between master and slave, it is
recommended that each slave channel copy the design
from the master channel. Select same inductors, same
power MOSFETs, same current sensing circuit and same
output capacitors between the master channel and slave
channels. Control loop and compensation design on the
LTC3870 has internal thermal shutdown protection which
pullsallTGandBGpinslowwhenthejunctiontemperature
I
TH
pin should start with the single phase operation of the
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master controller. If the master and slave channels are
exactly the same, then the transient response and loop
stability of the multiphase design is almost the same as
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles.Theoutputvoltagewillcontinuetoberegulated,but
the ripple voltage and current will increase. The minimum
on-time for the LTC3870 is approximately 90ns, with rea-
sonablygoodPCBlayout, minimum30%inductorcurrent
rippleandatleast10mVrippleonthecurrentsensesignal.
The minimum on-time can be affected by PCB switch-
ing noise in the current loop. As the peak sense voltage
decreases, the minimum on-time gradually increases to
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
the single phase operation of the master by tying the I
TH
pins together between the master and slaves. For example,
designthecompensationforasinglephase1.8V/20Aoutput
using LTC3880 with a 0.56µH inductor and 530µF output
capacitors.Toextendtheoutputto1.8V/40A,simplyparallel
onechannelofLTC3870withthesameinductorandoutput
capacitors (total output capacitors are 1060µF) and tie the
I
pin of LTC3870 to the master I . The loop stability
TH
TH
and transient responses of the two phase converter are
very similar to the single phase design without any extra
compensator on the I pin of LTC3870 slave controller.
TH
Furthermore, LTpowerCAD is provided on the LTC website
as a free download for transient and stability analysis.
PC Board Layout Checklist
To minimize the high frequency noise on the I trace
TH
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 5. Figure 6 illustrates the current
waveforms present in the various branches of the 2-phase
synchronousregulatorsoperatinginthecontinuousmode.
Check the following in the PC layout:
between master and slave I pins, a small filter capacitor
TH
in the range of tens of pF can be placed closely at each I
TH
pin of the slave controller. This small capacitor normally
doesnotsignificantlyaffecttheclosedloopbandwidthbut
increases the gain margin at high frequency.
Mode Selection and Pre-Biased Startup
1. Are the top N-channel MOSFETs M1 and M3 located
within1cmofeachotherwithacommondrainconnection
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging the
outputcapacitors. TheLTC3870can beconfiguredtoDCM
mode for pre-biased start-up. If PGOOD signal is available
on the master controller (e.g. LTC3883), the PGOOD pin
canbeconnectedtoMODEpinsofLTC3870toensureDCM
operation at startup and CCM operation at steady state.
at C ? Do not attempt to split the input bypassing for
IN
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
mustreturntothecombinedC (–)terminals.
INTVCC
OUT
The I traces should be as short as possible. The path
TH
formed by the top N-channel MOSFET, Schottky diode
and the C capacitor should have short leads and PC
Minimum On-Time Considerations
IN
trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals of
theinputcapacitorbyplacingthecapacitorsnexttoeach
otherandawayfromtheSchottkyloopdescribedabove.
Minimum on-time t
is the smallest time duration
ON(MIN)
thattheLTC3870iscapableofturningonthetopMOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
+
–
3. Are the I
and I
leads routed together with
SENSE
SENSE
minimumPCtracespacing?Thefiltercapacitorbetween
+
–
I
and I
should be as close as possible to
SENSE
SENSE
t
<T
V /V
SW OUT IN
ON(MIN)
the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
where T is the switching period.
SW
is used for current sensing.
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4. Is the INTV bypassing capacitor connected close to
difficultregionofoperationiswhenonecontrollerchannel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
CC
theIC, betweentheINTV andthepowergroundpins?
CC
ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.
Anadditional1µFceramiccapacitorplacedimmediately
next to the INTV and PGND pins can help improve
CC
noise performance substantially.
Reduce V from its nominal level to verify operation of
IN
the regulator in dropout. Check the operation of the un-
5. Keep the switching nodes (SW1, SW0), top gate nodes
(TG1, TG0), andboostnodes(BOOST1, BOOST0)away
from sensitive small-signal nodes, especially from the
opposite channel’s current sensing feedback pins. All
of these nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3870 and occupy minimum PC trace area. If
DCR sensing is used, place the right resistor (Block
dervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigatewhetheranyproblemsexistonlyathigheroutput
currentsoronlyathigherinputvoltages.Ifproblemscoincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of the
IC.Thiscapacitorhelpstominimizetheeffectsofdifferential
noise injection due to high frequency capacitive coupling. If
problems are encountered with high current output loading
at lower input voltages, look for inductive coupling between
Diagram, “R ”) close to the switching node.
C
6. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
bypassingcapacitor,thebottomofthevoltagefeedback
C , Schottky and the top MOSFET components to the
IN
resistive divider and the SGND pin of the IC.
sensitive current and voltage sensing traces. In addition,
investigate common ground path voltage pickup between
these components and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a DC-
50MHzcurrentprobetomonitorthecurrentintheinductor
whiletestingthecircuit.Monitortheoutputswitchingnode
(SW pin) to synchronize the oscilloscope to the internal
oscillatorandprobetheactualoutputvoltageaswell.Check
for proper performance over the operating voltage and
current range expected in the application. The frequency
of operation should be maintained over the input voltage
rangedowntodropoutanduntiltheoutputloaddropsbelow
the low current operation threshold—typically 10% of the
maximum designed current level in Burst Mode operation.
Design Example
AsadesignexampleusingmasterchipLTC3880andslave
chipLTC3870fora4-phasehighcurrentregulator,assume
V = 12V (nominal), V = 15V (maximum), V
= 1.0V,
IN
MAX
IN
OUT
I
= 100A, and f = 425kHz (see Typical Applications).
The master chip LTC3880 design can be found in the
LTC3880 data sheet Design Example section.
LTC3880's SYNC pin is connected to LTC3870's SYNC
pin and LTC3870's PHASMD is connected to LTC3870’s
INTV .
CC
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a sub-harmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controllerischeckedforitsindividualperformanceshould
bothcontrollersbeturnedonatthesametime.Aparticularly
Slave chip LTC3870 should use the same inductor, power
MOSFET, C , and C
as the master chip. DCR sensing
IN
OUT
is also used for the slave chip.
LTC3870's I pin is forced to 0V to match the master
LIM
chip's 50mV current limit. Both chips' V , V , RUN,
IN OUT
I
pins are connected together. LTC3880's GPIO pins are
TH
connectedtoLTC3870'sFAULTpinssotheslavecontroller
will be disabled during fault conditions.
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16
For more information www.linear.com/LTC3870
LTC3870
applicaTions inForMaTion
L1
I
I
TH1
+
–
V
TG1
SW1
OUT1
SENSE1
I
SENSE1
C
B1
M1
M2
BOOST1
D1
1µF
CERAMIC
BG1
LTC3870
f
IN
SYNC
RUN0
RUN1
C
V
OUT1
IN
R
C
IN
VIN
PGND
V
IN
GND
C
SGND
I
INTVCC
C
IN
–
INTV
CC
SENSE0
SENSE0
C
OUT0
D0
1µF
CERAMIC
+
I
BG0
M3
M4
BOOST0
C
B0
SW0
TG0
I
TH0
V
OUT0
L0
3870 F06
Figure 5. Recommended Printed Circuit Layout Diagram
SW1
L1
V
OUT1
C
R
L1
D1
OUT1
V
IN
R
IN
C
IN
SW0
L0
V
OUT0
C
R
L0
D0
OUT0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3870 F07
Figure 6. Branch Current Waveforms
3870fb
17
For more information www.linear.com/LTC3870
LTC3870
Typical applicaTions
3870fb
18
For more information www.linear.com/LTC3870
LTC3870
Typical applicaTions
High Efficiency 425kHz 3-phase 1.8V Step-Down Converter with Input Current Sensing
V
IN
6V TO 14V
5mΩ
D1
10µF
1µF
INTV
100Ω
100Ω
10nF
CC
M1
M2
1µF
TG
V
1.8V
50A
OUT
I
IN_SNS
BOOST
L0
0.56µH
0.1µF
V
IN_SNS
SW
BG
10nF
LTC3883
3Ω
+
1µF
530µF
V
IN
PGND
1.43k
1.43k
0.22µF
TSNS
+
MMBT3906
I
SENSE
10µF
–
10nF
I
SENSE
+
–
V
V
SENSE
SENSE
10k
SCL
SDA
10k
10k
10k
V
DD25
ALERT
24.9k
11.3k
20k
16.2k
17.4k
SHARE_CLK
1µF
V
OUT_CFG
TRIM_CFG
ASEL
V
DD33
10k
10k
10k
V
1µF
GPIO
RUN
SYNC
PGOOD
17.8k
10k
FREQ_CFG
WP
I
TH
GND
4.99k
2200pF
22µF
L1
D2
D3
4.7µF
V
INTV
IN
CC
TG1
M3
M4
TG0
L2
0.56µH
BOOST1
BOOST0
0.1µF
M6
0.56µH
0.1µF
SW0
BG0
SW1
BG1
M5
+
+
1µF
1µF
LTC3870
530µF
530µF
PGND
1.43k
1.43k
EXTV
CC
+
1.43k
0.22µF
0.22µF 1.43k
+
I
I
I
I
SENSE1
SENSE0
–
–
SENSE0
SENSE1
FAULT0
FAULT1
RUN0
PHASMD
RUN1
FREQ
100k
SYNC
MODE0
I
LIM
MODE1
SGND
I
TH0
D1 TO D3: CENTRAL CMDSH-3TR
L0 TO L2: VISHAY IHLP-4040DZ-11 0.56µH
M1, M3, M4: INFINEON BSC050NE2LS
M2, M5, M6: INFINEON BSC010NE2LSI
I
TH1
100pF
3870 TA03
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19
For more information www.linear.com/LTC3870
LTC3870
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.50 REF
2.65 ±0.05
3.65 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 ±0.05
4.00 ±0.10
(2 SIDES)
27
28
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ±0.10
(2 SIDES)
3.50 REF
3.65 ±0.10
2.65 ±0.10
(UFD28) QFN 0506 REV B
0.25 ±0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3870fb
20
For more information www.linear.com/LTC3870
LTC3870
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
8/14
Added Note 9
2
Miscellaneous typographical changes
Changed title and added master parts supported
1, 3, 8, 13, 16
1
B
7/15
3870fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
21
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3870
Typical applicaTion
4-Phase 1.5V Step-Down Converter with Sensing Resistors and External VCC
V
IN
6V TO 24V
4.7µF
V
IN
INTV
CC
TG0
PHASMD BOOST0
0.42µH 0.0015Ω
V
OUT
1.5V
80A
0.1µF
5V
CC
EXTV
SW0
BG0
CC
FREQ
+
84.5k
530µF
MODE0
MODE1
100Ω
1000pF
+
I
I
SENSE0
I
LIM
–
SGND
SENSE0
100Ω
LTC3870
LTC3880-1*
RUN0
TG1
RUN0
RUN1
5V
EXTV
RUN1
GPIO0
GPIO1
CC
BOOST1
SW1
CC
0.42µH 0.0015Ω
0.1µF
FAULT0
FAULT1
1.5V
+
V
V
SENSE0
SENSE1
I
BG1
PGND
+
+
I
TH0
I
TH0
530µF
TH1
I
TH1
SYNC
SYNC
100Ω
100Ω
I
SENSE1
* REFER TO LTC3880 DATA SHEET
FIGURE TA04 FOR MASTER SETUP
1000pF
–
I
SENSE1
3870 TA04
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTC3886
60V Dual Output Step-Down Controller
with Digital Power System Management
4.5V ≤ V ≤ 60V, 0.5V ≤ V
≤ 13.8V, Programmable Loop Compensation,
IN
OUT
Input Current Sense
LTM4676/
LTM4676A
Dual 13A or Single 26A Step-Down DC/DC µModule
Regulator with Digital Power System Management
4.5V ≤ V ≤ 17V/26.5V, 0.5V ≤ V
≤ 4V/5.5V, 1% V
Accuracy,
IN
OUT
OUT
2
Fault Logging, I C/PMBus Interface, 16mm × 16mm × 5mm, BGA Package
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Controller
4.5V ≤ V ≤ 24V, 0.5V ≤ V
≤ 5.5V, 70mS Start-Up, Analog Control Loop,
IN
OUT
2
with Digital Power System Management, 70ms Start-Up I C/PMBus Interface, -1 Version Drives DrMOS and Power Blocks
LTC3880/
LTC3880-1
Dual Output Multiphase Step-Down DC/DC Controller
with Digital Power System Management
4.5V ≤ V ≤ 24V, 0.5V ≤ V
≤ 5.4V, Analog Control Loop,
IN
OUT0
2
I C/PMBus Interface with EEPROM and 16-Bit ADC
LTC3883/
Single Phase Step-Down DC/DC Controller
with Digital Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Input Current Sense Amplifier,
IN
OUT
2
LTC3883-1
I C/PMBus Interface with EEPROM and 16-Bit ADC
Up to 38V, 0.5V ≤ V ≤ 5.25V, 0.5% V Accuracy
OUT
LTC3882
LTC3892-1
LTC2977
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
V
IN
OUT1,2
2
I C/PMBus Interface, Drives DrMOS and Power Blocks
V Up to 60V, 0.8V ≤ V ≤ 99%•V , 29µA Quiescent Current Adjustable
IN
60V Low I Dual, 2-Phase Synchronous Step-Down
Q
OUT
IN
DC/DC Controller
Gate Drive Voltage
8-Channel PMBus Power System Manager Featuring
Accurate Output Voltage Measurement
Sequence and Supervise Eight Power Supplies Margin or Trim Supplies to
0.25% Accuracy
3870fb
LT 0715 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
●
●
LINEAR TECHNOLOGY CORPORATION 2014
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3870
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