LTC3871HLXE#PBF_技术文档

LTC3871

®

Bidirectional PolyPhase

Synchronous Buck or Boost Controller

FEATURES

DESCRIPTION

The LTC^®3871 is a high performance bidirectional buck or

boost switching regulator controller that operates in either

buck or boost mode on demand. It regulates in buck mode

n

Unique Architecture Allows Dynamic Regulation of

Input Voltage, Output Voltage or Current

n

V

Voltages Up to 100V

Voltages Up to 30V

HIGH

LOW

from V

-to-V

and boost mode from V

-to-V

HIGH

LOW

LOW HIGH

Synchronous Rectiﬁcation: Up to 97% Efﬁciency

LTC-Proprietary Advanced Current Mode Control

1% Voltage Regulation Accuracy Over Temperature

Accurate, Programmable Output Current Monitoring

and Regulation for Both Buck and Boost Operation

Selectable Buck and Boost Current Sense Limits

depending on a control signal, making it ideal for 48V/12V

automotive dual battery systems. An accurate current

programming loop regulates the maximum current that

can be delivered in either direction. The LTC3871 allows

both batteries to supply energy to the load simultaneously

by converting energy from one battery to the other.

n

Programmable DRV /EXTV Optimizes Efﬁciency

CC

Its proprietary constant-frequency current mode

architecture enhances the signal-to-noise ratio enabling

low noise operation and provides excellent current

matching between phases. Additional features include

discontinuous or continuous mode of operation, OV/UV

monitors, independent loop compensation for buck and

boost operation, accurate output current monitoring and

overcurrent protection.

Programmable V

UV and OV Thresholds

OV Threshold

HIGH

LOW

Phase-Lockable Frequency: 60kHz to 460kHz

Multiphase/Multi-ICs Operation Up to 12 Phases

Selectable CCM/DCM Modes

Thermally Enhanced 48-Lead LQFP Package

APPLICATIONS

L, LT, LTC, LTM, Linear Technology, the Linear logo, μModule, PolyPhase and OPTI-LOOP are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620,

6177787, 6580258, 6100678, 6144154, 6304066.

n

Automotive 48V/12V Dual Battery Systems

Backup Power Systems

n

TYPICAL APPLICATION

High Efficiency Bidirectional Charger/Power Supply

V

HIGH

26V TO 58V

Buck-to-Boost Transition

OV

HIGH

EXTV

CC

UV

HIGH

VFB

LOW

BUCK

BOOST

BUCK

–

SNS1

ITH

HIGH

+

V

SNSD1

LOW

+

5V/DIV

SNSA1

DRV

BST1

I

CC

ITH

L

LOW

5A/DIV

TG1

SW1

BG1

SS

V

HIGH

V

12V

BATTERY

LOW

LTC3871

10V/DIV

BUCK BOOST

BUCK

SW

50V/DIV

VFB

HIGH

IMON

–

SNS2

3871 TA01b

FREQ

+

50μ/DIV

SNSD2

SNSA2

V

LOW

+

DRV

BST2

CC

OV

LOW

TG2

DRV

CC

SW2

V5

BG2

3871 TA01a

PINS NOT SHOWN IN THIS CIRCUIT:

CLKOUT, DRVSET, FAULT, ILIM, MODE,

PHSMD, RUN, SETCUR AND SYNC.

3871f

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For more information www.linear.com/LTC3871

LTC3871

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V

....................................................... –0.3V to 100V

HIGH

Top Side Driver Voltages

(BOOST1, BOOST2) ..............................–0.3V to 111V

Switch Voltage (SW1, SW2) ....................... –5V to 100V

Current Sense Voltages

+

–

+

SS

1

2

36 BG1

35 PGND1

34 N/C

33 PGATE

32 N/C

(SNSA , SNS , SNSD Channels 1 and 2).. –0.3V to 34V

(BOOST1-SW1), (BOOST2-SW2) ...........–0.3V to 11V

VFB

ITH

LOW

HIGH

V5

SGND

HIGH

LOW

3

ITH

4

EXTV ..................................................... –0.3V to 34V

VFB

5

CC

6

31 V

HIGH

49

GND

DRV ........................................................–0.3V to 11V

7

30 N/C

CC

HIGH

OV

UV

OV

8

29 DRV

CC

VFB

, VFB

........................................ –0.3V to V5

LOW

9

28 SGND

10

27 EXTV

CC

MODE, SS Voltages...................................... –0.3V to V5

RUN ............................................................. –0.3V to 6V

FAULT, SETCUR, Voltages ........................... –0.3V to V5

ILIM, DRVSET, BUCK Voltages .................... –0.3V to V5

IMON 11

26 PGND2

25 BG2

SETCUR 12

OV

, UV

, OV

Voltages................ –0.3V to 6V

HIGH

LOW

SYNC, PHSMD Voltages .............................. –0.3V to V5

Operating Junction Temperature

LXE PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

Range (Notes 2, 3)............................. –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

T

JMAX

= 150°C, θ = 36°C/W

JA

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

DRV /EXTV Peak Current...............................100mA

CC

ORDER INFORMATION

(http://www.linear.com/product/LTC3871#orderinfo)

LEAD FREE FINISH

LTC3871ELXE#PBF

LTC3871ILXE#PBF

LTC3871HLXE#PBF

PART MARKING*

LTC3871

PACKAGE DESCRIPTION

TEMPERATURE RANGE

48-Lead (7mm × 7mm) Plastic LQFP

–40°C to 125°C

–40°C to 150°C

LTC3871

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

3871f

2

For more information www.linear.com/LTC3871

LTC3871

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 50V, V_RUN= 5V unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

5

TYP

MAX

100

UNITS

V

HIGH

V

LOW

V

HIGH

V

LOW

V

LOW

V

HIGH

V

LOW

V

HIGH

Supply Voltage Range

Regulated Feedback Voltage

EA Feedback Current

V

> 5V

1.2

30

V

HIGH

l

(Note 4); ITH

(Note 4)

Voltage = 1.5V

Voltage = 0.5V

1.188

1.185

1.200

–115

0.02

1.212

1.215

–200

0.2

V

LOW

V

HIGH

nA

%

EA Feedback Current

(Note 4)

Reference Voltage Line Regulation

/V Voltage Load Regulation

(Note 4); V

= 7V to 80V

HIGH

V

Measured in Servo Loop;

0.01

0.2

%

LOW HIGH

∆I Voltage = 1V to 1.5V

TH

Measured in Servo Loop;

–0.01

–0.2

%

∆I Voltage = 1V to 0.5V

TH

g

Transconductance Amplifier g

(Note 4); ITH

(Note 5)

= 1.5V; Sink/Source 5µA

= 0.5V; Sink/Source 5µA

2

1

mmho

mA

µA

m-buck

LOW

m-boost

HIGH

I

Q

V

HIGH

DC Supply Current

8

14

Shutdown (V

)

V

RUN

= 0V; V = 50V

HIGH

140

4.15

0.5

1.22

80

HIGH

Undervoltage Lockout

V5 Ramping Down

3.7

1.1

4.5

V

Undervoltage Hysteresis

RUN Pin On Threshold

V

RUN

Rising

1.35

V

RUN Pin On Hysteresis

mV

µA

l

RUN Pin Source Current

Soft-Start Charging Current

Current Sensing Pins Current

Total DC Sense Signal Gain

ILIM Pin Input Resistance

V

< 1.2

> 1.3

1

3

2

RUN

6.5

1.25

0.1

0.01

1.5

5

µA

RUN

I

= 1.2V

SS

0.9

1.7

1

µA

SS

+

µA

SNSA 1,2

+

1

µA

SNSD 1,2

–

mA

V/V

kΩ

µA

SNS 1,2

DCR Configuration

100

7.5

l

I

Current to Program Initial Current Limit

6.75

8.25

10

SETCUR

IMON Current Proportional to V

Max Current

at

V

ILIM

= Float; R = 3mΩ

SENSE

%

LOW

IMON Zero Current Voltage

Sense Pin to IMON Gain

1.225

1.25

38

19

5

1.275

V

= 0V, 1/4 V , Float

V/V

ILIM

V5

= 3/4 V , V

V/V

Ω

ILIM

V5 V5

TG Pull-Up On-Resistance

TG Pull-Down On-Resistance

2.5

5

Ω

BG Driver Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

Total DC Sense Signal Gain

Maximum Duty Cycle

Ω

2.5

4

Ω

R

Configuration

V/V

SENSE

Buck Mode

Boost Mode

96

98

92

%

3871f

3

For more information www.linear.com/LTC3871

LTC3871

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 50V, V_RUN= 5V unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Maximum Current Sense Threshold

(Buck and Boost Mode)

0°C to 150°C

SENSE(MAX)

l

(DCR Sensing)

V

ILIM

V

ILIM

V

ILIM

V

ILIM

V

ILIM

= 0V

8

17

26.5

36

44.5

10

20

30

40

50

14.5

24

33.5

44.5

55.5

mV

= 1/4 V

= Float

= 3/4 V

V5

= V

V5

V

(R

Sensing)

Maximum Current Sense Threshold

(Buck and Boost Mode)

0°C to 150°C

SENSE(MAX)

l

V

ILIM

V

ILIM

V

ILIM

V

ILIM

V

ILIM

= 0V

10

12.5

25

37.5

50

18.2

30

41.9

55.6

69.4

mV

SENSE

= 1/4 V

= Float

= 3/4 V

21.3

33.2

45

V5

= V

55.6

62.5

V5

V

Maximum Current Sense Threshold

(Buck and Boost Mode)

–40°C to 150°C

SENSE(MAX)

l

(DCR Sensing)

V

= 0V

7

10

20

30

40

50

14.5

24

33.5

44.5

55.5

mV

ILIM

= 1/4 V

= Float

= 3/4 V

16

26

35

42

V5

= V

V5

V

(R

Sensing)

Maximum Current Sense Threshold

(Buck and Boost Mode)

–40°C to 150°C

SENSE(MAX)

l

V

ILIM

V

ILIM

V

ILIM

V

ILIM

V

ILIM

= 0V

8.8

20

32.5

43.8

52.5

12.5

25

37.5

50

18.2

30

41.9

55.6

69.4

mV

SENSE

= 1/4 V

= Float

= 3/4 V

V5

= V

62.5

V5

TG t

Top Gate Rise Time

Top Gate Fall Time

(Note 6)

60

ns

r

f

BG t

Bottom Gate Rise Time

Bottom Gate Fall Time

(Note 6)

r

f

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

(Note 6) C

= 3300pF Each Driver

LOAD

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

(Note 6) C

V5 Regulation Voltage

V5 Load Regulation

6V < V

< 10V

5.3

5.5

0.5

10

9

5.7

1

V

%

DRVCC

I

= 0mA to 20mA

V5

V

DRV Regulation Voltage

12V < V

< 30V, V

= V

V5

9.5

8.5

7.5

6.5

5.5

10.5

9.5

8.5

7.5

6.5

1

V

DRVCC

CC

EXTVCC

DRVSET

= 3/4 V

= Float

= 1/4 V

= 0V

V

V5

8

V

7

V

V5

6

V

DRV Load Regulation

I

CC

= 0mA to 20mA, V = 10V

EXTVCC

0.2

%

CC

EXTV Switchover Voltage

EXTV Ramping Positive

DRV –0.5V

V

EXTVCC

CC

EXTV Hysteresis

10

60

%

CC

CLKOUT Phasing Phase Relative to Channel 1

V

= 0V

Deg

PHSMD

= 1/4 V

= Float

= 3/4 V

60

V5

90

45

V5

= V

240

Deg

V5

3871f

4

For more information www.linear.com/LTC3871

LTC3871

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C, V_HIGH= 50V, V_RUN= 5V unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0

MAX

UNITS

Deg

V

SYNC Phasing

Phase Relative to Channel 1

V

= 0V

PHSMD

= 1/4 V

= Float

= 3/4 V

90

0

V5

0

V5

= V

0

V5

Channel to

Channel Phasing

Channel 1 to Channel 2

= 0V

180

120

5.5

0

= 1/4 V

= Float

= 3/4 V

V5

= V

V5

CLKOUT

Clock Output High Voltage

Clock Output Low Voltage

Sync Input Threshold

I

= 0.5mA

5.2

2

HI

LOAD

= –0.5mA

Rising

0.2

V

LO

V

SYNC

V

SYNC

Falling

1.2

220

60

V

Nominal Frequency

R

FREQ

R

FREQ

R

FREQ

= 51.1kΩ

= ≤20kΩ

= 117kΩ

180

40

200

50

kHz

kΩ

µA

f

Low Fixed Frequency

High Fixed Frequency

Synchronizable Frequency

SYNC Input Resistance

Frequency Setting Current

FAULT Voltage Low

LOW

450

60

500

550

460

HIGH

l

SYNC = External Clock

100

20

I

18

22

0.3

1

FREQ

I

= 2mA

= 5.5V

0.1

V

FAULT

FAULT Leakage Current

FAULT Delay

V

µA

FAULT

Going Low

125

1.2

5

µs

V

LOW

V

LOW

V

HIGH

V

HIGH

V

HIGH

V

HIGH

OV Comparator Threshold

OV Comparator Hysteresis

OV Comparator Threshold

OV Comparator Hysteresis

UV Comparator Threshold

UV Comparator Hysteresis

1.15

1.25

V

> 1.2V

< 1.2V

µA

OVLOW

OVHIGH

UVHIGH

1.2

5

V

µA

1.2

5

V

µA

BUCK Pin Pull-Up Resistance

BUCK Pin to V5

200

kΩ

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package

thermal impedance and other environmental factors.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability

and lifetime.

Note 3: T is calculated from the ambient temperature T and

J

A

power dissipation P according to the following formula: T = T +

(P • 36°C/W).

D

Note 2: The LTC3871 is tested under pulsed load conditions such that

D

J

A

T ≈ T . The LTC3871E is guaranteed to meet performance specifications

J

A

from 0°C to 85°C junction temperature. Specifications over the

Note 4: The LTC3871 is tested in a feedback loop that servos V

and

ITHHIGH

–40°C to 125°C operating junction temperature range are assured by

design, characterization and correlation with statistical process controls.

The LTC3875I is guaranteed over the –40°C to 125°C operating junction

temperature range. The LTC3871H is guaranteed over the full –40°C to

150°C operating junction temperature range. High junction temperature

degrades operating lifetimes; operating lifetime is derated for junction

temperatures greater than 125°C. Note that the maximum ambient

V

to a specified voltage and measures the resultant V

, respectively.

and

ITHLOW

FBHIGH

FBLOW

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

3871f

5

For more information www.linear.com/LTC3871

LTC3871

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency Buck Mode

Power Loss Buck Mode

Efficiency Boost Mode

100

95

90

85

80

75

70

65

60

30

25

20

15

10

5

100

95

90

85

80

75

70

65

60

55

50

V

HIGH

V

LOW

= 48V

= 12V

FIGURE 12 CIRCUIT

V

= 48V

= 12V

V

= 48V

= 12V

HIGH

LOW

HIGH

LOW

FIGURE 12 CIRCUIT

0

1

10

100

1

10

(A)

100

0.1

1

10

50

I

(A)

I

(A)

LOAD

3871 G01

3871 G02

3871 G03

SS Pull-Up Current

vs Temperature

Power Loss Boost Mode

RUN Threshold vs Temperature

30

25

20

15

10

5

2.0

1.8

1.6

1.4

1.2

1.0

1.4

1.3

1.2

1.1

1.0

0.9

V

HIGH

V

LOW

= 48V

= 12V

ON

OFF

FIGURE 12 CIRCUIT

0

0.1

1

10

50

–45 –20

5

30 55 80 105 130 155

–45 –20

5

30 55 80 105 130 155

I

(A)

TEMPERATURE (°C)

LOAD

3871 G04

3871 G05

3871 G06

Regulated Feedback Voltage

vs Temperature

Oscillator Frequency

vs Temperature

Undervoltage Lockout Threshold

(V₅) vs Temperature

1.206

1.204

1.202

1.200

1.198

1.196

1.194

230.0

220.0

210.0

200.0

190.0

180.0

170.0

5.0

4.8

4.6

4.4

4.2

4.0

RISING

–45 –20

5

30 55 80 105 130 155

–45 –20

5

30 55 80 105 130 155

–45 –20

5

30 55 80 105 130 155

TEMPERATURE (°C)

3871 G07

3871 G08

3871 G09

3871f

6

For more information www.linear.com/LTC3871

LTC3871

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ Pin Source Current

vs Temperature

Quiescent Current vs Temperature

Shutdown Current vs Temperature

21.5

21.0

20.5

20.0

19.5

19.0

18.5

10.0

9.0

8.0

7.0

6.0

5.0

200

180

160

140

120

100

V

= 50V

V

= 50V

HIGH

–45 –20

5

30 55 80 105 130 155

–45 –20

5

30 55 80 105 130 155

–45 –20

5

30 55 80 105 130 155

TEMPERATURE (°C)

3871 G12

3871 G10

3871 G11

Current Sense Threshold vs

ITH Voltage (DCR)

Maximum Current Sense Threshold

vs Duty Cycle – BUCK (DCR)

Maximum Current Sense Threshold

vs Feedback Voltage (DCR)

50

40

60.0

50.0

40.0

30.0

20.0

10.0

0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0

GND

1/4 V5

FLOAT

3/4 V5

V5

1/4 V5

FLOAT

3/4 V5

V5

1/4 V5

FLOAT

3/4 V5

V5

30

20

10

0

–10

–20

–30

–40

–50

0

0.5

1

1.5

2

0

0.2

0.5

0.7

1.0

1.2

0

10 20 30 40 50 60 70 80 90 100

ITH VOLTAGE (V)

FEEDBACK VOLTAGE (V)

DUTY CYCLE (%)

3871 G13

3871 G15

3871 G14

Current Sense Threshold vs

Maximum Current Sense Threshold

vs Feedback Voltage (R_SENSE)

ITH Voltage (R_SENSE

)

vs Duty Cycle – BUCK (R_SENSE

)

70

50

80.0

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0

GND

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0

1/4 V5

FLOAT

3/4 V5

V5

GND

1/4 V5

FLOAT

3/4 V5

V5

1/4 V5

FLOAT

3/4 V5

V5

30

10

–10

–30

–50

–70

0

0.5

1

1.5

2

0

10 20 30 40 50 60 70 80 90 100

0

0.2

0.5

0.7

1.0

1.2

ITH VOLTAGE (V)

DUTY CYCLE (%)

FEEDBACK VOLTAGE (V)

3871 G16

3871 G17

3871 G18

3871f

7

For more information www.linear.com/LTC3871

LTC3871

PIN FUNCTIONS

SS (Pin 1): Soft-Start Input. The voltage ramp rate at this

pin sets the voltage ramp rate of the regulated voltage. A

capacitortogroundaccomplishessoft-startinbuckmode.

This pin has a 1.25µA pull-up current.

SETCUR (Pin 12): This pin sets the maximum average

inductor current in buck or boost mode. This pin sources

7.5µA.

+

SNSA1 /SNSA2 (Pins 13 and 48): AC Positive Current

Sense Comparator Inputs. These inputs amplify the AC

portionofthecurrentsignaltotheIC’scurrentcomparator.

VFB

(Pin 2): V

Voltage Sensing Error Amplifier

LOW

Inverting Input.

–

ITH /ITH

(Pins 3 and 4): Current Control Thresh-

HIGH

SNS1 /SNS2 (Pins 14 and 47): Negative Current Sense

LOW

old and Error Amplifier Compensation Point. The current

Comparator Inputs. The negative input of the current

comparator is normally connected to V

comparator’sthresholdvarieswiththeITHcontrolvoltage.

.

LOW

+

VFB

(Pin 5): V

Voltage Sensing Error Amplifier

HIGH

SNSD1 /SNSD2 (Pins 15 and 46): DC Positive Current

Sense Comparator Inputs. These inputs amplify the DC

portionofthecurrentsignaltotheIC’scurrentcomparator.

HIGH

Inverting Input.

V5 (Pin 6): Internal 5.5V Regulator Output. The control

circuits are powered from this voltage. Bypass this pin

to SGND with a minimum of 4.7µF low ESR tantalum or

ceramic capacitor.

BUCK (Pin 16): The voltage on this pin determines if the

IC is regulating the V

or tie this pin to V5 for buck mode operation. Ground this

pin for boost mode operation.

or V

voltage/current. Float

LOW

HIGH

SGND (Pins 7 and 28): Signal Ground Pins.

ILIM (Pin 17): Current Comparator Sense Voltage Limit

Selection Pin. The input impedance of this pin is 100kΩ.

OV

(Pin 8): V

Overvoltage Threshold Set Pin. A

HIGH

resistor divider from V

is needed to set this thresh-

HIGH

old. When the voltage on this pin rises past the 1.2V trip

point, a 5µA current is sourced out of the pin to provide

RUN(Pin18):EnableControlInput.Avoltageabove1.22V

turns on the IC. There is a 2µA pull-up current on this pin.

Once the RUN pin rises above the 1.22V threshold the

pull-up current increases to 6µA.

externally adjustable hysteresis. When OV

above 3V, the controller stops switching.

voltage is

HIGH

UV

(Pin 9): V

Undervoltage Threshold Set Pin. A

HIGH

FAULT (Pin 19): Fault Indicator Output. Open-drain output

that pulls to ground during a fault condition.

HIGH

resistor divider from V

is needed to set this threshold.

HIGH

This pin also controls the state of the PGATE pin. When

the voltage on this pin falls below the 1.2V trip point,

a 5µA current is sunk into the pin to provide externally

adjustable hysteresis.

DRVSET(Pin20):Thevoltagesettingonthispinprograms

the DRV output voltage. The input impedance of this

CC

pin is 100kΩ.

NC (Pins 21, 30, 32, 34, 40): No Connect Pins.

OV

(Pin 10): V

Overvoltage Threshold Set Pin. A

LOW

TG1/TG2 (Pins 22 and 39): Top Gate Driver Outputs. This

resistor divider from V

is needed to set this threshold.

is the output of the floating driver with a voltage swing

When the voltage on this pin rises past the 1.2V trip point,

a5µAcurrentissourcedoutofthepintoprovideexternally

adjustable hysteresis.

equal to DRV superimposed on the SW voltage.

CC

SW1/SW2 (Pins 23 and 38): Switch Node Connections to

the Inductors. Voltage swing at this pin is from a Schottky

IMON (Pin 11): The voltage on this pin is directly propor-

tional to the average inductor currents of the 2 channels.

1.25V indicates zero average inductor current per phase.

diode (external) voltage drop below ground to V

.

HIGH

BOOST1/BOOST2 (Pins 24 and 37): Boosted Floating

DriverSupplies.The(+)terminalofthebootstrapcapacitor

connects to this pin. This pin swings from a diode drop

below DRV up to V

+DRV .

CC

HIGH

CC

3871f

8

For more information www.linear.com/LTC3871

LTC3871

PIN FUNCTIONS

BG1/BG2 (Pins 25 and 36): Bottom Gate Driver Outputs.

CLKOUT (Pin 41): Clock Output Pin. Use this pin to syn-

chronize multiple LTC3871 ICs. Signal swing is from V5

to ground.

This pin drives the gate(s) of the bottom N-channel

MOSFET(s) between PGND and DRV .

CC

PGND1/PGND2 (Pins 26 and 35): Power Ground Pin.

SYNC (Pin 42): Applying a clock signal to this pin causes

theinternalPLLtosynchronizetheinternaloscillatortothe

clock signal. The PLL compensation network is integrated

ontotheIC. Thispinhasa100kinternalresistortoground.

Connect this pin closely to the source(s) of the bottom

N-channel MOSFET(s), the (–) terminal of CDRV and

CC

(–) terminal of CV

.

HIGH

EXTV (Pin 27): External Power Input to an Internal

FREQ (Pin 43): Frequency Set Pin. A resistor between this

CC

LDO Connected to DRV . When the voltage on this pin

pin and SGND sets the switching frequency.

CC

is greater than the DRV LDO setting minus 500mV,

CC

MODE (Pin 44): Tying this pin to SGND enables forced

continuous mode in buck or boost modes. Floating this

pin results in discontinuous mode when in buck mode

and forced continuous mode in boost mode. Tying this

pin to V5 enables discontinuous mode in buck mode and

non-synchronous operation in boost mode. The input

impedance of this pin is 50kΩ.

this LDO bypasses the internal LDO powered from V

.

HIGH

DRV (Pin 29): Gate Driver Current Supply LDO Output.

CC

The voltage on this pin can be set from 6V to 10V in 1V

increments. Bypass this pin to PGND with a minimum of

4.7µF low ESR tantalum or ceramic capacitor.

V

(Pin 31): Main V

supply. Bypass this pin to

HIGH

PGND with a capacitor (0.1µF to 1µF)

PHSMD (Pin 45): Phase Mode Pin. This pin selects

CH1 – CH2 and CH1 – CLKOUT phasing.

PGATE (Pin 33): Gate Drive for Input Short Protection.If

a UV

fault is detected, PGATE drives the gate of an

GND (Exposed Pad Pin 49): Ground. Must be soldered

to PCB ground for rated thermal performance. Connect

this pin closely to the sources of the bottom N-channel

HIGH

external PMOS in series with the V

rail high. Signal

HIGH

–15V

HIGH .

swings is from V

to V

HIGH

MOSFETsandnegativeterminalofV

,DRV ,V bypass

HIGH

CC 5

capacitors. All small signal components and compensa-

tion components should connect here. Signal ground pin

should be connected to this exposed pad.

3871f

9

For more information www.linear.com/LTC3871

LTC3871

BLOCK DIAGRAM

Bidirectional Controller with Current Programming and Monitoring Functions

DRV

CC

BUCK

PGATE

V

MODE

V

HIGH

BOOST1

TG1

HIGH

BUCK_EN

BOOST_EN

V

LOW

V5

VHIGH_UV

–15V

200k

UV

100k

V

OV

LOW

HIGH

SW1

V5

+

–

CLK

+

FCB

100k

VLOW_OV

LOGIC1

DRV

CC

V

BG1

PGND

BG2

REF

V5

V

–

SNS1

–

REF

+

SNSA1

200k

ILIM

+

SNSD1

V

I

LOW

REV1,2

–

+

200k

V

HIGH

V

HIGH

V

REF

UV

HIGH

UV

CC

VFLD

VHIGH_UV

SW2

TG2

LOGIC2

CLK

V

REF

I

CMP1,2

+

–

OV

HIGH

–

SNS2

+

BOOST2

+

V5

SNSA2

SNSD2

V

_OV

LOW

–

SS

SETCUR

IMON

ILIM

V

HIGH

–

+

DRV

CC

EA_VHIGH

BOOST_EN

1.20V

VFB

HIGH

SLOPE

VFB

LOW

–

+

V

LOW

EA_CURRENT LIMIT

SYNC

EA_VLOW

BUCK_EN

1.20V

+

SS

PHASE DET

ITH

LOW

+

BUS

100k

V5

SNSA1

ICMP1

20µA

+

–

FREQ

+

SNSD1

SNS1

+

–

PLL/OSC

CLK

V5

+

–

SNSA2

SNSD2

SNS2

ICMP2

200k

+

–

PHSMD

CLKOUT

V5

200k

+

–

V

HIGH

200k

EXTV

CC

EXTV

LDO REG

INTERNAL

LDO REG

FAULT

CC

UV

VHIGH_UV

VLOW_OV

DRVSET

–

+

OV

HIGH

DRV

CC

6V TO 10V

+

V

REF

2µA/6µA

PGND

5V LDO

V5

RUN

SHDN

ITH

SGND

HIGH

3871 BD

3871f

10

For more information www.linear.com/LTC3871

LTC3871

OPERATION

Main Control Loop

to a DCR sense signal that has a 14dB (5 times) signal-

to-noise ratio. Accordingly, the current limit threshold is

still a function of the inductor peak-current and its DCR

value, and can be accurately set from 10mV to 50mV in

10mV steps with the ILIM pin. The filter time constant,

TheLTC3871isabidirectional,constant-frequency,current

mode step-down controller with two channels operating

180° or 120° out of phase. The LTC3871 is capable of

delivering power from V

to V

as well as from

HIGH

LOW

+

R1 • C1, of the SNSD pin should match the L/DCR of

V

back to V

LOW

. When power is delivered from V

LOW

to V

HIGH HIGH

, the LTC3871 operates as a peak-current mode

+

the output inductor, while the filter at SNSA pin should

+

have a bandwidth of five times larger than SNSD , R2 • C2

constant-frequency buck regulator; and when power

delivery is reversed, it operates as a valley current mode

constant-frequency boost regulator. Four control loops,

two for current and two for voltage, allow control of volt-

equals R1 • C1/5 (refer to Figure 3).

Current Sensing with Low Value R

SENSE

The LTC3871 can also be used with an external low value

age or current on either V

or V

. The LTC3871

LOW

HIGH

R

resistorforincreasedaccuracy.Toaccomplishthis,

uses an LTC-proprietary current sensing, current mode

architecture. During normal buck mode operation, the

top MOSFET is turned on every cycle when the oscillator

sets the RS latch, and turned off when the main current

SENSE

+

the SNSA pin needs a filter time constant R2 • C2 that

has a bandwidth that is four times larger than the L/(R

The SNSD pin is now connected to the R

).

SENSE

+

resistor as

SENSE

shown in Figure 1. A small filter cap may be used to filter

out high frequency noise (refer to Figure 4).

comparator, I

, resets the RS latch. The peak inductor

CMP

current at which I

resets the RS latch is controlled by

the voltage on the ITH pin, which is the output of the error

amplifier, EA. The error amplifier receives the feedback

signalandcomparesittotheinternal1.2Vreference.When

the load current increases, it causes a slight change in the

feedback pin voltage relative to the 1.2V reference, which

in turn causes the ITH voltage to change until the induc-

tor’s average current equals the new load current. After

the top MOSFET has turned off, the bottom synchronous

MOSFET is turned on until the beginning of the next cycle.

TO SENSE FILTER LOCATED

NEXT TO THE CONTROLLER

C

OUT

3871 F01

Figure 1. Sense Lines Placement with Sense Resistor

DRV /EXTV /V5 Power

CC

Power for the top and bottom MOSFET drivers is derived

from the DRV pin. The DRV voltage can be set to any-

CC

The main control loop is shut down by pulling the RUN pin

low. Releasing RUN allows an internal 2µA current source

to pull-up the RUN pin. When the RUN pin reaches 1.22V,

the main control loop is enabled and the IC is powered

up and the pull-up current increases to 6.5µA. When

the RUN pin is low, all functions are kept in a controlled

shutdown state.

where from 6V to 10V in 1V steps using the DRVSET pin.

When the EXTV pin is left open or tied to a voltage less

CC

than (DRV – 1V), an internal linear regulator supplies

CC

DRV power from V

When EXTV is taken above

CC

HIGH.

CC

(DRV – 500mV), the internal regulator between DRV

CC

and V

is turned off, and a second internal regulator is

HIGH

turned on between EXTV and DRV . Each top MOSFET

CC

driver is biased from a floating bootstrap capacitor, which

normally recharges during each off cycle through an ex-

ternal diode when the top MOSFET turns off. If the input

Current Sensing with Low DCR

TheLTC3871employsauniquearchitecturetoenhancethe

signal-to-noise ratio with low current sense offsets. That

enables it to operate with a small current sense signal of a

very low value inductor DCR to improve power efficiency,

and reduce jitter due to switching noise which could cor-

rupt the signal. The LTC3871 uses two positive current

voltage, V

, decreases to a voltage close to V

, the

HIGH

LOW

loop may enter dropout and attempt to turn on the top

MOSFET continuously. The dropout detector detects this

and forces the top MOSFET off for about one-twelfth of

the clock period plus 100ns every fifth cycle to allow the

bootstrap capacitor to recharge.

+

sense pins, SNSD and SNSA , to acquire signals and

processtheminternallytoprovidetheresponseequivalent

3871f

11

For more information www.linear.com/LTC3871

LTC3871

OPERATION

Most of the internal circuitry is powered from the V5

start-up of the controller’s V

voltage is controlled by

LOW

rail that is generated by an internal linear regulator from

the voltage on the SS pin. When the voltage on the SS pin

is less than the 1.2V internal reference, the LTC3871 regu-

DRV . The V5 pin needs to be bypassed with a 2.2µF

CC

to 10µF external capacitor between V5 and SGND. This

pin provides a 5.5V output that can supply up to 20mA

of current. See the Application section for more details.

lates the VFB

voltage to the SS pin voltage instead of

LOW

the 1.2V reference. This allows the SS pin to be used to

program a soft-start by connecting an external capacitor

fromtheSSpintoGND. Aninternal1.25µApull-upcurrent

charges this capacitor, creating a voltage ramp on the SS

pin. As the SS voltage rises linearly from 0V to 1.2V (and

Soft-Start (Buck Mode)

By default, the start-up of the V

voltage is normally

LOW

beyond), the V

voltage, rises smoothly from zero to

LOW

controlled by an internal soft-start ramp. The internal

soft-start ramp represents a non-inverting input to the

its final value. When the RUN pin is pulled low to disable

the controller, or when V5 drops below its undervoltage

lockout threshold of 4.15V, the SS pin is pulled low by

an internal MOSFET. When in undervoltage lockout, the

controller is disabled and the external MOSFETs are held

off. External circuitry can be added to discharge the soft-

startcapacitorduringfaultconditionstoensureasoft-start

when the faults are cleared.

error amplifier. The VFB

pin is regulated to the lower

LOW

of the error amplifier’s three non-inverting inputs (the

internal soft-start ramp, the SS pin or the internal 1.2V

reference). As the ramp voltage rises from 0V to 1.2V

over approximately 1ms, the V

voltage rises smoothly

LOW

from its pre-biased value to its final set value. Certain ap-

plications can require the start-up of the converter into a

non-zero load voltage, where residual charge is stored on

Frequency Selection and Phase-Locked Loop (FREQ

and SYNC Pins)

the V

capacitor at the onset of converter switching. In

LOW

order to prevent the V

from discharging under these

LOW

conditions, the top and bottom MOSFETs are disabled

until soft-start is greater than VFB

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

.

LOW

Soft-Start (Boost Mode)

The same internal soft-start capacitor and external soft-

start capacitor are also active if the controller starts with

boost mode of operation. The error amplifier for boost

mode also tries to regulate to the lowest reference during

start-up. However, the topology of the boost converter

limits the effectiveness of this soft-start mechanism until

the boost output voltage reaches its input voltage level.

Therefore, it is recommended that the controller starts in

buck mode of operation.

If the SYNC pin is not being driven by an external clock

source, the FREQ pin can be used to program the control-

ler’s operating frequency from 50kHz to 500kHz. There

is a precision 20µA current flowing out of the FREQ pin

so that the user can program the controller’s switching

frequency with a single resistor to SGND. A curve is pro-

videdlaterintheApplicationsInformationsectionshowing

the relationship between the voltage on the FREQ pin and

switching frequency (Figure 7).

Shutdown and Start-Up (RUN and SS Pins)

A phase-locked loop (PLL) is available on the LTC3871

to synchronize the internal oscillator to an external clock

source that is connected to the SYNC pin. The PLL loop

filter network is integrated inside the LTC3871. The

phase-locked loop is capable of locking any frequency

withintherangeof60kHzto460kHz.Thefrequencysetting

resistor should always be present to set the controller’s

initial switching frequency before locking to the external

TheLTC3871canbeshutdownusingtheRUNpin. Pulling

theRUNpinbelow1.14Vshutsdownthemaincontrolloop

for the controller and most internal circuits, including the

DRV and V5 regulators. Releasing the RUN pin allows

CC

an internal 2µA current to pull-up the pin and enable the

controller. Alternatively, the RUN pin may be externally

pulled up or driven directly by logic. Be careful not to ex-

ceed the absolute maximum rating of 6V on this pin. The

3871f

12

For more information www.linear.com/LTC3871

LTC3871

OPERATION

clock. The controller operates in the user selected mode

when it is synchronized.

Fault Flag (FAULT, OV

, OV

and UV

Pins)

HIGH

LOW

HIGH

TheFAULTpinisconnectedtotheopen-drainofaninternal

N-channel MOSFET. It can be pulled high with an external

resistor connected to a voltage up to 6V, such as V5 or an

external bias voltage. The FAULT pin is pulled low when:

Multiphase Operation

For output loads that demand high current, multiple

LTC3871s can be daisy chained to run out of phase to

provide more output current without increasing input and

output voltage ripple. The SYNC pin allows the LTC3871

to synchronize to the CLKOUT signal of another LTC3871.

The CLKOUT signal can be connected to the SYNC pin of

the following LTC3871 stage to line up both the frequency

and the phase of the entire system. Tying the PHSMD

pin to V5, GND or floating, generates a phase difference

(between CH1 and CLKOUT) of 240°, 60° or 90° respec-

tively, and a phase difference (between CH1 and CH2)

of 120°, 180° or 180°. Tying PHSMD to 1/4 or 3/4 of V5

generates a phase difference of 60° or 45° between CH1

and CLKOUT. Figure 2 shows the PHSMD connections

necessary for 3-, 4-, 6-, 8- or 12-phase operation. A total

of 12 phases can be daisy chained to run simultaneously

out of phase with respect to each other. When paralleling

multiple ICs, please be aware of the input impedance of

pins connected to the same node.

a. The RUN pin is below its turn on threshold.

b. When V5 is below its UVLO threshold.

c. Any ofthe three OV/UV comparators have been tripped.

d. During a startup sequence until the SS pin charges up

past 1.2V.

TheOV

andOV

thresholdsaresetusinganexternal

LOW

HIGH

resistordividersoffofV

andV

,respectively.When

HIGH

LOW

the voltage at the pin exceeds the comparator threshold

of 1.2V, a 5µA hysteresis current is sourced out of the

respectivepin and the FAULT signalgoes lowaftera 125µs

delay. The UV

threshold is also set using an external

HIGH

resistor divider off V

. When the voltage at the pin falls

below the comparator threshold of 1.2V, a 5µA hysteresis

current is sunk in to the UV pin and the FAULT signal

goes low after a 125µs delay. The amount of hysteresis

can be adjusted by changing the total impedance of the

resistor divider, while the resistor ratio sets the UV/OV

trip point.

HIGH

Undervoltage Lockout

The LTC3871 has two functions that help protect the

controller in case of undervoltage conditions. A precision

UVLO comparator constantly monitors the V5 voltage to

ensure that an adequate voltage is present. It locks out

the switching action when V5 is below 4.15V. To prevent

oscillationwhenthereisadisturbanceontheV5,theUVLO

comparator has 500mV of precision hysteresis.

BesidesflaggingtheFAULTpin,theUV/OVcomparatorsalso

affect the operation of the controller, as shown in Table 1.

When the OV

comparator crosses its 1.2V threshold:

LOW

a. In buck mode, the controller stops switching.

b. In boost mode, the controller continues to switch.

c. ITH and SS are unaffected in both buck and boost

modes. Whenever a fault is detected, discharge the SS

pin as needed externally.

Anotherwaytodetectanundervoltageconditionistomoni-

tor the V

supply. Because the RUN pin has a precision

HIGH

turn-on reference of 1.22V, one can use a resistor divider

to V to turn on the IC when V is high enough.

When the OV

of 1.2V:

comparator crosses its 1st threshold

HIGH

An extra 4.5µA of current flows out of the RUN pin once

the RUN pin voltage passes 1.22V. The RUN comparator

itself has about 80mV of hysteresis. Additional hysteresis

for the RUN comparator can be programmed by adjust-

a. The controller stops switching in both buck and

boost modes.

ing the values of the resistive divider. For accurate V

b. ITH and SS are unaffected in both buck and boost

modes. Whenever a fault is detected, discharge the SS

pin as needed externally.

HIGH

undervoltage detection, V

needs to be higher than 5V.

HIGH

3871f

13

For more information www.linear.com/LTC3871

LTC3871

OPERATION

0,180

90,270

0,120

LTC3871

SYNC

240,60

LTC3871

SYNC

+90

+240

CLKOUT

PHSMD

V5

PHSMD

3871 F02b

3871 F02a

Figure 2a. 3-Phase Operation

Figure 2b. 4-Phase Operation

0,180

LTC3871

SYNC

60,240

120,300

LTC3871

SYNC

LTC3871

SYNC

+60

CLKOUT

PHSMD

CLKOUT

PHSMD

3871 F02c

Figure 2c. 6-Phase Operation

0,180

90,270

LTC3871

SYNC

135,315

LTC3871

225,45

LTC3871

SYNC

+90

+45

+90

CLKOUT

PHSMD

3/4 V5

PHSMD

3871 F02d

Figure 2d. 8-Phase Operation

0,180

LTC3871

SYNC

60,240

120,300

LTC3871

SYNC

+60

CLKOUT

PHSMD

150,330

LTC3871

210,30

270,90

LTC3871

SYNC

LTC3871

SYNC

+60

CLKOUT

1/4 V5

PHSMD

3871 F02e

Figure 2. 12-Phase Operation

3871f

14

For more information www.linear.com/LTC3871

LTC3871

OPERATION

WhentheOV

comparatorcrossesits2ndthresholdof3V:

The PGATE pin drives the gate of an external MOSFET

HIGH

betweenV andV

–15V—thispinisinternallyclamped

IN

HIGH

a. The controller stops switching in both buck and boost

modes.

to V

–15V to protect the gate oxide of the external

HIGH

MOSFET. In normal operation, the P-channel MOSFET is

b. BothITHandIMONpinsaredrivenintohighimpedance.

This feature allows the users to isolate one LTC3871

from a multiphase system in the case a fault is detected

on one particular IC.

always on, with its gate-source voltage clamped to 15V

maximum. When the UV

pin voltage goes below its

HIGH

1.2V threshold, FAULT goes low 125µs later. At this point,

thePGATEpinvoltagetransitionsfromV –15VtoV

,

HIGH

turning off the external P-channel MOSFET. The MOSFET

c. The SS pin is unaffected.

needs to be connected such that its body diode will block

When the UV

comparator crosses its 1.2V threshold:

HIGH

the current path from V

to V . In buck mode, the

HIGH

LOW

switching action stops when PGATE is off and a fault con-

dition is reported; In boost mode, the controller will still

switch and regulate the programmed boost voltage on the

source side of the PGATE. Output cap should be present

at the source side of the PGATE. A fault condition is also

reported in this case. The external P-channel MOSFET

a. In buck mode, the controller stops switching after a

125μsec delay and disconnects V

from V

with

HIGH

LOW

an external P-channel MOSFET via the PGATE pin.

b. In boost mode, the controller continues to switch, but it

disconnectsV

fromV

withanexternalP-channel

HIGH

LOW

MOSFETaftera125μsecdelay.Thevoltageatthesource

side of the P-channel MOSFET is still regulated.

remains disconnected until V

rises high enough to

HIGH

un-trip the UV

comparator.

HIGH

c. ITH and SS are unaffected in both buck and boost

modes. Whenever a fault is detected, discharge the SS

pin as needed externally.

Current Monitoring and Regulation (IMON, SETCUR Pins)

The inductor current can be sensed using either its DCR

or a R

resistor. The current monitoring pin, IMON,

SENSE

Input Disconnect (PGATE Pin)

outputsavoltagethatisproportionaltotheaverageinduc-

tor current of the two channels sensed by the LTC3871.

The operational range of IMON is 0.5V to 2.5V. When the

average inductor current is zero, the IMON pin voltage

rests at 1.25V. As the inductor current increases in buck

In a typical boost controller, the synchronous diode or

the body diode of the synchronous MOSFET conducts

current from the input to the output until the output is a

diode drop below the input. As a result an output (V

)

HIGH

short will drag the input (V

) down without a blocking

mode, the I

voltage proportionally increases. The cur-

LOW

MON

diode or MOSFET to block the current. The LTC3871 uses

an external low RDS(ON) P-channel MOSFET for input

rent sense signal to I

gain is 38 for the 10mV, 20mV

MON

and 30mV ILIM settings, and 19 for the 40mV and 50mV

ILIM settings. An external voltage can be applied to the

SETCURpintoregulatetheaverageoutputcurrent.Because

short-circuit protection when V

is shorted to ground.

HIGH

Table 1: OV/UV Faults

FAULT

OV

1.2V Threshold

MODE

Buck

SWITCHING

Stops

ITH PINS

IMON

No Effect

Hi-Z

SS

PGATE PIN

Low

No Effect

Hi-Z

No Effect

LOW

Boost

Buck

Continues

Stops

Low

OV

Low

HIGH

1.2V Threshold

Boost

Buck

Stops

Low

OV

Stops

Low

HIGH

3V Threshold

Boost

Buck

Stops

Hi-Z

Low

UV

Stops

No Effect

High

HIGH

1.2V Threshold

Boost

Continues

3871f

15

For more information www.linear.com/LTC3871

LTC3871

OPERATION

SETCUR and IMON are the two inputs to the current loop

gain amplifier with SETCUR acting as the reference, as the

IMONpinvoltageapproachesSETCUR,theITHpincontrol

is taken over by the current regulation error amplifier from

the voltage loop error amplifier.

I

, the total average output current,

OUT

R

, the current sensing element value;

SENSE

m, the number of phases.

To defeat the current programming operation, tie the

SETCUR pin to V in buck mode and ground the SETCUR

pin in boost mode.

In boost mode, the inductor current polarity is reversed,

sothecorrespondingIMONandSETCURrangesare1.25V

to 0.5V with 0.5V being the maximum boost current. The

SETCUR pin sources an accurate 7.5µA current in both

modes,allowingthisvoltagetobesetwithasingleresistor

for convenience. The SETCUR value defaults to the zero

current value internally if the SETCUR pin sees a voltage

that is out of range for the selected mode. The valid range

of SETCUR is 1.25V to 2.5V for buck mode and 1.25V to

0.5V for boost mode. Therefore, if SETCUR voltage is set

below 1.25V in buck mode, the internal SETCUR voltage

is forced at 1.25V. If SETCUR voltage is set above 1.25V

in boost mode, the internal SETCUR voltage is also forced

at 1.25V. For battery charging applications, SETCUR can

be programmed dynamically on-the-fly to set the charg-

ing currents to the batteries in either buck or boost mode.

SETCURcanbeusedatstart-uptolimitthein-rushcurrent

in both buck mode and boost mode.

5

Buck and Boost Modes (BUCK Pin)

TheLTC3871canbedynamicallyandseamlesslyswitched

from buck mode to boost mode and vice versa via the

BUCK pin. Tie this pin to V5 to select buck mode and to

ground to select boost mode operation. This pin has an

internal pull up resistor that defaults to buck mode if left

floating. TherearetwoseparateerroramplifiersforV

HIGH

orV

regulation.Havingtwoerroramplifiersallowsfine

LOW

tuning of the loop compensation for the buck and boost

modes independently to optimize transient response.

When buck mode is selected, the corresponding error

amplifierisenabled,andITH

voltagecontrolsthepeak

LOW

inductor current. The other error amplifier is disabled

and ITH is parked at its zero current level. In boost

HIGH

mode, ITH

is enabled while ITH

is parked at its

HIGH

LOW

zero current level. During a buck to boost or a boost to

buck transition, the internal soft-start is reset. Resetting

soft-start and parking the ITH pin at the zero current level

ensures a smooth transition to the newly selected mode.

Refer to Table 2 for a summary.

Use the following equation to calculate the voltages on

IMON:

V

= V

+ K • I

• R

/m; Buck Mode

IMON

ZERO

OUT

SENSE

= V

– K • I

• R

/m; Boost Mode

To further minimize any transients, SETCUR can be

programmed to 1.25V or zero current level before

switching between boost and buck modes.

Where:

V

, the phase current voltage appears on IMON pin;

, the IMON voltage when average output current is

IMON

V

ZERO

Buck Mode Light Load Current Operation (DCM/CCM)

zero; V

= 1.25V typically

ZERO

Inbuckmode,theLTC3871canbeenabledtoenterdiscon-

tinuousconductionmodeorforcedcontinuousconduction

mode.Toselectforcedcontinuousoperation,tietheMODE

K = 38 if ILIM = 10mV; 20mV; or 30mV

K = 19 if ILIM = 40mV; or 50mV

Table 2: ITH PIN Parking Conditions

MODE

Buck

PARKED

COMMENTS

ITH

Parked

OV

HIGH

OV

HIGH

OV

LOW

OV

LOW

3V Threshold Overrides Park

HIGH

Boost

Buck

Parked in Prebias

Parked

ITH

and OV

3V Threshold Overrides Park

LOW

HIGH

Boost

3871f

16

For more information www.linear.com/LTC3871

LTC3871

OPERATION

pin to GND. To select discontinuous conduction mode of

operation, tie the MODE pin to V5 or float it.

it. To select discontinuous conduction mode of operation,

tie the MODE pin to V5.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The inductor current valley is determined by

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH

pin, just as in normal opera-

the voltage on the ITH

pin, just as in normal operation.

HIGH

LOW

tion. In this mode, the efficiency at light loads is lower.

However, continuous mode has the advantages of lower

output ripple.

In this mode, the efficiency at light loads is lower than in

DCM mode operation. However, continuous mode has the

advantages of lower output ripple and less interference

with audio circuitry.

WhentheMODEpinisconnectedtoV5,theLTC3871oper-

ates with the synchronous N-channel MOSFET disabled,

using the body diode of the MOSFET as the synchronous

diode to reduce switching losses, and prevent reverse

current. To reduce the MOSFET heat dissipation in this

mode, parallel Schottky diodes are recommended.

When the MODE pin is connected to V5 or left floating,

the LTC3871 operates in discontinuous conduction mode

at light loads. At very light loads, the current comparator,

I

, may remain tripped for several cycles and force the

CMP

external top MOSFET to stay off for the same number of

cycles (i.e., skipping-pulses). The inductor current is not

allowed to reverse (discontinuous operation). This mode,

likeforcedcontinuousoperation,exhibitslowoutputripple

as well as low audio noise and reduced RF interference.

It provides higher low current efficiency than forced con-

tinuous mode.

Thermal Shutdown

TheLTC3871hasatemperaturesensorintegratedontheIC,

to sense the die temperature near the gate driver circuits.

When the die temperature exceeds 175°C, all switching

actions stop, and the driver gate pins are held low, thus

turning off all external MOSFETs. At the same time, the

channels are disconnected from the IMON pins, and SS

Boost Mode Light Load Current Operation (DCM/CCM)

and ITH

/ITH

pins continue to function normally,

In boost mode, the LTC3871 can be enabled to enter

constant-frequency discontinuous conduction mode or

forced continuous conduction mode. To select forced-

continuous operation, tie the MODE pin to GND or float

HIGH

LOW

so as not to interfere with other LTC3871 chips that may

reference the common pins. When the temperature drops

10°C below the trip threshold, normal operation resumes.

3871f

17

For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

The Typical Application on the first page of this data sheet

is a basic LTC3871 application circuit. In general, external

component selection is driven by the load requirements,

amplifier are high impedance with input bias currents of

–

less than 1μA. The SNS pin is not a high impedance pin.

For V

voltages greater than V5, the current compara-

LOW

–

and begins with the DCR or R

and inductor value.

tors derive their bias currents directly off of SNS . The

SENSE

–

Next, power MOSFETs are selected. Finally, V

and

SNS pins should be connected directly to V

. Care

HIGH

LOW

V

capacitors are selected.

mustbetakennottofloatthesepinsduringnormalopera-

tion. Filter components, especially capacitors, must be

placed close to the LTC3871, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (Figure 1). Because the LTC3871

is designed to be used with a very low value sensing

element to sense inductor current, without proper care,

the parasitic resistance, capacitance and inductance will

degrade the current sense signal integrity, making the

programmed current limit unpredictable. As shown in

Figure 3, resistors R1 and R2 are placed close to the

output inductor and capacitors C1 and C2 are close to

the IC pins to prevent noise coupling to the sense signal.

LOW

Slope Compensation and Inductor Peak Current

Slope compensation provides stability in constant fre-

quency architectures by preventing sub-harmonic oscil-

lations at high duty cycles. It is accomplished internally

by adding a compensating ramp to the inductor current

signal at duty cycles in excess of 40%. For high duty cycle

applications, the maximum current is reduced. A curve

of maximum peak current vs. duty cycle is given in the

Typical Performance Characteristics section.

Current Limit Programming

The ILIM pin is a 5-level logic input which sets the maxi-

mum current limit of the controller. Table 3 shows the five

ILIM settings. Please note that these settings represent

the peak inductor current setting. Because of the inductor

ripple current, the average output current is lower than

the peak current. Setting ILIM using a resistor divider off

of V5 will allow the maximum current sense threshold

setting to not change when the 5.5V LDO is in dropout at

start-up. PleasenotethattheILIMpinhasaninternal200k

pull-down to SGND and a 200k pull-up to V5.

Inductor DCR Sensing

The LTC3871 is specifically designed for high load current

applications requiring the highest possible efficiency; it is

capable of sensing the signal of an inductor DCR in the

milliohm range (Figure 3). The DCR is the DC winding

resistance of the inductor’s copper, which is often 1mΩ

for high current inductors. In high current applications,

the conduction loss of a high DCR or a sense resistor

will cause a significant reduction in power efficiency. The

+

SNSD pin connects to the filter that has a R1 • C1 time

Table 3. ILIM Settings

+

constant matched to L/DCR of the inductor. The SNSA

Max Current Sense Threshold

pin is connected to the second filter with the time constant

one-fifth that of R1 • C1. For a specific output require-

ment, choose the inductor with the DCR that satisfies the

maximumdesiredsensevoltage,andusestherelationship

ILIM Pin Voltage

DCR Sensing

10mV

R

SENSE

0

12.5mV

25mV

1/4 V5

Float

3/4 V5

V5

20mV

30mV

37.5mV

50mV

40mV

LTC3871

R2

+

SNSA

50mV

62.5mV

C2

–

SNS

+

–

SNSD , SNSA and SNS Pins

C1

R1

+

SNSD

+

–

The SNSA and SNS pins are the inputs to the current

L1

+

SW

3871 F03

V

LOW

comparators, while the SNSD pin is the input of an in-

+

ternal DC amplifier. The operating input voltage range is

0V to 30V for all three sense pins. All the positive sense

pins that are connected to the current comparator or the

Figure 3. Inductor DCR Sensing

3871f

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LTC3871

APPLICATIONS INFORMATION

of the sense pin filters to output inductor characteristics

as depicted below.

+

–

across SNSA and SNS pins will be determined by the

following equation:

V

V_HIGH– V

LOW

V_SENSE(MAX)

LOW

∆V_SENSE

=

•

DCR =

V_HIGHR1• C1• f_OSC

∆I_L

I_MAX

+

2

Sensing Using an R Resistor

SENSE

L/DCR = R1 • C1 = 5 • R2 • C2

where:

The LTC3871 can be used with an external R

resis-

SENSE

tortosensecurrentaccurately. Theexternalcomponents

V

: Maximum sense voltage for a given ILIM

required to accomplish this are shown in Figure 4. The

SENSE(MAX)

threshold

+

SNSD pin senses directly across the R resistor. The

S

R1, C1 network provides the current signal path to the

∆I : Inductor ripple current

L

+

SNSA pin. Internally the signals from the AC and DC

L, DCR: Output inductor characteristics

paths are combined for accurate current sensing and low

jitter performance. Resistor R2 is used to divide down

+

R1 • C1: Filter time constant of the SNSD pin

+

the DC component of the signal seen by SNSA due to

+

R2 • C2: Filter time constant of the SNSA pin

the DCR of the inductor. As a rule of thumb, R2 needs

to be 10 times smaller than R1 so the DCR value can be

safely ignored.

To ensure that the load current will be delivered over the

full operating temperature range, the temperature coef-

ficient of DCR resistance, approximately 0.4%/°C, should

be taken into account.

The R1 • C1 time constant should be selected such that:

L/R = 4 • R1 • C1 for R1 = 10 • R2

S

Typically, C1 and C2 are selected in the range of 0.047μF

to 0.47μF. If C1 and C2 are chosen to be 0.47μF, and an

inductor of 10μH with 3mΩ DCR is selected, R1 and R2

will be 6.98kΩ and 1.4kΩ respectively. The bias current

Pre-Biased Output Start-Up

There may be situations that require the power supply to

start up with a pre-bias on the V

output capacitors.

+

LOW

at SNSD and SNSA is less than 1μA, and it introduces

a small error to the sense signal.

In this case, it is desirable to start up without discharging

that output pre-bias. The LTC3871 can safely power up

into a pre-biased output without discharging it.

There will be some power loss in R1 and R2 that relates to

the duty cycle, and will be the most in continuous mode

The LTC3871 accomplishes this by disabling both the

top and bottom MOSFETs until the SS pin voltage and

at the maximum V

voltage:

HIGH

V

_HIGH(MAX)– V

• V

the internal soft-start voltage are above the VFB

(

)

LOW

P

R =

_LOSS( )

voltage. When VFB

is higher than SS or the internal

R

LOW

LTC3871

Ensure that R1 and R2 have a power rating higher than

this value. Care has to be taken for voltage coefficients of

–

SNS

R2

these resistors at high V

voltages. Multiple resistors

HIGH

C1

canbeusedinseriestominimizethiseffect.However,DCR

sensingeliminatestheconductionlossofasenseresistor;

and provides better efficiency at heavy loads. To maintain

a good signal-to-noise ratio for the current sense signal,

use a minimum of 10mV between SNSA and SNS pins

or the equivalent of 2mV ripple on the current sense signal

for duty cycles less than 40%. The actual ripple voltage

+

SNSA

R1

L1

R

S

SW

V

LOW

+

SNSD

+

–

3871 F04

Figure 4. R_SENSEResistor Sensing

3871f

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For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

soft-start voltage, the error amp output is parked at its

zero current level. Disabling both top and bottom MOS-

FETs prevents the pre-biased output voltage from being

discharged.WhenSSandtheinternalsoft-startbothcross

voltage indicates excessive current, an external circuit

can be added to simulate an UV condition at the input

and turn off PGATE.

Inductor Value Calculation

1.32V or V , whichever is lower, both top and bottom

FB

MOSFETs are enabled.

Given the desired input and output voltages, the inductor

value and operating frequency, f , directly determine

OSC

Buck Mode Overcurrent Fault

the inductor’s peak-to-peak ripple current:

When the output of the power supply is loaded beyond

its preset current limit, the regulated output voltage will





V

V_HIGH

V

_HIGH– V

f_OSC•L



_LOW

LOW

I_RIPPLE

=













collapse depending on the load. The V

rail may be

LOW

shorted to ground through a very low impedance path or

it may be a resistive short, in which case the output will

collapse partially, until the load current equals the preset

currentlimit. Thecontrollerwillcontinuetosourcecurrent

into the short. The amount of current sourced depends

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, highest efficiency operation is obtained at

low frequency with a small ripple current. Achieving this,

however, requires a large inductor.

on the ILIM pin setting and the VFB

voltage as shown

LOW

in the Current Foldback graph in the Typical Performance

Characteristics section.

A reasonable starting point is to choose a ripple current

that is about 40% of the maximum inductor current. Note

that the largest ripple current occurs at the highest V

Upon removal of the short, V

soft starts using the

HIGH

LOW

voltage. To guarantee that ripple current does not exceed

a specified maximum, the inductor should be chosen

according to:

internal soft-start, thus reducing output overshoot. In

the absence of this feature, the output capacitors would

have been charged at current limit, and in applications

with minimal output capacitance this may have resulted

in output overshoot. Current limit foldback is not disabled

duringanovercurrentrecovery. Theloadmustdropbelow

the folded back current limit threshold in order to restart

from a hard short.

V_HIGH– V

f_OSC•I_RIPPLEV_HIGH

V

LOW

L ≥

•

Inductor Core Selection

Once the inductance value is determined, the type of in-

ductor must be selected. Core loss is independent of core

size for a fixed inductor value, but it is very dependent on

inductanceselected. Asinductanceincreases, corelosses

go down. Unfortunately, increased inductance requires

moreturnsofwireandthereforecopperlosseswillincrease.

Boost Mode Overcurrent Fault

When in boost mode, if the overcurrent situation persists

and discharges V

below the preset UV

trip point,

HIGH

ThePGATEpinturnsofftheexternaldisconnectP-channel

MOSFET,preventingV fromgettingdischargedviathe

LOW

top MOSFET body diode. For both buck and boost mode

of operation, current regulation loop can be used to limit

the current by forcing a voltage on SETCUR pin. The zero

average inductor current can be obtained by forcing 1.25V

on SETCUR. If the SETCUR voltage is set to an invalid

range for the selected mode of operation, the effective

SETCUR voltage is internally set to 1.25V.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

One way of protecting against an input V

in boost mode is to monitor the I

soft short

HIGH

voltage. If the I

MON

3871f

20

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LTC3871

APPLICATIONS INFORMATION

Power MOSFET and Schottky Diode (Optional)

Selection

the gate-to-source capacitance. The Miller charge (the

increase in coulombs on the horizontal axis from a to b

while the curve is flat) is specified for a given V drain

DS

At least two external power MOSFETs need to be selected:

OneN-channelMOSFETforthetopswitchandoneormore

N-channelMOSFET(s)forthebottomswitch.Thenumber,

type and on-resistance of all MOSFETs selected take into

account the voltage step-down ratio as well as the actual

position (main or synchronous) in which the MOSFET will

beused.Amuchsmallerandmuchlowerinputcapacitance

MOSFETshouldbeusedforthetopMOSFETinapplications

voltage, but can be adjusted for different V voltages by

DS

multiplying the ratio of the application V to the curve

DS

specified V values. A way to estimate the C

term

DS

MILLER

is to take the change in gate charge from points a and b

on a manufacturer’s data sheet and divide by the stated

V

voltage specified. C

is the most important se-

MILLER

DS

lection criteria for determining the transition loss term in

the top MOSFET but is not directly specified on MOSFET

that have an V

that is less than one-third of V

. In

LOW

HIGH

data sheets. C

and C are specified sometimes but

RSS

OS

applications where V

>> V

, the top MOSFETs’ on-

HIGH

LOW

definitionsoftheseparametersarenotincluded.Whenthe

controller is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

resistance is normally less important for overall efficiency

than its input capacitance at operating frequencies above

300kHz. MOSFET manufacturers have designed special

purposedevicesthatprovidereasonablylowon-resistance

with significantly reduced input capacitance for the main

switch application in switching regulators.

V

LOW

V_HIGH

MainSwitchDuty Cycle =





V

_HIGH– V



_LOW

Synchronous SwitchDuty Cycle =









The peak-to-peak MOSFET gate drive levels are set by the

V_HIGH





internal DRV regulator voltage. Pay close attention to

CC

theBV

specificationfortheMOSFETsaswell.Selection

DSS

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

criteria for the power MOSFETs include the on-resistance

, input capacitance, input voltage and maximum

R

DS(ON)

2

V

V_HIGH

LOW

outputcurrent.MOSFETinputcapacitanceisacombination

of several components but can be taken from the typical

gatechargecurveincludedonmostdatasheets(Figure5).

The curve is generated by forcing a constant input current

into the gate of a common source, current source loaded

stage and then plotting the gate voltage versus time.

P_MAIN

=

I

1+δ R

+

(

)

(

)

MAX

DS(ON)





I

² ^MAX

V

R

C

•

(

)

(

_DR)(

)





MILLER

HIGH





2











1



+

• f

The initial slope is the effect of the gate-to-source and

the gate-to-drain capacitance. The flat portion of the

curve is the result of the Miller multiplication effect of the

drain-to-gate capacitance as the drain drops the voltage

across the current source load. The upper sloping line is

due to the drain-to-gate accumulation capacitance and

 DRV_CC– V_TH(MIN)

V



^TH(MIN)

2

V_HIGH– V

LOW

P

=

I

(

1+δ R

DS(ON)

(

)

MAX

SYNC

V_HIGH

I

= Maximum Inductor Current.

MAX

where δ is the temperature dependency of R

, RDR

DS(ON)

V

IN

is the effective top driver resistance (approximately 5Ω at

=V );V isthedrainpotentialandthechange

MILLER EFFECT

V

GS

MILLER

HIGH

in drain potential in the particular application. V

a

b

TH(MIN)

+

–

is the data sheet specified typical gate threshold voltage

V

DS

+

Q

V

IN

= (Q – Q )/V

DS

GS

specified in the power MOSFET data sheet at the specified

–

C

MILLER

B

A

3871 F05

drain current. C

is the calculated capacitance using

MILLER

Figure 5. Gate Charge Characteristic

3871f

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LTC3871

APPLICATIONS INFORMATION

the gate charge curve from the MOSFET data sheet and

the technique described above.

offer much relief. Note that capacitor manufacturers’ ripple

current ratings are often based on only 2000 hours of life.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

This makes it advisable to further de-rate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet size

or height requirements in the design. Ceramic capacitors

equation includes an additional term for transition losses,

which peak at the highest input voltage. The bottom MOS-

FET losses are greatest at high V

switch duty factor is low or during a V

when the bottom switch is on close to 100% of the period.

voltage when the top

HIGH

short-circuit

can also be used for C . Always consult the manufacturer

LOW

IN

if there is any question.

The term (1 + δ) is generally given for a MOSFET in the

Ceramic capacitors are becoming very popular for small

designsbutseveralcautionsshouldbeobserved.X7R,X5R

and Y5V are examples of a few of the ceramic materials

used as the dielectric layer, and these different dielectrics

have very different effect on the capacitance value due to

thevoltageandtemperatureconditionsapplied.Physically,

if the capacitance value changes due to applied voltage

change, there is a concomitant piezo effect which results

in radiating sound! A load that draws varying current at an

audible rate may cause an attendant varying input voltage

on a ceramic capacitor, resulting in an audible signal. A

secondary issue relates to the energy flowing back into a

ceramiccapacitorwhosecapacitancevalueisbeingreduced

by the increasing charge. The voltage can increase at a

considerably higher rate than the constant current being

supplied because the capacitance value is decreasing as

thevoltageisincreasing!Nevertheless,ceramiccapacitors,

when properly selected and used, can provide the lowest

overall loss due to their extremely low ESR.

form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

An optional Schottky diode across the bottom MOSFET

conducts during the dead time between the conduction

of the two large power MOSFETs in buck mode. This pre-

vents the body diode of the bottom MOSFET from turning

on, storing charge during the dead time and requiring a

reverse-recoveryperiodwhichcouldcostasmuchassev-

eral percent in efficiency. A 2A to 8A Schottky is generally

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition loss due to their larger junction

capacitance.

An optional Schottky diode across the top MOSFET is

also recommended for Boost DCM operation. This will

increase efficiency and reduce heat dissipation for large

output currents.

A small (0.1μF to 1μF) bypass capacitor, C , between the

IN

chip V pin and ground, placed close to the LTC3871, is

IN

C

HIGH

and MOSFETs Selection (on V

and V

)

HIGH

LOW

also suggested. A 2.2Ω to 10Ω resistor placed between

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

C and V pin provides further isolation.

IN

LOW

HIGH

The selection of C

at V

is driven by the required

OUT

large voltage transients, a low ESR capacitor sized for

effective series resistance (ESR). Typically once the ESR

the maximum RMS current of one channel must be used.

requirement is satisfied the capacitance is adequate for

In the following discussion, it is assumed that C is

IN

. The

filtering. The steady-state output ripple (∆V ) is deter-

OUT

C

, C

is C

, V is V

, and V

is V

HIGH OUT

LOW IN

HIGH

OUT

LOW

mined by:

maximum RMS capacitor current is given by:



_RIPPLE







1

 ^1/2

I_MAX



∆V_OUT≈ ∆I

ESR+

C_INRequired I_RMS

≈

V

V – V

IN

OUT

(

_OUT)(

)









V

8fC

_OUT

IN

This formula has a maximum at V = 2V , where

RMS OUT

used for design because even significant deviations do not

where f = operating frequency, C

= output capacitance

OUT

IN

OUT

I

= I /2.Thissimpleworst-caseconditioniscommonly

and ∆I

= ripple current in the inductor. The output

RIPPLE

ripple is highest at maximum input voltage since ∆I

RIPPLE

3871f

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For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

increases with input voltage (V

). The output ripple

C

Capacitor Selection for Boost Operation

HIGH

will be less than 50mV at maximum V with ∆I

=

IN

RIPPLE

Contributions of ESR (equivalent series resistance), ESL

(equivalent series inductance) and the bulk capacitance

must be considered when choosing the correct combina-

tionofoutputcapacitorsforaboostconverterapplication.

0.4I

assuming:

OUT(MAX)

C

required ESR < N • R

OUT

SENSE

and

The choice of component(s) begins with the maximum

acceptable ripple voltage (expressed as a percentage of

the output voltage), and how this ripple should be divided

between the ESR step and the charging/discharging ∆V.

For the purpose of simplicity we will choose 2% for the

maximum output ripple, to be divided equally between the

ESR step and the charging/discharging ∆V. This percent-

age ripple will change, depending on the requirements

of the application, and the equations provided below can

easily be modified.

1

C_OUT

>

8f R

( )

(

)

SENSE

TheemergenceofverylowESRcapacitorsinsmall,surface

mount packages makes very small physical implementa-

tions possible. The ability to externally compensate the

switching regulator loop using the ITH pin allows a much

wider selection of output capacitor types. The impedance

characteristic of each capacitor type is significantly differ-

ent than an ideal capacitor and therefore requires accurate

modelingorbenchevaluationduringdesign.Manufacturers

suchasNichicon,NipponChemi-ConandSanyoshouldbe

consideredforhighperformancethrough-holecapacitors.

TheOS-CONsemiconductordielectriccapacitorsavailable

from Sanyo and the Panasonic SP surface mount types

have a good (ESR)(size) product.

One of the key benefits of multiphase operation is a reduc-

tion in the peak current supplied to the output capacitor

by the boost diodes. As a result, the ESR requirement

of the capacitor is relaxed. For a 1% contribution to the

total ripple voltage, the ESR of the output capacitor can

be determined using the following equation:

OncetheESRrequirementforC

hasbeenmet,theRMS

0.01• V_OUT

I_D(PEAK)

OUT

ESR_COUT

where:

≤

currentratinggenerallyfarexceedstheI

require-

RIPPLE(P-P)

ment. Ceramic capacitors from AVX, Taiyo Yuden, Murata

and TDK offer high capacitance value and very low ESR,

especially applicable for low output voltage applications.

I_O(MAX)







1

n

χ

2

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

electrolytic and dry tantalum capacitors are both available

in surface mount configurations. New special polymer

surface mount capacitors offer very low ESR also but

have much lower capacitive density per unit volume. In

the case of tantalum, it is critical that the capacitors are

surge tested for use in switching power supplies. Several

excellent choices are the AVX TPS, AVX TPSV, the KEMET

T510 series of surface mount tantalums or the Panasonic

SP series of surface mount special polymer capacitors

availableincaseheightsrangingfrom2mmto4mm.Other

capacitor types include Sanyo POSCAP, Sanyo OS-CON,

Nichicon PL series and Sprague 595D series. Consult the

manufacturers for other specific recommendations.

I_D(PEAK)= • 1+

•







1–D_MAX

The factor n represents the number of phases and the

factorχrepresentsthepercentageinductorripplecurrent.

For the bulk capacitance, which we assume contributes

1% to the total output ripple, the minimum required ca-

pacitance is approximately:

I_O(MAX)

C_OUT

≥

0.01•n • V_OUT• f

For many designs it will be necessary to use one type of

capacitor to obtain the required ESR, and another type

to satisfy the bulk capacitance. For example, using a

low ESR ceramic capacitor can minimize the ESR step,

3871f

23

For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

while an electrolytic capacitor can be used to supply the

required bulk C.

V

HIGH

LOW

C

FF2

R

C

FF1

D

C

B

A

LTC3871

VFB

The voltage rating of the output capacitor must be greater

than the maximum output voltage, with sufficient derating

to account for the maximum capacitor temperature.

VFB

LOW

HIGH

R

3871 F06

Becausetheripplecurrentintheoutputcapacitorisasquare

wave, the ripple current requirements for this capacitor

depend on the duty cycle, the number of phases and the

maximum output current. In order to choose a ripple

current rating for the output capacitor, first establish the

duty cycle range, based on the output voltage and range

of input voltage.

Figure 6. Setting Output Voltage

External Soft-Start

The LTC3871 has the ability to soft-start by itself using

the internal soft-start or at a slower rate with an external

capacitor on the SS pin. The controller is in the shutdown

state if its RUN pin voltage is below 1.14V and its SS pin

is actively pulled to ground in this shutdown state. If the

RUN pin voltage is above 1.22V, the controller powers up.

Once V5 passes its UVLO threshold and power on reset

delay expires, a soft-start current of 1.25μA then starts to

charge the SS soft-start capacitor. Note that soft-start is

The output ripple current is divided between the various

capacitors connected in parallel at the output voltage.

Although ceramic capacitors are generally known for low

ESR(especiallyX5RandX7R),thesecapacitorssufferfrom

a relatively high voltage coefficient. Therefore, it is not safe

toassumethattheentireripplecurrentflowsintheceramic

capacitor. Aluminum electrolytic capacitors are generally

chosen because of their high bulk capacitance, but they

have a relatively high ESR. As a result, some amount of

ripple current will flow in this capacitor. If the ripple cur-

rent flowing into a capacitor exceeds its RMS rating, the

capacitor will heat up, reducing its effective capacitance

and adversely affecting its reliability. After the output

capacitor configuration has been determined using the

equations provided, measure the individual capacitor case

temperatures in order to verify good thermal performance.

achieved not by limiting the maximum V

output cur-

LOW

rent of the controller but by controlling the output ramp

voltage according to the ramp rate on the SS pin. Current

foldback is enabled during this phase. The soft-startrange

is defined to be the voltage range from 0V to 1.2V on the

SS pin. The total soft-start time can be calculated as:

C_SS

t_SOFTSTART= 1.2 •

1.25µA

The Internal LDOs

The LTC3871 features three internal PMOS LDOs that

Setting Output Voltage

supplies power to DRV from either the V

or V

CC

HIGH

LOW

TheLTC3871outputvoltageissetbytwoexternalfeedback

resistive dividers carefully placed across V

supply, and also generates the V5 rail from DRV . DRV

CC

to ground

HIGH

powers the top and bottom gate drive circuits, and V5

and V

to ground, as shown in Figure 6. The regulated

LOW

powers the LTC3871’s internal circuitry.

output voltage is determined by:

There are two DRV LDOs—one that generates DRV

CC

from V

(LDO1) and another that generates DRV

HIGH











R_B

R_A

R

_D



(LDO2), thus allowing the part to start up with





LOW

V

= 1.2V • 1+

and V_HIGH= 1.2V • 1+



LOW













R_C

just one of the two rails present! Only one of them is ac-









tive at any given time. If V

is higher than the EXTV

LOW

CC

Toimprovethefrequencyresponse,afeedforwardcapaci-

switchover threshold, LDO2 is active; if it is below the

tor, C /C , may be used. Great care should be taken

switchoverthreshold,LDO1isactive.TheDRV pinregula-

FF1 FF2

CC

to route the feedback line away from noise sources, such

tion voltage is determined by the state of the DRVSET pin.

The DRVSET pin is a 5-level logic. When DRVSET is either

3871f

as the inductor or the SW line.

24

For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

After a short, or while starting up, make sure that the load

current takes the folded-back current limit into account.

grounded, floated or tied to V5, the typical value for the

DRV voltage will be 6V, 8V and 10V respectively. Use

CC

the 10V setting with careful PCB layout. This is because

Phase-Locked Loop and Frequency Synchronization

any overshoot between BOOST and SW would exceed the

ABS max voltage of 11V for the floating driver. Set DRV

CC

The LTC3871 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phasedetector. Thisallowstheturn-onofthetopMOSFET

to be locked to the rising edge of an external clock signal

applied to the SYNC pin. The phase detector is an edge

sensitivedigitaltypethatprovideszerodegreesphaseshift

between the external and internal oscillators. This type of

phase detector does not exhibit false lock to harmonics

of the external clock.

to one-fourth of V5 and three-fourths of V5 for 7V and 9V

DRV voltages. Setting DRVSET using a resistor divider

CC

offofV5willallowtheDRVSETsettingtonotchangewhen

the 5.5V LDO is in dropout at start-up. Please note that

the DRVSET pin has an internal 200k pull-down to SGND

and a 200k pull-up to V5. The EXTV turn on threshold is

CC

the selected DRV regulation voltage minus 500mV. The

CC

turn off threshold is 500mV below the turn on threshold.

The V5 LDO regulates the voltage at the V5 pin to 5.5V

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal filter

network. There is a precision 20μA current flowing out of

the FREQ pin. This allows the user to use a single resistor

to SGND to set the switching frequency when no external

clockisappliedtotheSYNCpin.Theinternalswitchbetween

the FREQ pin and the integrated PLL filter network is on,

allowing the filter network to be pre-charged at the same

voltage as of the FREQ pin. The relationship between the

voltageontheFREQpinandoperatingfrequencyisshown

in Figure 7 and specified in the Electrical Characteristics

table. If an external clock is detected on the SYNC pin, the

internal switch mentioned above turns off and isolates the

influence of the FREQ pin. Note that the LTC3871 can only

be synchronized to an external clock whose frequency is

within range of the LTC3871’s internal VCO. A simplified

block diagram is shown in Figure 8.

when DRV is at least 6V. The LDO can supply a peak

CC

current of 20mA and must be bypassed to ground with a

minimum of 4.7μF ceramic capacitor or low ESR electro-

lytic capacitor. No matter what type of bulk capacitor is

used,anadditional0.1μFceramiccapacitorplaceddirectly

adjacenttotheV5andSGNDpinsishighlyrecommended.

Fault Conditions: Current Limit and Current Foldback

In buck mode, the LTC3871 includes current foldback to

help limit power dissipation when the V

is shorted to

LOW

ground. If the V

falls below 85% of its nominal output

LOW

level, then the maximum sense voltage is progressively

loweredfromitsmaximumprogrammedvaluetoone-third

ofthemaximumvalue.Foldbackcurrentlimitingisenabled

during soft-start. Under short-circuit conditions with very

low duty cycles, the LTC3871 will begin cycle skipping in

order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short circuit ripple

600

500

400

300

200

100

0

current is determined by the minimum on-time t

ON(MIN)

voltage and inductor value:

of the LTC3871, the V

HIGH

V_HIGH

L

∆I_L(SC)= t_ON(MIN)

•

The resulting short-circuit current is:









_L(SC)



1/ 3V

^SENSE(MAX)− ∆I

R_SENSE

1

2

0

0.5

1

1.5

(V)

2

2.5

I_SC

=

V

FREQ

3871 F07

Figure 7. Relationship Between Oscillator Frequency

and Voltage at the FREQ Pin

3871f

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For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

2.4V 5.5V

to balance better communication between the ICs versus

increasingtheprobabilityofpreventingasinglepointfailure.

R

SET

20µA

FREQ

TheLTC3871featuresCLKOUTandPHSMDpinsthatallow

multipleICstobedaisychainedtogether. Theclockoutput

signal on the CLKOUT pin can be used to synchronize

additional ICs in a 3-, 4-, 6-, 8-, 10- or 12-phase power

supply solution feeding a single high current output, or

even several outputs from the same input supply. The

PHSMD pin is used to adjust the phase relationship

between channel 1 and channel 2, as well as the phase

relationship between channel 1 and CLKOUT. The phases

arecalculatedrelativetozerodegrees,definedastherising

edge of TG1. Refer to the Operation section and Figure 2

for more details on PHSMD settings and connections for

multiphase applications.

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

EXTERNAL

OSCILLATOR

VCO

3871 F08

Figure 8. Phase-Locked Loop Block Diagram

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

The SS pins should be tied together to enable every

LTC3871 IC to startup together. Not connecting them

together may result in some phases sourcing a lot of

current and others sinking current.

less than f , current is sunk continuously, pulling down

OSC

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

TheIMONpinsmayormaynotbetiedtogether,depending

on whether the customer wants to monitor the average

currentperICorthetotalaveragecurrentintheapplication.

The ILIM, SETCUR, FREQ, MODE, BUCK and DRVSET

pins may or may not be tied together based on conve-

nience. When tying these pins together, please be aware

of the pull-up/down currents/resistors on these pins! Any

external resistor or resistor divider network must take

those into account. For example, each FREQ pin sources

20μA. When four LTC3871 ICs have their FREQ pins tied

together, that is 80μA.

Typically, the external clock (on the SYNC pin) input high

threshold is 2V, while the input low threshold is 1.2V.

The LTC3871 switching frequency is determined by:

Frequency =

2

[335.8k • V

] – [32.7k • V

] – 106.5k

(FREQ)

Where, V

= I

(from spec table) • R

The OV

, OV

and UV

pins must be tied

HIGH

(FREQ)

FREQ (FREQ)

LOW

HIGH

together. This enables the entire system to react to an

OV/UVconditionappropriately. Theresistordividerused

on these pins must be scaled based on the number of

LTC3871s paralleled, as these pins have 5μA hysteresis

currents that turn on and off.

Or,

Frequency =

[6.72 • R

2

] – [1.3E-5 • R

] – 106.5k

(FREQ)

This assumes a perfect 20μA I

.

FREQ

TheITH

andITH

pinsofmultipleLTC3871sshould

HIGH

LOW

Shared Pin Connections in Multi-Chip Applications

be tied together. Tying the ITH

pins together and the

LOW

ITH

pins together gives the best current sharing be-

When multiple LTC3871 ICs are used together in high

current applications, a number of pins may or may not be

connected together at the customer’s discretion, trying

HIGH

tweenphases.Eacherroramplifier’scompensationnetwork

has to be placed local to the specific IC to minimize jitter

and stability issues.

3871f

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For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

The RUN pins must be tied together – this is very critical

for boost mode operation. In boost mode, when multiple

LTC3871 have their RUN pins connected together, care

must be taken to ensure that the logic signal on the RUN

pin is a clean fast rising/falling signal so all ICs are enabled

at the same instant. If a resistor divider is used on the

RUN pin, then the part must be started up in buck mode.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Using a resistor divider on the RUN pin off V

, set for

set point allows

fault is cleared.

HIGH

a start-up voltage higher than the UV

HIGH

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the part to soft start cleanly after a UV

HIGH

the losses in LTC3871 circuits: 1) IC V

MOSFET driver current, 3) I R losses, 4) topside MOSFET

transition losses.

current, 2)

HIGH

Minimum On-Time Considerations

2

Minimum on-time, t

, is the smallest time duration

ON(MIN)

thattheLTC3871iscapableofturningonthetopMOSFET.

It is determined by internal timing delays, power stage

timing delays and the gate charge required to turn on the

top MOSFET. Low duty cycle applications may approach

this minimum on-time limit and care should be taken to

ensure that:

1. The V

current is the DC supply current given in the

HIGH

Electrical Characteristics table. V

results in a small (<0.1%) loss.

current typically

HIGH

2. The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time a

MOSFET gate is switched from low to high to low again,

V

V_HIGH

LOW

a packet of charge d moves from the driver supply to

ground. The resulting d /d is a current out of the driver

t_ON(MIN)

<

Q

f

( )

Q

t

supply that is typically much larger than the control cir-

cuitcurrent. Incontinuousmode, I = f(Q + Q ),

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage and current will continue to

be regulated, but the voltage ripple and current ripple

will increase. The minimum on-time for the LTC3871 is

approximately 150ns, with good PCB layout, minimum

30% inductor current ripple and at least 2mV ripple on the

GATECHG

T

B

where Q and Q are the gate charges of the topside

T

B

and bottom side MOSFETs.

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor and current sense re-

sistor. In continuous mode, the average output current

+

flows through L and R , but is chopped between

SENSE

current sense signal or equivalent 10mV between SNSA

–

the topside MOSFET and the synchronous MOSFET.

If the two MOSFETs have approximately the same

and SNS pins.

The minimum on-time can be affected by PCB switching

noise in the voltage and current loop. As the peak sense

voltage decreases, the minimum on-time gradually in-

creases. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a significant amount of cycle skipping can occur

with correspondingly larger current and voltage ripple.

R

, then theresistance of oneMOSFETcansimply

DS(ON)

be summed with the resistances of L and R

to

SENSE

=10mΩ,

= 5mΩ, then the total resistance

2

obtainI Rlosses.Forexample,ifeachR

R = 10mΩ, R

DS(ON)

L

SENSE

is 25mΩ. This results in losses ranging from 0.6% to

3% as the output current increases from 3A to 15A for

a 12V output.

Efficiency varies as the inverse square of V

for the

LOW

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

3871f

27

For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

in the Typical Application circuit will provide an adequate

starting point for most applications. The ITH series RC-CC

filter sets the dominant pole-zero loop compensation. The

values can be modified slightly (from 0.5 to 2 times their

suggested values) to optimize transient response once

the final PC layout is done and the particular output ca-

pacitor type and value have been determined. The output

capacitors need to be selected because the various types

and values determine the loop gain and phase. An output

current pulse of 20% to 80% of full-load current having a

rise time of 1μs to 10μs will produce output voltage and

ITH pin waveforms that will give a sense of the overall

loop stability without breaking the feedback loop. Placing

a power MOSFET directly across the output capacitor and

driving the gate with an appropriate signal generator is a

practicalwaytoproducearealisticloadstepcondition.The

initial output voltage step resulting from the step change

in output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

phase margin. This is why it is better to look at the ITH pin

signal which is in the feedback loop and is the filtered and

compensated control loop response. The gain of the loop

willbeincreasedbyincreasingRCandthebandwidthofthe

loop will be increased by decreasing CC. If RC is increased

bythesamefactorthatCCisdecreased, thezerofrequency

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance. A second, more

severe transient is caused by switching in loads with large

(>1μF) supply bypass capacitors. The discharged bypass

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

2

Transition Loss = (1.7) V

O(MAX)

• I

LOW

• C

• f

HIGH

O(MAX)

RSS

I

= Maximum Load on V

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C

has

HIGH

adequate charge storage and very low ESR at the switch-

ingfrequency.OtherlossesincludingSchottkyconduction

lossesduringdeadtimeandinductorcorelossesgenerally

account for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

shifts by an

LOW

amount equal to ∆I

• ESR, where ESR is the effective

LOAD

series resistance of C

at V . ∆I

LOW

also begins to

generating the feedback error

OUT

LOAD

charge or discharge C

OUT

signalthatforcestheregulatortoadapttothecurrentchange

andreturnV toitssteady-statevalue.Duringthisrecov-

LOW

ery time V

can be monitored for excessive overshoot

LOW

or ringing, which would indicate a stability problem. The

availability of the ITH pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. Thebandwidthcanalsobeestimatedbyexaminingthe

rise time at the pin. The ITH external components shown

capacitors are effectively put in parallel with C

, causing

LOW

a rapid drop in V

. No regulator can alter its delivery of

LOW

current quickly enough to prevent this sudden step change

in output voltage if the load switch resistance is low and

it is driven quickly. If the ratio of C

to C

is greater

LOAD

OUT

than 1:50, the switch rise time should be controlled so that

the load rise time is limited to approximately 25 • C

.

LOAD

Thus a 10μF capacitor would require a 250μs rise time,

limiting the charging current to about 200mA.

3871f

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LTC3871

APPLICATIONS INFORMATION

PC Board Layout Checklist

6. Keep the switching nodes away from sensitive small-

+

–

signal nodes (SNSD , SNSA , SNS , V ). Ideally the

FB

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

IC.Theseitemsarealsoillustratedgraphicallyinthelayout

diagram of Figure 9. Check the following in the PC layout:

switchnodesprintedcircuittracesshouldberoutedaway

and separated from the IC and especially the quiet side

of the IC. Separate the high d /d traces from sensitive

v

t

small-signalnodeswithgroundtracesorgroundplanes.

1. The DRV bypass capacitor should be placed imme-

CC

7. Use a low impedance source such as a logic gate to

drive the SYNC pin and keep the PCB trace as short as

possible.

diately adjacent to the IC between the DRV pin and

CC

the GND plane. A 1μF ceramic capacitor of the X7R or

X5R type is small enough to fit very close to the IC. An

additional 4.7μF to 10μF of ceramic, tantalum or other

very low ESR capacitance is recommended in order to

keep the internal IC supply quiet.

8. The 47pF to 330pF ceramic capacitor between the ITH

pins and signal ground should be placed as close as

possible to the IC. Figure 9 illustrates all branch currents

in a switching regulator. It becomes very clear after

studying the current waveforms why it is critical to keep

the high switching current paths to a small physical size.

High electric and magnetic fields will radiate from these

loops just as radio stations transmit signals. The output

capacitor ground should return to the negative terminal

of the input capacitor and not share a common ground

path with any switched current paths. The left half of the

circuit gives rise to the noise generated by a switching

regulator. The ground terminations of the synchronous

MOSFETandSchottkydiodeshouldreturntothebottom

plate(s) of the input capacitor(s) with a short isolated

PC trace since very high switched currents are present.

External OPTI-LOOP^®compensation allows overcom-

pensation for PC layouts which are not optimized, but

this is not the recommended design procedure.

2. The V5 bypass capacitor should be placed immediately

adjacent to the IC between the V5 and the SGND pins.

A 4.7μF to 10μF capacitor of ceramic, tantalum or other

very low ESR capacitance is recommended.

3. Placethefeedbackdividerbetweenthe+and–terminals

of C

/C

. Route VFB

/VFB

with minimum

LOW HIGH

LOW

HIGH

PC trace spacing from the IC to the feedback dividers.

+

–

4. Are the SNSA , SNSD and SNS printed circuit traces

routed together with minimum PC trace spacing? The

+,

+

–

filter capacitors between SNSA SNSD and SNS

should be as close as possible to the pins of the IC.

5. Dothe(+)platesofC

decouplingcapconnecttothe

HIGH

drainofthetopsideMOSFETascloselyaspossible?This

capacitor provides the pulsed current to the MOSFET.

L1

V

LOW

V

HIGH

SW2

R

SENSE

R

HIGH

+

R

L

D1

C

LOW

C

HIGH

SW1

3871 F09

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

Figure 9. Branch Current Waveforms (Buck Mode Shown)

3871f

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LTC3871

APPLICATIONS INFORMATION

Special Layout Consideration

LTC3871

–

SNS

R3

499Ω

1. ExceedingABSMaxratingsonthesensepinscanresult

–

in damage to the controller. As the SNS1 /SNS2 pins

C2

0.33μF

are connected directly to V , it is recommended that

LOW

+

SNSA

a fast acting diode with an appropriately high voltage

rating be used to clamp these pins to reduce voltage

spiking below ground. The diodes should be placed

close to the controller IC, with the cathode connected

R2

7.15k

L1

10μH

RS

1mΩ

SW

V

LOW

+

SNSD

3871 F11

–

toSNS1 orSNS2 andtheanodeconnectedtoground.

Figure 11. Design Example

2. The TG traces from the controller IC to the gate of the

external MOSFET should be kept as short as possible

to minimize the parasitic inductance. This inductance

can cause voltage spikes that can potentially exceed

the ABS Max rating of the drivers and damage them.

A 3Ω resistor and 1nF capacitor can be used to filter

these spikes as shown in Figure 10. When using the

are based on a 35% maximum ripple current assumption

(7A for each phase). The highest value of ripple current

occurs at the maximum V

voltage:

HIGH





V_LOW

f•∆I_L(MAX)

V_LOW





L=

• 1–





V

^HIGH(MAX)

9V/10V DRV settings, or if the TG traces are longer

SET

than 25mm, this filter network must be used on both

TG1 and TG2. The 1nF capacitor should be placed as

close to the TG/SW pins as possible.

Eachphasewillrequire11.4µH.TheCoilcraftSER2918H-103,

10µH, 2.6mΩ inductor is chosen. At the nominal V

voltage (48V), the ripple current will be:

HIGH











V

HIGH

V_LOW

f•L

V_LOW

LTC3871

TG

∆I_L(NOM)

=

•

1–

3Ω

1nF

V

^HIGH(NOM)

SW

V

LOW

Each phase will have 7.5A (37.5%) ripple. The peak induc-

tor current will be the maximum DC value plus one-half

the ripple current, or 23.8A. The minimum on-time at the

BG

3871 F10

Figure 10. Filter for TG Traces > 25mm

maximum V

, and should not be less than 150ns:

HIGH

V_LOW

12V

Design Example

As a design example for a two-phase single output

high current regulator, assume V = 48V (nominal),

T_ON(MIN)

=

= 1.7µs

V_HIGH(MAX)•f 60V •120kHz

HIGH

= 12V, V

With ILIM floating, the equivalent R

resistor value

V

= 60V (maximum), V

I

=

SENSE

HIGH

LOW

LOW MAX

can be calculated by using the minimum value for the

40A (20A/phase), and f = 120kHz (see Figure 11). The

maximum current sense threshold (33.2mV).

regulated output voltages are determined by: V

1.2V • (1 + RB/RA).

=

LOW

V_SENSE(MIN)

R_SENSE(EQUIV)

=

Using 10k 1% resistors from VFB

node to ground, the

LOW

∆I_L(NOM)

I_LOAD(MAX)

+

top feedback resistors are (to the nearest 1% standard

value) 90.9k and 10k. The frequency is set by biasing the

FREQ pin to 0.7V (see Figure 7). The inductance values

2

3871f

30

For more information www.linear.com/LTC3871

LTC3871

APPLICATIONS INFORMATION

The equivalent required R

value is 1.4mΩ. Choose

The power to charge the MOSFET’s output capacitance is

imposed on the topside MOSFET as well:

SENSE

R = 1mΩ to allow some design margin. Set R3 to be

S

below 1/10th of the R2. Therefore, the DC component of

120kHz

PC_OSS= 660pF • (48V)²•

= 91mW

+

the SNSA filter is small enough to be omitted. R2 • C2

2

should have a bandwidth that is four times as high as

the L/R .

C

at V

is chosen for an equivalent RMS current

HIGH

S

IN

rating of at least 20A. C

at V

is chosen with an

OUT

LOW

Typically, C2 is selected in the range of 0.047µF to 0.47µF.

If C2 is chosen to be 0.33μF, R2 and R3 will be 7.15k and

equivalent ESR of 10mΩ for low output ripple. The V

LOW

output ripple in continuous mode will be highest at the

maximum V voltage. The V output voltage ripple

+

499Ω respectively. The bias current at SNSD and SNSA

HIGH

LOW

is about 10nA and 100nA respectively, and it causes some

small error to the current sense signal.

due to ESR is approximately:

= R = 0.01Ω • 7.5A = 75mV

P-P

V

LOWRIPPLE

ESR(∆IL)

ThepowerdissipationonthetopsideMOSFETcanbeeasily

Further reductions in V

output voltage ripple can be

estimated. Set the gate drive voltage (DRV ) to be 9V.

LOW

CC

made by placing a 100µF ceramic capacitor across C

.

Choosing an Infineon BSC097N06NS MOSFET results in:

LOW

If the output load is a battery, the voltage loop is first

set for the desired output voltage and then the charge

current can be regulated using the current regulation

loop – via the SETCUR and IMON pins. Selecting a

maximum charge current of 20A, the desired SETCUR

pin voltage is calculated using:

R

= 9.7mΩ (max), V

= 5.2V, C

J

≅ 32pF.

MILLER

DS(ON)

MILLER

At maximum input voltage with T (estimated) = 75°C:

P_MAIN

=













12V

48V

2

•(20A) •(1 + 0.005(75°C–25°C))•0.0097Ω









(48V)²•23.8A

2

1

















+

•2Ω • 32pF •

+

•120kHz

1.25V + [38 • 20A • 1mΩ]

9V –5.2V 5.2V

V_SETCUR

=

= 1.63V

2

= 1.21W + 96mW

= 1306mW

The SETCUR pin can be driven by an ADC’s output to

1.63V for the best accuracy. If one is not available, the

7.5μA current sourced out of the SETCUR pin can be used

to set the voltage with a resistor from SETCUR to ground,

calculated using:

An Infineon BSC028N06NS, R

= 2.8mΩ,

DS(ON)

C

= 660pF is chosen for the bottom FET. The resulting

OSS

power loss is:

PSYNC =

1.63V

7.5µA

48V –12V

48V

P_SYNC= 1.05W

•20A²• (1+ ((0.005) • (75°C– 25°C )))•0.0028Ω

R_SETCUR

=

= 217kΩ

A 1% or more accurate 217kΩ resistor should be used.

3871f

31

For more information www.linear.com/LTC3871

LTC3871

TYPICAL APPLICATIONS

V

HIGH

48V NOMINAL,

15A

5Ω

215k 603k

1μF

0Ω

OV

UV

HIGH

EXTV

OV

CC

HIGH

90.9k

HIGH

UV

HIGH

VFB

LOW

10k

ILIM

–

ITH

HIGH

SNS1

ITH

HIGH

+

SNSD1

0.33μF

+

PHSMD

SNSA1

0Ω

499Ω

ITH

LOW

DRV

BST1

CC1

ITH

LOW

0.1μF

0.22μF

7.15k

10μH

SS

TG1

SW1

SS

1mΩ

V

LOW

12V 60A

SETCUR

BUCK

RUN

SETCUR

BUCK

RUN

LTC3871

BG1

392k

CLKOUT

CLK1

10k

VFB

IMON

HIGH

IMON

–

SNS2

FREQ

+

10pF

SNSD2

V

LOW

0.33μF

45.2k

+

SNSA2

0Ω

102k

499Ω

DRV

BST2

CC1

OV

LOW

OV

0.22μF

LOW

7.15k

TG2

DRV

CC1

10μH

1mΩ

DRV

CC

10k

SW2

V5

BG2

4.7μF

V

HIGH

5Ω

603k

215k

1μF

0Ω

OV

UV

HIGH

EXTV

CC

OV

HIGH

90.9k

HIGH

UV

HIGH

VFB

LOW

10k

ILIM

10k

ITH

HIGH

–

ITH

SNS1

HIGH

+

SNSD1

PHSMD

0.33μF

+

SNSA1

0Ω

499Ω

ITH

LOW

DRV

BST1

CC2

ITH

LOW

0.1μF

0.22μF

7.15k

SS

TG1

SW1

BG1

SS

10μH

1mΩ

SETCUR

BUCK

RUN

SETCUR

BUCK

RUN

LTC3871

392k

SYNC

CLK1

10k

VFB

IMON

10pF

HIGH

–

IMON

SNS2

FREQ

+

SNSD2

V

LOW

0.33μF

45.2k

+

SNSA2

0Ω

102k

499Ω

DRV

BST2

CC2

OV

LOW

OV

LOW

0.22μF

7.15k

TG2

DRV

CC2

10μH

1mΩ

DRV

CC

10k

SW2

V5

BG2

3871 TA03

4.7μF

NOT ALL PINS SHOWN.

Figure 12. High Efficiency 12V, 60A 4-Phase Supply

3871f

32

For more information www.linear.com/LTC3871

LTC3871

PACKAGE DESCRIPTION

Please refer http://www.linear.com/product/LTC3871#packaging for the most recent package drawings.

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)

(Reference LTC DWG #05-08-1832 Rev C)

7.15 – 7.25

5.50 REF

48

37

36

1

0.50 BSC

C0.30

5.50 REF

7.15 – 7.25

0.20 – 0.30

3.60 0.05

e 3

12

13

25

PACKAGE OUTLINE

24

COMPONENT

PIN “A1”

1.30 MIN

TRAY PIN 1

BEVEL

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PACKAGE IN TRAY LOADING ORIENTATION

9.00 BSC

7.00 BSC

3.60 0.10

48

37

48

SEE NOTE: 3

1

36

1

C0.30

9.00 BSC

7.00 BSC

3.60 0.10

A

25

12

25

C0.30 – 0.50

24

13

24

BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)

1.60

11° – 13°

1.35 – 1.45 MAX

R0.08 – 0.20

GAUGE PLANE

0.25

0° – 7°

LXE48 LQFP 0113 REV

C

11° – 13°

1.00 REF

0.50

BSC

0.09 – 0.20

0.17 – 0.27

SIDE VIEW

0.05 – 0.15

0.45 – 0.75

SECTION A – A

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

4. DRAWING IS NOT TO SCALE

2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

3871f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3871

LTC3871

TYPICAL APPLICATION

High Efficiency PolyPhase Bidirectional Charger/Supply

V

HIGH

26V TO 58V

7.5A AT 48V

5Ω

215k 603k

1μF

0Ω

OV

EXTV

HIGH

CC

90.9k

UV

VFB

HIGH

LOW

10k

–

SNS1

SNSD1

SNSA1

ITH

HIGH

+

0.33μF

+

0Ω

499Ω

DRV

BST1

CC

ITH

LOW

0.1μF

0.22μF

7.15k

10μH

TG1

SW1

BG1

1mΩ

SS

V

LOW

SETCUR

BUCK

RUN

LTC3871

12V

30A

BUCK

392k

10k

RUN

VFB

HIGH

IMON

FREQ

–

SNS2

+

SNSD2

SNSA2

V

LOW

102k

10pF

0.33μF

45.2k

+

0Ω

499Ω

DRV

CC

BST2

0.22μF

OV

LOW

7.15k

PINS NOT SHOWN

IN THIS CIRCUIT:

CLKOUT, DRVSET,

FAULT, ILIM,

MODE, PHSMD

AND SYNC.

TG2

10μH

1mΩ

DRV

10k

CC

SW2

V5

BG2

3871 TA02

4.7μF

RELATED PARTS

PART NUMBER

DESCRIPTION

60V PolyPhase^®Synchronous Boost Controller

COMMENTS

4.5V (Down to 2.3V After Start-Up) ≤ V ≤ 60V, V

LTC3784

Up to 60V, I = 28µA

IN

OUT

Q

PLL Fixed Frequency 50kHZ to 900kHz, 3mm × 3mm QFN-16, MSOP-16E

LTC3769

LTC3899

60V Synchronous Boost Controller

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 60V, V Up to 60V, I = 28µA

PLL Fixed Frequency 50kHz to 900kHz, 4mm × 4mm QFN-24, TSSOP-20E

IN

OUT

Q

Triple Output, Buck/Buck/Boost Synchronous

Controller with Adjustable Gate Drive Voltage

4.5V (Down to 2.2V After Start-Up) ≤ V ≤ 60V, V Up to 60V, I = 29µA

IN

OUT

Q

Buck V

Range: 0.8V to 0.99V , Boost V

Up to 60V

OUT

IN

OUT

LTC3890/LTC3890-1/ 60V, Low I , Dual 2-Phase Synchronous Step-

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V

I = 50µA

Q

≤ 24V,

Q

IN

OUT

LTC3890-2

Down DC/DC Controller with 99% Duty Cycle

LTC3892/

LTC3892-1

60V Low I , Dual, 2-Phase Synchronous Step-

Down DC/DC Controller with Adjustable Gate Drive 0.99V , I = 29µA

PLL Fixed Frequency 50kHz to 900kHz, 4.5V ≤ V ≤ 60V, 0.8V ≤ V

≤

OUT

Q

IN

IN Q

LT^®8710

Synchronous SEPIC/Inverting/Boost Controller with 4.5V ≤ V ≤ 80V, Rail-to-Rail Output Current Monitor and Control,

IN

Output Current Control

Power Good

LT8705

80V V and V Synchronous 4-Switch

Buck-Boost DC/DC Controller

PLL Fixed Frequency 100kHz to 400kHz, 2.8V ≤ V ≤ 80V, 1.3V ≤ V

≤ 80V

IN

OUT

IN

OUT

LTM^®8056

58V , 48V

Buck-Boost μModule^®Regulator

PLL Fixed Frequency 200kHz to 700kHz, 5V ≤ V ≤ 58V, 1.2V ≤ V ≤ 48V,

OUT

Input/Output Current Monitors

IN

OUT

IN

3871f

LT 0816 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

34

For more information www.linear.com/LTC3871

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3871

●

 LINEAR TECHNOLOGY CORPORATION 2016


型号：	LTC3871HLXE#PBF
厂家：	Linear
描述：	LTC3871 - Bidirectional PolyPhase® Synchronous Buck or Boost Controller; Package: LQFP; Pins: 48; Temperature Range: -40°C to 125°C
文件：	总34页 (文件大小：1184K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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