LTC3876EFE#PBF_技术文档

LTC3876

Dual DC/DC Controller for

DDR Power with Differential VDDQ

Sensing and ±±50m VTT Referenꢀe

DESCRIPTION

FEATURES

The LTC^®3876 is a complete DDR power solution, com-

patible with DDR1, DDR2, DDR3 and future DDRX lower

voltage standards. The LTC3876 includes VDDQ and VTT

DC/DC controllers and a precision linear VTT reference. A

differential output sense amplifier and precision internal

reference combine to offer an accurate VDDQ supply. The

VTT controller tracks the precision VTTR linear reference

with less than 20mV total DC error. The precision VTTR

referencemaintains1.2%regulationaccuracytrackingone-

half VDDQ over temperature for a ±±0mA reference load.

n

Ctmnleꢁe DDR Ptwer StlpꢁitI wiꢁh VTT RefereIce

n

Wide V RaIge: ꢀ.5V ꢁt 38V, VDDQ: 1V ꢁt 2.5V

ꢂN

0.ꢃ7ꢄ VDDQ ꢅpꢁnpꢁ Vtlꢁage Accpracy

VDDQ aId VTT TermiIaꢁitI CtIꢁrtllers

1.2ꢄ 50mA ꢆiIear VTTR RefereIce ꢅpꢁnpꢁ

CtIꢁrtlled ꢅI-Time, Valley CprreIꢁ Mtde CtIꢁrtl

FreqpeIcy Prtgrammable frtm 200kHz ꢁt 2MHz

SyIchrtIizable ꢁt ExꢁerIal Cltck

n

ꢁ

= 30Is, ꢁ

= 90Is

ꢅN(MꢂN)

ꢅFF(MꢂN)

R

or Inductor DCR Current Sensing

SENSE

Power Good Output Voltage Monitor

Overvoltage Protection and Current Limit Foldback

Thermally Enhanced 38-Pin (±mm × 7mm) QFN and

TSSOP Packages

TheLTC3876allowsoperationfrom4.±Vto38Vmaximum

at the input. The VDDQ output can range from 1.0V to

2.±V, with a corresponding VTT and VTTR output range

of 0.±V to 1.2±V. Voltage tracking soft-start, PGOOD and

fault protection features are provided.

APPLICATIONS

L, LT, LTC, LTM, Linear Technology, OPTI-LOOP, and the Linear logo are registered trademarks

and Hot Swap and No R

are trademarks of Linear Technology Corporation. All other

SENSE

n

trademarks are the property of their respective owners. Protected by U.S. Patents including

±481178, ±487±±4, 6±802±8, 6304066, 6476±89, 6774611.

Motherboard Memory

Servers

n

TYPICAL APPLICATION

DDR3 1.5V VDDQ/20A 0.75VTT/ 10A ꢀ.5V ꢁt 1ꢀV ꢂInpꢁ

V

IN

EfficieIcy/Ptwer ꢆtss

V

4.±V TO

14V

IN

LTC3876

–

+

VDDR ChaIIel 1

SENSE1

SENSE2

C

0.1μF

1±k

0.1μF

IN1

+

SENSE2

100

90

80

70

60

±0

40

4.±

180μF

1±k

V

= 12V

0.1μF

IN

w2

VDDQ = 1.±V

4.0

3.±

BOOST1

TG1

BOOST2

TG2

3.±7k

L2

0.47μH

3.±7k

MT1

L1

0.47μH

MT2

MB2

VTT

0.7±V

±10A

1.±V, 20A

VDDQ

DISCONTINUOUS

MODE

3.0

2.±

2.0

SW1

SW2

DB1

DB2

DRV

CC1

DRV

CC2

C

OUT4

330μF

C

OUT2

330μF

INTV

CC

C

OUT3

100μF

1μF

4.7μF

w2

1.±

1.0

0.±

0

C

OUT1

100μF

30.1k

MB1

BG1

BG2

FORCED

CONTINUOUS

MODE

PGND

20k

+

–

V

1μF

OUTSENSE1

VTTRVCC

VTTSNS

VTTR

0.1

1

10

V

OUTSENSE1

100k

LOAD CURRENT (A)

PGOOD

0.1μF

PGOOD

VTTR

±±0mA

3876 TA01b

TRACK/SS1

2.2μF

1±k

1000pF

100k

1000pF

ITH1

RT

ITH2

SGND

RUN

3876 TA01a

3876f

1

LTC3876

ABSOLUTE MAXIMUM RATINGS

(Ntꢁe 1)

TRACK/SS1 Voltage..................................... –0.3V to ±V

Input Supply Voltage (V )......................... –0.3V to 40V

IN

DTR1, CVCC, PHASMD, RT, V

VDDQSNS, VTTR, ITH1, ITH2

, V

, VTTSNS,

RNG1 RNG2

BOOST1, BOOST2 Voltages ....................... –0.3V to 46V

SW1, SW2 Voltages...................................... –±V to 40V

Voltages................................ ..–0.3V to (INTV + 0.3V)

CC

INTV , DRV , DRV , EXTV , PGOOD, RUN,

CC

CC1

CC2

CC

Operating Junction Temperature Range

(BOOST1-SW1), (BOOST2-SW2), MODE/PLLIN

(Notes 2, 3, 4) ....................................... –40°C to 12±°C

Storage Temperature Range .................. –6±°C to 1±0°C

Lead Temperature (Soldering, 10 sec)

Voltages....................................................... –0.3V to 6V

+

–

+

–

V

, V

, SENSE1 , SENSE1 ,

OUTSENSE1

+

–

SENSE2 , SENSE2 Voltages ....................... –0.6V to 6V

FE Package ......................................................300°C

PIN CONFIGURATION

TOP VIEW

1

2

V

RNG2

38

37

36

3±

34

33

32

31

30

29

28

27

26

2±

24

23

22

21

20

CVCC

–

VTTSNS

BOOST

TG2

SENSE2

+

3

SENSE2

38 37 36 3± 34 33 32

4

PHASMD

ITH2

VDDQSNS

VTTR

1

2

3

4

±

6

7

8

9

31 TG2

30 SW2

±

SW2

6

BG2

VDDQSNS

VTTR

BG2

DRV

29

28

7

DRV

CC

VTTRVCC

MODE/PLLIN

CLKOUT

SGND

CC2

8

EXTV

CC

VTTRVCC

MODE/PLLIN

CLKOUT

SGND

27 EXTV

CC

9

INTV

CC

INTV

26

CC

PGND

39

PGND

39

10

11

12

13

14

1±

16

17

18

19

PGND

2± PGND

24

V

IN

RT

V

IN

DRV

CC1

RT

V

23 DRV

RNG1

CC1

BG1

V

ITH1 10

22 BG1

RNG1

SW1

ITH1

TRACK/SS1 11

+

21 SW1

20

TG1

V

12

TG1

TRACK/SS1

+

OUTSENSE1

13 14 1± 16 17 18 19

BOOST1

PGOOD

RUN

V

OUTSENSE1

–

+

–

OUTSENSE1

SENSE1

DTR1

SENSE1

UHF PACKAGE

38-LEAD (±mm × 7mm) PLASTIC QFN

FE PACKAGE

38-LEAD PLASTIC TSSOP

T

= 12±°C, θ = 34°C/W

JA

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB PGND

JMAX

T

JMAX

= 12±°C, θ = 28°C/W

JA

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

ꢆEAD FREE FꢂNꢂSH

LTC3876EUHF#PBF

LTC3876IUHF#PBF

LTC3876EFE#PBF

LTC3876IFE#PBF

TAPE AND REEꢆ

PART MARKꢂNG*

3876

PACKAGE DESCRꢂPTꢂꢅN

TEMPERATURE RANGE

LTC3876EUHF#TRPBF

LTC3876IUHF#TRPBF

LTC3876EFE#TRPBF

LTC3876IFE#TRPBF

–40°C to 12±°C

38-Lead (±mm × 7mm) Plastic QFN

38-Lead Plastic TSSOP

3876

LTC3876FE

38-Lead Plastic TSSOP

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3876f

2

LTC3876

ELECTRICAL CHARACTERISTICS ^Thel deItꢁes ꢁhe snecificaꢁitIs which annly tver ꢁhe snecified tneraꢁiIg

jpIcꢁitI ꢁemneraꢁpre raIge, tꢁherwise snecificaꢁitIs are aꢁ T_A= 25°C. V_ꢂN= 15V pIless tꢁherwise Itꢁed. (Ntꢁe 3)

SYMBꢅꢆ

PARAMETER

CꢅNDꢂTꢂꢅNS

MꢂN

TYP

MAX UNꢂTS

MaiI CtIꢁrtl ꢆttn

V

IN

Input Voltage Operating Range

4.±

38

V

VDDQ(REG)

VTTR(REG)

VTTSNS(REG)

VDDQ Regulated Operating Range

VTTR Regulated Operating Range

VTTSNS Regulated Operating Range

VDDQ Regulates Differentially with Respect

1.0

0.±

2.±

1.2±

V

–

to V

, VTTSNS and VTTR Regulate

OUTSENSE1

Differentially to One-Half VDDQ with Respect to

–

V

OUSTSENSE1

I

Q

Input DC Supply Current

Both Channels Enabled

Shutdown Supply Current

MODE/PLLIN = 0V, No Load

RUN1 = RUN2 = 0V

±000

20

μA

V

Regulated Differential Feedback Voltage on ITH1 = 1.2V (Note ±)

DFB1(REG)

Channel 1, VDDQ

T = 2±°C

0.±98±

0.±96

0.±94

0.601±

0.604

0.606

V

A

+

–

l

(V

– V

)

T = 0°C to 8±°C

0.6

OUTSENSE1

T = –40°C to 12±°C

A

Regulated Differential Feedback Voltage

on Channel 1, VDDQ Over Line, Load and

Common Mode

V

= 4.±V to 38V, ITH1 = 0.±V to 1.9V,

IN

–

= ±±00mV (Notes ±, 7)

OUTSENSE1

l

T = 0°C to 8±°C

0.±94

0.±91

0.6

0.606

0.609

V

A

T = –40°C to 12±°C

A

VTTSNS(REG)

Regulated Voltage Error on Channel 2,

VTTSNS (Referenced to VTTR)

ITH2 = 1.4V (Note ±)

T = 0°C to 8±°C

l

–10

–1±

10

1±

mV

A

T = –40°C to 12±°C

A

Regulated Voltage Error on Channel 2,

VTTSNS Over Line, Load and Common

Mode. (Referenced to VTTR)

V = 4.±V to 38V, ITH1 = 0.±V to 1.9V,

IN

(Notes ±, 7)

l

T = 0°C to 8±°C

–1±

–20

1±

20

mV

A

T = –40°C to 12±°C

A

+

–

I

V

Input Bias Current

V

[V

– V

] = 0.6V

±±

–2±

±±

±2±

–±0

±±0

nA

μA

nA

mS

ns

VOUTSENSE1

VTTSNS

OUTSENSE1

DFB1 OUTSENSE1

OUTSENSE1

–

+

[V

DFB1 OUTSENSE1

I

Input Bias Current

I

= 7±0mV

VTTSNS

g

Error Amplifier Transconductance

Minimum On-Time

ITH = 1.2V (Note 3)

1.7

30

m(EA)1,2

–

t

V

IN

= 38V, R = 20k, VDDSNS = 1.2V, V

= 0.6V

ON(MIN)1,2

OFF(MIN)1,2

T

SENSE

Minimum Off-Time

90

ns

CprreIꢁ SeIsiIg

–

l

V

Maximum Valley Current Sense Threshold

SENSE1

V

= 2V, V

= 0V, V

= 0.±7V, V

= 1.±V

80

21

39

100

30

120

40

mV

SENSE1(MAX)

SENSE1(MIN)

SENSE2(MAX)

SENSE2(MIN)

RNG

DFB1

SENSE1

+

–

(V

– V

)

SENSE1

= 1.±V

–

= INTV , V

= 0.±7V, V

= 1.±V

±0

61

CC DFB1

SENSE1

–

Minimum Valley Current Sense Threshold

V

= 2V, V

= 0V, V

= 0.63V, V

= 1.±V

SENSE1

–±0

–1±

–2±

mV

RNG

DFB1

+

–

(V

– V

)

= 0.63V, V

= 1.±V

SENSE1

–

(Forced Continuous Mode)

= INTV , V

= 0.63V, V

= 1.±V

CC DFB1

SENSE1

–

l

Maximum Valley Current Sense Threshold

V

RNG

V

RNG

V

RNG

= 2V, VTTSNS = 0.72V, V

= 0V, VTTSNS = 0.72V, V

= 0.7±V

80

21

39

100

30

±0

120

40

61

mV

SENSE2

+

–

(V

– V

)

SENSE2

= 0.7±V

SENSE2

–

= INTV , VTTSNS = 0.72V, V

= 0.7±V

CC

SENSE2

–

Minimum Valley Current Sense Threshold

V

RNG

V

RNG

V

RNG

= 2V, VTTSNS = 0.78V, V

= 0V, VTTSNS = 0.78V, V

= 0.7±V

–120

–36

–60

mV

SENSE2

+

–

(V

– V

)

= 0.7±V

SENSE1

SENSE2

–

(Forced Continuous Mode)

= INTV , VTTSNS = 0.78V, V

= 0.7±V

CC

SENSE2

+

I

SENSE1,2 Pins Input Bias Current

V

= 0.6V

= 2.±V

±±

1

±±0

±2

nA

μA

SENSE1,2

SENSE

–

SENSE2 Pins Input Bias Current

(Internal ±00k Resistor to SGND)

V

= 0.6V

= 2.±V

1.2

±

μA

SENSE1,2

SENSE1

–

3876f

3

LTC3876

ELECTRICAL CHARACTERISTICS ^Thel deItꢁes ꢁhe snecificaꢁitIs which annly tver ꢁhe snecified tneraꢁiIg

jpIcꢁitI ꢁemneraꢁpre raIge, tꢁherwise snecificaꢁitIs are aꢁ T_A= 25°C. V_ꢂN= 15V pIless tꢁherwise Itꢁed. (Ntꢁe 3)

SYMBꢅꢆ

PARAMETER

CꢅNDꢂTꢂꢅNS

MꢂN

TYP

MAX UNꢂTS

Sꢁarꢁ-Un aId ShpꢁdtwI

l

V

RUN Pin On Threshold

V

Rising

1.1±

1.2

100

2.±

10

1.2±

V

mV

μA

RUN(TH)

RUN(HYS)

RUN(OFF)

RUN(HYS)

RUN

RUN Pin On Hysteresis

Falling from V

RUN

RUN(TH)

I

RUN Pin Pull-Up Current When Off

RUN Pin Pull-Up Current Hysteresis

RUN = SGND

= I

I

– I

RUN(OFF)

μA

RUN(HYS)

RUN(ON)

l

V

INTV Undervoltage Lockout

INTV Falling

3.3

3.7

4.2

V

UVLO(INTVCC)

CC

INTV Rising

4.±

CC

I

Soft-Start Pull-Up Current

0V < TRACK/SS < 0.6V

1

μA

TRACK/SS

FreqpeIcy aId Cltck SyIchrtIizaꢁitI

f

Clock Output Frequency

(Steady-State Switching Frequency)

R = 20±k

200

±00

2000

kHz

CLKOUT

T

R = 80.6k

4±0

±±0

T

R = 18.2k

T

VTT Channel 2 Phase

(Relative to Channel 1)

V

= SGND

180

240

Deg

φ

PHASMD

VTT

= Floating

= INTV

CC

CLKOUT Phase

(Relative to Channel 1)

V

= SGND

60

90

120

Deg

PHASMD

CLKOUT

= Floating

= INTV

CC

V

Clock Output Voltage High

Clock Output Voltage Low

Clock Input Voltage High

Clock Input Voltage Low

Pulling to INTV

V

CLKOUT(H)

CLKOUT(L)

PLLIN(H)

CC

INTVCC

Pulling to SGND

0

2

f

>100kHz

V

MODE/PLLIN

–0.±

V

PLLIN(L)

R

MODE/PLLIN Input DC Resistance

600

kΩ

MODE/PLLIN

Gaꢁe Drivers

R

TG Driver Pull-Up On-Resistance

TG Driver Pull-Down On-Resistance

BG Driver 1 Pull-Up On-Resistance

BG Driver 2 Pull-Up On-Resistance

BG Driver Pull-Down On-Resistance

TG High

TG Low

2.±

1.2

2.±

1.6

0.8

20

Ω

ns

TG(UP)1,2

TG(DOWN)1,2

BG(UP)1

BG1 High

BG2 High

BG Low

BG(UP)2

BG(DOWN)1,2

D(TG/BG)1,2

D(BG/TG)1,2

T

Top Gate Off to Bottom Gate On Delay Time (Note 6)

Bottom Gate Off to Top Gate On Delay Time (Note 6)

1±

VTT RefereIce

VTTR(I

)

VTTR Load Regulation

(VTTR(I ) is Measured Through an

–±0mA < I

< ±0mA; T = –40°C to 12±°C

VTTR

VTTR A

1.± < VDDQ < 2.±

1.0 < VDDQ < 1.±

l

0.4940

0.4930

0.±060

0.±070

V/V

VTTR

Internal Kelvin Connection to the VTTR Pin

and is Specified as the Ratio (VTTR(I

VDDQ)

)/

VTTR

ꢂIꢁerIal V Regplaꢁtr

CC

V

Internal Regulated DRV

Voltage

6V < V < 38V

±.0

4.4

±.3

–1.±

4.6

±.6

–3

V

%

DRVCC1

CC1

IN

DRV

Load Regulation

I

= 0mA to 100mA

CC

∆V

CC1

DRVCC1

V

EXTV Switchover Voltage

EXTV Rising

4.8

V

EXTVCC(TH)

EXTVCC(HYS)

CC

EXTV Switchover Hysteresis

200

mV

CC

EXTV to DRV

Voltage Drop

V

= ±V, I

= 100mA

∆V

CC

CC2

EXTVCC

DRVCC2

3876f

4

LTC3876

ELECTRICAL CHARACTERISTICS ^Thel deItꢁes ꢁhe snecificaꢁitIs which annly tver ꢁhe snecified tneraꢁiIg

jpIcꢁitI ꢁemneraꢁpre raIge, tꢁherwise snecificaꢁitIs are aꢁ T_A= 25°C. V_ꢂN= 15V pIless tꢁherwise Itꢁed. (Ntꢁe 3)

SYMBꢅꢆ

PARAMETER

CꢅNDꢂTꢂꢅNS

MꢂN

TYP

MAX UNꢂTS

PGttd ꢅpꢁnpꢁ

PGD

PGOOD Overvoltage Threshold

PGOOD Undervoltage Threshold

PGOOD Threshold Hysteresis

PGOOD Low Voltage

V

, VTTSNS Rising, with Respect to

±

7.±

–7.±

2.0

10

%

V

OV

OUTSENSE

Reference Voltage

V

, VTTSNS Falling, with Respect to

–±

–10

UV

OUTSENSE

Reference Voltage

V

, VTTSNS Returning to Reference

HYS

OUTSENSE

Voltage

V

I

= 2mA

0.1

0.3

PGD(LO)

PGOOD

t

Delay from OV/UV Fault to PGOOD Falling

Delay from OV/UV Recovery to PGOOD

Rising

±0

20

μs

PGD(FALL)

PGD(RISE)

Ntꢁe 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Continuous operation above the specified absolute maximum operating

junction temperature may impair the device reliability or permanently

damage the device.

Ntꢁe 5: The LTC3876 is tested in a feedback loop that adjusts

+

–

Ntꢁe 2: T is calculated from the ambient temperature T and power

(V

V

) and VTTSNS to achieve specified error

J

A

OUTSENSE1

dissipation P according to the following formulas:

amplifier output voltages (ITH1,2).

D

LTC3876UHF: T = T + (P • 34°C/W)

Ntꢁe ꢃ: Delay times are measured using ±0% levels.

Ntꢁe 7: In order to simplify the total system error computation, the

J

A

D

LTC3876FE: T = T + (P • 28°C/W)

J

A

D

Ntꢁe 3: The LTC3876 is tested under pulsed load conditions such that

T ≈ T . The LTC3876E is guaranteed to meet performance specifications

regulated voltage is defined in one combined specification which includes

the effects of line, load and common mode variation. The combined

regulated voltage specification is tested by independently varying line,

load, and common mode, which by design do not significantly affect one

another. For any combination of line, load, and common mode variation,

the regulated voltage should be within the limits specified that are tested in

production to the following conditions:

J

A

from 0°C to 8±°C. Specifications over the –40°C to 12±°C operating

junction temperature range are assured by design, characterization

and correlation with statistical process controls. The LTC3876I is

guaranteed to meet performance specifications over the full –40°C to

12±°C operating junction temperature range. The maximum ambient

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the package thermal

impedance and other environmental factors.

–

a. Line: V = 4.±V to 38V, ITH = 1V, V

= 0V

IN

OUTSENSE1

–

b. Load: V = 1±V, ITH = 0.±V to 1.9V, V

= 0V

IN

OUTSENSE1

–

c. Common mode: V = 1±V, ITH = 1V, to V

= ±±00mV, (Ch1)

IN

OUTSENSE1

Ntꢁe ꢀ: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

3876f

5

LTC3876

TYPICAL PERFORMANCE CHARACTERISTICS

TraIsieIꢁ ResntIse VDDQ

(Ftrced CtIꢁiIptps Mtde)

ꢆtad Sꢁen VDDQ

(Ftrced CtIꢁiIptps Mtde)

ꢆtad Release VDDQ

(Ftrced CtIꢁiIptps Mtde)

I

LOAD

20A/DIV

V

SW

V

SW

20V/DIV

V

OUT

V

OUT

/DIV

±0mV/DIV

V

OUT

±0mV/DIV

±0mV

I

L

I

L

20A/DIV

3876 G02

3876 G01

3876 G03

±μs/DIV

LOAD STEP = 0A TO 1±A

10μs/DIV

LOAD TRANSIENT = 0A TO 1±A

±μs/DIV

LOAD RELEASE = 1±A TO ±00mA

V

= 12V

V

= 12V

IN

OUT

V

= 12V

IN

OUT

IN

OUT

= 1.±V

FIGURE 10 CIRCUIT, VDDQ CHANNEL 1

TraIsieIꢁ ResntIse VDDQ

(DisctIꢁiIptps Mtde)

ꢆtad Sꢁen VDDQ

(DisctIꢁiIptps Mtde)

ꢆtad Release VDDQ

(DisctIꢁiIptps Mtde)

I

LOAD

I

LOAD

20A/DIV

LOAD

20A/DIV

V

SW

20V/DIV

V

OUT

V

±0mV/DIV

OUT

V

OUT

±0mV/DIV

I

L

I

20A/DIV

L

20A/DIV

3876 G04

3876 G0±

3876 G06

10μs/DIV

±μs/DIV

LOAD TRANSIENT = 0A TO 1±A

LOAD STEP = ±00mA TO 1±A

LOAD RELEASE = 1±A TO ±00mA

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 1.±V

FIGURE 10 CIRCUIT, VDDQ CHANNEL 1

TraIsieIꢁ ResntIse VTT

(Ftrced CtIꢁiIptps Mtde)

ꢆtad Sꢁen VTT

(Ftrced CtIꢁiIptps Mtde)

ꢆtad Release VTT

I

LOAD

I

LOAD

20A/DIV

V

SW

20V/DIV

V

OUT

V

OUT

±0mV/DIV

I

L

I

L

I

10A/DIV

L

20A/DIV

10A/DIV

3876 G07

3876 G09

3876 G08

10μs/DIV

LOAD TRANSIENT = 0A TO 1±A

±μs/DIV

LOAD STEP = 0A TO 10A

LOAD RELEASE = 10A TO 0A

V

= 12V

V

= 12V

IN

OUT

V

= 12V

IN

OUT

IN

OUT

= 1.±V

= 0.7±V

FIGURE 10 CIRCUIT, VDDQ CHANNEL 1

FIGURE 10 CIRCUIT, VTT CHANNEL 2

3876f

6

LTC3876

TYPICAL PERFORMANCE CHARACTERISTICS

ꢅpꢁnpꢁ TrackiIg

(Ftrced CtIꢁiIptps Mtde)

Regplar Stfꢁ Sꢁarꢁ-Un

(Ftrced CtIꢁiIptps Mtde)

Stfꢁ Sꢁarꢁ-Un ꢂIꢁt

Prebiased ꢅpꢁnpꢁ

RUN

±V/DIV

V

IN

±V/DIV

VDDQ

±00mV/DIV

TRACK/SS

200mV/DIV

VTT

VDDQ

±00mV/DIV

VTT

TRACK/SS

200mV/DIV

VDDQ

±00mV/DIV

VTT

±00mV/DIV

TRACK/SS

200mV/DIV

3876 G11

3876 G12

3876 G10

1ms/DIV

10ms/DIV

2ms/DIV

CSS = 10nF

= 12V

V

= 12V

C

V

= 10nF

= 12V

IN

SS

IN

V

VDDQ = 1.±V, VTT - 0.7±V

FIGURE 10 CIRCUIT

IN

VDDQ = 1.±V, VTT = 0.7±V

VDDQ PREBIASED TO 0.7±V

VTT PREBIASED TO 0.6V

FIGURE 10 CIRCUIT

VDDQ = 1.±V, VTT = 0.7±V

FIGURE 10 CIRCUIT

ꢅvercprreIꢁ PrtꢁecꢁitI

(Ftrced CtIꢁiIptps Mtde)

Shtrꢁ-Circpiꢁ PrtꢁecꢁitI

(Ftrced CtIꢁiIptps Mtde)

ꢅvervtlꢁage PrtꢁecꢁitI

(Ftrced CtIꢁiIptps Mtde)

SHORT-

CIRCUIT

TRIGGER

1V/DIV

24A

10A

±0A

I

L

LOAD

CURRENT

20A/DIV

0A

C

OUT

V

DISCHARGE

OUT

I

L

1V/DIV

10A/DIV

V

OUT

200mV/DIV

C

OUT

FULL CURRENT LIMIT V

THAN HALF REGULATED SETTING

GREATER

OUT

RECHARGE

V

OUT

BG1

±V/DIV

±0mV/DIV

I

L

20A/DIV

BG STAYS

3876 G13

3876 G1±

3876 G14

ON UNTIL V

±00μs/DIV

±ms/DIV

20μs/DIV

OUT

OVERVOLTAGE

PULLED BELOW

V

= 12V

CURRENT LIMIT

FOLDBACK V

= 0A, SHORT = ±0A DROPS BELOW

V

= 12V

V

= 12V

IN

CREATED BY

APPLYING A

CHARGED

OVERVOLTAGE

THRESHOLD

VDDQ = 1.±V

= 0A

OUT

I

CURRENT LIMIT = 23A

I

LOAD

FIGURE 10 CIRCUIT,

VDDQ CHANNEL 1

HALF REGULATED

SET POINT

OVERLOAD = 10A TO 17.±A

FICURE 10 CIRCUIT, VDDQ CHANNEL 1

FIGURE 10 CIRCUIT,

VDDQ CHANNEL 1

CAPACITOR

TO V

OUT

Phase RelaꢁitIshin:

PHASMD = Fltaꢁ

(Ftrced CtIꢁiIptps Mtde)

Phase RelaꢁitIshin:

PHASMD = GrtpId

(Ftrced CtIꢁiIptps Mtde)

Phase RelaꢁitIshin:

PHASMD = ꢂNTV_CC

(Ftrced CtIꢁiIptps Mtde)

PLLIN

±V/DIV

PLLIN

±V/DIV

PLLIN

±V/DIV

SW1

±V/DIV

SW1

±V/DIV

SW1

±V/DIV

0°

SW2

±V/DIV

SW2

±V/DIV

SW2

±V/DIV

180°

240°

CLKOUT

±V/DIV

CLKOUT

±V/DIV

CLKOUT

±V/DIV

90°

60°

120°

3876 G17

3876 G18

3876 G16

±00ns/DIV

PHASMD = INTV

CC

±00ns/DIV

PHASMD = FLOAT

PHASMD = GND

V

= 6V

V

= 6V

IN

V

= 6V

IN

VDDQ = 1.±V, VTT = 0.7±V

LOAD = 0A

FIGURE 10 CIRCUIT

VDDQ = 1.±V, VTT = 0.7±V

LOAD = 0A

FIGURE 10 CIRCUIT

VDDQ = 1.±V, VTT = 0.7±V

LOAD = 0A

FIGURE 10 CIRCUIT

3876f

7

LTC3876

TYPICAL PERFORMANCE CHARACTERISTICS

ꢅpꢁnpꢁ RegplaꢁitI vs ꢂInpꢁ Vtlꢁage

VDDQ ChaIIel 1

ꢅpꢁnpꢁ RegplaꢁitI vs ꢆtad CprreIꢁ

VDDQ ChaIIel 1

ꢅpꢁnpꢁ RegplaꢁitI vs Temneraꢁpre

VDDQ ChaIIel 1

0.2

0.1

0.2

0.1

0.6

0.4

0.2

0

–0.1

–0.2

0

–0.1

–0.2

–0.4

–0.6

V

I

= 1±V

IN

OUT

V

I

= 1.±V

= ±A

V

= 1±V

OUT

LOAD

OUT

= 1.±V

= 0A

IN

= 1.±V

OUT

LOAD

V

NORMALIZED AT V = 1±V

NORMALIZED AT I

= 4A

IN

V

NORMALIZED AT T = 2±°C

LOAD

OUT

A

20

(V)

0

±

10 1±

2± 30 3± 40

0

2

4

I

6

8

10

–±0 –2±

0

2± ±0 7± 100 12± 1±0

TEMPERATURE (°C)

V

(A)

LOAD

IN

3876 G19

3876 G20

3876 G21

CꢆKꢅUT/SwiꢁchiIg FreqpeIcy

vs ꢂInpꢁ Vtlꢁage

CꢆKꢅUT/SwiꢁchiIg FreqpeIcy

vs ꢆtad CprreIꢁ

CꢆKꢅUT/SwiꢁchiIg FreqpeIcy

vs Temneraꢁpre

2

1

2

1

0

–1

–2

–1

–2

–1

V

= 1.6V

= ±A

V

= 1±V

OUT

IN

OUT

I

= 1.±V

LOAD

f = 200kHz

FREQUENCY NORMALIZED AT V = 1±V

V

LOAD

= 1±V, V

= 1.±V

OUT

IN

f = 200kHz

I

= 0A, f = 200kHz

FREQUENCY NORMALIZED AT I

= 4A

IN

LOAD

8

FREQUENCY NORMALIZED AT T = 2±°C

A

–2

–±0 –2±

0

2

4

6

10

0

±

10 1± 20 2± 30 3± 40

(V)

0

2± ±0 7± 100 12± 1±0

TEMPERATURE (°C)

3876 G24

I

(A)

V

LOAD

IN

3876 G23

3876 G22

VTTR ꢆtad RegplaꢁitI

VDDQ = 1.5V

VTTR ꢆtad RegplaꢁitI

VDDQ = 1V

VTTR ꢆtad RegplaꢁitI

VDDQ = 2.5V

0.±20

0.±1±

0.±10

0.±0±

0.±00

0.49±

0.490

0.48±

0.480

0.±20

0.±1±

0.±10

0.±0±

0.±00

0.49±

0.490

0.48±

0.480

0.±20

0.±1±

0.±10

0.±0±

0.±00

0.49±

0.490

0.48±

0.480

V

= 1±V

–40°C

2±°C

V

= 1±V

IN

–40°C

2±°C

8±°C

12±°C

V

= 1±V

–40°C

2±°C

IN

f = 400kHz

8±°C

12±°C

–±0

–2±

0

2±

±0

–±0

–2±

0

2±

±0

–±0

–2±

0

2±

±0

I

(mA)

I

(mA)

I

(mA)

VTTR

3876 G26

3876 G27

3876 G24

3876f

8

LTC3876

TYPICAL PERFORMANCE CHARACTERISTICS

Errtr Amnlifier TraIsctIdpcꢁaIce

vs Temneraꢁpre

VTT CprreIꢁ SeIse Vtlꢁage

vs ꢂTH Vtlꢁage

VDDQ CprreIꢁ SeIse Vtlꢁage

vs ꢂTH Vtlꢁage

1.80

1.7±

1.70

1.6±

1.60

1.±±

1.±0

120

100

80

120

90

VDDQ CH2

VTT CH2

60

30

40

0

20

–30

–60

–90

–120

0

–20

–40

–60

V

= 2V

V

RNG

V

RNG

V

RNG

= 2V

RNG

V

= 1V

V

= 0.6V

±0

TEMPERATURE (°C)

1.6

ITH VOLTAGE (V)

–±0 –2±

0

2±

7± 100 12± 1±0

0

0.4

0.8

1.2

2

2.4

1.6

ITH VOLTAGE (V)

0

0.4

0.8

1.2

2

2.4

3876 G28

3876 G29

3876 G30

RUN PiI Threshtlds

vs Temneraꢁpre

RUN Ppll-Un CprreIꢁs

vs Temneraꢁpre

TRACK/SS Ppll-Un CprreIꢁ

vs Temneraꢁpre

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

16

14

12

10

8

1.20

1.1±

1.10

1.0±

1.00

0.9±

0.90

SWITCHING REGION

STAND-BY REGION

RUN PIN ABOVE SWITCHING

THRESHOLD

6

SHUTDOWN REGION

RUN PIN BELOW SWITCHING

THRESHOLD

4

2

0

0.8±

0.80

±0

–±0 –2±

0

2±

7± 100 12± 1±0

–±0 –2±

0

2±

7± 100 12± 1±0

±0

–±0 –2±

0

2±

7± 100 12± 1±0

TEMPERATURE (°C)

3876 G31

3876 G32

3876 G33

ShpꢁdtwI CprreIꢁ iIꢁt V_ꢂNPiI

vs Vtlꢁage tI V_ꢂNPiI

ꢂNTV_CCUIdervtlꢁage ꢆtcktpꢁ

Threshtlds vs Temneraꢁpre

QpiesceIꢁ CprreIꢁ ꢂIꢁt V_ꢂNPiI

vs Temneraꢁpre wiꢁh EXTV_CC= 0V

4.±

4.3

4.1

3.9

3.7

3.±

3.3

40

3±

30

2±

20

1±

10

±

3.8

3.7

3.6

3.±

3.4

3.3

3.2

UVLO RELEASE

(INTV RISING)

CC

UVLO LOCK

(INTV FALLING)

CC

130°C

3.1

3.0

2±°C

–4±°C

0

±0

TEMPERATURE (°C)

–±0 –2±

0

2±

7± 100 12± 1±0

–±0 –2±

0

2±

7± 100 12± 1±0

20

(V)

0

±

10 1±

2± 30 3± 40

TEMPERATURE (°C)

V

IN

3876 G34

3876 G36

3876 G3±

3876f

9

LTC3876

PIN FUNCTIONS ^{(QFN/TSSꢅP)}

ꢂTH2 (PiI 1/PiI 5): Channel 2 VTT Current Control

Threshold. This pin is the output of the error amplifier

and the switching regulator’s compensation point. The

current comparator threshold increases with this control

voltage. This voltage ranges from 0V to 2.2V. ITH2 has

been optimized to support a symmetric range of positive

and negative current by moving the zero sense voltage to

1.2V. (zero inductor valley current).

operates in forced continuous mode. When an external

clockisappliedatthispin, bothchannelsoperateinforced

continuous mode and are synchronized to the external

clock. Channel 2 VTT operates in forced continuous mode

only; permitting it to accurately track VTTR when sourcing

and sinking load current.

CꢆKꢅUT (PiI ꢃ/PiI 10): Clock Output of Internal Clock

Generator. Its output level swings between INTV and

CC

VDDQSNS (PiI 2/PiI ꢃ): VDDQ Sense. VDDQSNS

provides the VDDQ regulation reference point to the

VTT differential reference resistor divider. The positive

SGND. If clock input is present at the MODE/PLLIN pin,

it will be synchronized to the input clock, with phase set

by the PHASMD pin. If no clock is present at the MODE/

PLLIN pin, its frequency will be set by the RT pin. To syn-

chronize other controllers, CLKOUT can be connected to

their MODE/PLLIN pins.

Input to the VTT differential reference resistor divider is

–

VDDQSNS and negative input is V

. The resistor

OUTSENSE

divider is connected internally between VDDQSNS and

–

V

and is composed of two equally sized 10±k

OUTSENSE

SGND (PiI 7/PiI 11): Signal Ground. All small-signal

analog components should be connected to this ground.

Connect SGND to the exposed pad and PGND pin using

a single PCB trace.

resistors in series for 210K total resistance.

WhenVDDQSNSistiedtoINTV ,theVTTRlinearreference

CC

outputs are three-stated and VTTR becomes the VTTSNS

reference input. This allows the option to tie the VTTR

reference input to the VTTR output of a second LTC3876

in a multiphase application.

RT (PiI 8/PiI 12): Clock Generator Frequency Program-

ming Pin. Connect an external resistor from RT to SGND

to program the switching frequency between 200kHz and

2MHz. An external clock applied to MODE/PLLIN should

be within ±30% of this programmed frequency to ensure

frequency lock. When the RT pin is floating, the frequency

is internally set to be slightly under 200kHz.

VTTR (PiI 3/PiI 7): VTT Reference. VTTR is the buffered

output of the VTT differential reference resistor divider.

VTTR is specifically designed for large DDR memory

systems by providing superior accuracy and load regula-

tion specified for up to ±±0mA. Connect VTTR directly to

V

, V

(PiI 9, PiI 3ꢀ/PiI 13, PiI 38): Current

RNG1

RNG2

the DDR memory V input. VTTR is a high output linear

REF

SenseVoltageRangeInputs. Whenprogrammedbetween

referencewhichtrackstheVTTdifferentialreferenceresis-

0.6V and 2V, the voltage applied to V

(20x)themaximumsensevoltagebetweenSENSE1,2 and

SENSE1,2 , i.e., for either channel, (V

0.± • V . If a V

is twenty times

RNG1,2

–

tor divider and is equal to 0.± • (VDDQSNS – V

).

+

OUTSENSE

Power is supplied through VTTRVCC. Internally the VTTR

connection is connected to VDDQSNS reference in order

to provide Kelvin sensing of VTTR. The output capacitor

minimum should be 2.2μF.

–

+

–

– V

) =

SENSE

is tied to SGND the channel operates

RNG

with a maximum sense voltage of 30mV, equivalent to a

of 0.6V; If tied to INTV , a maximum sense voltage

V

RNG

CC

VTTRVCC (PiI ꢀ/PiI 8): VTTR Supply Input for VTTR

of±0mV,equivalenttoaV

of1V.Donotfloatthesepins.

RNG

Reference. Connect to DRV through an RC decoupling

CC

ꢂTH1 (PiI 10/PiI 1ꢀ): Channel 1 VDDQ Current Control

Threshold. This pin is the output of the error amplifier

and the switching regulator’s compensation point. The

current comparator threshold increases with this control

voltage. The voltage ranges from 0V to 2.4V, with 0.8V

corresponding to the zero sense voltage (zero inductor

valley current).

filter of 2.2μF and 1Ω typically.

MꢅDE/PꢆꢆꢂN (PiI 5/PiI 9): Operation Mode Selection

or External Clock Synchronization Input. When this pin

is tied to INTV forced continuous mode operation is

CC

selected. Typing this pin to SGND allows discontinuous

mode operation on channel 1, VDDQ while channel 2, VTT

3876f

10

LTC3876

PIN FUNCTIONS ^{(QFN/TSSꢅP)}

TRACK/SS1 (PiI 11/PiI 15): External Tracking and Soft-

Start Input for Channel 1 VDDQ . An internal 1μA temper-

ature-independent pull-up current source is connected

to the TRACK/SS1 pin. A capacitor to ground at this pin

sets the ramp time to the final regulated output voltage.

DTR1 (PiI 1ꢃ/PiI 20): Detect Load Transient Transient for

Overshoot Reduction. When load current suddenly drops,

if voltage on this DTR pin drops below half of INTV ,

CC

the bottom gate (BG) will turn off and allow the inductor

current to drop to zero faster, thus reducing the V

OUT

The LTC3876 regulates V

, the differential feedback

OUTSENSE1

overshoot. (Refer to Load-Release Transient Detection in

DFB1

– V

+

–

voltages (V

) to the smaller of

the Applications Information section for more details.) To

disable the DTR feature, simply tie the DTR pin to INTV .

OUTSENSE1

0.6V or the voltage on the TRACK/SS1 pin. Alternatively,

another voltage supply connected to this pin allows the

output to track the outer supply during start-up.

CC

RUN (PiI 17/PiI 21): Run Control Input. An internal pro-

portional-to-absolute temperature (PTAT) pull-up current

source (~2.±μA at 2±°) is constantly connected to this pin.

Taking RUN below a threshold (~0.8V at 2±°) shuts down

+

V

(PiI 12/PiI 1ꢃ): VDDQ Differential Output

ꢅUTSENSE1

Sense Amplifier (+) Input of Channel 1. Connect this pin

to a feedback resistor divider between the positive and

all bias of INTV and DRV and places the LTC3876 into

CC

negative output capacitor terminals of V

. In nominal

micropowershutdownmode. AllowingtheRUNpintorise

above this threshold turns on the internal bias supply and

all circuitry while forcing TG and BG off. When the RUN

pin rises above 1.2V the TG and BG drivers are turned on

and an additional 10μA temperature-independent pull-up

current is connected internally to the RUN pin. The RUN

pin can sink up to ±0μA or be forced as high as 6V.

OUT1

operation the LTC3876 will attempt to regulate the dif-

ferential output voltage V

feedback resistor divider ratio.

to 0.6V multiplied by the

OUT1

–

V

(PiI 13/PiI 17): Differential Output Sense

ꢅUTSENSE1

Amplifier (–) Input of Channel 1. Connect this pin to the

negative terminal of the output load capacitor. This pin is

the remote ground connection for VDDQSNS which pro-

videstheinputtotheVTTreference(VTTR)resistordivider.

PGꢅꢅD (PiI 18/PiI 22): Power Good Indicator Output.

This open-drain logic output is pulled to ground when

VDDQ goes out of a ±7.±% or VTT goes out of a ±10%

windowaroundtheregulationpoint,aftera±0μspower-bad

masking delay. Returning to the regulation point, there is

a much shorted delay to power good, and a hysteresis of

around 1±mV on both sides of the window.

+

SENSE1 , SENSE2 (PiI 1ꢀ, PiI 37/PiI 18, PiI 3): Differ-

entialCurrentComparator(+)Input.TheITHpinvoltageand

controlled offsets between the SENSE and SENSE pins

set the current trip threshold. The comparator can be used

+

–

for R

sensing or inductor DCR sensing. For R

SENSE

+

sensing Kelvin (4-wire) connect the SENSE pin to the (+)

BꢅꢅST1,BꢅꢅST2(PiI19,PiI32/PiI23,PiI3ꢃ):Boosted

Floating Driver Supply for Top MOSFET Drivers. The (+)

terminalofthebootstrapcapacitorCBconnectstothispin.

+

terminal of R

. For DCR sensing tie the SENSE pin

SENSE

to the connection between the DCR sense capacitor and

sense resistor connected across the inductor.

The BOOST pins swings between (DRV – V

)

CC

SCHOTTKY

and (V + DRV – V ).

–

IN

CC

SCHOTTKY

SENSE1 , SENSE2 (PiI 15, PiI 3ꢃ/PiI 19, PiI 2): Dif-

ferential Current Comparator(–) Input. The comparator

TG1, TG2 (PiI 20, PiI 31/PiI 2ꢀ, PiI 35): Top Gate Driver

can be used for R

ing. For R

the SENSE pin to the (–) terminal of R

sensing or inductor DCR sens-

Outputs. The TG pins drive the gates of the top N-channel

SENSE

current sensing Kelvin (4-wire) connect

power MOSFET with a voltage swing of DRV between

SENSE

CC

–

. For DCR

SENSE

SW and BOOST.

–

sensing tie the SENSE pin to the DCR sense capacitor

tied to the inductor V

SW1, SW2 (PiI 21, PiI 30/PiI 25, PiI 3ꢀ): Switch Node

node connection. These pins

OUT

Connection to Inductors. Voltage swings are from a di-

also function as output voltage sense pins for the top

MOSFET on-time adjustment. The impedance looking

ode voltage below ground to V . The (–) terminal of the

IN

bootstrap capacitor, CB connects to this node.

+

into these pins is different from the SENSE pins because

there is an additional ±00k internal resistor from each of

–

the SENSE pins to SGND.

3876f

11

LTC3876

PIN FUNCTIONS ^{(QFN/TSSꢅP)}

BG1, BG2 (PiI 22, PiI 29/PiI 2ꢃ, PiI 33): Bottom Gate

EXTV (PiI 27/PiI 31): External Power Input. When

CC

Driver Outputs. The BG pins drive the gates of the bottom

EXTV exceeds 4.7V, an internal switch connects this pin

CC

N-channel power MOSFET between PGND and DRV .

to DRV

and shuts down the internal regulator so that

CC

CC2

INTV and gate-drive power is drawn from EXTV . The

CC

DRV , DRV

(PiI 23, PiI 28/PiI 27, PiI 32): Sup-

CC1

CC2

V pin still needs to be powered up but draws minimum

IN

plies of Bottom Gate Drivers. DRV

is also the output

CC1

CC2

current.

of an internal ±.3V regulator, DRV

of the EXTV switch. Normally the two DRV pins are

VTTSNS (PiI 33/PiI 37): VTT Sense, Channel 2 Error

Amplifier Feedback Input. Kelvin-connect this pin directly

to desired regulation point on the VTT supply, VTTSNS

provides the inverting regulation feedback signal for the

VTT termination supply. Internally the VTT error amplifier

positive input connects to the VTTR output for accurate

VTTR reference tracking. VTTSNS will regulate channel 2

CC

shorted together on the PCB, and decoupled to PGND with

a minimum of 4.7ꢀF ceramic capacitor, C

.

DRVCC

V

(PiI 2ꢀ/PiI 28): Input Voltage Supply. The supply

ꢂN

voltage can range from 4.±V to 38V. For increased noise

immunity decouple this pin to SGND with an RC filter.

Voltage at this pin is also used to adjust top gate on-time,

therefore it is recommended to tie this pin to the main

power input supply through an RC filter.

VTTterminationsupplytothedifferentialreferencevoltage

–

0.± • (VDDQSNS – V

).

OUTSENSE1

PHASMD (PiI 38/PiI ꢀ): Phase Selector Input. This pin

determinestherelativephasesofchannelsandtheCLKOUT

signal. With zero phase being defined as the rising edge

of TG1: Pulling this pin to SGND locks TG2 to 180° and

PGND (PiI 25, Exntsed Pad PiI 39/PiI 29, Exntsed

Pad PiI 39): Power Ground. Connect this pin as close

as practical to the source of the bottom N-channel power

MOSFET, the (–) terminal of C

and the (–) terminal

DRVCC

CLKOUT to 60°, Connecting this pin to INTV locks TG2

CC

of C . Connect the exposed pad and PGND pin to SGND

IN

to 240° and CLKOUT to 120° and floating this pin locks

TG2 to 180° and CLKOUT to 90°.

pin using a single PCB trace under the IC. The exposed

pad must be soldered to the circuit board for electrical

and rated thermal performance.

CVCC (PiI 35/PiI 1): Connect V . This pin should always

CC

be connected to INTV .

CC

ꢂNTV (PiI2ꢃ/PiI 30):Supply InputforInternalCircuitry

CC

(Not Including Gate Drivers). Normally powered from the

DRV pins through a decoupling RC filter to SGND (typi-

CC

cally 2.2Ω and 1ꢀF)

3876f

12

LTC3876

FUNCTIONAL DIAGRAM

V

IN

EN LDO

OUT SD

2μA

10μA

TO ±μA

+

–

4.2V

UVLO

PTAT

BOOST

TG

DRV

RUN

C

B

D

B

+

VTT

CHANNEL 2

M

T

R

L

SENSE

SW

EN_DRV

1.2V

–

DRV

CC

VDDQ

EXTV

CC

CHANNEL 1

+

–

+

4.7V

INTV

0.7V

CC

C

OUT

–

LOGIC

CONTROL

C

INTVCC

DRV

CC2

CC1

–

SENSE

START

STOP

V

2±0k

IN

ONE-SHOT

TIMER

C

DRVCC

R

FB1

FB2

BG DRV

2±0k

BG

M

B

FORCED

CONTINUOUS

MODE

ON-TIME

ADJUST

PGND

MODE/PLLIN

PHASE

DETECTOR

MODE/CLK

DETECT

I

REV

CMP

+

–

CLK1

CLK2

+

–

RT

SENSE

CLOCK PLL/

GENERATOR

TO CHANNEL 2

R

T

CLKOUT

CVCC

INTV

CC

1μA

g

m

INTV

CC

EA1

TRACK/SS

+

–

R

0.6V

PGD

C

SS

PGOOD

+

V

OUTSENSE1

OV

CH1

+

–

DIFFAMP

(A = 1)

DELAY

–

OUTSENSE1

UV

10±k

VDDQSNS

VTTRVCC

DRV

CC

C

VTTR(VCC)

OV

VTTR

CH2

UV

EA2

VTTR

+

–

VTTSNS

INTV

CC

3876 FD

CHANNEL 2

LOAD

RELEASE

DETECTION

1/2 INTV

DTR

+

–

CC

TO LOGIC

CONTROL

DUPLICATE DASHED

LINE BOX FOR

CHANNEL 2

V

RNG

ITH

INTV

CC

INTV

CC

C

ITH1

R

ITH2

R

ITH1

C

ITH2

3876f

13

LTC3876

OPERATION ^{(Refer ꢁt FpIcꢁitIal Diagram)}

DDR ꢅneraꢁitI

The VTT supply operates in forced continuous mode and

tracksVDDQinstart-upandinnormaloperationregardless

of the MODE/PLLIN settings. In start-up the VTT supply is

enabled coincident with the VDDQ supply. Operating the

VTT supply in forced continuous allows accurate tracking

in startup and under all operating conditions.

The LTC3876 is a dual channel, current mode step-down

controller designed to provide high efficiency power con-

version for high power DDR memory and bus termination

supplies.Itsuniquecontrolledon-timearchitectureallows

extremely low step-down ratio’s while maintaining a fast,

constant switching frequency.

VTT RefereIce (VTTR)

The LTC3876 is a complete DDR power solution with one

master RUN pin, TRACK/SS input and PGOOD output.

The RUN pin enables all supplies. The TRACK/SS pin

determines the VDDQ soft-start characteristics and VTT

tracks 0.± • VDDQ. PGOOD monitors both VDDQ and

VTT to ensure regulation within a ±7.±% typical window.

The current limit settings are set independently on both

VDDQ and VTT channels. The VDDQ, VTT and CLKOUT

phase relationships are set by the PHASMD pin to permit

multiphase operation in high power DDR solutions which

require more than one VDDQ or VTT channel.

The linear VTT reference, VTTR, is specifically designed

for large DDR memory systems by providing superior

accuracy and load regulation for up to ±±0mA output

load. VTTR is the buffered output of the VTT differential

reference resistor divider.

VTTR is a high output linear reference which tracks the

VTT differential reference resistor divider and is equal to

–

0.± •(VDDQSNS – V

the DDR memory V

). Connect VTTR directly to

OUTSENSE

REF

input. Power is supplied through

VTTRVCC. Internally the VTTR connection is connected to

VDDQSNS reference to provide Kelvin sensing of VTTR.

VDDQ Spnnly

Both input and output supply decoupling is important to

performance and accuracy. A 2.2ꢀF output capacitor is

recommendedformosttypicalapplications. Itissuggested

to use no less than 1ꢀF and no more than 47ꢀF on the

VTTR output. The typical recommended input VTTRVCC

RC decoupling filter is 2.2μF and 1Ω.

The LTC3876 is designed to support any DDR applica-

tion where VDDQ can range from 2.±V down to 1V. The

LTC3876supportshighpowerapplicationsbydifferentially

regulating the VDDQ supply, VTTR reference and VTT sup-

ply. The channel 1 feedback resistor divider, VDDQSNS

–

and V

should be tied directly to the differential

OUTSENSE

When VDDQSNS is tied to INTV , the VTTR linear

VDDQ regulation points. For best results these connec-

tions should be routed separately and Kelvin connected.

CC

reference output is three-stated and VTTR becomes the

VTTSNS reference input. This allows the option to tie the

VTTR reference input to the VTTR output of a second

LTC3876 in a multiphase application.

VDDQSNS is the VDDQ regulation sense point or positive

–

input and V

is the remote ground sense point

OUTSENSE

or negative input to the VTT differential reference resistor

divider.Theresistordividerisconnectedinternallybetween

MaiI CtIꢁrtl ꢆttn

–

VDDQSNSandV

andiscomposedoftwoequally

OUTSENSE

The LTC3876 is a controlled on-time, valley current mode

step-down DC/DC dual controller with two channels op-

erating out of phase. Each channel drives both main and

synchronousN-channelMOSFETs.Thetwochannelsoper-

ate independently where channel 1 is VDDQ and channel 2

is the VTT termination supply which tracks 0.± • VDDQ.

sized 10±k resistors in series for 210K total resistance.

VTT Spnnly

The VTT supply reference is connected internally to the

outputoftheVTTRVTTreferenceoutput.VTTSNSprovides

the inverting regulation feedback signal for the VTT ter-

mination supply. Kelvin-connect the VTTSNS pin directly

to desired regulation point on the VTT supply. By sensing

VTTSNS the channel 2 VTT supply regulates to VTTR.

The top MOSFET is turned on for a time interval deter-

mined by a one-shot timer. The one-shot timer or the top

MOSFET’son-timeiscontrolledtomaintainafixedswitch-

3876f

14

LTC3876

OPERATION ^{(Refer ꢁt FpIcꢁitIal Diagram)}

ingfrequency.AsthetopMOSFETisturnedoff,thebottom

MOSFETisturnedonafterasmalldelay.Thedelay,ordead

time, is to avoid both top and bottom MOSFETs being on

at the same time, causing shoot-through current from

forward-conduction voltage. This creates a more nega-

tive differential voltage (V – V ) across the inductor,

SW

OUT

allowing the inductor current to drop faster to zero, thus

creating less overshoot on V . See Load-Release Tran-

OUT

V directly to power ground. The next switching cycle is

sient Detection in Applications Information for details.

IN

initiated when the current comparator, I

, senses that

CMP

DiffereIꢁial ꢅpꢁnpꢁ SeIsiIg

inductor current falls below the trip level set by voltages

at the ITH and V pins. The bottom MOSFET is turned

RNG

This dual controller’s first channel, VDDQ features dif-

ferential output voltage sensing. The output voltage is

resistivelydividedexternallytocreateafeedbackvoltagefor

the controller. The internal difference amplifier (DIFFAMP)

senses this feedback voltage with respect to the output’s

remote ground reference to create a differential feedback

voltage. This scheme eliminates any ground offsets be-

tweenlocalgroundandremoteoutputground,resultingin

a more accurate output voltage. Channel 1 allows remote

output ground deviate as much as ±±00mV with respect

to local ground (SGND). Channel 2 VTT is referenced to

off immediately and the top MOSFET on again, restarting

the one-shot timer and repeating the cycle. Again in order

to avoid shoot-through current, there is a small dead-time

delaybeforethetopMOSFETturnson.Atthismoment,the

inductor current hits its “valley” and starts to rise again.

Inductor current is determined by sensing the voltage

+

–

between SENSE and SENSE , either by using an explicit

resistorconnectedinserieswiththeinductororbyimplic-

itly sensing the inductor’s DC resistive (DCR) voltage drop

through an RC filter connected across the inductor. The

VTTRinternallywhichdifferentiallytracks0.±•(VDDQSNS

trip level of the current comparator, I

, is proportional

CMP

–

– V

).

to the voltage at the ITH pin, with a zero-current threshold

corresponding to an ITH of 0.8V for channel 1 and 1.2V

for channel 2.

OUTSENSE

DRV /EXTV /ꢂNTV Ptwer

CC

DRV

are the power for the bottom MOSFET drivers.

CC1,2

Theerroramplifier(EA)adjuststhisITHvoltagebycompar-

ing the feedback signal to the internal reference voltage.

On channel 1, the difference amplifier (DA) converts the

Normally the two DRV pins are shorted together on

CC

the PCB, and decoupled to PGND with a minimum 4.7μF

+

–

ceramic capacitor, C

. The top MOSFET drivers are

DRVCC

differential feedback signal (V

– V

)

OUTSENSE1

biased from the floating bootstrap capacitors (C ) which

B

to a single-ended input for the EA; channel 2 uses VTTSNS

directly. Output voltage is regulated so that the feedback

voltage is equal to the internal reference. If the load current

increases/decreases, it causes a momentary drop/rise in

the differential feedback voltage relative to the reference.

The EA then moves ITH voltage, or inductor valley current

setpoint, higher/lower until the average inductor current

again matches the load current, so that the output voltage

comes back to the regulated voltage.

are recharged during each cycle through an external

Schottky diode when the top MOSFET turns off and the

SW pin swings down.

The DRV can be powered on two ways: an internal low-

CC

dropout (LDO) linear voltage regulator that is powered

from V and can output ±.3V to DRV . Alternatively,

IN

CC1

an internal EXTV switch (with on-resistance of around

CC

2Ω) can short the EXTV pin to DRV

.

CC

CC2

The LTC3876 features a detect transient (DTR) pin on

channel 1 to detect “load-release”, or a transient where

the load current suddenly drops, by monitoring the first

derivative of the ITH voltage. When detected, the bottom

gate (BG) is turned off and inductor current flows through

the body diode in the bottom MOSFET, allowing the SW

node voltage to drop below PGND by the body diode’s

If the EXTV pin is below the EXTV switchover voltage

CC

(typically 4.7V with 200mV hysteresis, see the Electrical

Characteristics Table), then the internal ±.3V LDO is en-

abled.IftheEXTV pinistiedtoanexternalvoltagesource

CC

greaterthanthisEXTV switchovervoltage, thentheLDO

CC

is shut down and the internal EXTV switch shorts the

CC

EXTV pin to the DRV

pin, thereby powering DRV

CC

CC2

CC

3876f

15

LTC3876

OPERATION ^{(Refer ꢁt FpIcꢁitIal Diagram)}

and INTV with the external voltage source and helping

usedtoprogramtheoutputvoltagesoft-startramp-uptime

by connecting an external capacitor from a TRACK/SS pin

tosignalground.Aninternaltemperature-independent1μA

pull-up current charges this capacitor, creating a voltage

rampontheTRACK/SSpin.AstheTRACK/SSvoltagerises

linearly from ground to 0.6V, the switching starts, VDDQ

ramps up smoothly to its final value and the feedback

voltage to 0.6V. TRACK/SS will keep rising beyond 0.6V,

until being clamped to around 3.7V.

CC

to increase overall efficiency and decrease internal self

heating from power dissipated in the LDO. This exter-

nal power source could be the output of the step-down

converter itself, given that the output is programmed to

higher than 4.7V. The V pin still needs to be powered up

IN

but now draws minimum current.

Power for most internal control circuitry other than gate

driversisderivedfromtheINTV pin.INTV canbepow-

CC

ered from the combined DRV pins through an external

Alternatively, the TRACK/SS pin can be used to track an

external supply like in a master slave configuration. Typi-

cally, this requires connecting a resistor divider from the

master supply to the TRACK/SS pin (see the Applications

Information section).

CC

RC filter to SGND to filter out noises due to switching.

ShpꢁdtwI aId Sꢁarꢁ-Un

The RUN pin has an internal proportional-to-absolute

temperature(PTAT)currentsource(around2.±μAat2±°C)

to pull up the pin. Taking the RUN pin below a certain

threshold voltage (around 0.8V at 2±°C) shuts down all

bias of INTV and DRV and places the LTC3876 into

TRACK/SS1 is pulled low internally when the correspond-

ing channel’s RUN pin is pulled below the 1.2V threshold

(hysteresis applies), or when INTV or either of the

CC

DRV

pins drop below their respective undervoltage

CC

CC1,2

micropower shutdown mode with a minimum I at the

lockout (UVLO) thresholds.

Q

V pin. The LTC3876’s DRV (through the internal ±.3V

IN

CC

LDOregulatororEXTV )andthecorrespondingchannel’s

ChaIIel 1 VDDQ ꢆighꢁ ꢆtad ꢅneraꢁitI

CC

internal circuitry off INTV will be biased up when either

CC

IftheMODE/PLLINpinistiedtoINTV oranexternalclock

CC

or both RUN pins are pulled up above the 0.8V threshold,

either by the internal pull-up current or driven directly by

external voltage source such as logic gate output.

is applied to MODE/PLLIN, the LTC3876 will be forced to

operate in continuous mode. With load current less than

one-half of the full load peak-to-peak ripple, the inductor

current valley can drop to zero or become negative. This

allows constant-frequency operation but at the cost of low

efficiency at light loads.

No channel of the LTC3876 will start switching until

the RUN pin is pulled up to 1.2V. When the RUN pin

rises above 1.2V, the TG and BG drivers are enabled, and

TRACK/SS released. An additional 10μA temperature-

independent pull-up current is connected internally

to the RUN pin. To turn off TG, BG and the additional

10μA pull-up current, RUN needs to be pulled down

below 1.2V by about 100mV. These built-in current and

voltagehysteresespreventfalsejitteryturn-onandturn-off

due to noise. Such features on the RUN pin allows input

undervoltage lockout (UVLO) to be set up using external

If the MODE/PLLIN pin is left open or connected to signal

ground, channel 1 will transition into discontinuous mode

operation, where a current reversal comparator (I

)

REV

shuts off the bottom MOSFET (M ) as the inductor cur-

B

rent approaches zero, thus preventing negative inductor

current and improving light-load efficiency. Only VDDQ

channel 1 is allowed to operate in discontinuous mode.

The VTT channel 2 operates in forced continuous mode at

all times independent of the MODE/PLLIN setting. In this

mode, both channel 1 switches remain off. As the output

capacitor discharges by load current and the output volt-

age droops lower, channel 1 EA will eventually move the

ITH voltage above the zero current level (0.8V) to initiate

another switching cycle.

voltage dividers from V .

IN

At start-up channel 1 is controlled by the voltage on the

TRACK/SS pin and channel 2 tracks 0.±00 • (VDDQSNS

–

– V

). When the voltage on the TRACK/SS pin

OUTSENSE1

is less than the 0.6V internal reference, the (differential)

feedback voltage is regulated to the TRACK/SS voltage

instead of the 0.6V reference. The TRACK/SS pin can be

3876f

16

LTC3876

OPERATION ^{(Refer ꢁt FpIcꢁitIal Diagram)}

Ptwer Gttd aId Faplꢁ PrtꢁecꢁitI

ing the top MOSFET turn-on time (on-time) through the

one-shot timer. This is achieved by sensing the phase

relationship between a top MOSFET turn-on signal and

its internal reference clock through a phase detector. The

time interval of the one-shot timer is adjusted on a cycle-

by-cycle basis, so that the rising edge of the top MOSFET

turn-on is always trying to synchronize to the internal

reference clock signal for the respective channel.

The PGOOD pin is connected to an internal open-drain

N-channel MOSFET. An external resistor or current source

can be used to pull this pin up to 6V (e.g., VDDQ/VTT or

DRV ).Overvoltageorundervoltagecomparators(OV,UV)

CC

turn on the MOSFET and pull the PGOOD pin low when the

feedback voltage is outside the ±7.±% window of the 0.6V

referencevoltage.ThePGOODpinisalsopulledlowwhenthe

channel’s RUN pin is below the 1.2V threshold (hysteresis

applies),orinundervoltagelockout(UVLO).Notethatfeed-

back voltage of channel 1 is sensed differentially through

Thefrequencyoftheinternaloscillatorcanbeprogrammed

from200kHzto2MHzbyconnectingaresistor,R ,fromthe

T

RT pin to signal ground (SGND). The RT pin is regulated

+

–

V

withrespecttoV

, whilechannel 2

to 1.2V internally.

OUTSENSE1

issensedthroughVTTSNS.PGOODisonlyhighwhenboth

channels are within window.

For applications with stringent frequency or interference

requirements, an external clock source connected to the

MODE/PLLIN pin can be used to synchronize the internal

clock signals through a clock phase-locked loop (Clock

PLL). The LTC3876 operates in forced continuous mode

of operation when it is synchronized to the external clock.

The external clock frequency has to be within ±30% of the

internal oscillator frequency for successful synchroniza-

tion. The clock input levels should be no less than 2V for

“high” and no greater than 0.±V for “low”. The MODE/

PLLIN pin has an internal 600k pull-down resistor.

When the feedback voltage of channel 1 is within the

±7.±% window and channel 2 within the ±10% window,

the open-drain NMOS is turned off and the pin is pulled

up by the external source. The PGOOD pin will indicate

power good immediately after the feedback is within the

window. But when a feedback voltage of a channel goes

out of the window, there is an internal ±0μs delay before

its PGOOD is pulled low. In an overvoltage (OV) condition,

M is turned off and M is turned on immediately without

T

B

delay and held on until the overvoltage condition clears.

Mplꢁichin ꢅneraꢁitIs

Foldback current limiting is provided if the output is below

one-half of the regulated voltage, such as being shorted to

ground.Asthefeedbackdropsbelowone-halfofthenormal

regulation point approaching 0V, the internal ITH clamp

voltage gradually drops 2.4V to 1.3V for VDDQ channel 1

and2.2Vto1.8VforVTTchannel2.Thisreducestheinduc-

tor valley current level to about one-third of its maximum

value as the feedback approaches 0V. Foldback current

limiting is disabled at start-up.

The PHASMD pin determines the relative phases between

the internal reference clock signals for the two channels

as well as the CLKOUT signal, as shown in Table 1. The

phases tabulated are relative to zero degree (0°) being

defined as the rising edge of the internal reference clock

signal of channel 1. The CLKOUT signal can be used to

synchronizeadditionalpowerstagesinamultiphasepower

supplysolutionfeedingeitherasinglehighcurrentoutput,

or separate outputs.

FreqpeIcy SelecꢁitI aId ExꢁerIal Cltck

SyIchrtIizaꢁitI

Table 1

PHASMD

VDDQ Channel 1

VTT Channel 2

CLKOUT

SGND

0°

FꢆꢅAT

0°

ꢂNTV

CC

An internal oscillator (clock generator) provides phase-

interleaved internal clock signals for individual channels

to lock up to. The switching frequency and phase of each

switching channel is independently controlled by adjust-

0°

180°

60°

180°

90°

240°

120°

3876f

17

LTC3876

APPLICATIONS INFORMATION

+

Once the required output voltage and operating frequency

have been determined, external component selection is

driven by load requirement, and begins with the selec-

tion of inductors and current sense method (either sense

The V

pin is a high impedance pin with no

OUTSENSE1

input bias current other than leakage in the nA range. The

–

V

pin has about 30μA of current flowing out

OUTSENSE1

of the pin. The VTTSNS pin is quasi-high impedance pin

resistors R

or inductor DCR sensing). Next, power

with minimum bias current out of the pin.

SENSE

MOSFETs are selected. Finally, input and output capaci-

Differentialoutputsensingallowsformoreaccurateoutput

regulation in high power distributed systems having large

line losses. Figure 2 illustrates the potential variations in

the power and ground lines due to parasitic elements.

The variations may be exacerbated in multi-application

systems with shared ground planes. Without differential

outputsensing, thesevariationsdirectlyreflectasanerror

in the regulated output voltage. The LTC3876 channel 1’s

differential output sensing can correct for up to ±±00mV

of variation in the output’s power and ground lines.

tors are selected.

ꢅpꢁnpꢁ Vtlꢁage PrtgrammiIg

As shown in Figure 1, external resistor dividers are used

from the regulated outputs to their respective ground

references to program the output voltages. On channel 1,

+

the resistive divider is tapped by the V

pin,

OUTSENSE1

and the ground reference is remotely sensed by the

–

V

pin, this voltage is sensed differentially.

OUTSENSE1

Connect the VTTSNS pin directly to the VTT output. By

regulatingthetapped(differential)feedbackvoltagestothe

internal reference 0.6V, the resulting output voltages are:

TheLTC3876channel1’sdifferentialoutputsensingscheme

isdistinctfromconventionalschemeswheretheregulated

output and its ground reference are directly sensed with

a difference amplifier whose output is then divided down

with an external resistor divider and fed into the error

amplifier input. This conventional scheme is limited by

the common mode input range of the difference amplifier

and typically limits differential sensing to the lower range

of output voltages.

–

V(VDDQ) – V

= 0.6V • (1 + R /R

)

OUTSENSE1

FB2 FB1

and

V(VTT) = 0.±00 • (VDDQ – V

–

)

OUTSENSE1

For example, if V

is programmed to 1.±V and the

OUT1

output ground reference is sitting at –0.±V with respect to

SGND, then the absolute value of the output will be 2.0V

with respect to SGND. The minimum (differential) output

voltages are limited to the internal reference 0.6V, and the

maximum are ±.±V.

The LTC3876’s channel 1 allows for seamless differential

outputsensingbysensingtheresistivelydividedfeedback

voltagedifferentially. Thisallowsfordifferentialsensingin

the full output range. The difference amplifier (DIFFAMP)

of the LTC3876 has a bandwidth of 8MHz, high enough

so that it will not affect main loop compensation and

transient behavior.

To avoid noise coupling into the feedback voltage

V

OUT

+

(V

),theresistordividersshouldbeplacedclose

OUTSENSE1

+

–

LTC3876

C

to the V

and V

. Remote output and

FF

OUTSENSE1

R

FB2

(OPT)

ground traces should be routed together as a differential

pair to the remote output. For best accuracy, these traces

to the remote output and ground should be connected as

close as possible to the desired regulation point.

+

–

C

V

OUT

OUTSENSE1

FB1

3876 F01

V

OUTSENSE1

Figpre 1. SeꢁꢁiIg ꢅpꢁnpꢁ Vtlꢁage

3876f

18

LTC3876

APPLICATIONS INFORMATION

+

C

IN

V

C

IN

–

POWER TRACE

PARASITICS

M

T

L

LTC3876

±V

DROP(PWR)

M

B

+

–

V

R

V

OUTSENSE1

I

LOAD

C

OUT1

OUT2

I

R

LOAD

FB2

FB1

GROUND TRACE

PARASITICS

±V

DROP(GND)

OTHER CURRENTS

FLOWING IN

SHARED GROUND

PLANE

3876 F02

Figpre 2. DiffereIꢁial ꢅpꢁnpꢁ SeIsiIg Used ꢁt Ctrrecꢁ ꢆiIe ꢆtss VariaꢁitIs

iI a High Ptwer Disꢁribpꢁed Sysꢁem wiꢁh a Shared GrtpId PlaIe

SwiꢁchiIg FreqpeIcy PrtgrammiIg

ꢂIdpcꢁtr Valpe CalcplaꢁitI

The choice of operating frequency is a trade-off between

efficiencyandcomponentsize.Loweringtheoperatingfre-

quencyimprovesefficiencybyreducingMOSFETswitching

losses but requires larger inductance and/or capacitance

to maintain low output ripple voltage. Conversely, raising

the operating frequency degrades efficiency but reduces

component size.

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of MOSFET

gate charge losses. In addition to this basic trade-off, the

effect of inductor value on ripple current and low current

operation must also be considered.

The switching frequency of the LTC3876 can be pro-

grammed from 200kHz to 2MHz by connecting a resistor

from the RT pin to signal ground. The value of this resistor

can be chosen according to:

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I decreases with higher

L

inductance or frequency and increases with higher V :

IN

⎛

⎞

V

f •L

V_OUT

⎛

⎞

OUT

ΔI_L=

1–

41550

⎜

⎝

⎟

⎠

⎜

⎟

V

⎝

⎠

R_T[kꢁ] =

–2.2

IN

f kHz

(

)

Accepting larger values of ∆I allows the use of low induc-

L

The overall controller system, including the clock PLL

and switching channels, has a synchronization range of

no less than ±30% around this programmed frequency.

Therefore, during external clock synchronization be sure

thattheexternalclockfrequencyiswithinthis±30%range

of the RT programmed frequency. It is advisable that the

RT programmed frequency be equal the external clock for

maximum synchronization margin. Refer to the “Phase

and Frequency Synchronization” section for more details.

tances, but results in higher output voltage ripple, higher

ESRlossesintheoutputcapacitor,andgreatercorelosses.

A reasonable starting point for setting ripple current is ∆I

L

= 0.4 • I

. The maximum ∆I occurs at the maximum

MAX

L

input voltage. To guarantee that ripple current does not

exceed a specified maximum, the inductance should be

chosen according to:

⎛

⎞ ⎛

⎟ ⎜

⎞

V_OUT

f • ΔI

V_OUT

L =

1–

⎜

⎟

V

⎝

_L(MAX)⎠ ⎝

⎠

IN(MAX)

3876f

19

LTC3876

APPLICATIONS INFORMATION

ꢂIdpcꢁtr Ctre SelecꢁitI

CprreIꢁ ꢆimiꢁ PrtgrammiIg

Once the value for L is known, the type of inductor must

be selected. The two basic types are iron powder and fer-

rite. The iron powder types have a soft saturation curve

which means they do not saturate hard like ferrites do.

However, iron powder type inductors have higher core

losses. Ferrite designs have very low core loss and are

preferred at high switching frequencies, so design goals

canconcentrateoncopperlossandpreventingsaturation.

The current sense comparators’ maximum trip voltage

+

–

between SENSE and SENSE (or “sense voltage”), when

ITH is clamped at its maximum, is set by the voltage ap-

plied to the V

pin and is given by:

RNG

V

= 0.0±V

RNG

SENSE(MAX)

The valley current mode control loop does not allow the

inductorcurrentvalleytoexceed0.0±V .Inpractice,one

RNG

should allow sufficient margin, to account for tolerance of

the parts and external component values. Note that ITH is

close to 2.4V for channel 1 and 2.2V for channel 2 when

in positive current limit.

Core loss is independent of core size for a fixed inductor

value, but it is very dependent on inductance selected. As

inductanceincreases,corelossesgodown.Unfortunately,

increased inductance requires more turns of wire and

therefore copper losses will increase.

AnexternalresistivedividerfromINTV canbeusedtoset

CC

the voltage on a V

pin between 0.6V and 2V, resulting

RNG

Ferrite core material saturates hard, which means that in-

ductance collapses abruptly when the peak design current

is exceeded. This results an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

in a maximum sense voltage between 30mV and 100mV.

Such wide voltage range allows for variety of applications.

The V

pin can also be tied to either SGND or INTV

CC

RNG

to force internal defaults. When V

is tied to SGND, the

of 0.6V. When the V

RNG

device has an equivalent V

RNG

A variety of inductors designed for high current, low volt-

ageapplicationsareavailablefrommanufacturerssuchas

Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,

Pulse and Würth.

is tied to INTV , the device has an equivalent V

of 2V.

CC

RNG

R

ꢂIdpcꢁtr CprreIꢁ SeIsiIg

SENSE

The LTC3876 can be configured to sense the inductor

currents through either low value series current sensing

CprreIꢁ SeIse PiIs

resistors (R

) or inductor DC resistance (DCR). The

SENSE

Inductor current is sensed through voltage between

choicebetweenthetwocurrentsensingschemesislargely

a design trade-off between cost, power consumption and

accuracy. DCR sensing is becoming popular because it

saves expensive current sensing resistors and is more

power efficient, especially in high current applications.

However, current sensing resistors provide the most ac-

curate current limits for the controller.

+

–

SENSE andSENSE pins,theinputsoftheinternalcurrent

comparators. TheinputvoltagerangeoftheSENSEpinsis

–0.±V to ±.±V. Care must be taken not to float these pins

+

during normal operation. The SENSE pins are quasi-high

+

impedance inputs. There is no bias current into a SENSE

–

pin when its corresponding channel’s SENSE pin ramps

up from below 1.1V and stays below 1.4V. But there is a

AtypicalR

inductorcurrentsensingschemeisshown

SENSE

+

small (~1μA) current flowing into a SENSE pin when its

in Figure 3a. The filter components (R , C ) need to be

F

–

corresponding SENSE pin ramps down from 1.4V and

placed close to the IC. The positive and negative sense

traces need to be routed as a differential pair close to-

getherand(4-wire)Kelvinconnectedunderneaththesense

resistor, asshowninFigure3b. Sensingcurrentelsewhere

caneffectivelyaddparasiticinductancetothecurrentsense

element, degrading the information at the sense terminals

and making the programmed current limit unpredictable.

–

staysabove1.1V.SuchcurrentsalsoexistonSENSE pins.

–

But in addition, each SENSE pin has an internal ±00k

resistor to SGND. The resulted current (V /±00k) will

OUT

–

dominate the total current flowing into the SENSE pins.

+

–

SENSE and SENSE pin currents have to be taken into

account when designing either R

current sensing.

or DCR inductor

SENSE

3876f

20

LTC3876

APPLICATIONS INFORMATION

For today’s highest current density solutions the value

of the sense resistor can be less than 1mΩ and the

peak sense voltage can be as low as 20mV. In addition,

inductor ripple currents greater than ±0% with operation

up to 2MHz are becoming more common. Under these

conditions, the voltage drop across the sense resistor’s

parasitic inductance becomes more relevant. A small RC

filter placed near the IC has been traditionally used to re-

duce the effects of capacitive and inductive noise coupled

in the sense traces on the PCB. A typical filter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

R

RESISTOR

SENSE

AND

PARASITIC INDUCTANCE

R

ESL

V

OUT

LTC3876

C ꢀtꢀꢁ3 ≤ ESL/R

F

S

POLE-ZERO

R

F

CANCELLATION

+

–

SENSE

C

F

3876 F03a

SENSE

FILTER COMPONENTS

PLACED NEAR SENSE PINS

Figpre 3a. R_SENSECprreIꢁ SeIsiIg

This same RC filter, with minor modifications, can be

used to extract the resistive component of the current

sense signal in the presence of parasitic inductance.

For example, Figure 4a illustrates the voltage waveform

across a 2mΩ sense resistor with a 2010 footprint for a

1.2V/1±Aconverteroperatingat100%load.Thewaveform

is the superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

inductor ripple current and the on-time and off-time of

the top switch, the value of the parasitic inductance was

determined to be 0.±nH using the equation:

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

3876 F03b

R

SENSE

Figpre 3b. SeIse ꢆiIes PlacemeIꢁ wiꢁh SeIse Resisꢁtr

R

is chosen based on the required maximum output

SENSE

current.Giventhemaximumcurrent,I

,maximum

OUT(MAX)

sense voltage, V

, set by V , and maximum

L(MAX)

SENSE(MAX)

RNG

inductor ripple current ∆I

, the value of R

can

SENSE

be chosen as:

V_ESL(STEP)

t_ON• t_OFF

t_ON+ t_OFF

V_SENSE(MAX)

ESL =

•

R_SENSE

=

ΔI_L

ΔI_L(MAX)

I_OUT(MAX)

–

2

where V

is the voltage step caused by the ESL

ESL(STEP)

and shown in Figure 4a, and t and t are top MOSFET

ON

OFF

Conversely, given R

thusV

and I

, V

and

SENSE

OUT(MAX) SENSE(MAX)

on-time and off-time respectively. If the RC time constant

ischosentobeclosetotheparasiticinductancedividedby

the sense resistor (L/R), the resulting waveform looks re-

sistiveagain,asshowninFigure4b.Forapplicationsusing

voltagecanbedeterminedfromtheaboveequa-

RNG

tion. To ensure the maximum output current, sufficient

margin should be built in the calculations to account for

variationsofLTC3876underdifferentoperatingconditions

and tolerances of external components.

low V

, check the sense resistor manufacturer’s

SENSE(MAX)

data sheet for information about parasitic inductance. In

the absence of data, measure the voltage drop directly

across the sense resistor to extract the magnitude of the

ESLstepandusetheequationabovetodeterminetheESL.

However, do not over filter. Keep the RC time constant less

than or equal to the inductor time constant to maintain a

Because of possible PCB noise in the current sensing

loop, the current sensing voltage ripple ∆V

= ∆I •

SENSE

L

R

SENSE

also needs to be checked in the design to get a

good signal-to-noise ratio. In general, for a reasonably

is recommended as

good PCB layout, 10mV of ∆V

SENSE

a conservative number to start with, either for R

inductor DCR sensing applications.

or

high enough ripple voltage on V

.

SENSE

RSENSE

3876f

21

LTC3876

APPLICATIONS INFORMATION

The previous discussion generally applies to high density/

high current applications where I > 10A and low

OUT(MAX)

inductorvaluesareused.ForapplicationswhereI

OUT(MAX)

< 10A, set R to 10Ω and C to 1000pF. This will provide

F

V

SENSE

20mV/DIV

a good starting point.

V

ESL(STEP)

The filter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

as a differential pair and Kelvin (4-wire) connected to the

sense resistor.

3876 F04a

±00ns/DIV

Figpre ꢀa. Vtlꢁage Waveftrm Measpred

Direcꢁly Acrtss ꢁhe SeIse Resisꢁtr

DCR ꢂIdpcꢁtr CprreIꢁ SeIsiIg

For applications requiring higher efficiency at high load

currents, the LTC3876 is capable of sensing the voltage

drop across the inductor DCR, as shown in Figure ±. The

DCR of the inductor represents the small amount of DC

windingresistance,whichcanbelessthan1mΩfortoday’s

low value, high current inductors.

V

SENSE

20mV/DIV

In a high current application requiring such an inductor,

conductionlossthroughasenseresistorwouldcostseveral

points of efficiency compared to DCR sensing.

3876 F04b

±00ns/DIV

Figpre ꢀb. Vtlꢁage Waveftrm Measpred Afꢁer ꢁhe

SeIse Resisꢁtr Filꢁer. C_F= 1000nF, R_F= 100Ω

The inductor DCR is sensed by connecting an RC filter

across the inductor. This filter typically consists of one or

tworesistors(R1andR2)andonecapacitor(C1)asshown

in Figure ±. If the external (R1||R2) • C1 time constant is

chosen to be exactly equal to the L/DCR time constant, the

voltage drop across the external capacitor is equal to the

voltage drop across the inductor DCR multiplied by R2/

(R1 + R2). Therefore, R2 may be used to scale the voltage

across the sense terminals when the DCR is greater than

–

Note that the SENSE1 and SENSE2 pins are also used

for sensing the output voltage for the adjustment of top

gate on time, t . For this purpose, there is an additional

ON

–

internal ±00k resistor from each SENSE pin to SGND,

therefore there is an impedance mismatch with their cor-

+

responding SENSE pins. The voltage drop across the

R causes an offset in sense voltage. For example, with

F

–

R = 100Ω, at V

= V

= ±V, the sense-voltage

OUT

SENSE

offset V

• R /±00k = 1mV. Such

SENSE(OFFSET)

SENSE F

INDUCTOR

small offset may seem harmless for current limit, but

L

DCR

could be significant for current reversal detection (I ),

V

REV

OUT

C

causingexcessnegativeinductorcurrentatdiscontinuous

OUT

L/DCR = (R1||R2) C1

R1

LTC3876

mode. Also, at V

= 30mV, a mere 1mV offset

SENSE(MAX)

+

–

will cause a significant shift of zero-current ITH voltage

by (2.4V – 0.8V) • 1mV/30mV = ±3mV. Too much shift

maynotallowtheoutputvoltagetoreturntoitsregulated

value after the output is shorted due to ITH foldback.

SENSE

R2

(OPT)

C1

3876 F0±

SENSE

C1 NEAR SENSE PINS

Therefore, when a larger filter resistor R value is used,

F

it is recommended to use an external ±00k resistor from

Figpre 5. DCR CprreIꢁ SeIsiIg

+

each SENSE pin to SGND, to balance the internal ±00k

–

resistor at its corresponding SENSE pin.

3876f

22

LTC3876

APPLICATIONS INFORMATION

the target sense resistance. With the ability to program

power loss when deciding whether to use DCR sensing or

SENSE

current limit through the V

pin, R2 may be optional. C1

R

sensing. Light load power loss can be modestly

RNG

is usually selected in the range of 0.01μF to 0.47μF. This

forcesR1||R2toaround2kto4k,reducingerrorthatmight

have been caused by the SENSE pins’ input bias currents.

higher with a DCR network than with a sense resistor due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

Resistor R1 should be placed close to the switching node,

to prevent noise from coupling into sensitive small-signal

nodes. Capacitor C1 should be placed close to the IC pins.

To maintain a good signal-to-noise ratio for the current

sense signal, start with a ∆V

of 10mV. For a DCR

SENSE

The first step in designing DCR current sensing is to

determine the DCR of the inductor. Where provided, use

themanufacturer’smaximumvalue, usuallygivenat2±°C.

Increase this value to account for the temperature coef-

ficient of resistance, which is approximately 0.4%/°C. A

sensing application, the actual ripple voltage will be de-

termined by:

V – V_OUTV_OUT

IN

ΔV_SENSE

=

•

R1•C1 V • f

IN

conservative value for inductor temperature T is 100°C.

L

TheDCRoftheinductorcanalsobemeasuredusingagood

RLC meter, but the DCR tolerance is not always the same

and varies with temperature; consult the manufacturers’

data sheets for detailed information.

Ptwer MꢅSFET SelecꢁitI

Two external N-channel power MOSFETs must be selected

for each channel of the LTC3876 controller: one for the

top (main) switch and one for the bottom (synchronous)

switch. The gate drive levels are set by the DRV voltage.

This voltage is typically ±.3V. Pay close attention to the

From the DCR value, V

is easily calculated as:

SENSE(MAX)

CC

V_SENSE(MAX)=DCR_MAX(25°C)

BV

specification for the MOSFETs as well; most of the

DSS

⎡

⎤

⎦

• 1+0.4% T

–25°C

(

)

L(MAX)

logic-level MOSFETs are limited to 30V or less.

⎣

⎛

ΔI_L

⎞

Selection criteria for the power MOSFETs include the on-

• I

–

⎜ ^OUT(MAX)

⎟

⎠

resistance, R

, Miller capacitance, C

DS(ON)

, input

⎝

2

MILLER

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

IfV

iswithinthemaximumsensevoltage(30mV

C

SENSE(MAX)

MILLER

to 100mV) of the LTC3876 as programmed by the V

pin, then the RC filter only needs R1. If V

usually provided on the MOSFET manufacturers’ data

sheet. C isequaltotheincreaseingatechargealong

RNG

is

SENSE(MAX)

MILLER

higher, then R2 may be used to scale down the maximum

the horizontal axis while the curve is approximately flat,

sense voltage so that it falls within range.

divided by the specified V test voltage.

DS

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

When the IC is operating in continuous mode, the duty

cycles for the top and bottom MOSFETs are given by:

V_OUT

D_TOP

=

V

_IN(MAX)– V_OUT• V

V

(

)

OUT

IN

P

R1 =

_LOSS( )

V_OUT

R1

D_BOT=1–

V

IN

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

3876f

23

LTC3876

APPLICATIONS INFORMATION

The MOSFET power dissipations at maximum output

current are given by:

a single-phase application. The maximum RMS capacitor

current is given by:

P_TOP=D_TOP•I_OUT(MAX)²•R_DS(ON)(MAX)1+δ + V

2

(

)

V_OUT

V

V_OUT

IN

I_RMS≅I_OUT(MAX)

•

–1

V

I

R_TG(HI)

R_TG(LO)

⎛

⎜

⎞

⎟

⎡

⎢

⎣

⎤

⎥

⎦

IN

OUT(MAX)

•

•C_MILLER

+

• f

2

V_DRVCC– V_MILLERV_MILLER

⎝

⎠

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT(MAX)/2. This simple worst-case condition

is commonly used for design because even significant

deviations do not offer much relief. Note that capacitor

manufacturers’ ripple current ratings are often based on

only 2000 hours of life. This makes it advisable to further

derate the capacitor or to choose a capacitor rated at a

highertemperaturethanrequired.Severalcapacitorsmay

also be paralleled to meet size or height requirements in

the design. Due to the high operating frequency of the

LTC3876, additional ceramic capacitors should also be

used in parallel for C_INclose to the IC and power switches

to bypass the high frequency switching noises. Typically

multipleX±RorX7Rceramiccapacitorsareputinparallel

with either conductive-polymer or aluminum-electrolytic

types of bulk capacitors. Because of its low ESR, the ce-

ramic capacitors will take most of the RMS ripple current.

Vendors do not consistently specify the ripple current

rating for ceramics, but ceramics could also fail due to

excessiveripplecurrent.Alwaysconsultthemanufacturer

if there is any question.

2

P

= D

• I

• R

• (1 + δ )

BOT

BOT OUT(MAX)

DS(ON)(MAX)

whereδisthetemperaturedependencyofR

is the TG pull-up resistance, and R

,R

DS(ON) TG(HI)

is the TG pull-

TG(LO)

down resistance. V

is the Miller effect V voltage

MILLER

GS

and is taken graphically from the MOSFET’s data sheet.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V < 20V,

IN

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V, the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

short-circuit when the synchronous switch is on close to

100% of the period.

The term (1 + δ) is generally given for a MOSFET in the

form of a normalized R

vs temperature curve in the

DS(ON)

power MOSFET data sheet. For low voltage MOSFETs,

Figure6representsasimplifiedcircuitmodelforcalculat-

ing the ripple currents in each of these capacitors. The

input inductance (L_IN) between the input source and the

inputoftheconverterwillaffecttheripplecurrentthrough

0.±% per degree (°C) can be used to estimate δ as an

approximation of percentage change of R

:

DS(ON)

δ = 0.00±/°C • (T – T )

J

A

whereT isestimatedjunctiontemperatureoftheMOSFET

J

L

IN

1μH

and T is ambient temperature.

A

ESR

ESL

ESR

ESL

(BULK)

(CERAMIC)

C SelecꢁitI

ꢂN

+

V

IN

I

PULSE(PHASE2)

PULSE(PHASE1)

(BULK)

(CERAMIC)

–

In continuous mode, the source current of the top

N-channel MOSFET is a square wave of duty cycle V

/

+

OUT

C

IN(CERAMIC)

IN(BULK)

V . To prevent large voltage transients, a low ESR input

IN

3876 F06

capacitor sized for the maximum RMS current must be

used. The worst-case RMS current occurs by assuming

Figpre ꢃ. Circpiꢁ Mtdel ftr ꢂInpꢁ Canaciꢁtr

Rinnle CprreIꢁ SimplaꢁitI

3876f

24

LTC3876

APPLICATIONS INFORMATION

the capacitors. A lower input inductance will result in less

ripple current through the input capacitors since more

ripple current will now be flowing out of the input source.

operate at sustained negative current for any significant

period of time in normal operation. There could be DDR

testconditionswhichdoexercisesuchextremes,butagain

this should not be continuous. Therefore, determine the

worst-case RMS requirement for the input capacitors and

reduce as appropriate for sufficient margin.

For simulating positive output current loading using this

model, look at the ripple current during steady-state for

the case where one phase is fully loaded and the other

is not loaded. This will in general be the worst-case for

ripple current since the ripple current from one phase will

not be cancelled by ripple current from the other phase.

The V sources of the top MOSFETs should be placed

IN

close to each other and share common C (s). Separating

IN

the sources and C may produce undesirable voltage and

IN

current resonances at V .

IN

The LTC3876 is more complex than this example because

the VTT channel can provide significant negative current.

For the LTC3876 steady state worst-case, look at the

condition where VDDQ channel is fully loaded and the

VTT channel is supplying maximum negative current.

This will in general be the worst-case for ripple current

since the ripple current from VTT will add with ripple cur-

rent from VDDQ when the VTT channel sinks or provides

negative current.

A small (0.1μF to 1μF) bypass capacitor between the IC’s

V pin and ground, placed close to the IC, is suggested.

IN

A 2.2Ω to 10Ω resistor placed between C and the V

IN

pin is also recommended as it provides further isolation

from switching noise of the two channels.

C

SelecꢁitI

ꢅUT

The selection of output capacitance C

is primarily

OUT

determined by the effective series resistance, ESR, to

Note that the bulk capacitor also has to be chosen for

RMS rating with ample margin beyond its RMS current

persimulationwiththecircuitmodelprovided.Foralower

V_INrange, a conductive-polymer type (such as Sanyo

OS-CON) can be used for its higher ripple current rating

and lower ESR. For a wide V_INrange that also require

highervoltagerating,aluminum-electrolyticcapacitorsare

more attractive since it can provide a larger capacitance

for more damping. An aluminum-electrolytic capacitor

with a ripple current rating that is high enough to handle

all of the ripple current by itself will be very large. But

when in parallel with ceramics, an aluminum-electrolytic

capacitor will take a much smaller portion of the RMS

ripple current due to its high ESR. However, it is crucial

that the ripple current through the aluminum-electrolytic

capacitor should not exceed its rating since this will

produce significant heat, which will cause the electrolyte

inside the capacitor to dry over time and its capacitance

to go down and ESR to go up.

minimize voltage ripple. The output voltage ripple ∆V

in continuous mode is determined by:

,

OUT

⎛

⎞

1

ΔV_OUT≤ ΔI_LR_ESR

+

⎜

⎝

⎟

8• f •C_OUT

⎠

where f is operating frequency, and ∆I is ripple current

L

in the inductor. The output ripple is highest at maximum

input voltage since ∆I increases with input voltage. Typi-

L

cally, once the ESR requirement for C

has been met,

OUT

the RMS current rating generally far exceeds that required

from ripple current.

In single-output applications, for the same reason that

LTC3876 is only truly phase interleaved at steady state,

ripple current of individual channels could add up in

transient, it is advisable to consider using the worst-case

∆I , i.e., the sum of the ∆I of all individual channels, in

L

the calculation of ∆V

.

OUT

While it is always safest to choose the input capacitors

RMS rating according to the worst-case single-phase ap-

plicationwithnegativeVTTcurrentasdiscussedabove,itis

likelynotnecessary.ForDDRmemory,theVTToutputload

current will statistically approach zero and should never

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

maintain the ripple voltage.

3876f

25

LTC3876

APPLICATIONS INFORMATION

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramiccapacitorsareallavailableinsurfacemountpack-

ages. Special polymer capacitors offer very low ESR but

havelowercapacitancedensitythanothertypes.Tantalum

capacitors have the highest capacitance density but it is

important to only use types that have been surge tested

foruseinswitchingpowersupplies.Aluminumelectrolytic

capacitors have significantly higher ESR, but can be used

in cost-sensitive applications provided that consideration

is given to ripple current ratings and long-term reliability.

rises to approximately V + INTV . The boost capacitor

IN CC

needs to store approximately 100 times the gate charge

required by the top MOSFET. In most applications a 0.1μF

to 0.47μF, X±R or X7R dielectric capacitor is adequate. It

is recommended that the BOOST capacitor be no larger

than 10% of the DRV capacitor, C

, to ensure that

CC

DRVCC

the C

can supply the upper MOSFET gate charge

DRVCC

and BOOST capacitor under all operating conditions. Vari-

able frequency in response to load steps offers superior

transient performance but requires higher instantaneous

gate drive. Gate charge demands are greatest in high

frequency low duty factor applications under high load

steps and at start-up.

Ceramic capacitors have excellent low ESR characteristics

but can have a high voltage coefficient and audible piezo-

electriceffects.Thehigh-Qofceramiccapacitorswithtrace

inductance can also lead to significant ringing. When used

as input capacitors, care must be taken to ensure that ring-

ing from inrush currents and switching does not pose an

overvoltage hazard to the power switches and controller.

DRV Regplaꢁtr aId EXTV Ptwer

CC

The LTC3876 features a PMOS low dropout (LDO) linear

regulatorthatsuppliespowertoDRV fromtheV supply.

CC

IN

The LDO regulates its output at the DRV

pin to ±.3V.

CC1

The LDO can supply a maximum current of 100mA and

must be bypassed to ground with a minimum of 4.7μF

ceramic capacitor. Good bypassing is needed to supply

the high transient currents required by the MOSFET gate

drivers and to minimize interaction between the channels.

Forhighswitchingfrequencies,reducingoutputrippleand

betterEMIfilteringmayrequiresmallvaluecapacitorsthat

have low ESL (and correspondingly higher self-resonant

frequencies) to be placed in parallel with larger value

capacitors that have higher ESL. This will ensure good

noise and EMI filtering in the entire frequency spectrum

of interest. Even though ceramic capacitors generally

have good high frequency performance, small ceramic

capacitors may still have to be parallel connected with

large ones to optimize performance.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3876 to be

exceeded, especially if the LDO is active and provides

DRV . Power dissipation for the IC in this case is high-

CC

est and is approximately equal to V • I

. The gate

IN DRVCC

charge current is dependent on operating frequency as

discussed in the Efficiency Considerations section. The

junction temperature can be estimated by using the equa-

tion given in Note 2 of the Electrical Characteristics. For

High performance through-hole capacitors may also be

used, but an additional ceramic capacitor in parallel is

recommendedtoreducetheeffectoftheirleadinductance.

Rememberalsotoplacehighfrequencydecouplingcapaci-

tors as close as possible to the power pins of the load.

example, when using the LDO, LTC3876’s DRV current

CC

is limited to less than ±2mA from a 38V supply at T =

A

70°C in the FE package:

Ttn MꢅSFET Driver Spnnly (C , D )

B

T = 70°C + (±2mA)(38V)(28°C/W) = 12±°C

J

An external bootstrap capacitor, C , connected to the

B

BOOST pin supplies the gate drive voltage for the topside

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

MOSFET. This capacitor is charged through diode D from

B

DRV whentheswitchnodeislow.WhenthetopMOSFET

operatingincontinuousconductionmodeatmaximumV .

CC

IN

turns on, the switch node rises to V and the BOOST pin

IN

3876f

26

LTC3876

APPLICATIONS INFORMATION

When the voltage applied to the EXTV pin rises above

Forapplicationswherethemaininputpowerneverexceeds

CC

4.7V,theV LDOisturnedoffandtheEXTV isconnected

±.3V, tie the DRV

and DRV

pins to the V input

IN

CC

CC1

CC2 IN

toDRV pinwithaninternalswitch. Thisswitchremains

through a small resistor, (such as 1Ω to 2Ω) as shown

in Figure 7 to minimize the voltage drop caused by the

gate charge current. This will override the LDO and will

CC2

on as long as the voltage applied to EXTV remains

CC

above 4.±V. Using EXTV allows the MOSFET driver and

CC

control power to be derived from the LTC3876’s switching

prevent DRV from dropping too low due to the dropout

CC

regulator output V

during normal operation and from

voltage.MakesuretheDRV voltageexceedstheR

CC DS(ON)

OUT

the LDO when the output is out of regulation (e.g., start-

test voltage for the external MOSFET which is typically at

4.±V for logic-level devices.

up, short-circuit). If more current is required through the

EXTV than is specified, an external Schottky diode can

CC

be added between the EXTV and DRV pins. Do not

CC

LTC3876

apply more than 6V to the EXTV pin and make sure that

CC

DRV

CC2

CC1

EXTV is less than V .

CC

IN

R

DRVCC

DRV

Significant efficiency and thermal gains can be realized

V

IN

C

DRVCC

IN

by powering DRV from the switching converter output,

CC

since the V current resulting from the driver and control

IN

currentswillbescaledbyafactorof(dutycycle)/(switcher

efficiency).

3876 F07

Tying the EXTV pin to a ±V supply reduces the junction

CC

temperature in the previous example from 12±°C to:

Figpre 7. Seꢁpn ftr V_ꢂN≤ 5.3V

T = 70°C + (±2mA)(±V)(28°C/W) = 77°C

J

However, for 3.3V and other low voltage outputs, ad-

ꢂInpꢁ UIdervtlꢁage ꢆtcktpꢁ (UVꢆꢅ)

ditional circuitry is required to derive DRV power from

CC

the converter output.

The LTC3876 has two functions that help protect the con-

trollerincaseofinputundervoltageconditions.Aninternal

The following list summarizes the four possible connec-

UVLO comparator constantly monitors the INTV and

CC

tions for EXTV :

CC

DRV voltagestoensurethatadequatevoltagesarepres-

CC

1. EXTV left open (or grounded). This will cause INTV

CC

ent. The comparator enables internal UVLO signal, which

to be powered from the internal ±.3V LDO resulting

in an efficiency penalty of up to 10% at high input

voltages.

locks out the switching action of both channels, until the

INTV and DR

pins are all above their respective

VCC1,2

CC

UVLO thresholds. The rising threshold (to release UVLO)

of the INTV is typically 4.2V, with 0.±V falling hysteresis

CC

2. EXTV connecteddirectlytoswitchingconverteroutput

CC

(tore-enableUVLO).TheUVLOthresholdsforDR

are

VCC1,2

V

OUT

> 4.7V. This provides the highest efficiency.

lower than that of INTV but higher than typical threshold

CC

3. EXTV connected to an external supply. If a 4.7V or

CC

voltagesofpowerMOSFETs, topreventthemfromturning

greater external supply is available, it may be used to

on without sufficient gate drive voltages.

power EXTV providing that the external supply is

CC

GenerallyforV >6V,aUVLOcanbesetthroughmonitoring

IN

sufficient for MOSFET gate drive requirements.

theV supplybyusingexternalvoltagedividersattheRUN

IN

4. EXTV connectedtoanoutput-derivedboostnetwork.

CC

pins from V to SGND. To design the voltage divider, note

IN

For 3.3V and other low voltage converters, efficiency

that both RUN pins have two levels of threshold voltages.

gains can still be realized by connecting EXTV to an

CC

The precision gate-drive-enable threshold voltage of 1.2V

output-derivedvoltagethathasbeenboostedtogreater

than 4.7V.

3876f

27

LTC3876

APPLICATIONS INFORMATION

can be used to set a V to turn on a channel’s switching.

this phase to ensure smooth soft-start or tracking. The

soft-start or tracking range is defined to be the voltage

range from 0V to 0.6V on the TRACK/SS pin. The total

soft-start time can be calculated as:

IN

If resistor dividers are used on both RUN pins, when V

IN

is low enough and both RUN pins are pulled below the

~0.8V threshold, the part will shut down all bias of INTV

CC

and DRV and be put in micropower shutdown mode.

CC

C_SS(µF)

1(µA)

t

= 0.6(V)•

_SS(SEC)

The RUN pins’ bias currents depend on the RUN voltages.

The bias current changes should be taken into account

when designing the external voltage divider UVLO circuit.

An internal proportional-to-absolute-temperature (PTAT)

pull-up current source (~2.±μA at 2±°C) is constantly con-

nected to this pin. When a RUN pin rises above 1.2V, the

corresponding channel’s TG and BG drives are turned on

and an additional 4μA temperature-independent pull-up

current is connected internally to the RUN pin. Pulling the

RUN pin to fall below 1.2V by more than an 80mV hyster-

esis turns off TG and BG of the corresponding channel,

and the additional 10μA pull-up current is disconnected.

When one particular channel is configured to track an

external supply, a voltage divider can be used from the

external supply to the TRACK/SS pin to scale the ramp

rate appropriately. Two common implementations are co-

incidentaltrackingandratiometrictracking.Forcoincident

tracking, make the divider ratio from the external supply

the same as the divider ratio for the differential feedback

voltage. Ratiometric tracking could be achieved by using

a different ratio than the differential feedback.

Note that the 1μA soft-start capacitor charging current is

still flowing, producing a small offset error. To minimize

this error, select the tracking resistive divider values to be

small enough to make this offset error negligible.

As voltage on a RUN pin increases, typically beyond 3V,

its bias current will start to reverse direction and flow into

the RUN pin. Keep in mind that neither of the RUN pins

can sink more than ±0μA; Even if a RUN pin may slightly

exceed 6V when sinking ±0μA, a RUN pin should never

be forced to higher than 6V by a low impedance voltage

source to prevent faulty conditions.

The LTC3876 allows the user to program how channel 1

VDDQ tracks an external power supply. Channel 2 VTT will

always track VDDQ and be equal to 0.± • VDDQ.

By selecting different resistors, the LTC3876 can achieve

different modes of tracking including the two in Figure 8a.

Toimplementthecoincidenttracking,connectanadditional

resistive divider to the external power supply and connect

its midpoint to the TRACK/SS pin of the slave channel.

The ratio of this divider should be the same as that of the

slave channel’s feedback divider shown in Figure 8b. In

this tracking mode, the external power supply must be set

higher than VDDQ. To implement the ratiometric tracking,

the master channel’s feedback divider can be also used

to provide TRACK/SS voltage for the slave channel, since

the additional divider, if used, should be of the same ratio

as the master channel’s feedback divider.

Stfꢁ-Sꢁarꢁ aId TrackiIg

The LTC3876 has the ability to either soft-start by itself

with a capacitor or track the output of another channel

or an external supply. Note that the soft-start or tracking

features are achieved not by limiting the maximum output

currentofthecontroller,butbycontrollingtheoutputramp

voltage according to the ramp rate on the TRACK/SS pin.

Whenchannel1isconfiguredtosoft-startbyitself,acapaci-

tor should be connected to its TRACK/SS pin. TRACK/SS

is pulled low until the RUN pin voltage exceeds 1.2V and

UVLO is released, at which point an internal current of

1μAchargesthesoft-startcapacitor, C , connectedtothe

TRACK/SS pin. Current-limit foldback is disabled during

SS

3876f

28

LTC3876

APPLICATIONS INFORMATION

So which mode should be programmed? While either

mode satisfies most practical applications, some trade-

offs exist. The ratiometric mode saves a pair of resistors,

but the coincident mode offers better output regulation.

to an external clock signal applied to the MODE/PLLIN pin.

The applied clock signal needs to be within ±30% of the

RT programmed frequency to ensure proper frequency

and phase lock. The clock signal levels should generally

comply to V

> 2V and V

< 0.±V. The MODE/

PLLIN(H)

PLLIN(L)

When the master channel’s output experiences dynamic

excursion (under load transient, for example), the slave

channel output will be affected as well. For better output

regulation, use the coincident tracking mode instead of

ratiometric.

PLLINpinhasaninternal600kpull-downresistortoensure

discontinuouscurrentmodeoperationifthepinisleftopen.

TheLTC3876usesthevoltagesonV andV pinsaswell

IN

OUT

as R to adjust the top gate on-time in order to maintain

T

phase and frequency lock for wide ranges of V , V

IN OUT

Phase aId FreqpeIcy SyIchrtIizaꢁitI

and R -programmed switching frequency f:

T

For applications that require better control of EMI and

switchingnoiseorhavespecialsynchronizationneeds,the

LTC3876 can synchronize the turn-on of the top MOSFET

V_OUT

t_ON

≈

V • f

IN

EXTERNAL

POWER

SUPPLY

EXTERNAL

POWER

SUPPLY

VDDQ

3876 F08a

TIME

CtiIcideIꢁ TrackiIg

Raꢁitmeꢁric TrackiIg

Figpre 8a. Twt DiffereIꢁ Mtdes tf ꢅpꢁnpꢁ TrackiIg

EXTERNAL

POWER

EXTERNAL

POWER

VDDQ

SUPPLY

R

R2

R1

R

FB2(1)

FB1(1)

FB2(1)

FB2(2)

TO

+

TO

TRACK/SS1

TO

OUTSENSE1

TO

V

+

–

TRACK/SS1

V

OUTSENSE1

FB1(1)

FB1(2)

TO

–

OUTSENSE1

3876 F08b

CtiIcideIꢁ TrackiIg Seꢁpn

Raꢁitmeꢁric TrackiIg Seꢁpn

Figpre 8b. Seꢁpn ftr CtiIcideIꢁ aId Raꢁitmeꢁric TrackiIg

3876f

29

LTC3876

APPLICATIONS INFORMATION

As the on-time is a function of the switching regulator’s

architecture. However, this process may understandably

lose phase and even frequency lock momentarily. For

relatively slow changes, phase and frequency lock can

still be maintained. For large load current steps with fast

slew rates, phase lock will be lost until the system returns

back to a steady-state condition (see Figure 9). It may

take up to several hundred microseconds to fully resume

the phase lock, but the frequency lock generally recovers

quickly, long before phase lock does.

output voltage, this output is measured by the V

OUT

to set the required on-time. Simply connecting V

to

the regulator’s local output point is preferable for most

applications, as the remotely regulated output point could

be significantly different from the local output point due to

linelosses,andlocaloutputversuslocalgroundistypically

the V

required for the calculation of t .

OUT

ON

However, there could be circumstances where this V

OUT

programmed on-time differs significantly different from

the on-time required in order to maintain frequency

and phase lock. For example, lower efficiencies in the

switching regulator can cause the required on-time to be

substantially higher than the internally set on-time (see

For light load conditions, the phase and frequency syn-

chronization depends on the MODE/PLLIN pin setting. If

theexternalclockisapplied, synchronizationwillbeactive

and switching in continuous mode. If MODE/PLLIN is tied

to INTV , it will operate in forced continuous mode at

CC

Efficiency Considerations). If a regulated V

is relatively

the R -programmed frequency. If the MODE/PLLIN pin is

OUT

T

low, proportionally there could be significant error caused

by the difference between the local ground and remote

ground, due to other currents flowing through the shared

ground plane.

tied to SGND, the LTC3876 will operate in discontinuous

mode at light load and switch into continuous conduction

attheR programmedfrequencyasloadincreases.TheTG

T

on-time during discontinuous conduction is intentionally

slightlyextended(approximately1.2timesthecontinuous

During dynamic transient conditions either in the line

voltage or load current (e.g., load step or release), the top

switch will turn on more or less frequently in response

to achieve faster transient response. This is the benefit

of the LTC3876’s controlled on-time, valley current mode

conduction on-time as calculated from V , V

and f) to

IN OUT

create hysteresis at the load-current boundary of continu-

ous/discontinuous conduction.

I

LOAD

CLOCK

INPUT

PHASE AND

FREQUENCY

LOCKED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

PHASE LOCK

RESUMED

PHASE AND

FREQUENCY

LOCK LOST

DUE TO FAST

LOAD STEP

FREQUENCY

RESTORED

QUICKLY

SW

V

OUT

3876 F09

Figpre 9. Phase aId FreqpeIcy ꢆtckiIg Behavitr DpriIg TraIsieIꢁ CtIdiꢁitIs

3876f

30

LTC3876

APPLICATIONS INFORMATION

Ifanapplicationrequiresverylow(approachingminimum)

on-time, the system may not be able to maintain its full

frequency synchronization range. Getting closer to mini-

mumon-time, itmayevenlosephase/frequencylockatno

load or light load conditions, under which the SW on-time

is effectively longer than TG on-time due to TG/BG dead

times. This is discussed further under Minimum On-Time,

Minimum Off-Time and Dropout Operation.

and before the bottom FET turns on, the SW node lingers

high for a longer duration due to a smaller peak inductor

current available in light load to pull the SW node low. As

a result of the sluggish SW node rising and falling edges,

the effective on-time is extended and not fully controlled

by the TG on-time. Closer to minimum on-time, this may

cause some phase jitter to appear at light load. As load

currentincrease,theedgesbecomesharper,andthephase

locking behavior improves.

MiIimpm ꢅI-Time, MiIimpm ꢅff-Time

aId Drtntpꢁ ꢅneraꢁitI

Theminimumon-timeoftheVTTchannelisfurtherlimited

by the fact that it must support negative current operation.

Both the TG to BG and BG to TG dead-time delays add

The minimum on-time is the smallest duration that

LTC3876’s TG (top gate) pin can be in high or “on” state.

It has dependency on the operating conditions of the

switching regulator, and is a function of voltages on the

TG-SW

(V OF TOP

GS

MOSFET)

DEAD-TIME

DELAYS

V and V

pins, as well as the value of external resistor

IN

OUT

BG

(V OF

GS

BOTTOM

MOSFET)

R . A minimum on-time of 30ns can be achieved when the

T

V

pin is tied to its minimum value of 0.6V while the V

OUT

IN

is tied to its maximum value of 38V. For larger values of

and/orsmallervaluesofV ,theminimumachievable

V

OUT

IN

I

L

0

on-timewillbelonger.Thevalleymodecontrolarchitecture

allows low on-time, making the LTC3876 suitable for high

step-down ratio applications.

NEGATIVE

INDUCTOR

CURRENT

IN FCM

V

IN

SW

3876 F10

The effective on-time, as determined by the SW node

pulse width, can be different from this TG on-time, as it

also depends on external components, as well as loading

conditionsoftheswitchingregulator.Oneofthefactorsthat

contributestothisdiscrepancyisthecharacteristicsofthe

power MOSFETs. For example, if the top power MOSFET’s

turn-on delay is much smaller than the turn-off delay,

the effective on-time will be longer than the TG on-time,

limiting the effective minimum on-time to a larger value.

DURING BG-TG DEAD TIME,

DURING TG-BG DEAD TIME,

THE RATE OF SW NODE DISCHARGE

WILL DEPEND ON THE CAPACITANCE

ON THE SW NODE AND INDUCTOR

CURRENT MAGNITUDE

NEGATIVE INDUCTOR CURRENT

WILL FLOW THROUGH TOP MOSFET’S

BODY DIODE TO PRECHARGE SW NODE

+

V

I

L

IN

–

L

SW

I

L

Light-load operation, in forced continuous mode, will

further elongate the effective on-time due to the dead

times between the “on” states of TG and BG, as shown in

Figure 10. During the dead time from BG turn-off to TG

turn-on,theinductorcurrentflowsinthereversedirection,

charging the SW node high before the TG actually turns

on. The reverse current is typically small, causing a slow

rising edge. On the falling edge, after the top FET turns off

TOTAL CAPACITANCE

ON THE SW NODE

Figpre 10. ꢆighꢁ ꢆtadiIg ꢅI-Time ExꢁeIsitI ftr Ftrced

CtIꢁiIptps Mtde ꢅneraꢁitI

3876f

31

LTC3876

APPLICATIONS INFORMATION

to the minimum on-time of 30ns as shown in Figure 10.

Each of the dead times are in the order of 3±ns. Therefore,

the VTT channel minimum on time should be no less than

100ns with 1±0ns preferred.

the other hand, imbalances in turn-on and turn-off delays

could reduce the effective minimum off-time.

The minimum off-time limit imposes a maximum duty

cycle of:

Incontinuousmodeoperation, theminimumon-timelimit

imposes a minimum duty cycle of:

D

= 1 – f • t

OFF(MIN)

MAX

where t

is the effective minimum off-time of the

OFF(MIN)

D

= f • t

MIN

ON(MIN)

switchingregulator.Reducingtheoperatingfrequencycan

alleviate the maximum duty cycle constraint.

where t

is the effective minimum on-time for the

ON(MIN)

switching regulator. As the equation shows, reducing the

operating frequency will alleviate the minimum duty cycle

constraint. If the minimum on-time that LTC3876 can

provide is longer than the on-time required by the duty

cycle to maintain the switching frequency, the switching

frequency will have to decrease to maintain the duty cycle,

but the output voltage will still remain in regulation. This is

generally more preferable to skipping cycles and causing

larger ripple at the output, which is typically seen in fixed

frequency switching regulators.

If the maximum duty cycle is reached, due to a drooping

input voltage for example, the output will drop out of

regulation.Theminimuminputvoltagetoavoiddropoutis:

V_OUT

D_MAX

V

=

IN(MIN)

At the onset of drop-out, there is a region of V of about

IN

±00mV that generates two discrete off-times, one being

the minimum off time and the other being an off-time that

is about 40ns to 60ns longer than the minimum off-time.

This secondary off-time is due to the extra delay in trip-

ping the internal current comparator. The two off-times

average out to the required duty cycle to keep the output

inregulation.TheremaybehigherSWnodejitter,apparent

especially when synchronized to an external clock, but the

output voltage ripple remains relatively small.

Forapplicationsthatrequirerelativelylowon-time, proper

cautionhastobetakenwhenchoosingthepowerMOSFET.

If the gate of the MOSFET is not able to fully turn on due

to insufficient on-time, there could be significant heat dis-

sipation and efficiency loss as a result of larger R

.

DS(ON)

This may even cause early failure of the power MOSFET.

The minimum off-time is the smallest duration of time

that the TG pin can be turned low and then immediately

turned back high. This minimum off-time includes the

time to turn on the BG (bottom gate) and turn it back off,

plus the dead-time delays from TG off to BG on and from

BG off to TG on. The minimum off-time that the LTC3876

can achieve is 90ns.

Faplꢁ CtIdiꢁitIs: CprreIꢁ ꢆimiꢁiIg aId ꢅvervtlꢁage

The maximum inductor current is inherently limited in a

current mode controller by the maximum sense voltage.

In the LTC3876, the maximum sense voltage is controlled

by the voltage on the V

pin. With valley current mode

RNG

control, the maximum sense voltage and the sense re-

sistance determine the maximum allowed inductor valley

current. The corresponding output current limit is:

The effective minimum off-time of the switching regulator,

or the shortest period of time that the SW node can stay

low,canbedifferentfromthisminimumoff-time.Themain

factor impacting the effective minimum off-time is the top

and bottom power MOSFETs’ electrical characteristics,

such as Qg and turn-on/off delays. These characteristics

can either extend or shorten the SW nodes’ effective

minimum off-time. Large size (high Qg) power MOSFETs

generally tend to increase the effective minimum off-time

due to longer gate charging and discharging times. On

V

1

2

I_LIMIT

=

^SENSE(MAX)+ • ΔI_L

R_SENSE

The current limit value should be checked to ensure that

> I . The current limit value should

I

LIMIT(MIN)

OUT(MAX)

be greater than the inductor current required to produce

maximum output power at the worst-case efficiency.

3876f

32

LTC3876

APPLICATIONS INFORMATION

Worst-case efficiency typically occurs at the highest V

and highest ambient temperature. It is important to check

for consistency between the assumed MOSFET junction

An additional small capacitor, C

, can be placed from

ITH2

IN

the ITH pin to SGND to attenuate high frequency noise.

Note this C

contributes an additional pole in the loop

ITH2

temperatures and the resulting value of I

the MOSFET switches.

which heats

gain therefore can affect system stability if too large. It

should be chosen so that the added pole is higher than

the loop bandwidth by a significant margin.

LIMIT

To further limit current in the event of a short circuit to

ground, the LTC3876 includes foldback current limiting.

If the output falls by more than ±0%, the maximum sense

voltage is progressively lowered, to about one-fourth of

its full value as the feedback voltage reaches 0V.

The regulator loop response can also be checked by

looking at the load transient response. An output current

pulse of 20% to 100% of full-load current having a rise

time of 1μs to 10μs will produce V_OUTand ITH voltage

transient-responsewaveformsthatcangiveasenseofthe

overall loop stability without breaking the feedback loop.

For a detailed explanation of OPTI-LOOP compensation,

refer to Application Note 76.

A feedback voltage exceeding 7.±% for VDDQ channel 1

and 10% for VTT channel 2 of the regulated target of

0.6V is considered as overvoltage (OV). In such an OV

condition, the top MOSFET is immediately turned off and

the bottom MOSFET is turned on indefinitely until the OV

condition is removed, i.e., the feedback voltage falling

back below the threshold by more than a hysteresis of

typical 1±mV. Current limiting is not active during an OV.

If the OV persists, and the BG turns on for a longer time,

the current through the inductor and the bottom MOSFET

mayexceedtheirmaximumratings,sacrificingthemselves

to protect the load.

Switching regulators take several cycles to respond to

a step in load current. When a load step occurs, V

OUT

immediately shifts by an amount equal to ∆I

• ESR,

LOAD

whereESRistheeffectiveseriesresistanceofC .∆I

OUT

LOAD

also begins to charge or discharge C , generating a

OUT

feedback error signal used by the regulator to return V

OUT

to its steady-state value. During this recovery time, V

can be monitored for overshoot or ringing that would

indicate a stability problem.

ꢅPTꢂ-ꢆꢅꢅP CtmneIsaꢁitI

ConnectingaresistiveloadinserieswithapowerMOSFET,

then placing the two directly across the output capacitor

and driving the gate with an appropriate signal generator

is a practical way to produce a realistic load step condi-

tion. The initial output voltage step resulting from the step

change in load current may not be within the bandwidth

of the feedback loop, so it cannot be used to determine

phasemargin.Theoutputvoltagesettlingbehaviorismore

relatedtothestabilityoftheclosed-loopsystem. However,

itisbettertolookatthefilteredandcompensatedfeedback

loop response at the ITH pin.

OPTI-LOOP^®compensation, through the availability of the

ITH pin, allows the transient response to be optimized for

a wide range of loads and output capacitors. The ITH pin

not only allows optimization of the control-loop behavior

butalsoprovidesaDC-coupledandAC-filteredclosed-loop

response test point. The DC step, rise time and settling

at this test point truly reflects the closed-loop response.

Assuming a predominantly 2nd order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin.

The external series R -C

filter at the ITH pin sets the

The gain of the loop increases with the R and the band-

ITH ITH1

ITH

dominant pole-zero loop compensation. The values can

be adjusted to optimize transient response once the final

PCBlayoutisdoneandtheparticularoutputcapacitortype

and value have been determined. The output capacitors

need to be selected first because their various types and

values determine the loop feedback factor gain and phase.

width of the loop increases with decreasing C

. If R

ITH1

ITH

isincreasedbythesamefactorthatC

isdecreased, the

ITH1

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

feedback loop. In addition, a feedforward capacitor, C ,

FF

3876f

33

LTC3876

APPLICATIONS INFORMATION

can be added to improve the high frequency response, as

Theload-releaseovershootatV causestheerrorampli-

OUT

shown in Figure 1. Capacitor C provides phase lead by

fieroutput,ITH,todropquickly.ITHvoltageisproportional

to the inductor current setpoint. A load transient will

result in a quick change of this load current setpoint, i.e.,

a negative spike of the first derivative of the ITH voltage.

FF

creating a high frequency zero with R which improves

FB2

the phase margin.

A more severe transient can be caused by switching in

loadswithlargesupplybypasscapacitors.Thedischarged

bypass capacitors of the load are effectively put in parallel

The LTC3876 uses a detect transient (DTR) pin to monitor

the first derivative of the ITH voltage, and detect the load-

release transient. Referring to the Functional Diagram, the

DTR pin is the input of a DTR comparator, and the internal

with the converter’s C , causing a rapid drop in V

.

OUT

No regulator can deliver current quick enough to prevent

this sudden step change in output voltage, if the switch

referencevoltagefortheDTRcomparatorishalfofINTV .

CC

connecting the C

to the load has low resistance and is

To use this pin for transient detection, ITH compensation

OUT

driven quickly. The solution is to limit the turn-on speed of

theloadswitchdriver.HotSwap™controllersaredesigned

specificallyforthispurposeandusuallyincorporatecurrent

limiting, short-circuit protection and soft starting.

needs an additional R resistor tied to INTV , and con-

ITH CC

nectsthejunctionpointofITHcompensationcomponents

, R and R to the DTR pin as shown in the

C

ITH1 ITH1

ITH2

Functional Diagram. The DTR pin is now proportional to

thefirstderivativeoftheinductorcurrentsetpoint,through

ꢆtad-Release TraIsieIꢁ DeꢁecꢁitI

the highpass filter of C

and (R

//R

ITH1 ITH2

).

ITH1

Astheoutputvoltagerequirementofstep-downswitching

The two R resistors establish a voltage divider from

ITH

regulators becomes lower, V to V

step-down ratio

INTV to SGND, and bias the DC voltage on DTR pin (at

IN

OUT

CC

increases, and load transients become faster, a major

steady-state load or ITH voltage) slightly above half of

challenge is to limit the overshoot in V during a fast

INTV . Compensation performance will be identical by

OUT

CC

load current drop, or “load-release” transient.

using the same C

and make R

//R

equal the

ITH1

ITH1 ITH2

R

ITH

as used in conventional single resistor OPTI-LOOP

Inductor current slew rate di /dt = V /L is proportional

L

compensation.ThiswillalsoprovidetheR-Ctimeconstant

needed for the DTR duration. The DTR sensitivity can be

adjusted by the DC bias voltage difference between DTR

to voltage across the inductor V = V – V . When

L

SW

OUT

the top MOSFET is turned on, V = V – V , inductor

L

IN

OUT

current ramps up. When bottom MOSFET turns on, V =

L

and half INTV . This difference could be set as low as

CC

V

– V

= –V , inductor current ramps down. At

very low V , the low differential voltage, V , across the

SW

OUT OUT

OUT

100mV, as long as the ITH ripple voltage with DC load

L

current does not trigger the DTR.

inductor during the ramp down makes the slew rate of the

inductor current much slower than needed to follow the

load current change. The excess inductor current charges

When load current suddenly drops, V

overshoots, and

OUT

ITH drops quickly. The voltage on the DTR pin will also

drop quickly, since it is coupled to the ITH pin through a

capacitor. If the load transient is fast enough that the DTR

up the output capacitor, which causes overshoot at V

.

OUT

If the bottom MOSFET could be turned off during the load-

release transient, the inductor current would flow through

the body diode of the bottom MOSFET, and the equation

can be modified to include the bottom MOSFET body

voltage drops below half of INTV , a load release event

CC

is detected. The bottom gate (BG) will be turned off, so

that the inductor current flows through the body diode

in the bottom MOSFET. This allows the SW node to drop

below PGND by a voltage of a forward-conducted silicon

diode. This creates a more negative differential voltage

diode drop to become V = –(V

+ V ). Obviously the

L

OUT

BD

benefit increases as the output voltage gets lower, since

V

BD

would increase the sum significantly, compared to a

(V – V ) across the inductor, allowing the inductor

SW

OUT

single V

only.

OUT

current to drop at a faster rate to zero, therefore creating

less overshoot on V

.

OUT

3876f

34

LTC3876

APPLICATIONS INFORMATION

2

The DTR comparator output is overridden by reverse

1. I R loss. These arise from the DC resistances of the

MOSFETs,inductor,currentsenseresistorandisthema-

jority of power loss at high output currents. In continu-

ous mode the average output current flows though the

inductor L, but is chopped between the top and bottom

MOSFETs. If the two MOSFETs have approximately the

inductor current detection (I ) and overvoltage (OV)

REV

+

condition. This means BG will be turned off when SENSE

–

is higher than SENSE (i.e., inductor current is positive),

as long as the OV condition is not present. When inductor

current drops to zero and starts to reverse, BG will turn

back on in forced continuous mode (e.g., the MODE/

same R

, then the resistance of one MOSFET can

DS(ON)

PLLIN pin tied to INTV , or an input clock is present),

simply be summed with the inductor’s DC resistances

CC

2

even if DTR is still below half INTV . This is to allow the

(DCR) and the board traces to obtain the I R loss. For

CC

inductor current to go negative to quickly pull down the

example,ifeachR

=8mΩ,R =±mΩ,andR

DS(ON) L SENSE

V

OUT

overshoot. Of course, if the MODE/PLLIN pin is set

= 2mΩ the loss will range from 1±mW to 1.±W as the

outputcurrentvariesfrom1Ato10A.Thisresultsinloss

from 0.3% to 3% a ±V output, or 1% to 10% for a 1.±V

to discontinuous mode (i.e., tied to SGND), BG will stay

off as inductor current reverse, as it would with the DTR

feature disabled.

output. Efficiency varies as the inverse square of V

OUT

for the same external components and output power

level. The combined effects of lower output voltages

and higher currents load demands greater importance

of this loss term in the switching regulator system.

Note that it is expected that this DTR feature will cause

additional loss on the bottom MOSFET, due to its body

diode conduction. The bottom FET temperature may be

higher with a load of frequent and large load steps. This

is an important design consideration. Experiments on the

demo board shows a 20°C increase when a continuous

100% to ±0% load step pulse train with ±0% duty cycle

and 100kHz frequency is applied to the output.

2. Transition loss. This loss mostly arises from the brief

amount of time the top MOSFET spends in the satura-

tion (Miller) region during switch node transitions. It

depends upon the input voltage, load current, driver

strength and MOSFET capacitance, among other fac-

tors, and can be significant at higher input voltages or

higher switching frequencies.

If not needed, this DTR feature can be disabled by tying

the DTR pin to INTV , or simply leave the DTR pin open

CC

so that an internal 2.±A current source will pull itself up

to INTV .

3. DRV current. This is the sum of the MOSFET driver

CC

and INTV control currents. The MOSFET driver cur-

CC

EfficieIcy CtIsideraꢁitIs

rents result from switching the gate capacitance of the

power MOSFETs. Each time a MOSFET gate is switched

from low to high to low again, a packet of charge dQ

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percentage efficiency

can be expressed as:

moves from DRV to ground. The resulting dQ/dt is a

CC

current out of DRV that is typically much larger than

CC

the controller I current. In continuous mode,

Q

I

= f • (Qg

+ Qg

),

GATECHG

(TOP)

(BOT)

%Efficiency = 100% – (L1% + L2% + L3% + ...)

where Qg

and Qg

are the gate charges of the

(TOP)

(BOT)

top and bottom MOSFETs, respectively.

where L1%, L2%, etc. are the individual losses as a per-

centage of input power. Although all dissipative elements

in the circuit produce power losses, several main sources

usuallyaccountformostofthelossesinLTC3876circuits:

Supplying DRV power through EXTV could save

CC

several percents of efficiency, especially for high V

IN

applications. Connecting EXTV to an output-derived

CC

3876f

35

LTC3876

APPLICATIONS INFORMATION

source will scale the V current required for the driver

VDDQ at 20A, a 0.7±V VTT 10A maximum average operat-

ing current with a VTT reference output (VTTR) capable of

supplying up to ±±0mA. (see Figure 11, LTC3876 demo

circuit 1631A)

IN

and controller circuits by a factor of (duty cycle)/(ef-

ficiency). Forexample, ina20Vto±Vapplication, 10mA

of DRV current results in approximately 2.±mA of V

CC

IN

current. This reduces the mid-current loss from 10%

The regulated channel 1 VDDQ output supply voltage is

determined by:

or more (if the driver was powered directly from V )

IN

to only a few percent.

R_FB2

R_FB1

⎛

⎝

⎞

⎠

4. C loss. The input capacitor filters large square-wave

VDDQ = 0.6V 1+

IN

input current drawn by the regulator into an averaged

DC current from the supply. The capacitor itself has

a zero average DC current, but square-wave-like AC

current flows through it. Therefore the input capacitor

must have a very low ESR to minimize the RMS current

loss on ESR. It must also have sufficient capacitance

to filter out the AC component of the input current to

prevent additional RMS losses in upstream cabling,

fuses or batteries. The LTC3876 2-phase architecture

improves the ESR loss.

Set VDDQ to 1.±V for DDRIII application. Using a 20k

resistor for R , the resulting R is 30k.

FB1

BF2

The regulated channel 2 VTT termination supply is differ-

entiallyreferencedtoaninternalresistordividerconnected

–

between the VDDQSNS and the V

. The resulting

OUTSENSE

differential VTT reference output (VTTR) is one-half VDDQ

which in this design example is 0.7±V. The VTT termina-

tion supply nominally regulates to 0.7±V and will track

any dynamic movement of the channel 1 VDDQ supply.

“Hidden” copper trace, fuse and battery resistance, even

at DC current, can cause a significant amount of efficiency

degradation, so it is important to consider them during

Theswitchingfrequencyforbothchannelsisprogrammed

by:

the design phase. Other losses, which include the C

OUT

41±50

R kꢁ = 4•

–2.2

ESR loss, bottom MOSFET’s body diode reverse-recovery

loss, and inductor core loss generally account for less

than 2% additional loss.

[

]

T

f kHz

[

]

For f=400kHz,R_T=102kꢁ.

Power losses in the switching regulator will reflect as

a higher than ideal duty cycle, or a longer on-time for a

constant frequency. This efficiency accounted on-time

can be calculated as:

The minimum on-time occurs for maximum V and

IN

should be greater than the typical minimum of 30ns with

adequate margin. The minimum on-time margin should

allow for device variability and the extension of effective

on-time at light load due to the dead times. The reason

for the on-time extension at light load is that the negative

inductor current causes the switch node to rise which

effectively adds to the on time. This is of limited concern

to the channel 1 VDDQ but is of greater concern to the

channel 2 VTT supply because it supplies significant

negative current. For the LTC3876 the minimum on-time

without any extension is 30ns, with driver dead times of

30ns. For strong negative currents in VTT the total dead

time is the total of the minimum on-time, plus both dead

times for 90ns. It is therefore recommended to keep the

minimum on-time greater than 100ns for channel 2 VTT

to assure PLL lock under all operating conditions.

t

≈ t /Efficiency

ON(IDEAL)

ON

Whenmakingadjustmentstoimproveefficiency, theinput

current is the best indicator of changes in efficiency. If you

make a change and the input current decreases, then the

efficiency has increased.

DesigI Examnle

The following design example is the DDR3 application

circuit as implemented on the standard LTC3876 QFN

demo board 1631A. This DC/DC step-down converter

design accommodates an input V range of 4.±V to 14V,

IN

with a VDDQ output of 1.±V and a VTT output of 0.7±V.

The DDRIII output channels are designed to produce 1.±V

3876f

36

LTC3876

APPLICATIONS INFORMATION

The minimum on-time for channel 1 VDDQ is:

For Figure 11, standard demo board the current limit is set

usingsenseresistors.TheV

isgroundedwhichresults

RNG

V_OUT

1.5V

in a maximum V

voltage across the R

resistor

t_ON(MIN)

=

= 268ns

SENSE

V

_IN(MAX)•f 14V •400kHz

of 30mV. If we assume ±0% over the nominal output of

20A this gives a starting point of 1mΩ for channel 1 VDDQ

and 2mΩ for channel 2 VTT.

The minimum on-time for channel 2 VTT is:

V_OUT

0.75V

_IN(MAX)•f 14V •400kHz

Channel 1 VDDQ current limit for 1mΩ R

.

SENSE

t_ON(MIN)

=

=134ns

V

V_SENSEΔI 30mV 7.12A

L

ILIMIT_VDDQ

=

+

=

+

= 33.5A

R_SENSE

2

1mꢁ

2

Set the channel 1 VDDQ inductor value L1 to give 3±%

ripple current at the maximum load to 20A for the maxi-

Channel 2 VTT current limit for 2mΩ R

.

SENSE

mum V of 14V using the adjusted operating frequency.

IN

V_SENSEΔI 30mV 3.78A

L

ILIMIT_VTT

=

+

=

+

=16.9A

⎛

⎞

⎟

⎠

V

OUT

V

IN(MAX)

OUT

R_SENSE

2

2mꢁ

2

L1=

1−

⎜

f I

)(

⎝

(

)

RIPPLE

In high power applications, DCR current sensing is often

⎛

⎞

⎟

⎠

1.5V

1.5

preferred to R in order to maximize efficiency. The

SENSE

=

1−

= 0.47μH

⎜

400kHz 35% t20A

14

inductor model is selected based on its inductor and DCR

value. The Würth WE7443330047 with a rated current of

20A, a saturation current of 47A and DCR of 0.8mΩ is

chosen for channel 1 VDDQ. The Würth WE7443340047

with a rated current of 19A, a saturation current of 32A

and DCR of 1.72mΩ is chosen for channel 2 VTT. The DCR

demo board design is Figure 13.

⎝

)

(

)

Set the channel 2 VTT inductor value L2 to give 3±% ripple

current at the maximum load to 10A for the maximum V

of 14V using the adjusted operating frequency.

IN

⎛

⎞

⎟

⎠

V

OUT

V

IN(MAX)

OUT

L1=

1−

⎜

In this design example V

was grounded to produce an

RNG

f I

(

)(

⎝

)

RIPPLE

internal default value of 30mV on V

.

SENSE

⎛

⎞

0.75V

0.75

Channel 1 VDDQ DCR Current limit:

=

1−

⎟ = 0.47μH

⎜

400kHz 37.5% t10A

14

)

(

)

⎝

⎠

V

R

ΔI

SENSE

L

ILIMIT

=

+

VDDQ

Choosetheneareststandardvalueof0.47μHforL2,which

will result in 37.±% ripple current.

2

30mV

7.12A

2

=

+

The resulting channel 1 VDDQ maximum ripple current is:

°

0.8mꢁ •(1+(100 C – 2± C)•0.4% / C)

⎛

⎞

1.5V

14V

= 32.4A

ΔI_L1=

1−

⎟ = 7.12A

⎜

400kHz 0.47μH

(

)

(

)

⎝

⎠

Channel 2 VTT DCR Current Limit:

The resulting channel 2 VTT maximum ripple current is:

V

R

ΔIL

SENSE

ILIMIT

=

+

VTT

⎛

⎞

2

0.75V

⎟

⎠

⎜

ΔI_L2=

1−

= 3.78A

30mV

3.78A

⎝

400kHz 0.47μH

14V

(

)

(

)

=

+

°

1.72mꢁ •(1+(100 C – 2± C)•0.4% / C)

2

= 1±.3A

3876f

37

LTC3876

APPLICATIONS INFORMATION

The DCR sense filter is designed using a simple RC filter

acrosstheinductor.IftheinductorvalueandDCRisknown,

choose a sense filter C and calculate filter resistance.

These numbers show that careful attention should be paid

to proper heat sinking when operating at higher ambient

temperatures.

Channel 1 DCR filter resistor R

:

Select C capacitors to give ample capacitance and RMS

DCR1

IN

ripple current rating. Consider worst-case duty cycles per

Figure 6. If operated at steady-state with SW nodes fully

interleaved, the two channels would generate not more

than 7.±A RMS at full load. In this design example, 2X

10μF2±VX±Rceramiccapacitorsareputinparalleltotake

the RMS ripple current with 330μF aluminum electrolytic

bulk capacitors for stability. For 10μF 1210 X±R ceramic

capacitors, try to keep the ripple current less than 3A RMS

through each device. The bulk capacitor is chosen for

RMSratingpersimulationwiththecircuitmodelprovided.

L1

DCR•C_DCR0.8mꢁ •0.1μF

Channel 2 DCR filter resistor R

0.47μH

R_DCR1

=

= 5.9k

:

DCR2

L1

0.47μH

R_DCR1

=

= 2.74k

DCR•C_DCR1.72mꢁ •0.1μF

The external N-channel MOSFETs are chosen based

on current capability and efficiency. The Renesas

RJK030±DBP(R

=13mΩ(maximum),C

=1±0pF,

DS(ON)

MILLER

J(MAX)

The power supply output capacitor’s C

are chosen

OUT

VGS = 4.±V, V

= 3V, θ = 40°C/W, T

= 1±0°C)

MILLER

JA

for a low ESR. For channel 1 VDDQ, the output capacitor

SANYO2R±TPE330M9, hasanESRof9mΩwhichresults

in 4.±mΩ for two in parallel. For channel 2 VTT, the output

capacitor SANYO 2R±TPE330M9, has an ESR of 9mΩ.

is chosen for the top MOSFET (main switch). The Renesas

RJK0330DBP (R

= 3.9mΩ(maximum), V = 4.±V,

DS(ON)

GS

θ

= 40°C/W, T

=1±0°C) is chosen for the bottom

JA

J(MAX)

MOSFET (synchronous switch).The power dissipation for

each MOSFET can be calculated for V = 14V and typical

The output ripple for each channel is given as:

IN

T =12±°C.

J

ΔVDDQ(RIPPLE) = ΔI

(ESR)

L(MAX)

The power dissipation for V = 14V and T =12±°C for

IN

J

= (7.12A) • (4.±mΩ) = 32mV

ΔVTT(RIPPLE) = ΔI (ESR)

the top MOSFET is:

L(MAX)

1.5V

14V

20A ²1+0.4% 125°C–25°C

(

0.013ꢁ +

= (3.78A) • (9mΩ) = 34mV

P_TOP

=

(

)

(

)

(

A0Ato10AloadstepinVDDQwillcauseanoutputchange

of up to:

⎛

⎞

⎛

⎜

⎞

20A

2.5ꢁ

1.2ꢁ

2

⎟

⎠

14V

150pF

(

+

400kHz

(

)

(

)

⎜

2

5.3V –3V 3V

⎝

⎠

ΔVDDQ(STEP) = ΔI

4±mV

(ESR) = 10A • 0.004±mΩ =

LOAD

= 0.78W+0.17W = 0.95W

The power dissipation for V = 14V and T =12±°C for

IN

J

A 0A to ±A load step in VTT will cause an output change

of up to:

2X bottom MOSFETs is:

2

⎛

⎞

14V –1.5V 20A

ΔVTT(STEP) = ΔI

(ESR) = ±A • 0.009mΩ = 4±mV

LOAD

P_BOT

=

⎟

⎜

14V

2X

⎠

⎝

Optional 100μF ceramic output capacitors are included

to minimize the effect of ESL in the output ripple and to

improve load step response.

1+0.4% 125°C–25°C

(

0.0039ꢁ

)

(

)

= 0.4875W

(

)

The resulting junction temperatures for ambient tempera-

ture T = 7±°C are:

A

T

= 7±°C + (0.9±W)(40°C/W) = 113°C

= 7±°C + (0.97±W)(40°C/W) = 94.±°C

J(TOP)

J(BOT)

3876f

38

LTC3876

APPLICATIONS INFORMATION

PCB ꢆaytpꢁ Checklisꢁ

• The top N-channel MOSFETs of the two channels have

to be located within a short distance from (preferably

<1cm) each other with a common drain connection at

The printed circuit board layout is illustrated graphically

in Figure 12. Use the following checklist to ensure proper

operation of the LTC3876:

C . Do not attempt to split the input decoupling for the

IN

two channels as it can result in a large resonant loop.

• Amultilayerprintedcircuitboardwithdedicatedground

planes is generally preferred to reduce noise coupling

and improve heat sinking. The ground plane layer

should be immediately next to the routing layer for the

power components, e.g., MOSFETs, inductors, sense

resistors, input and output capacitors etc.

• Connect the input capacitor(s), C , close to the power

IN

MOSFETs.ThiscapacitorprovidestheMOSFETtransient

spike current. Connect the drain of the top MOSFET as

close as possible to the (+) plate of the ceramic portion

of input capacitors C . Connect the source of the bot-

IN

tom MOSFET as close as possible to the (–) terminal

• Keep SGND and PGND separate. Upon finishing the

layout, connect SGND and PGND together with a single

PCBtraceunderneaththeICfromtheSGNDpinthrough

the exposed PGND pad to the PGND pin.

of the same ceramic C capacitor(s). These ceramic

IN

capacitor(s) bypass the high di/dt current locally, and

both top and bottom MOSFET should have short PCB

trace lengths to minimize high frequency EMI and

prevent MOSFET voltage stress from inductive ringing.

• All power train components should be referenced to

PGND; all components connected to noise-sensitive

• The path formed by the top and bottom N-channel

pins, e.g., ITH, RT, TRACK/SS and V , should return

MOSFETs, and the C capacitors should have short

RNG

IN

to the SGND pin. Keep PGND ample, but SGND area

compact.Useamodified“starground”technique:alow

impedance, large copper area central PCB point on the

same side of the as the input and output capacitors.

leads and PCB trace. The (–) terminal of output capaci-

tors should be connected close to the (–) terminal of

C , but away from the loop described above. This is

IN

to achieve an effect of Kevin (4-wire) connection to the

input ground so that the “chopped” switching current

will not flow through the path between the input ground

andtheoutputground,andcausecommonmodeoutput

voltage ripple.

• Placepowercomponents,suchasC ,C ,MOSFETs,

IN OUT

D and inductors, in one compact area. Use wide but

B

shortest possible traces for high current paths (e.g.,

V , V , PGND etc.) to this area to minimize copper

IN OUT

loss.

• Several smaller sized ceramic output capacitors, C

,

OUT

can be placed close to the sense resistors and before

• Keep the switch nodes (SW1,2), top gates (TG1,2) and

boost nodes (BOOST1,2) away from noise-sensitive

small-signal nodes, especially from the opposite

channel’s voltage and current sensing feedback pins.

These nodes have very large and fast moving signals

and therefore should be kept on the “output side” of

the LTC3876 (power-related pins are toward the right

hand side of the IC), and occupy minimum PC trace

area. Usecompactswitchnode(SW)planestoimprove

cooling of the MOSFETs and to keep EMI down. If DCR

sensing is used, place the top filter resistor (R1 only in

Figure ±) close to the switch node.

the rest bulk output capacitors.

+

–

• ThefiltercapacitorbetweentheSENSE andSENSE pins

should always be as close as possible to these pins.

Ensure accurate current sensing with Kevin (4-wire)

connections to the soldering pads from underneath

the sense resistors or inductor. A pair of sense traces

should be routed together with minimum spacing.

R

, if used, should be connected to the inductor

SENSE

on the noiseless output side, and its filter resistors

+

–

close to the SENSE /SENSE pins. For DCR sensing,

however, filter resistor should be placed close to the

inductor, and away from the SENSE /SENSE pins, as

its terminal is the SW node.

+

–

3876f

39

LTC3876

APPLICATIONS INFORMATION

V

IN

4.±V TO 14V

C

IN1

C

IN2

180μF

2.2Ω

10μF

w2

w3

LTC3876

1μF

V

IN

–

SENSE1

SENSE2

0.1μF

+

SENSE1

SENSE2

0.1μF

BOOST1

TG1

BOOST2

TG2

±.9K

2.74K

L1

MT1

MB1

MT2

MB2

L1

0.47μH

DB1

DB2

0.47μH

VTT

0.7±V

±10A

VDDQ

1.±V

20A

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

OUT2

C

INTV

C

OUT3

100μF

OUT1

CC

OUT4

330μF

100μF

1μF

4.7μF

w2

BG1

BG2

PGND

1Ω

VDDQSNS

1μF

30.1k

+

–

VTTRVCC

VTTSNS

V

OUTSENSE1

20k

VTTR

±±0mA

V

OUTSENSE1

100k

2.2μF

PGOOD

0.01μF

PGOOD

TRACK/SS1

ITH1

VTTR

120pF

470pF

ITH2

1±00pF

100k

4700pF

12.7k

13.7k

C

: SANYO 16SVP180M

IN1

MURATA GRM32DR61E106KA12L

IN2:

OUT2 OUT4

, C

,C

: SANYO 2R±TPE330M9

: MURATA GRM31CR60J107ME39L

DTR1

CVCC

V

OUT1 OUT3

RNG1

RNG2

DB1, DB2: CENTRAL SEMI CMDSH-3

L1: WÜRTH 7443330047

L2: WÜRTH 7443340047

PHASMD

RT

SGND

MODE/PLLIN

MT1, MB2: INFINEON BSC0901NS

MB1: INFINEON BSC010NE2LS

MT2: INFINEON BSC0±0NE2LS

RUN

CLKOUT

3876 F11a

100

90

80

70

60

±0

40

4.±

V

= 12V

IN

DDQ

= 1.±V

4.0

3.±

DISCONTINUOUS

MODE

3.0

2.±

2.0

1.±

1.0

0.±

0

FORCED

CONTINUOUS

MODE

0.1

1

10

LOAD CURRENT (A)

3876 F11b

Figpre 11. DesigI Examnle: ꢀ.5V ꢁt 1ꢀV ꢂInpꢁ, VDDQ 1.5V/20A aId VTT 0.75V/ 10A ꢅpꢁnpꢁ,

ꢀ00kHz, DCR, Sꢁen-DtwI CtIverꢁer

• Keepsmall-signalcomponentsconnectednoise-sensi-

into these pins. If the LTC3876 can be placed on the

bottom side of a multilayer board, use ground planes

to isolate from the major power components on the top

side of the board, and prevent noise coupling to noise

sensitive components on the bottom side.

+

–

+

tivepins(giveprioritytoSENSE /SENSE ,V

/

OUTSENSE1

pins) on the left hand

side of the IC as close to their respective pins as pos-

–

V

, V , RT, ITH, V

OUTSENSE1

FB2

RNG

sible. This minimizes the possibility of noise coupling

3876f

40

LTC3876

APPLICATIONS INFORMATION

–

SENSE2

PGOOD2

BOOST2

+

SENSE2

VTTSNS

C

B2

L2

R

SENSE2

TG2

SW2

BG2

V

OUT2

LTC3876

D

B2

MT2

C

ITH1(2)

DRV

CC2

MB2

R

ITH1(2)

ITH2

EXTV

CC

R

INTVCC

C

ITH2(2)

INTV

C

CC

CERAMIC

C

VCC

INTVCC

V

RNG2

C

OUT2

PHASMD

MODE/PLLIN

CLKOUT

SGND

PGND

LOCALIZED

SGND TRACE

V

C

GND

IN

VIN

+

RT

C

V

IN

R

T

R

VIN

CERAMIC

V

RNG1

C

DRVCC

C

ITH2(1)

OUT1

DRV

CC1

R

ITH1(1)

ITH2(1)

D

B1

ITH1

MT1

R

MB1

C

ITH1(1)

BG1

SW1

TG1

TRACK/SS1

R

SENSE1

V

OUT1

C

SS1

R

FB2(1)

+

–

L1

V

OUTSENSE1

C

B1

R

FB1(1)

BOOST1

PGOOD1

V

OUTSENSE1

+

SENSE1

RUN1

DTR1

–

3876 F12

Figpre 12. RectmmeIded PCB ꢆaytpꢁ Diagram

• Place the resistor feedback divider R , R close to • PlacetheceramicdecouplingcapacitorC

between

FB1 FB2

pins for channel 1, or

INTVCC

+

–

V

and V

the INTV pin and SGND and as close as possible to

OUTSENSE1

CC

pin for channel 2, so that the feedback voltage

the IC.

FB2

tapped from the resistor divider will not be disturbed by

noise sources. Route remote sense PCB traces (use a

pair of wires closely together for differential sensing in

channel 1) directly to the terminals of output capacitors

for best output regulation.

• Place the ceramic decoupling capacitor C

close

DRVCC

to the IC, between the combined DRV

PGND.

pins and

CC1,2

• Filter the V input to the LTC3876 with an RC filter.

IN

Place the filter capacitor close to the V pin.

IN

• Place decoupling capacitors C

next to the ITH and

ITH2

• If vias have to be used, use immediate vias to connect

componentstotheSGNDandPGNDplanesofLTC3876.

Use multiple large vias for power components.

SGND pins with short, direct trace connections.

• Use sufficient isolation when routing a clock signal into

the MODE/PLLIN pin or out of the CLKOUT pin, so that

the clock does not couple into sensitive pins.

3876f

41

LTC3876

APPLICATIONS INFORMATION

• Floodallunusedareasonalllayerswithcopper.Flooding

with copper will reduce the temperature rise of power

components. ConnectthecopperareastoDCrailsonly,

e.g., PGND.

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins.

PCB ꢆaytpꢁ DebpggiIg

Only after each controller is checked for its individual

performance should both controllers be turned on at

the same time. It is helpful to use a DC-±0MHz current

probe to monitor the current in the inductor while testing

the circuit. Monitor the output switching node (SW pin)

to synchronize the oscilloscope to the internal oscillator

output CLKOUT, or external clock if used. Probe the actual

outputvoltageaswell. Checkforproperperformanceover

the operating voltage and current range expected in the

application.

Thecapacitorplacedacrossthecurrentsensingpinsneeds

to be placed immediately adjacent to the pins of the IC.

This capacitor helps to minimize the effects of differential

noise injection due to high frequency capacitive coupling.

If problems are encountered with high current output

loadingatlowerinputvoltages,lookforinductivecoupling

The frequency of operation should be maintained over

the input voltage range. The phase should be maintained

from cycle to cycle in a well designed, low noise PCB

implementation. Variation in the phase of SW node pulse

can suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PCB layout if

regulator bandwidth optimization is not required.

between C , top and bottom MOSFET components to the

IN

sensitive current and voltage sensing traces.

Inaddition,investigatecommongroundpathvoltagepickup

between these components and the SGND pin of the IC.

High SwiꢁchiIg FreqpeIcy ꢅneraꢁitI

At high switching frequencies there may be an increased

sensitivity to noise. Special care may need to be taken to

prevent cycle-by-cycle instability and/or phase-lock jitter.

First, carefullyfollowtherecommendedlayouttechniques

toreducecouplingfromthehighswitchingvoltage/current

traces. Additionally, use low ESR and low impedance X±R

or X7R ceramic input capacitors: up to ±μF per Amp. of

load current may be needed. If necessary, increase ripple

sense voltage by increasing sense resistance value and

A particularly difficult region of operation is when one

controller channel is turning on (right after its current

comparator trip point) while the other channel is turning

off its top MOSFET at the end of its on-time. This may

cause minor phase-lock jitter at either channel due to

noise coupling.

V

RNG

setting, to improve noise immunity.

3876f

42

LTC3876

APPLICATIONS INFORMATION

V

IN

4.±V TO 14V

C

IN1

C

IN2

180μF

2.2Ω

10μF

w2

w3

LTC3876

1μF

V

IN

–

SENSE1

SENSE2

0.1μF

+

SENSE1

SENSE2

0.1μF

2.2Ω

0.1μF

BOOST1

TG1

BOOST2

TG2

±.9k

2.74k

MT1

MB1

MT2

MB2

L1

0.47μH

L1

0.47μH

DB1

DB2

VTT

0.9V

±10A

VDDQ

1.8V

20A

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

CC

C

OUT2

C

INTV

C

OUT1

CC

OUT4

330μF

OUT3

100μF

330μF

100μF

1μF

4.7μF

w2

BG1

BG2

PGND

1Ω

VDDQSNS

1μF

30.1k

+

–

VTTRVCC

VTTSNS

V

OUTSENSE1

20k

VTTR

±±0mA

V

OUTSENSE1

100k

2.2μF

PGOOD

0.01μF

PGOOD

TRACK/SS1

ITH1

VTTR

120pF

470pF

ITH2

1±00pF

100k

4700pF

12.7k

13.7k

C

: SANYO 16SVP180M

IN1

IN2

: MURATA GRM32DR61E106KA12L

,C

: SANYO 2R±TPE330M9

: MURATA GRM31CR60J107ME39L

DTR1

CVCC

OUT2 OUT4

, C

V

RNG1

V

OUT1 OUT3

RNG2

DB1, DB2: CENTRAL SEMI CMDSH-3

L1: WÜRTH 7443330047

L2: WÜRTH 7443340047

PHASMD

RT

SGND

MODE/PLLIN

MT1, MB2: INFINEON BSC0901NS

MB1: INFINEON BSC010NE2LS

MT2: INFINEON BSC0±0NE2LS

RUN

CLKOUT

3876 F13a

100

90

80

70

60

±0

40

4.±

4.0

3.±

V

= 12V

IN

VDDQ = 1.8V

DISCONTINUOUS

MODE

3.0

2.±

2.0

1.±

1.0

0.±

0

FORCED

CONTINUOUS

MODE

0.1

1

10

LOAD CURRENT (A)

3876 F13b

Figpre 13. ꢀ.5V ꢁt 1ꢀV ꢂInpꢁ, VDDQ 1.8V/20A aId VTT 0.9V/ 10A ꢅpꢁnpꢁ, ꢀ00kHz, DCR, Sꢁen-DtwI CtIverꢁer

3876f

43

LTC3876

APPLICATIONS INFORMATION

V

IN

4.±V TO 28V

C

IN2

C

IN1

100μF

10μF

2.2Ω

w3

LTC3876

1μF

1nF

V

IN

100Ω

–

SENSE1

SENSE2

1nF

100Ω

0.1μF

+

SENSE1

SENSE2

0.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

0.67μH

L2

0.68μH

R32

0.003Ω

DB1

DB2

VDDQ

1V

20A

R31

0.002Ω

VTT

0.±V

±10A

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

OUT2

C

INTV

C

OUT3

100μF

OUT1

CC

OUT4

330μF

100μF

1μF

4.7μF

w2

BG1

BG2

PGND

1Ω

VDDQSNS

1μF

30.1k

+

–

VTTRVCC

VTTSNS

V

OUTSENSE1

20k

VTTR

±±0mA

V

OUTSENSE1

100k

2.2μF

PGOOD

0.1μF

PGOOD

TRACK/SS1

ITH1

VTTR

C

: NICHICON UCJ1H101MCL1GS

: MURATA GRM32ER71H106K

IN1

220pF

1000pF

2700pF

C

IN2

OUT2 OUT4

OUT1 OUT3

DB1, DB2: CENTRAL SEMI CMDSH-3

L1: WÜRTH 74431±067

,C

: SANYO 2R±TPE330M9

ITH2

, C

: MURATA GRM31CR60J107ME39L

220pF

18.2k

2.±±k

L2: WÜRTH 744311068

DTR1

CVCC

MT1: INFINEON BSC03±N04LS

MB1, MB2: INFINEON BSC011N03LS

MT2: VISHAY SiR462DP

V

RNG1

V

RNG2

113k

20k

20±k

PHASMD

RT

SGND

MODE/PLLIN

RUN

CLKOUT

3876 F14a

4.0

100

90

80

70

60

±0

40

V

= 12V

IN

VDDQ = 1V

3.±

3.0

2.±

2.0

1.±

1.0

0.±

0

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

0.1

1

LOAD CURRENT (A)

10

3876 F14b

Figpre 1ꢀ. ꢀ.5V ꢁt 28V ꢂInpꢁ, VDDQ 1V/20A aId VTT 0.50V/ 10A ꢅpꢁnpꢁ, 200kHz, R_SENSE, Sꢁen-DtwI CtIverꢁer

3876f

44

LTC3876

APPLICATIONS INFORMATION

V

IN

4.±V TO 38V

C

IN1

IN2

100μF

2.2Ω

10μF

w4

LTC3876

1μF

V

IN

–

SENSE1

SENSE2

1nF

+

SENSE1

SENSE2

0.1μF

2.2Ω

0.1μF

DB2

2.49Ω

1.1±Ω

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

0.82μH

L2

0.82μH

R32

0.002Ω

R31

DB1

VTT

0.6V

±10A

VDDQ

1.2V

20A

0.002Ω

SW1

SW2

DRV

CC1

DRV

CC2

EXTV

CC

C

OUT2

330μF

C

INTV

C

OUT1

CC

OUT4

OUT3

100μF

330μF

1μF

4.7μF

w4

w2

BG1

BG2

PGND

1Ω

VDDQSNS

1μF

20k

+

–

VTTRVCC

VTTSNS

V

OUTSENSE1

20k

VTTR

±±0mA

V

OUTSENSE1

100k

2.2μF

PGOOD

0.01μF

PGOOD

TRACK/SS1

ITH1

VTTR

180pF

±60pF

ITH2

±60pF

86.6k

1800pF

13.7k

4.22k

C

: NICHICON UCJ1H101MCL1GS

IN1

, C , C : MURATA GRM32ER71H106K

IN3 IN4 IN±

, C

: SANYO 2R±TPE330M9

DTR1

CVCC

OUT1 OUT2 OUT±

, C : MURATA GRM31CR60J107ME39L

V

RNG1

V

OUT4 OUT7

RNG2

118k

DB1, DB2: CENTRAL SEMI CMDSH-3

L1: WÜRTH 74431±067

L2: WÜRTH 744311068

PHASMD

RT

SGND

MODE/PLLIN

MT1: INFINEON BSC03±N04LS

MB1 MB2: INFINEON BSC011N03LS

MT2: VISHAY SiR462DP

RUN

CLKOUT

3876 F1±a

±.0

4.±

4.0

3.±

3.0

2.±

2.0

1.±

1.0

0.±

0

100

V

= 12V

IN

VDDQ = 1.2V

90

80

70

60

±0

40

DISCONTINUOUS

MODE

FORCED

CONTINUOUS

MODE

0.1

1

10

LOAD CURRENT (A)

3876 F1±b

Figpre 15. ꢀ.5V ꢁt 38V ꢂInpꢁ, VDDQ 1.2V/20A aId VTT 0.ꢃ0V/ 10A ꢅpꢁnpꢁ, 200kHz, R_SENSE, Sꢁen-DtwI CtIverꢁer

3876f

45

LTC3876

PACKAGE DESCRIPTION

Please refer ꢁt hꢁꢁn://www.liIear.ctm/desigIꢁttls/nackagiIg/ ftr ꢁhe mtsꢁ receIꢁ nackage drawiIgs.

UHF Package

38-ꢆead Plasꢁic QFN (5mm × 7mm)

(Reference LTC DWG # 0±-08-1701 Rev C)

0.70 p 0.0±

±.±0 p 0.0±

±.1± ± 0.0±

4.10 p 0.0±

3.1± ± 0.0±

3.00 REF

PACKAGE

OUTLINE

0.2± p 0.0±

0.±0 BSC

±.± REF

6.10 p 0.0±

7.±0 p 0.0±

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.30 TYP OR

0.3± s 4±o CHAMFER

0.7± p 0.0±

3.00 REF

±.00 p 0.10

37 38

0.00 – 0.0±

0.40 p0.10

PIN 1

TOP MARK

1

2

(SEE NOTE 6)

±.1± ± 0.10

±.±0 REF

7.00 p 0.10

3.1± ± 0.10

(UH) QFN REF C 1107

0.200 REF 0.2± p 0.0±

R = 0.12±

TYP

R = 0.10

TYP

0.±0 BSC

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

±. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3876f

46

LTC3876

PACKAGE DESCRIPTION

Please refer ꢁt hꢁꢁn://www.liIear.ctm/desigIꢁttls/nackagiIg/ ftr ꢁhe mtsꢁ receIꢁ nackage drawiIgs.

FE Package

38-ꢆead Plasꢁic TSSꢅP (ꢀ.ꢀmm)

(Reference LTC DWG # 0±-08-1772 Rev C)

Exntsed Pad VariaꢁitI AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

2.74

REF (.252)

(.108)

0.315 0.05

BSC

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0s – 8s

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) TSSOP REV C 0910

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3876f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

47

LTC3876

TYPICAL APPLICATION

ꢀ.5V ꢁt 5.5V ꢂInpꢁ, VDDQ 1.5V/20A aId VTT 0.75V/ 10A ꢅpꢁnpꢁ, 1.2MHz, R_SENSE, Sꢁen-DtwI CtIverꢁer

V

IN

4.±V TO ±.±V

C

IN2

C

IN1

180μF

10μF

2.2Ω

w3

LTC3876

1μF

V

IN

100Ω

–

SENSE1

SENSE2

1nF

649Ω

1nF

100Ω

+

SENSE1

SENSE2

0.1μF

BOOST1

TG1

BOOST2

TG2

MT1

MB1

MT2

MB2

L1

0.18μH

L2

0.22μH

R32

0.003Ω

R31

0.002Ω

DB1

DB2

VTT

0.7±A

±10A

VDDQ

1.±V

20A

SW1

SW2

2.2Ω

DRV

CC1

DRV

CC2

EXTV

C

OUT2

C

INTV

V

IN

C

OUT3

100μF

OUT1

CC

OUT4

330μF

100μF

1μF

4.7μF

w2

BG1

BG2

PGND

1Ω

VDDQSNS

1μF

30.1k

+

–

VTTRVCC

VTTSNS

V

OUTSENSE1

20k

VTTR

±±0mA

V

OUTSENSE1

100k

39pF

2.2μF

PGOOD

0.01μF

PGOOD

TRACK/SS1

ITH1

VTTR

120pF

ITH2

1±0pF

32.4k

270pF

68.1k

33.2k

C

: SANYO 16SVP180M

IN1

IN2

: MURATA GRM32DR61E106KA12L

, C

: SANYO 2R±TPE330M9

: MURATA GRM31CR60J107ME39L

OUT2 OUT4

, C

DTR1

CVCC

OUT1 OUT3

V

RNG1

V

RNG2

DB1, DB2: CENTRAL SEMI CMDSH-3

L1: TOKO FCUL1040-H-R18M

L2: TOKO FDUE0640-R22M

PHASMD

RT

SGND

MODE/PLLIN

MT1, MB1, MB2:INFINEON BSC0901NS

MT2: INFINEON BSC0±0NE2LS

RUN

CLKOUT

3876 TA02

RELATED PARTS

PART NUMBER DESCRꢂPTꢂꢅN

CꢅMMENTS

LTC3776

Dual, 2-Phase, No R

™, Synchronous Controller for 2.7±V ≤ V ≤ 9.8V, V

Tracks One-Half V , 4mm × 4mm QFN-24, SSOP-24

OUT REF

SENSE

IN

DDR/QDR Memory Termination

LTC3717

LTC3718

LTC3831

LTC3413

LTC3833

High Power DDR Memory Termination Regulator

4V ≤ V ≤ 36V, V

Tracks One-Half V or V

IN

OUT IN REF

Bus Termination Supply for Low Voltage V

1.±V ≤ V , Supplies ±V Gate Drive for N-Channel MOSFETs

IN

High Power DDR Memory Termination Regulator

3A Monolithic DDR Memory Termination Regulator

V Tracks One-Half V or V , 3V ≤ V ≤ 8V

OUT IN REF IN

2.2±V ≤ V ≤ ±.±V, TSSOP-16E

IN

Fast Controller On-Time, High Frequency Synchronous

Step-Down Controller with Diff Amp

Up to 2MHz Operating Frequency 4.±V < V < 38V, 0.6V < V

3mm × 4mm QFN-20, TSSOP-20E

< ±.±V,

IN

OUT

LTC3838

Dual, Fast, Accurate Step-Down DC/DC Controller with

Differential Output Sensing

Up to 2MHz Operating Frequency 4.±V < V < 38V, 0.6V < V

±mm × 7mm QFN-38, TSSOP-38E

IN

OUT

LTC3634

LTC3617

LTC3618

1±V Dual 3A Monolithic DDR Memory Termination

6A Monolithic DDR Memory Termination

3.6V ≤ V ≤ 1±V, 4mm × ±mm QFN-28, TSSOP-28E

IN

2.2±V ≤ V ≤ ±.±V, 3mm × ±mm QFN-24

IN

Dual 3A Monolithic DDR Memory Termination

2.2±V ≤ V ≤ ±.±V, 4mm × 4mm QFN-24, TSSOP-24

IN

3876f

LT 1111 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 9±03±-7417

48

●

(408) 432-1900 FAX: (408) 434-0±07 www.linear.com


型号：	LTC3876EFE#PBF
厂家：	Linear
描述：	LTC3876 - Dual DC/DC Controller for DDR Power with Differential VDDQ Sensing and ±50mA VTT Reference; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C 双倍数据速率开关光电二极管
文件：	总48页 (文件大小：624K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3876EFE#PBF [Linear]

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