LTC3877 [Linear]
PolyPhase Step-Down Synchronous Slave Controller with Sub-Milliohm DCR Sensing;
| 型号： | LTC3877 |
| 厂家： | 
Linear |
| 描述： | PolyPhase Step-Down Synchronous Slave Controller with Sub-Milliohm DCR Sensing |
| 文件： | 总22页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3874-1
PolyPhase Step-Down
Synchronous Slave Controller with
Sub-Milliohm DCR Sensing
FeaTures
DescripTion
The LTC®3874-1 is a dual PolyPhase® current mode syn-
chronous step-down slave controller. It enables high cur-
rent,multiphaseapplicationswhenpairedwithacompanion
master controller by extending the phase count. Compat-
ible master controllers include the LTC3884-1, LTC3774,
LTC3875,LTC3877andLTC3866.TheLTC3874-1employs
a unique architecture that enhances the signal-to-noise
ratio of the current sense signal, allowing the use of sub-
milliohm DC resistance power inductors to maximize
efficiency while reducing switching jitter. Its peak current
mode architecture allows for accurate phase-to-phase
current sharing even for dynamic loads.
n
Phase Extender for High Phase Count Voltage Rails
Operates with Power Blocks, DrMOS or External
Gate Drivers and MOSFETs
Accurate Phase-to-Phase Current Sharing
Sub-Milliohm DCR Current Sensing
n
n
n
n
n
n
n
n
Phase-Lockable Fixed Frequency 250kHz to 1MHz
Immediate Response to Master IC's Fault
Up to 12-Phase Operation
Wide V Range: 4.5 to 38V
IN
V
Range : Up to 3.5V (LOWDCR Pin High)
OUT
Up to 5.5V (LOWDCR Pin Low)
n
n
n
n
Proprietary Current Mode Control Loop
Programmable CCM/DCM Operation
Programmable Phase Shift Control
24-Lead (4mm × 4mm) QFN Package
Effectivelyworkingwithamastercontroller,theLTC3874-1
supports all the programmable features as well as fault
protection.
L, LT, LTC, LTM, Linear Technology, the Linear logo, PolyPhase and µModule are registered
trademarks of Analog Devices, Inc. All other trademarks are the property of their respective
owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6144194, 6177787,
6580258, 5408150.
applicaTions
n
High Current Distributed Power Systems
n
Telecom, Datacom and Storage Systems
n
Intelligent Energy Efficient Power Regulation
Typical applicaTion
High Efficiency, 4-Phase 1.8V/120A Step-Down Supply
V
IN
7V TO 14V
4-Phase Efficiency and Power
V
IN
LTC3874-1
PWM0
PWM1
Loss vs Output Current, Sub-
(0.29mΩ DCR)
0.215µH
(0.29mΩ DCR)
0.215µH
V
OUT
Milliohm DCR vs Traditional
DCR
1.8V
DrMOS
DrMOS
120A
649Ω
649Ω
100µF
×3
100µF
×3
470µF
×2
470µF
×2
100
95
90
85
80
75
70
20
17
14
11
8
0.22µF
0.22µF
V
V
f
= 12V
+
IN
OUT
= 425kHz
+
= 1.8V
+
–
+
–
SW
I
I
I
I
SENSE0
SENSE0
SENSE1
SENSE1
CCM
EFFICIENCY
LTC3884-1
RUN0
RUN1
RUN0
INTV
CC
RUN1
V
CC0
4.7µF
FAULT0
FAULT1
PGOOD0
FAULT0
FAULT1
V
CC1
PHASMD
POWER LOSS
1.8V
MODE0 LDWDCR
+
+
V
V
SENSE0
SENSE1
PGOOD1
MODE1
TH0
ILIM
0.29mΩ
1.5mΩ
0.29mΩ
1.5mΩ
I
I
TH0
100k
5
I
I
FREQ
GND
TH1
SYNC
TH1
SYNC
2
0
10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
38741 TA01a
38741 TA01b
REFER TO LTC3884-1 DATA SHEET
FOR MASTER SETUP
PIN NOT USED IN THIS CIRCUIT: EXTV
CC
38741f
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For more information www.linear/LTC3874-1
LTC3874-1
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V ............................................................. −0.3V to 40V
IN
V
, V .................................................... −0.3V to 6V
CC0 CC1
+
–
+
–
I
, I
, I
, I
.....−0.3V to INTV
SENSE0 SENSE0 SENSE1 SENSE1 CC
24 23 22 21 20 19
+
EXTV , INTV , RUN0, RUN1 .................... −0.3V to 6V
CC
CC
I
I
1
2
3
4
5
6
18
17
V
V
SENSE0
CC0
IN
MODE0, MODE1, ILIM, LOWDCR,
–
SENSE0
PHASMD, FREQ .................................... −0.3V to INTVcc
RUN0
RUN1
16 INTV
CC
25
GND
SYNC, FAULT0, FAULT1, I , I ......... −0.3V to INTVcc
15 EXTV
TH0 TH1
CC
–
I
I
INTV Peak Output Current................................100mA
14
13
V
CC1
SENSE1
CC
+
PWM1
SENSE1
Operating Junction Temperature Range
7
8
9 10 11 12
(Note 2).................................................. −40°C to 125°C
Storage Temperature Range .................. −65°C to 150°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 125°C, θ = 46.9°C/W, θ = 4.5°C/W
JMAX
JA
JC_BOT
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
http://www.linear.com/product/LTC3874-1#orderinfo
LEAD FREE FINISH
LTC3874EUF-1#PBF
LTC3874IUF-1#PBF
TAPE AND REEL
PART MARKING*
38741
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTC3874EUF-1#TRPBF
LTC3874IUF-1#TRPBF
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
38741
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
38741f
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For more information www.linear.com/LTC3874-1
LTC3874-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN0,1 = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Input Voltage Range
Output Voltage Range
4.5
38
V
IN
LOWDCR = INTV (Note 3)
3.5
5.5
V
V
OUT
CC
LOWDCR = 0V
I
Q
Input DC Supply Current
Normal Operation
Shutdown
V
V
= 3.3V
= 0V
4.6
1.8
mA
mA
RUN0,1
RUN0,1
V
UVLO
Undervoltage Lockout Threshold
V
V
Falling
Rising
3.5
3.8
V
V
INTVCC
INTVCC
Control Loop
l
I
I
Pins Bias Current
V
V
< (V
> (V
– 3.3V)
– 3.3V)
0.15
1
0.4
3
µA
µA
ISENSE0,1
SENSE
ISENSE0,1
ISENSE0,1
INTVCC
INTVCC
V
Maximum Current Sense Threshold
(Table 3)
ILIM = INTV , LOWDCR = INTV
ISENSE0,1
ISENSE(MAX)
l
l
l
l
,
CC
26.8
14.5
65
28.8
16
30.8
17.5
79
mV
mV
mV
mV
CC
V
= 1.2V, V = 2.18V
ITH
ILIM = 0V, LOWDCR = INTV
ISENSE0,1
,
CC
V
= 1.2V, V = 2.18V
ITH
ILIM = INTV , LOWDCR = 0V,
72
CC
V
= 1.2V, V = 2.18V
ITH
ISENSE0,1
ILIM = 0V, LOWDCR = 0V,
= 1.2V, V = 2.18V
33
40
47
V
ISENSE0,1
ITH
PWM Outputs
l
l
PWM
PWM Output High Voltage
PWM Output Low Voltage
PWM Output Current in Hi-Z State
I
I
= 500µA
= –500µA
V
CC
– 0.2
V
V
µA
LOAD
LOAD
0.2
5
–5
t
Minimum On-Time
(Note 4)
60
ns
ON(MIN)
INTV Regulator
CC
V
V
V
V
V
Internal V Voltage No Load
6V < V < 38V
5.25
4.5
5.5
0.5
4.7
50
5.75
2
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I
= 0mA to 20mA
CC
LDO
CC
l
EXTV Switchover Voltage
V Ramping Positive (Note 5)
EXTVCC
V
EXTVCC
CC
EXT
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
100
mV
mV
LDO
CC
CC
EXTV Hysteresis
300
LDOHYS
CC
Oscillator and Phase-Locked Loop
l
f
f
I
PLL SYNC Range
250
9
1000
11
kHz
kHz
µA
RANGE
NOM
Nominal Frequency
V
FREQ
= 0.9V
500
10
Frequency Setting Current
FREQ
-
-
SYNC to Ch0 Phase Relationship Based on
PHASMD = 0
180
60
Deg
Deg
Deg
Deg
θ
θ
θ
SYNC
0
the Falling Edge of SYNC and Rising Edge of PHASMD = 1/3 • INTV
CC
CC
PWM0
PHASMD = 2/3 • INTV
PHASMD = INTV
120
90
CC
SYNC to Ch1 Phase Relationship Based on
PHASMD = 0
0
Deg
Deg
Deg
Deg
θ
SYNC
1
the Falling Edge of SYNC and Rising Edge of PHASMD = 1/3 • INTV
300
240
270
CC
CC
PWM1
PHASMD = 2/3 • INTV
PHASMD = INTV
CC
Digital Inputs RUN0, RUN1, MODE0, MODE1, FAULT0, FAULT1, LOWDCR
l
l
V
IH
V
IL
Input High Threshold Voltage
Input Low Threshold Voltage
2.0
V
V
1.4
38741f
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For more information www.linear/LTC3874-1
LTC3874-1
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
conditions in conjunction with board layout, the related package thermal
impedance and other environmental factors. The junction temperature T
J
is calculated from the ambient temperature T and power dissipation PD
A
according to the following formula: T = T + (PD • 46.9°C/W)
J
A
Note 2: The LTC3874-1 is tested under pulsed load conditions such
Note 3: Output voltage is set and controlled by master controller in
multiphase operations.
that T ≈ T . The LTC3874E-1 is guaranteed to meet specifications
J
A
from 0°C to 85°C junction temperature. Specifications over the –40°Ç
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3874I-1 is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
Note 4: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
MAX
Considerations in the Applications Information section).
Note 5: EXTV is enabled only if V is higher than 6.5V.
CC
IN
Typical perForMance characTerisTics (TA = 25°C unless otherwise specified)
Efficiency vs Output Current
and Mode (4-Phase with Master
Controller LTC3884-1)
Efficiency vs Output Current
and Mode (4-Phase with Master
Controller LTC3884-1)
Efficiency and Power Loss vs
Output Current (4-Phase with
Master Controller LTC3884-1)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
20
17
14
11
8
V
V
f
= 12V
= 1.8V
= 425kHz
IN
OUT
SW
CCM
EFFICIENCY
V
= 12V
IN
V
V
V
f
= 12V
IN
OUT
SW
= 1.2V
OUT
SW
= 1.8V
f
= 425kHz
= 425kHz
POWER LOSS
0.29mΩ
1.5mΩ
0.29mΩ
1.5mΩ
CCM
DCM
5
CCM
DCM
2
0
10 20 30 40 50 60 70 80 90 100 110 120
0
10 20 30 40 50 60 70 80 90 100 110 120
0
10 20 30 40 50 60 70 80 90 100 110 120
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
38741 G1
38741 G2
38741 G3
Load Step (Forced Continuous
Mode) 4-Phase with Master
Controller LTC3884-1
Load Step (Discontinuous
Conduction Mode) 4-Phase with
Master Controller LTC3884-1
I
I
LOAD
LOAD
50A/DIV
50A/DIV
I
I
L(MASTER0)
10A/DIV
(MASTER0)
10A/DIV
I
(SLAVE0)
I
L(SLAVE0)
10A/DIV
10A/DIV
V
V
OUT
OUT
AC-COUPLED
AC-COUPLED
50mV/DIV
50mV/DIV
38741 G04
38741 G05
50µs/DIV
50µs/DIV
V
= 12V
IN
V
= 12V
IN
V
= 1.2V
OUT
V
= 1.2V
OUT
I
0A TO 20A
LOAD
I
0A TO 20A
LOAD
38741f
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For more information www.linear.com/LTC3874-1
LTC3874-1
Typical perForMance characTerisTics (TA = 25°C unless otherwise specified)
Start-Up Into a Prebiased Load
2-Phase Operation LTC3884-1
and LTC3874-1
Inductor Current at Light Load
RUN
ALL RUN PINS
TIED TOGETHER
2V/DIV
FORCED
CONTINUOUS
MODE
5A/DIV
V
OUT
IN CCM
DISCONTINUOUS
CONDUCTION
MODE
500mV/DIV
5A/DIV
38741 G06
38741 G07
1µs/DIV
2ms/DIV
V
V
12V
OUT
V
OUT
= 12V
IN
IN
= 1.2V
V
= 1.2V
Current Sense Threshold vs
Quiescent Current vs Temperature
without EXTVCC
INTVCC Line Regulation
ITH Voltage
6
5
4
3
100
80
6
5
4
3
2
1
0
LOWDCR = L, RANGE = H
60
LOWDCR = L,
RANGE = L
40
20
LOWDCR = H,
RANGE = L
0
LOWDCR = H,
RANGE = H
–20
–40
0
0.5
1
1.5
(V)
2
2.5
3
–50
0
50
100
150
0
10
20
INPUT VOLTAGE (V)
30
40
TEMPERATURE (°C)
V
ITH
38741 G10
38741 G8
38741 G9
Maximum Current Sense Threshold
vs Common Mode Voltage
(LOWDCR = INTVCC, VITH = 2.18V)
Undervoltage Lockout Threshold
(INTVCC vs Threshold)
Quiescent Current vs Input
Voltage without EXTVCC
6
4.1
30
25
20
15
10
5
I
= INTV
CC
LIM
RISING
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
5
4
3
FALLING
I
= GND
LIM
0
45
125
0
10
20
30
40
0.5 1.0 1.5 2.0
–50
–5
95
0
2.5 3.0 3.5
INPUT VOLTAGE (V)
TEMPERATURE (°C)
V
COMMON MODE VOLTAGE (V)
ISENSE
38741 G13
38741 G12
38741 G11
38741f
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For more information www.linear/LTC3874-1
LTC3874-1
pin FuncTions
+
+
I
/I
(Pin 1/Pin 6): Current Sense Compara-
is a three-state compatible output. To support three-state
mode, an external resistor divider is typically used from
CC0 CC1
SENSE0 SENSE1
tor Inputs. The (+) inputs to the current comparators are
normally connected to DCR sensing networks.
V
/V
to ground.
−
−
I
/I
(Pin 2/Pin 5): Current Sense Compara-
V
/V (Pin 18/Pin 14): PWM Pin Driver Supplies.
SENSE0 SENSE1
CC0 CC1
tor Inputs. The (−) inputs to the current comparators are
Decouple this pin to GND with a capacitor (0.1μF) to an
connected to the outputs.
external supply or tie this pin to the INTV pin. PWM0/
PWM1 signal swing is from ground to V /V
CC
.
CC0 CC1
RUN0/RUN1 (Pin 3/Pin 4): Enable Run Inputs. Logic high
on the RUN pin enables the corresponding channel.
EXTV (Pin15):ExternalPowerInputtoanInternalSwitch
CC
Connected to INTV . The switch closes and supplies the
CC
MODE0/MODE1(Pin 24/Pin 7): DCM/CCM Mode Control
Pins. Each channel runs in forced continuous mode if the
modepinislogichigh. Thereisaninternal500kpull-down
resistor on the mode pin. To select discontinuous conduc-
tion mode, float or pull down the mode pin.
IC power, bypassing the internal low dropout regulator,
whenever EXTV is higher than 4.7V and V is greater
CC
IN
than 7V. Do not exceed 6V on this pin.
INTV (Pin16):Internal5.5VRegulatorOutput.Thecontrol
CC
circuits are powered from this voltage. Decouple this pin
to GND with a minimum of 4.7μF low ESR tantalum or
ceramic capacitor.
I
/I (Pin 23/Pin 8): Current Control Threshold. Each
TH0 TH1
associatedchannel’scurrentcomparatortrippingthreshold
increases with its I voltage. These pins must be con-
nected to the master controller’s I pins.
TH
V (Pin 17): Main Input Supply. Decouple this pin to GND
TH
IN
with a capacitor (0.1μF to 1μF).
FREQ(Pin 9): Frequency Set Pin. There is a precision
10µA current flowing out of this pin. A resistor to ground
sets a voltage which in turn programs the frequency. This
pin sets the default switching frequency when there is no
externalclockontheSYNCpin.Seetheapplicationsection
for detailed information.
FAULT0/FAULT1 (Pin 21/Pin 20): Master Controller Fault
Inputs. Connect these pins to the master chip fault indica-
tor pins to respond to the fault signals from the master
controller. When a FAULT pin is floating or low, the PWM
pin of the corresponding channel is in three-state. There
is an internal 500k pull-down resistor on each FAULT pin.
ILIM(Pin 10): Current Comparators Sense Voltage Limit.
Program a DC voltage at this pin to set the maximum cur-
rent sense threshold for the current comparators.
LOWDCR(Pin 22): Sub-milliohm DCR Current Sensing
Enable Pin. There is an internal 500k pull-up resistor
between the LOWDCR pin and INTV . Floating or pull-
CC
SYNC(Pin11):ExternalClockSynchronizationInput.Ifan
externalclockispresentatthispin,theswitchingfrequency
will be synchronized to the falling edge of external clock.
Tie this pin to GND if not used.
ing this pin logic high will enable the sub-milliohm DCR
current sensing. Pulling this pin logic low will disable the
sub-milliohm DCR current sensing.
GND(Exposed Pad Pin 25): Ground. Connect this pad,
through vias, to a solid ground plane under the circuit.
The sources of the bottom N-channel MOSFETs, the (–)
PHASMD (Pin 12): Phase Set Pin. This pin determines the
relative phases between the external clock on pin SYNC
and the internal controllers. See Table 1 in the Operation
section for details.
terminal of C
, and the (–) terminal of C should
INTVCC
IN
connect to this ground plane as closely as possible to
the IC. All small-signal components and compensation
components should also connect to this ground plane.
PWM0/PWM1(Pin 19/Pin 13): (Top) Gate Signal Outputs.
This signal goes to the PWM or top gate input of the exter-
nal driver, integrated driver MOSFET or power block. This
38741f
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For more information www.linear.com/LTC3874-1
LTC3874-1
One of Two Channels (CH0) Shown
FuncTional block DiagraM
10µA
SYNC
PHASMD
EXTV
CC
4.7V
V
IN
FREQ
SYNC/PHASE
DETECT
V
IN
+
C
IN
PLL-SYNC
5.5V
REG
OSC
S
R
INTV
CC
Q
I
I
–
5K
CMP
REV
+
–
+
V
CC0
ON
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
REV
UVLO
FAULTB
FCNT
PWM0
I
DrMOS
LIM
I
RANGE SELECT
HI: 1:1
LO: 1:1.8
LIM
1
5k
+
C
OUT0
DC
AMP
RUN
SLOPE
COMPENSATION
+
–
I
I
SENSE0
SENSE0
INTV
CC
UVLO
38741 BD
1
60k
INTV
CC
1.7V
REF
I
TH0
SGND
LOWDCR MODE0
RUN0
FAULT0
38741f
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For more information www.linear/LTC3874-1
LTC3874-1
operaTion
Main Control Loop
current mode architectures, the current limit threshold is
still a function of the inductor peak current and the DCR
The LTC3874-1 is a constant frequency, LTC proprietary
currentmodestep-downslavecontrollerforparallelopera-
tionwithmastercontrollers.Duringnormaloperation,each
top MOSFET is turned on when the clock for that channel
sets the RS latch, and turned off when the main current
value, andcanbeaccuratelysetwiththeILIMandI pins.
TH
INTV /EXTV Power
CC
CC
PowerformostinternalcircuitryisderivedfromtheINTV
CC
pin. When the EXTV pin is left open or tied to a voltage
comparator, I
, resets the RS latch. The peak inductor
CMP
TH
CC
CMP
less than 4.7V, an internal 5.5V linear regulator supplies
INTV power from V . If EXTV is taken above 4.7V
current at which I
resets the RS latch is controlled by
thevoltageontheI pin, whichistheoutputofthemaster
CC
IN
CC
and V is higher than 7V, the 5.5V regulator is turned off
controller. When the load current increases, the master
IN
and an internal switch is turned on connecting EXTV .
controller increases the I voltage, which in turn causes
CC
TH
EXTV canbeappliedbeforeV .UsingtheEXTV allows
the peak current in the corresponding slave channels to
increase, until the average inductor current matches the
new load current. After the top MOSFET has turned off,
the bottom MOSFET is turned on until the beginning of
the next cycle in Continuous Conduction Mode (CCM) or
until the inductor current starts to reverse, as indicated
CC
IN
CC
the INTV power to be drawn from an external source.
CC
Start-Up and Shutdown (RUN0, RUN1)
The two channels of the LTC3874-1 can be independently
shut down using the RUN0 and RUN1 pins. Pulling either
of these pins below 1.4V shuts down the main control
circuitsforthatchannel. Duringshutdown, thePWMpinis
in three-state mode. Pulling either of these pins above 2V
enables the controller. The RUN0/1 pins are actively pulled
by the reverse current comparator I , in Discontinuous
REV
ConductionMode(DCM).TheLTC3874-1slavecontrollers
DO NOT regulate the output voltage but regulate the cur-
rent in each channel for current sharing with the master
controllers. Output voltage regulation is achieved through
thevoltagefeedbackcontrolloopinthemastercontrollers.
down until the INTV voltage passes the undervoltage
CC
lockout threshold of 3.8V. For multiphase operation, the
RUN0/1 pins must be connected together and driven by
the RUN pins on the master controller. Because a large
RC filter in the LTC3874-1 needs to settle during initializa-
Sub-Milliohm DCR Current Sensing
The LTC3874-1 employs a unique architecture to enhance
the signal-to-noise ratio that enables it to operate with
a small sense signal of a sub-milliohm value inductor
DCR to improve power efficiency and reduce jitter due to
switching noise.
tion, the RUN pins can only be pulled up 4ms after V
IN
is ready. Do not exceed the Absolute Maximum Rating of
6V on these pins.
The start-up of each channel’s output voltage V
is
OUT
controlled by the master controller. After the RUN pins are
released, the master controller drives the output based on
the programmed delay time and rise time. The slave con-
Floating or pulling the LOWDCR pin high will enable sub-
milliohm DCR current sensing. The LTC3874-1 can sense
a DCR value as low as 0.2mΩ with careful PCB layout.
The proprietary signal processing circuit provides a 14dB
signal-to-noise ratio improvement. As with conventional
trollerLTC3874-1followstheI voltagesetbythemaster
TH
to supply the same current to the output during startup.
38741f
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LTC3874-1
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Light Load Current Operation (Discontinuous
Conduction Mode, Continuous Conduction Mode)
The SYNC pin is used to synchronize switching frequency
betweenthemasterandslavecontrollers.Inputcapacitance
ESR requirements and efficiency losses are substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A two stage, single output voltage implementa-
tion can reduce input path power loss by 75% and radi-
cally reduce the required RMS current rating of the input
capacitor(s).
The LTC3874-1 can operate either in discontinuous con-
duction mode or forced continuous conduction mode.
To select forced continuous mode, tie the MODE pin to a
DC voltage above 2V (e.g., INTV ). To select discontinu-
CC
ous conduction mode, tie the MODE pin to a DC voltage
below 1.4V (e.g., GND).In forced continuous mode,
the inductor current is allowed to reverse at light loads
or under large transient conditions. The peak inductor
current is determined by the voltage on the I pin. In
TH
Single Output Multiphase Operation
this mode, the efficiency at light loads is lower than in
discontinuous mode. However, continuous mode has the
advantages of lower output ripple and less interference
with audio circuitry. When the MODE pin is connected to
GND, the LTC3874-1 operates in discontinuous mode at
light loads. At very light loads, the current comparator
The LTC3874-1 is configured for single output multiphase
converters with a master controller by making these con-
nections
• Tie all the I pins of paralleled channels together for
TH
current sharing between masters and slaves;
I
may remain tripped for several cycles and force the
CMP
• Tie all SYNC or PLLIN pins of paralleled channels to-
gether or tie the master chip’s CLKOUT pin to the slave
chip’sSYNCpinforswitchingfrequencysynchronization
among channels.
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). This mode provides higher
light load efficiency than forced continuous mode and the
inductor current is not allowed to reverse. There is a 500k
pull-down resistor internally connected to the MODE pin.
If the MODE0/1 pins are left floating, both channels are in
discontinuous conduction mode by default.
• Tie all the RUN pins of paralleled channels together for
startup and shutdown at the same time.
• Tie the fault indictor pin of the master controller if avail-
able to the FAULT pin of the slave controller for fault
protection.
Multichip Operations (PHASMD and SYNC Pins)
The PHASMD pin determines the relative phases between
theinternalchannelsaswellastheexternalclocksignalon
SYNC pin as shown in Table 1. The phases tabulated are
relative to zero degree phase being defined as the falling
edge of the clock on SYNC pin.
• TheLTC3874-1MODEpincanbetiedtothemasterchip
PGOOD pin for start-up control. During soft-start, the
LTC3874-1operatesinDCMmode. Whenthesoft-start
intervalisdone, theLTC3874-1operatesinCCMmode.
Examples of single output multiphase converters are
shown in Figure 1.
Table 1
PHASMD
CHANNEL 0 PHASE
CHANNEL 1 PHASE
GND
180°
60°
0°
The Typical Application on the first page of this data sheet
is a basic LTC3874-1 application circuit configured as a
slavecontroller.Inparalleledoperation,thecurrentsensing
scheme and circuit parameters in the LTC3874-1 have to
be the same as the master controller to achieve balanced
current sharing between masters and slaves. Input and
output capacitors are selected based on RMS current
rating, ripple and transient specs.
1/3 INTV
300°
240°
270°
CC
2/3 INTV or Float
120°
90°
CC
INTV
CC
38741f
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3 PHASE OPERATION
3 PHASE + 1 PHASE OPERATION
CH0
CH1
120°
CH1
CH2
180°
LTC3884-1
SYNC
CH0
60°
LTC3874-1
SYNC
CH1
0°
240°
0°
300°
LTC3866
CLKOUT
LTC3874-1
SYNC
PHASMD = 1/3 INTV
PHASMD = 1/3 INTV
CC
CC
4 PHASE OPERATION
4 PHASE OPERATION
CH1
CH2
180°
CH0
90°
LTC3874-1
SYNC
CH1
CH1
CH2
180°
LTC3884-1
SYNC
CH0
90°
LTC3874-1
SYNC
CH1
0°
270°
0°
270°
LTC3774
CLKOUT
PHASMD = FLOAT
PHASMD = GND
PHASMD = INTV
CC
6 PHASE OPERATION
6 PHASE OPERATION
CH1
CH2
120°
LTC3774
CLKOUT
CH0
240°
LTC3874-1
SYNC
CH1
CH0
180°
CH1
300°
CH1
CH2
180°
LTC3884-1
SYNC
CH0
60°
LTC3874-1
SYNC
CH1
CH0
120°
LTC3874-1
SYNC
CH1
0°
60°
0°
300°
240°
LTC3874-1
SYNC
PHASMD = INTV
PHASMD = GND
PHASMD = 2/3 INTV
PHASMD = 1/3 INTV
PHASMD = 2/3 INTV
CC
CC
CC
CC
38741 F01
Figure 1. Multiphase Operation
Frequency Selection and Phase-Locked Loop
(FREQ and SYNC Pins)
flowing out of the FREQ pin, so the user can program the
controller’s switching frequency with a single resistor to
GND. A curve is provided later in the application section
showing the relationship between the voltage on the FREQ
pin and switching frequency (Figure 5). A phase-locked
loop (PLL) is integrated in the LTC3874-1 to synchronize
the internal oscillator to an external clock source on the
SYNC pin. The PLL loop filter network is integrated inside
the LTC3874-1. The phase-locked loop is capable of lock-
ing to any frequency within the range of 250kHz to 1MHz.
The frequency setting resistor should always be present
to set the controller’s initial switching frequency before
locking to the external clock.
The selection of switching frequency is a trade-off be-
tween efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET
switching losses, but requires larger inductance and/or
capacitance to maintain low output ripple voltage. The
switching frequency of the LTC3874-1 controllers can be
selected using the FREQ pin. If the SYNC pin is not be-
ing driven by an external clock source, the FREQ pin can
be used to program the controller’s operating frequency
from 250kHz to 1MHz. There is a precision 10µA current
38741f
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Current Limit Programming
Table 3. Current Sense Threshold vs ITH Voltage (continued)
CURRENT SENSE THRESHOLD (mV)
To match the master controller current limit, each channel
of the LTC3874-1 can be programmed separately with
the ILIM and LOWDCR pins. The 4-level logic input pin
ILIM setup summary is shown in Table 2. When ILIM is
grounded, both channels are set to be low current range.
LOWDCR = H
LOWDCR = L
I
(V)
RANGE = H
RANGE = L
10.5
RANGE = H
RANGE = L
26.2
TH
1.58
1.51
1.45
1.38
18.9
17.7
16.6
15.5
47.2
44.3
41.5
38.6
9.9
24.6
9.2
23.0
When ILIM is tied to INTV , both channels are set to be
CC
8.6
21.4
high current range.
Which setting should be used? For balanced load current
sharing, use the same current range setting as in the
master controller. Note, the LTC3874-1 does not have
+
−
I
and I
Pins
SENSE
SENSE
+
–
I
and I
are the inputs to the current com-
SENSE
SENSE
active clamping circuit on I pin for peak current limit
TH
parators. When the LOWDCR pin is high, their common
–
and over current protection. Over current protection relies
mode input voltage range is 0V to 3.5V. I
should
SENSE
on the master controller to drive the I pin not to exceed
TH
be connected directly to V
of the master controller.
OUT
+
the clamped voltage. The relationship between the current
I
is connected to an R • C filter with time constant
SENSE
sense threshold and I voltage can be found in Table 3.
TH
one-fifth of L/DCR of the output inductor. Care must be
takennottofloatthesepinsduringnormaloperation.Filter
components, especially capacitors, must be placed close
to the LTC3874-1, and the sense lines should run close
together to a Kelvin connection underneath the current
senseelement.TheLTC3874-1isdesignedtobeusedwith
a sub-milliohm DCR value; without proper care, parasitic
resistance, capacitance and inductance will degrade the
current sense signal integrity, making the programmed
current limit unpredictable. In Figure 2, resistor R must be
placedclosetotheoutputinductorandcapacitorCcloseto
the IC pins to prevent noise coupling to the sense signal.
Table 2. ILIM vs Range
CHANNEL 0
CURRENT LIMIT
CHANNEL 1
CURRENT LIMIT
ILIM
GND
Range Low
Range High
Range Low
Range High
Range Low
Range Low
Range High
Range High
1/3 INTV
CC
2/3 INTV or Float
CC
INTVcc
Table 3. Current Sense Threshold vs ITH Voltage
CURRENT SENSE THRESHOLD (mV)
LOWDCR = H
LOWDCR = L
The LTC3874-1 can also be used like any conventional
current mode controller by disabling the LOWDCR pin,
I
(V)
RANGE = H
RANGE = L
18.1
RANGE = H
81.3
RANGE = L
45.1
TH
2.40
2.33
2.26
2.20
2.18
2.13
2.06
1.99
1.92
1.85
1.79
1.72
1.68
32.5
31.4
30.2
29.1
28.8
28.0
26.8
25.7
24.6
23.4
22.3
21.1
20.4
connecting it to ground. An RC filter can be used to sense
17.4
78.4
43.6
+
the output inductor signal and connects to the I
16.8
75.6
42.0
SENSE
pin. Its time constant, R • C, should equal to L/DCR of
the output inductor. By pulling down the LOWDCR pin,
the current limit increases by 2.5 times. See Table 3 for
details. In these applications, the common mode operat-
16.2
72.7
40.4
16.0
72.0
40.0
15.5
69.9
38.8
14.9
67.1
37.3
+
–
ing voltage range of I
, I
is from 0V to 5.5V.
SENSE SENSE
14.3
64.2
35.7
13.6
61.4
34.1
Table 4. Output Voltage Range vs LOWDCR Pin
13.0
58.5
32.5
LOWDCR
Low
OUTPUT VOLTAGE
12.4
55.7
30.9
0V to 5.5V
0V to 3.5V
11.7
52.8
29.4
High
11.3
51.0
28.4
38741f
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V
IN
Toensurethattheloadcurrentwillbedeliveredoverthefull
operating temperature range, the temperature coefficient
of the DCR resistance, approximately 0.4%/°C, should be
taken into consideration.
V
IN
INDUCTANCE
DCR
LTC3874-1
PWM
L
DrMOS
V
OUT
Typically, C is selected in the range of 0.047µF to 0.47µF.
This forces R to around 2kΩ, reducing error that might
have been caused by the I
pins’ 1uA current.
SENSE
R
+
–
I
I
SENSE
SENSE
There will be some power loss in R that relates to the duty
cycle. It will be highest in continuous mode at maximum
input voltage:
C
38741 F02
V
IN(MAX) − VOUT •V
Figure 2 Inductor DCR Current Sensing
(
LOSS (R)=
)
OUT
P
R
Inductor DCR Current Sensing
Ensure that R has a power rating higher than this value.
However, DCR sensing eliminates the conduction loss
of a sense resistor; it will provide a better efficiency at
heavy loads. To maintain a good signal-to-noise ratio for
the current sense signal, using a minimum ∆V
2mV for duty cycles less than 40% is desirable when the
LOWDCR pin is high; use a minimum ∆V of 10mV
for duty cycles less than 40% when the LOWDCR pin is
low. The actual ripple voltage will be determined by the
following equation:
TheLTC3874-1isspecificallydesignedforhighloadcurrent
applications requiring the highest possible efficiency; it is
capable of sensing the signal of an inductor DCR in the
sub-milliohm range (Figure 2). The DCR is the DC winding
resistance of the inductor’s copper, which is often less
than 1mΩ for high current inductors. In high current and
low output voltage applications, conduction loss of a high
DCR or a sense resistor will cause a significant reduction
in power efficiency. For a specific output requirement,
choose the inductor with the DCR that satisfies the maxi-
mum desirable sense voltage, and use the relationship of
the sense pin filters to output inductor characteristics as
depicted below.
of
ISENSE
ISENSE
⎛
⎞
VOUT V − V
IN
OUT
ΔV
=
ISENSE
⎜
⎟
V
R C•fOSC
⎝
⎠
IN
V
Inductor Value Calculation
ISENSE(MAX)
DCR=
ΔIL
Given the desired input and output voltages, the inductor
IMAX
+
2
value and operating frequency, f , directly determine
OSC
the inductor’s peak-to-peak ripple current:
RC = L/(5 • DCR) when the LOWDCR pin is high
⎛
⎞
VOUT V – V
RC = L/DCR when the LOWDCR pin is low
IN
OUT
IRIPPLE
=
⎜
⎟
V
fOSC •L
⎝
⎠
IN
where:
V
: Maximum sense voltage for a given I
TH
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
ISENSE(MAX)
voltage
I
: Maximum load current
MAX
∆I : Inductor ripple current
L
L, DCR: Output inductor characteristics
R, C: Filter time constant
A reasonable starting point is to choose a ripple current
that is about 40% of I
. Note that the largest ripple
OUT(MAX)
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current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
The peak-to-peak MOSFET gate drive levels are set by the
internal regulator voltage, V
, requiring the use of
INTVCC
logic-level threshold MOSFETs in most applications. Pay
closeattentiontotheBV specificationfortheMOSFETs
DSS
V – V
fOSC •IRIPPLE
VOUT
V
IN
IN
OUT
L ≥
•
as well; many of the logic-level MOSFETs are limited to
30V or less. Selection criteria for the power MOSFETs
include the on-resistance, R , input capacitance,
DS(ON)
Inductor Core Selection
inputvoltageandmaximumoutputcurrent.MOSFETinput
capacitance is a combination of several components but
can be taken from the typical gate charge curve included
on most data sheets (Figure 3). The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gate voltage versus time.
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductanceselected. Asinductanceincreases, corelosses
go down. Unfortunately, increased inductance requires
moreturnsofwireandthereforecopperlosseswillincrease.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
V
IN
MILLER EFFECT
V
V
GS
a
b
+
–
V
DS
+
Q
IN
V
GS
–
C
= (Q – Q )/V
B A DS
MILLER
38741 F03
Figure 3. Gate Charge Characteristic
Power MOSFET and Schottky Diode
(Optional) Selection
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
When we use discrete gate driver and MOSFETs, at least
two external power MOSFETs need to be selected: One
N-channel MOSFET for the top (main) switch and one or
moreN-channelMOSFET(s)forthebottom(synchronous)
switch.Thenumber,typeandon-resistanceofallMOSFETs
selected take into account the voltage step-down ratio
as well as the actual position (main or synchronous) in
whichtheMOSFETwillbeused. Amuchsmallerandmuch
lower input capacitance MOSFET should be used for the
top MOSFET in applications that have an output voltage
that is less than one-third of the input voltage. In applica-
tions where V >> V , the top MOSFETs’ on-resistance
while the curve is flat) is specified for a given V drain
DS
voltage, but can be adjusted for different V voltages by
DS
multiplying the ratio of the application V to the curve
DS
specified V values. A way to estimate the C
term
DS
MILLER
is to take the change in gate charge from points a and b
IN
OUT
is normally less important for overall efficiency than its
input capacitance at operating frequencies above 300kHz.
MOSFET manufacturers have designed special purpose
devices that provide reasonably low on-resistance with
significantlyreducedinputcapacitanceforthemainswitch
application in switching regulators.
on a manufacturer’s data sheet and divide by the stated
V
voltage specified. C
is the most important se-
MILLER
DS
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. C
and C are specified sometimes but
RSS
OS
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definitionsoftheseparametersarenotincluded.Whenthe
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R
vs temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
VOUT
MainSwitchDuty Cycle =
An optional Schottky diode across the synchronous
MOSFET conducts during the dead time between the con-
ductionofthetwolargepowerMOSFETs.Thispreventsthe
bodydiodeofthebottomMOSFETfromturningon,storing
chargeduringthedeadtimeandrequiringareverse-recov-
ery period which could cost as much as several percent in
efficiency. A 2A to 8A Schottky is generally a good com-
promise for both regions of operation due to the relatively
small average current. Larger diodes result in additional
transition loss due to their larger junction capacitance.
V
IN
⎛
⎞
V – V
IN
OUT
Synchronous SwitchDuty Cycle =
⎜
⎟
V
⎝
⎠
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
2
)
VOUT
PMAIN
=
I
(
1+ δ R
+
(
)
MAX
DS(ON)
V
IN
I
⎛
⎞
MAX
2
V
R
C
•
(
)
(
DR)(
)
INTV Regulators and EXTV
IN
MILLER
⎜
⎟
CC
CC
2
⎝
⎠
The LTC3874-1 features a PMOS LDO that supplies power
to INTV from the V supply. INTV powers most of
⎡
⎤
⎥
⎦
1
1
CC
IN
CC
+
• f
⎢
V
INTVCC – VTH(MIN) VTH(MIN) ⎥
the LTC3874-1’s internal circuitry. The linear regulator
regulates the voltage at the INTV pin to 5.5V when V
⎢
⎣
CC
IN
2
)
V – V
IN
OUT
is greater than 6V. EXTV connects to INTV through
PSYNC
=
I
(
1+ δ R
( )
DS(ON)
CC
CC
MAX
V
IN
another P-channel MOSFET and can supply the needed
power when its voltage is higher than 4.7V and V is
IN
where δ is the temperature dependency of R
, R
DS(ON) DR
higher than 7V. Each of these can supply a peak current of
100mA and must be bypassed to ground with a minimum
value of 4.7µF ceramic capacitor or low ESR electrolytic
capacitor. No matter what type of bulk capacitor is used,
anadditional0.1µFceramiccapacitorplaceddirectlyadja-
is the effective top driver resistance (approximately 2Ω at
= V ), V is the drain potential and the change
V
GS
MILLER
IN
in drain potential in the particular application. V
TH(MIN)
is the data sheet specified typical gate threshold voltage
specified in the power MOSFET data sheet at the specified
cent to the INTV and GND pins is highly recommended.
CC
drain current. C
is the calculated capacitance using
MILLER
Good bypassing is needed to prevent interaction between
the gate charge curve from the MOSFET data sheet and
the channels.
the technique described above.
When the voltage applied to EXTV rises above 4.7V and
2
CC
BothMOSFETshaveI RlosseswhilethetopsideN-channel
V above 7V, the INTV linear regulator is turned off and
IN
CC
equation includes an additional term for transition losses,
the EXTV is connected to INTV . Using the EXTV al-
CC
CC
CC
which peak at the highest input voltage. For V < 20V,
IN
lows the MOSFET driver and control power to be derived
the high current efficiency generally improves with larger
from other high efficiency sources such as +5V rails in
MOSFETs, whileforV >20V, thetransitionlossesrapidly
IN
the system. Do not apply more than 6V to the EXTV pin.
CC
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
For applications where the main input power is 5V, tie
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
the V and INTV pins together and tie the combined
IN
CC
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 4 to minimize the voltage drop caused by the
gate charge current. This will override the INTV linear
CC
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regulator and will prevent INTV from dropping too low
The relationship between the voltage on the FREQ pin and
the operating frequency is shown in Figure 5 and specified
in the Electrical Characteristic table. If an external clock is
detected on the SYNC pin, the internal switch mentioned
above will turn off and isolate the influence of the FREQ
pin. Note that the LTC3874-1 can only be synchronized
to an external clock whose frequency is within the range
of the LTC3874-1’s internal VCO. This is guaranteed to be
between 250kHz and 1MHz. A simplified block diagram
is shown in Figure 6.
CC
due to the dropout voltage. Make sure the INTV voltage
CC
is at or exceeds the R
test voltage for the MOSFET,
DS(ON)
which is typically 4.5V for logic-level devices.
LTC3874-1
V
R
IN
VIN
1Ω
INTV
5V
CC
+
C
INTVCC
C
IN
4.7µF
38741 F04
Figure 4. Setup for a 5V Input
1600
1400
1200
1000
800
600
400
200
0
Undervoltage Lockout
The LTC3874-1 has a precision UVLO comparator con-
stantly monitoring the INTV voltage. It locks out the
CC
switching action and pulls down RUN pins when INTV is
CC
below3.5V.Inmultiphaseoperation,whentheLTC3874-1
is in undervoltage lockout, the RUN pin is pulled down to
disable the master’s switching action. To prevent oscilla-
tion when there is a disturbance on the INTV , the UVLO
CC
comparator has 300mV of precision hysteresis.
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
38741 F05
Phase-Locked Loop and Frequency Synchronization
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the FREQ Pin
The LTC3874-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the internal clock to be locked
to the falling edge of an external clock signal applied to the
SYNC pin. The turn-on of the top MOSFET is synchronized
or out-of-phase with the falling edge of external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
2.4V 5.5V
R
SET
10µA
FREQ
DIGITAL
PHASE/
SYNC
SYNC
EXTERNAL
OSCILLATOR
FREQUENCY
DETECTOR
VCO
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. There is a precision 10µA of current flowing
out of the FREQ pin. This allows the user to use a single
resistor to GND to set the switching frequency when no
external clock is applied to the SYNC pin. The internal
switch between the FREQ pin and the integrated PLL
filter network is ON, allowing the filter network to be pre-
charged to the same voltage potential as the FREQ pin.
38741 F06
Figure 6. Phase-Locked Loop Block Diagram
38741f
15
For more information www.linear/LTC3874-1
LTC3874-1
applicaTions inForMaTion
If the external clock frequency is greater than the inter-
Transient Response and Loop Stability
nal oscillator’s frequency, f , then current is sourced
OSC
In a typical parallel operation, the LTC3874-1 cooperates
withmastercontrollerstosupplymorecurrent. Toachieve
balanced current sharing between master and slave, it is
recommended that each slave channel copies the power
stage design from the master channel. Select the same
inductors, same MOSFET driver, same power MOSFETs,
and same output capacitors between the master and slave
channels. Control loop and compensation design on the
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f , current is sunk continuously, pulling down
OSC
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
I
pin should start with the single phase operation of the
TH
master controller. The multiphase transient response and
loopstabilityisalmostthesameasthesinglephaseopera-
tion of the master by tying the I pins together between
TH
Typically, the external clock (on the SYNC pin) input high
threshold is 2V, while the input low threshold is 1.4V.
master and slaves. For example, design the compensation
for a single phase 1.8V/20A output using LTC3884-1 with
a 0.33μH inductor and 530μF output capacitors. To extend
the output to 1.8V/40A, simply parallel one channel of
LTC3874-1 with the same inductor and output capacitors
Fault Protection and Response
Master controllers monitor system voltage, current, tem-
perature and provide many protection features during all
kinds of fault conditions. The LTC3874-1 slave control-
lers do not provide as many fault protections as master
controllers but respond to the fault signal from the master
controller. FAULT0 and FAULT1 pins are designed to share
the fault signal between masters and slaves. In a typical
parallel application, connect the fault pins on LTC3874-1
to the master fault indictor pins, so that the slave control-
ler can respond to all fault signals from the master. When
the FAULT pin is pulled below 1.4V, the PWM pin in the
corresponding channel is in three-state. When the FAULT
pinvoltageisabove2V, thecorrespondingchannelisback
to normal operation. During fault conditions, all internal
circuits in the LTC3874-1 are still running so the slave
controllers can immediately return to normal operation
when the FAULT pin is released.
(total output capacitors are 1060μF) and tie the I pin of
TH
LTC3874-1tothemasterI .Theloopstabilityandtransient
TH
responses of the two phase converter are very similar to
the single phase design without any extra compensator
on the I pin of the slave controller. Furthermore, LTpow-
TH
erCAD is provided on the LTC website as a free download
for transient and stability analysis.
To minimize the high frequency noise on the I trace
TH
between master and slave I pins, a small filter capacitor
TH
in the range of tens of pF can be placed closely at each I
TH
pin of the slave controller. This small capacitor normally
does not significantly affect the closed-loop bandwidth
but increases the gain margin at high frequency.
Mode Selection and Pre-Biased Startup
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging the
output capacitors. The LTC3874-1 can be configured to
operate in DCM mode for pre-biased start-up. The master
chip’s PGOOD pin can be connected to the MODE pins of
the LTC3874-1 to ensure the DCM operation at startup
and CCM operation in steady state.
The LTC3874-1 has internal thermal shutdown protection
which forces the PWM pin three-state when the junction
temperature is higher than 160°C. The thermal shutdown
has 10°C of hysteresis. In thermal shutdown, the FAULT0
and FAULT1 pins are also pulled low. The RUN pins are not
internally pulled low. There is a 500k pull-down resistor
on each FAULT pin which sets the default voltage on the
FAULT pins low if the FAULT pins are floating.
38741f
16
For more information www.linear.com/LTC3874-1
LTC3874-1
applicaTions inForMaTion
Minimum On-Time Considerations
MOSFET Driver Selection
Gate driver ICs, DrMOSs and power blocks with an inter-
face compatible with the LTC3874-1’s three-state PWM
outputs should be used.
Minimumon-timet
isthesmallesttimedurationthat
ON(MIN)
the LTC3874-1 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 7 illustrates the current waveforms pres-
ent in the various branches of the 2-phase synchronous
regulators operating in the continuous mode. Check the
following in the PC layout:
VOUT
tON(MIN)
<
V •f
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles.Theoutputvoltagewillcontinuetoberegulated,but
the ripple voltage and current will increase. The minimum
on-time for the LTC3874-1 is approximately 60ns, with
reasonably good PCB layout, minimum 30% inductor cur-
rent ripple and at least 2mV – 3mV (10mV – 15mV when
theLOWDCRpinislow)rippleonthecurrentsensesignal.
The minimum on-time can be affected by PCB switch-
ing noise in the current loop. As the peak sense voltage
decreases the minimum on-time gradually increases to
100ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
must return to the combined C
TH
(–) ter-
INTVCC
OUT
minals. The I traces should be as short as possible.
The C capacitor should have short leads and PC trace
IN
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
+
–
2. Are the I
and I
leads routed together with
SENSE
SENSE
minimumPCtracespacing?Thefiltercapacitorbetween
+
–
I
and I
should be as close as possible to
SENSE
SENSE
the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
is used for current sensing.
PWM Pins
The PWM output pins are three-state compatible outputs,
designedtodriveMOSFETdrivers, DrMOSs, etc. whichdo
not represent a heavy capacitive load. An external resistor
divider may be used on the PWM pins to set the voltage
to mid-rail while in the high impedance state.
3. Is the INTV decoupling capacitor connected close to
CC
the IC, between the INTV and the ground pins? This
CC
capacitorcarriestheMOSFETdriverscurrentpeaks. An
additional 1μF ceramic capacitor placed immediately
next to the INTV and GND pins can help improve
CC
noise performance substantially.
The V pin is the corresponding PWM pin driver supply.
CC
Decouple this pin to GND with a capacitor (0.1μF) or tie
4. Keep the switching nodes (SW1, SW0), away from
sensitive small-signal nodes, especially from the op-
posite channel’s current sensing feedback pins. All of
these nodes have very large and fast moving signals
and therefore should be kept on the output side of the
LTC3874-1 and occupy minimum PC trace area. If DCR
sensing is used, place the resistor (Figure 2, “R”) close
to the switching node.
this pin to the INTV pin. If the V pin is connected to
CC
CC
an external supply, make sure it comes first before the
RUN pin goes high.
38741f
17
For more information www.linear/LTC3874-1
LTC3874-1
applicaTions inForMaTion
SW1
L1
V
OUT1
D1
C
OUT1
R
L1
V
IN
R
IN
C
IN
SW0
L0
V
OUT0
D0
C
OUT0
R
L0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38741 F07
Figure 7. Recommended Printed Circuit Layout Diagram
5. Useamodifiedstargroundtechnique:alowimpedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
drops below the low current operation threshold.
with tie-ins for the bottom of the INTV decoupling
CC
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controllerischeckedforitsindividualperformanceshould
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
38741f
18
For more information www.linear.com/LTC3874-1
LTC3874-1
applicaTions inForMaTion
bothcontrollersbeturnedonatthesametime.Aparticularly
difficultregionofoperationiswhenonecontrollerchannel
is nearing its current comparator trip point when the other
channel is turning on its top MOSFET. This occurs around
50% duty cycle on either channel due to the phasing of
the internal clocks and may cause minor duty cycle jitter.
The master chip LTC3884-1 design can be found in the
LTC3884-1 data sheet (Design Example section).
The LTC3884-1 SYNC pin is connected to the LTC3874-1
SYNC pin for switching frequency synchronization. The
LTC3874-1 PHASMD pin is tied to INTV to form a
CC
PolyPhase configuration.
Reduce V from its nominal level to verify operation of
IN
The slave chip LTC3874-1 should use the same inductor,
the regulator in dropout. Check the operation of the un-
DrMOS, C , and C
as the master chip. DCR sensing
IN
OUT
dervoltage lockout circuit by further lowering V while
IN
is also used for the slave chip. The LTC3884-1 I pins
TH
monitoring the outputs to verify operation.
and the LTC3874-1 I pins are connected together. The
TH
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
LTC3874-1 LOWDCR pin is pulled high and the ILIM pin
is forced to INTV to obtain the same current limit as
CC
LTC3884-1.
The LTC3884-1 RUN pins and the LTC3874-1 RUN pins
are connected together. The LTC3884-1 FAULT pins are
connected to LTC3874-1 FAULT pins so the LTC3874-1
will be disabled if the LTC3884-1 is under any fault event.
The LTC3874-1 MODE pins are tied to the LTC3884-1
PGOOD pins for start-up control. During soft-start, the
LTC3874-1 operates in DCM mode. When the soft-start
interval is done, the LTC3874-1 operates in CCM mode.
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
Design Example
Using master controller LTC3884-1 and slave controller
LTC3874-1 for a single-output, 4-phase high current
regulator, assume V = 12V (nominal), and V = 15V
IN
IN
(maximum), V
(see Figure 8).
= 1.05V, I
= 120A, and f = 500kHz
OUT
MAX
38741f
19
For more information www.linear/LTC3874-1
LTC3874-1
applicaTions inForMaTion
0.47µF
1mΩ
0Ω
V
IN1
649Ω
BOOT
1Ω
V
IN
7V TO 14V
V
IN1
V
IN
PHASE
4.7µF
0.215µH, L1
V
OUT
220nF
22µF
×4
TDA21470
1.05 V
120A
EN
SW
2.2µF
C
C
OUT2
OUT1
+
–
+
V
IN
I
I
IN
INTV
CC
IN
V
100µF
×3
470µF
×2
OS
+
+
–
–
PWM
T
/FLT
V
V
V
V
V
PWM0
OUT
OUT
SENSE0
SENSE1
SENSE0
SENSE1
6.3V
2.5V
+
V
PGND
I
I
I
I
DRV
SENSE0
V
DR
5V
–
V
CC
SENSE0
4.7µF
LGND
–
330pF
SENSE1
4.7µF
10nF
10nF
+
WP
220nF
SENSE1
PWM1
TSNS0
TSNS1
LTC3884-1
I
I
I
TH0
5k
5k
TH
SDA
SCL
330pF
6.8nF
TH1
0.47µF
0Ω
I
I
THR0
THR1
DD25
5k
5k
649Ω
SHARE_CLK
BOOT
ALERT
V
V
V
PHASE
IN1
IN
0.215µH, L2
V
V
V
V
0_CFG
1_CFG
DD33
DD33
22µF
×4
OUT
TDA21470
24.9k
7.32k
20k
24.9k
EN
SW
1µF
V
V
CC0
C
C
OUT3
OUT4
OUT
+
V
100µF
×3
470µF
×2
OS
CC1
4.7µF
5k
5k
5k
PWM
T
/FLT
FAULT0
17.8k
5.76k
OUT
6.3V
2.5V
V
PGND
FAULT1
RUN0
DRV
V
DR
5V
V
CC
ASEL0
4.7µF
LGND
RUN1
330pF
FREQ_CFG
4.7µF
SYNC
PGOOD0
EXTV
CC
5k
PGOOD1
PHAS_CFG
GND
0.47µF
0Ω
2Ω
V
IN
7V TO 14V
BOOT
V
INTV
PHASM0
LTC3874-1
IN
CC
V
IN1
V
PHASE
4.7µF
IN
0.1µF
0.215µH, L3
RUN0
22µF
×4
TDA21470
EN
SW
RUN1
ILIM
C
C
OUT6
OUT5
+
V
100µF
×3
470µF
×2
OS
SYNC
LOWDCR
PWM
T
/FLT
MODE0
MODE1
PWM0
+
OUT
6.3V
2.5V
I
V
PGND
SENSE0
DRV
–
V
DR
5V
I
SENSE0
V
220nF
CC
4.7µF
LGND
FAULT0
FAULT1
330pF
4.7µF
PWM1
+
V
V
I
I
CC0
CC1
SENSE1
I
SENSE1
649Ω
–
V
DD33
I
TH
TH0
TH1
100k
1µF
47pF
I
FREQ
GND
0.47µF
0Ω
BOOT
V
IN1
V
PHASE
IN
PIN NOT USED IN CIRCUIT LTC3884-1: ASEL1
PIN NOT USED IN CIRCUIT LTC3874-1: EXTV
0.215µH, L4
22µF
×4
TDA21470
EN
SW
C
C
OUT8
OUT7
CC
+
V
100µF
×3
470µF
×2
OS
PINS NOT USED IN CIRCUITS TDA21470: REFIN , GATEL, I , OCSET
OUT
PWM
T
/FLT
OUT
6.3V
2.5V
COUT1, 3, 5, 7: MURATA GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)
COUT2, 4, 6, 8: PANASONIC ETPF470M5H (470µF, 2.5V)
V
V
PGND
DRV
CC
V
DR
5V
L1, L2, L3, L4: EATON FP1007R3-R22-R (0.215µH, DCR = 0.29mΩ)
220nF
3874 F08
V
IS FROM EXTERNAL 5V POWER SUPPLY
4.7µF
DR
LGND
330pF
4.7µF
649Ω
Figure 8. High Efficiency 500kHz 4-Phase 1.05V Step-Down Converter
38741f
20
For more information www.linear.com/LTC3874-1
LTC3874-1
package DescripTion
Please refer to http://www.linear.com/product/LTC3874-1#packaging for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
R = 0.ꢀꢀ5
TYP
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38741f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
21
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3874-1
Typical applicaTion
High Efficiency Dual 1.0V/1.5V Step-Down Converter
V
IN
7V TO 14V
V
IN
LTC3874-1
PWM0
PWM1
(0.29mΩ DCR)
0.215µH
(0.29mΩ DCR)
0.215µH
V
V
1.5V
60A
OUT0
1V
60A
OUT1
DrMOS
DrMOS
649Ω
649Ω
100µF
×3
100µF
×3
470µF
×2
470µF
×2
0.22µF
0.22µF
+
+
+
–
+
–
I
I
I
I
SENSE0
SENSE0
SENSE1
SENSE1
LTC3884-1
RUN0
RUN1
FAULT0
FAULT1
RUN0
RUN1
INTV
CC
V
CC0
4.7µF
FAULT0
FAULT1
MODE0
MODE1
V
CC1
PHASMD
LDWDCR
ILIM
PGOOD0
1V
+
+
V
V
SENSE0
PGOOD1
1.5V
I
I
TH0
TH0
100k
SENSE1
V
OUT1
I
I
FREQ
GND
REFER TO LTC3884-1 DATA SHEET
FOR MASTER SETUP
TH1
TH1
SYNC
SYNC
PIN NOT USED IN THIS CIRCUIT: EXTV
CC
3874 TA02
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
2
LTM4676A
LTM4675
LTM4677
Dual 13A or Single 26A Step-Down DC/DC µModule® Regulator 4.5V ≤ V ≤17V; 0.5V ≤ V
( 0.5%) ≤ 5.5V, I C/PMBus Interface,
OUT
IN
with Digital Power System Management
16mm × 16mm × 5mm, BGA Package
2
Dual 9A or Single 18A μModule Regulator with Digital Power
System Management
4.5V ≤ V ≤17V; 0.5V ≤ V ( 0.5%) ≤ 5.5V, I C/PMBus Interface,
IN
OUT
11.9mm × 16mm × 5mm, BGA Package
2
Dual 18A or Single 36A μModule Regulator with Digital Power
System Management
4.5V ≤ V ≤16V; 0.5V ≤ V ( 0.5%) ≤ 1.8V, I C/PMBus Interface,
IN
OUT
16mm × 16mm × 5.01mm, BGA Package
4.5V ≤ V ≤ 38V, 0.5V ≤ V ( 0.5%) ≤ 5.5V, 70ms Start-Up, I C/
OUT
2
LTC3884/
LTC3884-1
Dual Output Multiphase Step-Down Controller with Sub mΩ
DCR Sensing Current Mode Control and Digital Power System
Management
IN
PMBus Interface, Programmable Analog Loop Compensation, Input
Current Sense
2
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Controller with
Digital Power System Management, 70ms Start-Up
4.5V ≤ V ≤ 24V, 0.5V ≤ V
, ( 0.5%) ≤ 5.5V, 70ms Start-Up, I C/
IN
OUT0 1
PMBus Interface, -1 Version Uses DrMOS or Power Blocks
2
LTC3882/
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ V ≤ 38V, 0.5V ≤ V ≤ 5.25V, 0.5% V Accuracy I C/
IN
OUT1,2
OUT
LTC3882-1
PMBus Interface, Uses DrMOS or Power Blocks
4.5V ≤ V ≤ 38V, 0.6V ≤ V ≤ 3.5V, with Remote V Sense, 4mm
OUT
LTC3866
Single Output Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing
IN
OUT
× 4mm, QFN-24, TSSOP-24 Packages
2
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller with Digital Power
System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Input Current Sense Amplifier, I C/
IN
OUT
PMBus Interface with EEPROM and 16-Bit ADC, 0.5% V
Accuracy
OUT
LTC3875
Dual, Multiphase Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases
4.5V ≤ V ≤ 38V, 0.6V ≤ V
≤ 3.5V, with Remote Sense
IN
OUT
LTC3774
Dual, Multiphase Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases
V
Up to 40V, 0.6V ≤ V
≤ 3.5V, Very High Output Current
IN
OUT
Applications with Accurate Current Share Between Phases
Supporting LTC3880/-1, LTC3883/-1, LTC3886, LTC3887/-1
LTC3877
Dual Phase Step-Down Synchronous Controller with 6-Bit V
Output Voltage Programming and Low Value DCR Sensing
4.5V ≤ V ≤ 38V, 0.6V ≤ V
OUT
≤ 1.23V with V in 10mV Steps, 0.6V ≤
ID
IN
OUT ID
V
≤ 5V without V , Up to 12-Phase Operation
ID
38741f
LT 0917 • PRINTED IN USA
www.linear.com/LTC3874-1
22
LINEAR TECHNOLOGY CORPORATION 2017
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LTC3880/
Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing
Linear
LTC3880EUJ#PBF
LTC3880 - Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C
Linear
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