LTC3880-1_技术文档

LTC3729

550kHz, PolyPhase,

High Efﬁciency, Synchronous

Step-Down Switching Regulator

DESCRIPTION

FEATURES

The LTC^®3729 is a multiple phase, synchronous

n

Wide V Range: 4V to 36V Operation

IN

n

Reduces Required Input Capacitance and Power

step‑down current mode switching regulator controller

that drives N‑channel external power MOSFET stages in a

phase‑lockableﬁxedfrequencyarchitecture.ThePolyPhase

controller drives its two output stages out of phase at

frequencies up to 550kHz to minimize the RMS ripple

currents in both input and output capacitors. The output

clock signal allows expansion for up to 12 evenly phased

controllers for systems requiring 15A to 200A of output

current.Themultiplephasetechniqueeffectivelymultiplies

the fundamental frequency by the number of channels

used, improving transient response while operating each

channel at an optimum frequency for efﬁciency. Thermal

design is also simpliﬁed.

Supply Induced Noise

n

±1% Output Voltage Accuracy

Phase-Lockable Fixed Frequency: 250kHz to 550kHz

True Remote Sensing Differential Ampliﬁer

PolyPhase^®Extends from Two to Twelve Phases

Reduces the Size and Value of Inductors

Current Mode Control Ensures Current Sharing

1.1MHz Effective Switching Frequency (2‑Phase)

OPTI‑LOOP^®Compensation Reduces C

OUT

Power Good Output Voltage Indicator

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft‑Start Current Ramping

Internal Current Foldback Plus Shutdown Timer

Overvoltage Soft‑Latch Eliminates Nuisance Trips

Available in 5mm × 5mm QFN

Aninternaldifferentialampliﬁerprovidestrueremotesens‑

ing of the regulated supply’s positive and negative output

terminals as required for high current applications.

and 28‑Lead SSOP Packages

A RUN/SS pin provides both soft‑start and optional timed,

short‑circuit shutdown. Current foldback limits MOSFET

dissipation during short‑circuit conditions when the

overcurrentlatchoffisdisabled.OPTI‑LOOPcompensation

allows the transient response to be optimized over a wide

range of output capacitance and ESR values. The LTC3729

includes a power good output pin that indicates when the

output is within ±7.5% of the designed set point.

APPLICATIONS

n

Desktop Computers/Servers

n

Large Memory Arrays

n

DC Power Distribution Systems

L, LT, LTC, LTM, PolyPhase, OPTI‑LOOP, Linear Technology and the Linear logo are registered

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

TYPICAL APPLICATION

V

IN

5V TO 28V

0.1µF

10Ω

S

10µF

35V

CERAMIC

×4

M1

S

LTC3729

V

TG1

BOOST1

SW1

IN

0.002Ω

0.47µF

0.1µF

L1

0.8µH

S

M2

×2

D1

RUN/SS

PGOOD

BG1

PGND

+

SENSE1

I

TH

–

3.3k

16k

1000pF

16k

M3

TG2

BOOST2

SW2

S

0.002Ω

SGND

V

OUT

1.6V/40A

0.47µF

L2

0.8µH

S

M4

×2

V

BG2

DIFFOUT

D2

EAIN

–

INTV

CC

+

10µF

+

C

OUT

V

SENSE2

OS

1000µF ×2

+

–

4V

C

: T510E108K004AS

L1, L2: CEPH149-IROMC

M1, M3: IRF7811W

M2, M4: IRF7822

OUT

3729 TA01

D1, D2: UP5840

Figure 1. High Current Dual Phase Step-Down Converter

3729fb

1

LTC3729

(Note 1)

ABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (V )......................... 36V to –0.3V

V

TH

Voltages.............V – 2V to –0.3V for V < 7V

DIFFOUT IN IN

IN

Topside Driver Voltages (BOOST1,2) ......... 42V to –0.3V

Switch Voltage (SW1, 2).............................. 36V to –5 V

I

Voltage ............................................... 2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2) .................5A

+

–

+

–

SENSE1 , SENSE2 , SENSE1 ,

INTV RMS Output Current................................. 50mA

CC

SENSE2 Voltages .........................(1.1)INTV to –0.3V

Operating Ambient Temperature

CC

+

–

EAIN, V , V , EXTV , INTV ,

Range (Note 6)......................................... –40°C to 85°C

Junction Temperature (Note 2) ............................. 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

OS

CC

RUN/SS, PGOOD Voltages .......................... 7V to –0.3V

Boosted Driver Voltage (BOOST‑SW)........... 7V to –0.3V

PLLFLTR, PLLIN, CLKOUT, PHASMD,

V

Voltages ..............INTV to –0.3V for V ≥ 7V

(G Package Only).............................................. 300°C

DIFFOUT

CC

IN

PIN CONFIGURATION

TOP VIEW

1

CLKOUT

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS

+

2

SENSE1

–

32 31 30 29 28 27 26 25

3

SW1

SENSE1

EAIN

PLLFLTR

PLLIN

1

2

3

4

5

6

7

8

24 BOOST1

4

BOOST1

EAIN

23

22

21

V

IN

5

V

PLLFLTR

IN

BG1

6

BG1

PLLIN

PHASMD

EXTV

CC

7

EXTV

CC

PHASMD

I

TH

20 INTV

CC

8

INTV

CC

I

TH

SGND

PGND

19

9

PGND

BG2

SGND

V

18 BG2

DIFFOUT

–

10

V

DIFFOUT

–

V

17 BOOST2

OS

11

12

13

14

BOOST2

SW2

V

OS

9

10 11 12 13 14 15 16

+

–

TG2

SENSE2

+

PGOOD

UH PACKAGE

32-LEAD 5mm × 5mm PLASTIC QFN

= 34°C/W

G PACKAGE

28-LEAD PLASTIC SSOP

= 125°C, θ = 95°C/W

θ

JA

EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC3729EG#PBF

LTC3729EUH#PBF

TAPE AND REEL

PART MARKING

LTC3729

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

LTC3729EG#TRPBF

LTC3729EUH#TRPBF

28‑Lead Plastic SSOP

3729

–40°C to 85°C

32‑Lead (5mm × 5mm)Plastic QFN

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non‑standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3729fb

2

LTC3729

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

l

V

Regulated Feedback Voltage

(Note 3); I Voltage = 1.2V

0.792

0.800

0.808

V

EAIN

TH

–

Maximum Current Sense Threshold

V

SENSE

V

= 5V

62

65

75

88

85

mV

SENSEMAX

= 5V

SENSE1, 2

I

Feedback Current

(Note 3)

–5

–50

nA

INEAIN

V

Output Voltage Load Regulation

LOADREG

l

Measured in Servo Loop; I Voltage = 0.7V

0.1

–0.1

0.5

–0.5

%

TH

Measured in Servo Loop; I Voltage = 2V

TH

V

Reference Voltage Line Regulation

Output Overvoltage Threshold

Undervoltage Lockout

V

= 3.6V to 30V (Note 3)

0.002

0.86

3.5

0.02

0.88

4

%/V

V

REFLNREG

IN

l

Measured at V

0.84

3

OVL

EAIN

UVLO

V

Ramping Down

V

IN

TH

g

Transconductance Ampliﬁer g

I

= 1.2V; Sink/Source 5µA; (Note 3)

3

mmho

V/mV

m

Transconductance Ampliﬁer Gain

= 1.2V; (g xZ ; No Ext Load); (Note 3)

1.5

mOL

m

L

I

Input DC Supply Current

Normal Mode

(Note 4)

Q

EXTV Tied to V

; V = 5V

580

20

µA

CC

OUT OUT

Shutdown

V

= 0V

40

RUN/SS

I

Soft‑Start Charge Current

RUN/SS Pin ON Threshold

RUN/SS Pin Latchoff Arming

RUN/SS Discharge Current

Shutdown Latch Disable Current

Total Sense Pins Source Current

Maximum Duty Factor

= 1.9V

Rising

–0.5

1.0

–1.2

1.5

3.8

2

µA

V

RUN/SS

V

1.9

4.5

4

RUN/SS

RUN/SSLO

SCL

Rising from 3V

V

I

Soft Short Condition V

= 0.5V; V

= 4.5V

RUN/SS

0.5

µA

%

EAIN

V

EAIN

= 0.5V

1.6

–60

99.5

5

SDLDO

SENSE

–

+

Each Channel; V

In Dropout

= V

= 0V

–85

98

SENSE1 , 2

DF

MAX

Top Gate Transition Time:

Rise Time

Fall Time

TG1, 2 t

C

LOAD

C

LOAD

= 3300pF

30

40

90

ns

r

f

Bottom Gate Transition Time:

Rise Time

Fall Time

BG1, 2 t

C

LOAD

C

LOAD

= 3300pF

30

20

90

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch‑On Delay Time

1D

C

= 3300pF Each Driver

90

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch‑On Delay Time

2D

90

ns

LOAD

t

Minimum On‑Time

Tested with a Square Wave (Note 5)

100

ON(MIN)

Internal V Regulator

CC

V

Internal V Voltage

6V < V < 30V; V = 4V

EXTVCC

4.8

4.5

5.0

0.2

80

5.2

1.0

V

%

INTVCC

CC

IN

INT

INTV Load Regulation

I

CC

I

CC

I

CC

I

CC

= 0 to 20mA; V

= 4V

LDO

CC

EXTVCC

EXT

EXTV Voltage Drop

= 20mA; V

= 5V

EXTVCC

160

mV

V

CC

l

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

4.7

0.2

EXTVCC

LDOHYS

CC

EXTV Switchover Hysteresis

= 20mA, EXTV Ramping Negative

V

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

360

230

480

400

260

550

50

440

290

590

kHz

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

kΩ

PLLIN

3729fb

3

LTC3729

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 15V, V_RUN/SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

> f

–15

15

µA

PLLIN

OSC

R

Controller 2‑Controller 1 Phase

Phase (Relative to Controller 1)

V

= 0V, Open

= 5V

180

240

Deg

RELPHS

PHASMD

CLKOUT

V

= 0V

= Open

= 5V

60

90

120

Deg

PHASMD

CLK

Clock High Output Voltage

Clock Low Output Voltage

4

V

HIGH

LOW

0.2

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

EAIN

V

–6

6

–7.5

7.5

–9.5

9.5

%

EAIN

Differential

Ampliﬁer

A

Gain

0.995

46

1

1.005

V/V

dB

DA

CMRR

Common Mode Rejection Ratio

Input Resistance

0V < V < 5V

55

80

DA

CM

+

R

Measured at V

Input

kΩ

IN

OS

Note 1: Absolute Maximum Ratings are those values beyond which

the life of a device may be impaired.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: T is calculated from the ambient temperature T and power

Note 5: The minimum on‑time condition corresponds to the on inductor

J

A

dissipation P according to the following formulas:

peak‑to‑peak ripple current ≥40% of I

(see Minimum On‑Time

D

MAX

Considerations in the Applications Information section).

LTC3729EG: T = T + (P • 95°C/W)

J

A

D

Note 6: The LTC3729E is guaranteed to meet performance speciﬁcations

from 0°C to 70°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

LTC3729EUH: T = T + (P • 34°C/W)

Note 3: The LTC3729 is tested in a feedback loop that servos V to a

J

A

D

ITH

speciﬁed voltage and measures the resultant V

.

EAIN

3729fb

4

LTC3729

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs Output Current

(Figure 12)

Efﬁciency vs Output Current

(Figure 12)

Efﬁciency vs Input Voltage

(Figure 12)

100

80

60

40

20

0

100

90

100

90

80

70

60

50

V

OUT

= 3.3V

= 5V

= 20A

OUT

EXTVCC

V

= 5V

EXTVCC

I

f = 250kHz

V

= 5V

IN

V

= 0V

EXTVCC

= 8V

= 12V

= 20V

80

V

OUT

= 3.3V

OUT

EXTVCC

= 5V

= 20A

I

V

= 3.3V

OUT

f = 250kHz

10

OUTPUT CURRENT (A)

f = 250kHz

70

0.1

1

100

1

10

OUTPUT CURRENT (A)

100

5

10

15

20

V

(V)

IN

3729 G01

3729 G02

3729 G03

Supply Current vs Input Voltage

and Mode

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

EXTV_CCVoltage Drop

1000

800

600

400

200

0

250

200

150

100

50

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

INTV VOLTAGE

CC

ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

0

10

20

30

40

50

–50 –25

0

25

50

TEMPERATURE (°C)

75

100 125

0

5

10

15

20

25

30

35

INPUT VOLTAGE (V)

CURRENT (mA)

3729 G05

3729 G06

3729 G04

Maximum Current Sense Threshold

vs Percent of Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs Duty Factor

Internal 5V LDO Line Reg

5.1

5.0

75

50

25

0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

50

20

INPUT VOLTAGE (V)

30

35

0

25

75

100

0

5

10

15

25

0

20

40

60

80

100

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

3729 G09

3729 G07

3729 G08

3729fb

5

LTC3729

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Current Sense Threshold

vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

Current Sense Threshold

vs I_THVoltage

80

76

72

68

64

60

90

80

60

40

20

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

6

0

1

2

3

4

5

0

0.5

1.5

(V)

2

1

2.5

V

(V)

COMMON MODE VOLTAGE (V)

V

RUN/SS

ITH

3729 G10

3729 G11

3729 G12

Load Regulation

V_ITHvs V_RUN/SS

SENSE Pins Total Source Current

2.5

2.0

1.5

1.0

100

50

0.0

–0.1

–0.2

–0.3

–0.4

V

= 0.7V

OSENSE

FCB = 0V

= 15V

V

IN

FIGURE 1

0

–50

–100

0.5

0

2

3

4

5

6

1

2

4

0

6

0

1

2

3

4

5

V

(V)

V

COMMON MODE VOLTAGE (V)

RUN/SS

LOAD CURRENT (A)

SENSE

3729 G14

3729 G15

3729 G13

Maximum Current Sense

Threshold vs Temperature

RUN/SS Current vs Temperature

80

78

76

74

72

70

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3729 G17

3729 G19

3729fb

6

LTC3729

TYPICAL PERFORMANCE CHARACTERISTICS

Soft-Start Up (Figure 12)

Load Step (Figure 12)

V

ITH

I

OUT

1V/DIV

0/30A

V

ITH

1V/DIV

V

OUT

2V/DIV

V

OUT

200mV/DIV

V

RUNSS

2V/DIV

3729 G20

3729 G21

100ms/DIV

10µs/DIV

Current Sense Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

Oscillator Frequency

vs Temperature

35

33

31

29

27

25

10

8

700

600

V

= 5V

OUT

V

= 2.4V

PLLFLTR

500

400

300

200

100

V

= 1.2V

= 0V

PLLFLTR

6

V

4

PLLFLTR

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50

25

50

75

100 125

–25

0

TEMPERATURE (°C)

3729 G23

3729 G24

3729 G25

Undervoltage Lockout

vs Temperature

Shutdown Latch Thresholds

vs Temperature

3.50

3.45

3.40

3.35

4.5

LATCH ARMING

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3729 G26

3729 G27

3729fb

7

LTC3729

PIN FUNCTIONS ^{G Package/UH Package}

RUN/SS (Pin 1/Pin 28): Combination of Soft‑Start, Run

Control Input and Short‑Circuit Detection Timer. A capaci‑

tor to ground at this pin sets the ramp time to full current

output. Forcing this pin below 0.8V causes the IC to shut

down all internal circuitry. All functions are disabled in

shutdown.

V

(Pin 10/Pin 7): Output of a Differential Ampliﬁer

DIFFOUT

that provides true remote output voltage sensing. This pin

normally drives an external resistive divider that sets the

output voltage.

–

+

V

,V (Pins11,12/Pins8,9):InputstoanOperational

OS

Ampliﬁer. Internal precision resistors capable of being

electronically switched in or out can conﬁgure it as a dif‑

ferential ampliﬁer or an uncommitted Op Amp.

+

SENSE1 , SENSE2 (Pins 2,14/Pins 30, 12): The (+)

Input to the Differential Current Comparators. The I

pin voltage and built‑in offsets between SENSE and

SENSE pins in conjunction with R

trip threshold.

TH

–

PGOOD(Pin15/Pin13):Open‑DrainLogicOutput.PGOOD

is pulled to ground when the voltage on the EAIN pin is

not within ±7.5% of its set point.

+

set the current

SENSE

–

SENSE1 , SENSE2 (Pins 3, 13/Pins 31, 11): The (–)

TG2, TG1 (Pins 16, 27/Pins 14, 26): High Current Gate

DrivesforTopN‑ChannelMOSFETS.Thesearetheoutputs

Input to the Differential Current Comparators.

EAIN (Pin 4/Pin 1): Input to the Error Ampliﬁer that com‑

pares the feedback voltage to the internal 0.8V reference

voltage.Thispinisnormallyconnectedtoaresistivedivider

from the output of the differential ampliﬁer (DIFFOUT).

of ﬂoating drivers with a voltage swing equal to INTV

superimposed on the switch node voltage SW.

CC

SW2, SW1 (Pins 17, 26/Pins 15, 25): Switch Node

Connections to Inductors. Voltage swing at these pins

is from a Schottky diode (external) voltage drop below

PLLFLTR (Pin 5/Pin 2): The Phase‑Locked Loop’s Low

Pass Filter is tied to this pin. Alternatively, this pin can

be driven with an AC or DC voltage source to vary the

frequency of the internal oscillator.

ground to V .

IN

BOOST2,BOOST1(Pins18,25/Pins17,24):Bootstrapped

Supplies to the Topside Floating Drivers. Capacitors

are connected between the Boost and Switch pins and

PLLIN (Pin 6/Pin 3): External Synchronization Input to

Phase Detector. This pin is internally terminated to SGND

with 50kΩ. The phase‑locked loop will force the rising

top gate signal of controller 1 to be synchronized with

the rising edge of the PLLIN signal.

Schottky diodes are tied between the Boost and INTV

CC

pins. Voltage swing at the Boost pins is from INTV to

CC

(V + INTV ).

IN

CC

BG2, BG1 (Pins 19, 23/Pins 18, 22): High Current Gate

PHASMD (Pin 7/Pin 4): Control Input to Phase Selector

whichdeterminesthephaserelationshipsbetweencontrol‑

ler 1, controller 2 and the CLKOUT signal.

Drives for Bottom Synchronous N‑Channel MOSFETS.

Voltage swing at these pins is from ground to INTV .

CC

PGND (Pin 20/Pin 19): Driver Power Ground. Connect

I

TH

(Pin 8/Pin 5): Error Ampliﬁer Output and Switching

to sources of bottom N‑channel MOSFETS and the (–)

RegulatorCompensationPoint.Bothcurrentcomparator’s

thresholds increase with this control voltage. The normal

voltage range of this pin is from 0V to 2.4V.

terminals of C .

IN

INTV (Pin 21/Pin 20): Output of the Internal 5V Linear

CC

LowDropoutRegulatorandtheEXTV Switch. Thedriver

CC

SGND (Pin 9/Pin 6):Signal Ground, common to both con‑

trollers,mustberoutedseparatelyfromtheinputswitched

current ground path to the common (–) terminal(s) of the

and control circuits are powered from this voltage source.

Decouple to power ground with a 1µF ceramic capacitor

placed directly adjacent to the IC and minimum of 4.7µF

additional tantalum or other low ESR capacitor.

C

capacitor(s).

OUT

3729fb

8

LTC3729

PIN FUNCTIONS ^{G Package/UH Package}

EXTV (Pin 22/Pin 21): External Power Input to an

V (Pin 24/Pin 23): Main Supply Pin. Should be closely

CC

IN

Internal Switch . This switch closes and supplies INTV ,

decoupled to the IC’s signal ground pin.

CC

bypassing the internal low dropout regulator whenever

CLKOUT (Pin 28/Pin 27): Output Clock Signal available

to daisychain other controller ICs for additional MOSFET

driver stages/phases.

EXTV is higher than 4.7V. See EXTV Connection in

CC

the Applications Information section. Do not exceed 7V

on this pin and ensure V

≤ V

.

EXTVCC

INTVCC

FUNCTIONAL DIAGRAM

PLLIN

INTV

CC

V

IN

PHASE DET

F

IN

50k

PLLLPF

D

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

B

BOOST

TG

R

C

LP

C

B

DROP

OUT

DET

+

CLKOUT

CLK1

CLK2

TOP

C

LP

IN

OSCILLATOR

PHASE LOGIC

BOT FCB

FORCE BOT

SW

S

Q

SWITCH

LOGIC

PHASMD

INTV

CC

R

BG

±2µA

BOT

DIFFOUT

PGND

40k

–

V

OS

SHDN

A1

INTV

L

CC

–

+

OS

I1

+

–

SENSE

30k

–

+

40k

+

0.86V

4(V

R

SENSE

–

C

OUT

)

SENSE

FB

PGOOD

–

+

0.86V

SLOPE

COMP

45k

2.4V

V

OUT

EAIN

–

+

EAIN

0.74V

R1

–

+

EA

V

0.80V

REF

0.80V

0.86V

V

IN

R2

V

OV

IN

+

–

+

–

4.7V

5V

LDO

REG

C

I

TH

EXTV

INTV

CC

1.2µA

SHDN

RST

RUN

SOFT

START

R

C

CC

5V

+

4(V

)

FB

6V

INTERNAL

SUPPLY

RUN/SS

SGND

C

SS

3729 FBD

3729fb

9

LTC3729

OPERATION ^{(Refer to Functional Diagram)}

Main Control Loop

Low Current Operation

The LTC3729 uses a constant frequency, current mode

step‑down architecture. During normal operation, the

top MOSFET is turned on each cycle when the oscillator

sets the RS latch, and turned off when the main current

comparator, I1, resets the RS latch. The peak inductor

current at which I1 resets the RS latch is controlled by

TheLTC3729operatesinacontinuous,PWMcontrolmode.

The resulting operation at low output currents optimizes

transient response at the expense of substantial negative

inductorcurrentduringthelatterpartoftheperiod.Thelevel

of ripple current is determined by the inductor value, input

voltage, output voltage, and frequency of operation.

the voltage on the I pin, which is the output of the error

TH

Frequency Synchronization

ampliﬁer EA. The differential ampliﬁer, A1, produces a

signal equal to the differential voltage sensed across the

output capacitor but re‑references it to the internal signal

ground (SGND) reference. TheEAINpinreceives aportion

of this voltage feedback signal at the DIFFOUT pin which is

comparedtotheinternalreferencevoltagebytheEA.When

the load current increases, it causes a slight decrease in

the EAIN pin voltage relative to the 0.8V reference, which

The phase‑locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DCfrequencycontrolinputoftheoscillatorthatoperatesover

a 250kHz to 550kHz range corresponding to a DC voltage

input from 0V to 2.4V. When locked, the PLL aligns the turn

onofthetopMOSFETtotherisingedgeofthesynchronizing

signal. When PLLIN is left open, the PLLFLTR pin goes low,

forcing the oscillator to minimum frequency.

in turn causes the I voltage to increase until the average

TH

inductor current matches the new load current. After the

top MOSFET has turned off, the bottom MOSFET is turned

on for the rest of the period.

The internal master oscillator runs at a frequency twelve

times that of each controller’s frequency. The PHASMD

pin determines the relative phases between the internal

controllers as well as the CLKOUT signal as shown in

Table 1. The phases tabulated are relative to zero phase

being deﬁned as the rising edge of the top gate (TG1)

driver output of controller 1.

ThetopMOSFETdriversarebiasedfromﬂoatingbootstrap

capacitor C , which normally is recharged during each

B

off cycle through an external Schottky diode. When V

IN

decreases to a voltage close to V , however, the loop

OUT

may enter dropout and attempt to turn on the top MOSFET

continuously.Adropoutdetectordetectsthisconditionand

forces the top MOSFET to turn off for about 400ns every

10th cycle to recharge the bootstrap capacitor.

Table 1.

V

GND

180°

60°

OPEN

180°

90°

INTV

CC

PHASMD

Controller 2

CLKOUT

240°

120°

The main control loop is shut down by pulling Pin 1

(RUN/SS)low.ReleasingRUN/SSallowsaninternal1.2µA

current source to charge soft‑start capacitor C . When

The CLKOUT signal can be used to synchronize additional

powerstagesinamultiphasepowersupplysolutionfeeding

a single, high current output or separate outputs. Input

capacitance ESR requirements and efﬁciency losses are

substantiallyreducedbecausethepeakcurrentdrawnfrom

the input capacitor is effectively divided by the number

of phases used and power loss is proportional to the

RMS current squared. A two stage, single output voltage

implementation can reduce input path power loss by 75%

and radically reduce the required RMS current rating of

the input capacitor(s).

SS

C

I

reaches1.5V, themaincontrolloopisenabledwiththe

SS

TH

voltageclampedatapproximately30%ofitsmaximum

value.AsC continuestocharge,I isgraduallyreleased

SS

TH

allowing normal operation to resume. When the RUN/SS

pin is low, all LTC3729 functions are shut down. If V

OUT

has not reached 70% of its nominal value when C has

SS

charged to 4.1V, an overcurrent latchoff can be invoked as

described in the Applications Information section.

3729fb

10

LTC3729

OPERATION ^{(Refer to Functional Diagram)}

INTV /EXTV Power

the feedback divider. When the output is within ±7.5% of

its nominal value, the MOSFET is turned off within 10µs

and the PGOOD pin should be pulled up by an external

resistor to a source of up to 7V.

CC

PowerforthetopandbottomMOSFETdriversandmostof

the IC circuitry is derived from INTV . When the EXTV

CC

pin is left open, an internal 5V low dropout regulator

supplies INTV power. If the EXTV pin is taken above

CC

Short-Circuit Detection

4.7V, the 5V regulator is turned off and an internal switch

The RUN/SS capacitor is used initially to limit the inrush

current from the input power source. Once the controllers

have been given time, as determined by the capacitor on

the RUN/SS pin, to charge up the output capacitors and

provide full load current, the RUN/SS capacitor is then

used as a short‑circuit timeout circuit. If the output volt‑

age falls to less than 70% of its nominal output voltage

the RUN/SS capacitor begins discharging assuming that

the output is in a severe overcurrent and/or short‑circuit

condition. If the condition lasts for a long enough period

as determined by the size of the RUN/SS capacitor, the

controller will be shut down until the RUN/SS pin voltage

is recycled. This built‑in latchoff can be overidden by

providing a >5µA pull‑up current at a compliance of 5V

to the RUN/SS pin. This current shortens the soft‑start

period but also prevents net discharge of the RUN/SS

capacitor during a severe overcurrent and/or short‑circuit

condition. Foldback current limiting is activated when the

outputvoltagefallsbelow70%ofitsnominallevelwhether

or not the short‑circuit latchoff circuit is enabled.

is turned on connecting EXTV to INTV . This allows

CC

the INTV power to be derived from a high efﬁciency

CC

external source such as the output of the regulator itself

or a secondary winding, as described in the Applications

Information section. An external Schottky diode can be

used to minimize the voltage drop from EXTV to INTV

CC

in applications requiring greater than the speciﬁed INTV

current. Voltages up to 7V can be applied to EXTV for

CC

additional gate drive capability.

Differential Ampliﬁer

This ampliﬁer provides true differential output voltage

+

–

sensing.SensingbothV

andV

beneﬁtsregulation

OUT

in high current applications and/or applications having

electrical interconnection losses.

Power Good (PGOOD)

The PGOOD pin is connected to the drain of an internal

MOSFET. The MOSFET turns on when the output is not

within ±7.5% of its nominal output level as determined by

APPLICATIONS INFORMATION

R

Selection For Output Current

SENSE

ThebasicLTC3729applicationcircuitisshowninFigure 1

on the ﬁrst page. External component selection is driven

by the load requirement, and begins with the selection

R

are chosen based on the required output cur‑

SENSE1, 2

rent. The LTC3729 current comparator has a maximum

of R

. Once R

are known, L1 and L2 can

SENSE1, 2

threshold of 75mV/R

and an input common mode

SENSE

be chosen. Next, the power MOSFETs and D1 and D2 are

selected. The operating frequency and the inductor are

chosen based mainly on the amount of ripple current.

range of SGND to 1.1( INTV ). The current comparator

CC

threshold sets the peak inductor current, yielding a maxi‑

mum average output current I

less half the peak‑to‑peak ripple current, ∆I .

equal to the peak value

MAX

Finally, C is selected for its ability to handle the input

IN

L

ripple current (that PolyPhase operation minimizes) and

AllowingamarginforvariationsintheLTC3729andexternal

component values yields:

C

is chosen with low enough ESR to meet the output

OUT

ripplevoltageandloadstepspeciﬁcations(alsominimized

with PolyPhase). The circuit shown in Figure 1 can be

conﬁgured for operation up to an input voltage of 28V

(limited by the external MOSFETs).

R

= (50mV/I

)N

SENSE

MAX

where N = number of stages.

3729fb

11

LTC3729

APPLICATIONS INFORMATION

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁciency. A higher

frequency generally results in lower efﬁciency because

of MOSFET gate charge and transition losses. In addi‑

tion to this basic tradeoff, the effect of inductor value on

ripple current and low current operation must also be

considered. The PolyPhase approach reduces both input

and output ripple currents while optimizing individual

output stages to run at a lower fundamental frequency,

enhancing efﬁciency.

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

internal slope compensation required to meet stability

criterionforbuckregulatorsoperatingatgreaterthan50%

duty factor. A curve is provided to estimate this reduction

in peak output current level depending upon the operating

duty factor.

Operating Frequency

The LTC3729 uses a constant frequency, phase‑lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a ﬁxed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase‑Locked Loop

and Frequency Synchronization in the Applications Infor‑

mation section for additional information.

The inductor value has a direct effect on ripple current.

The inductor ripple current ∆I per individual section,

L

N, decreases with higher inductance or frequency and

increases with higher V or V

:

IN

OUT





V_OUT

fL

V_OUT

V_IN

∆I_L=

1−









A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 2. As the operating frequency

isincreasedthegatechargelosseswillbehigher, reducing

efﬁciency (see Efﬁciency Considerations). The maximum

switching frequency is approximately 550kHz.

where f is the individual output stage operating frequency.

In a PolyPhase converter, the net ripple current seen by

the output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

2.5

2.0

1.5

1.0

0.5

Figure 3 shows the net ripple current seen by the output

capacitorsforthedifferentphaseconﬁgurations.Theoutput

ripple current is plotted for a ﬁxed output voltage as the

duty factor is varied between 10% and 90% on the x‑axis.

Theoutputripplecurrentisnormalizedagainsttheinductor

ripple current at zero duty factor. The graph can be used

in place of tedious calculations. As shown in Figure 3, the

zero output ripple current is obtained when:

0

200 250 300 350 400 450 500 550

OPERATING FREQUENCY (kHz)

3729 F02

V_OUT

V_IN

k

N

=

where k = 1, 2, …, N – 1

Figure 2. Operating Frequency vs V_PLLFLTR

Sothenumberofphasesusedcanbeselectedtominimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In appli‑

cations having a highly varying input voltage, additional

phases will produce the best results.

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter‑

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

3729fb

12

LTC3729

APPLICATIONS INFORMATION

1.0

ripple current and consequent output voltage ripple. Do

1-PHASE

0.9

2-PHASE

not allow the core to saturate!

3-PHASE

4-PHASE

6-PHASE

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive

than ferrite. A reasonable compromise from the same

manufacturer is Kool Mµ. Toroids are very space efﬁ‑

cient, especially when you can use several layers of wire.

Because they lack a bobbin, mounting is more difﬁcult.

However, designs for surface mount are available which

do not increase the height signiﬁcantly.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3729 F03

Power MOSFET, D1 and D2 Selection

Figure 3. Normalized Peak Output Current vs

Two external power MOSFETs must be selected for each

controller with the LTC3729: One N‑channel MOSFET for

the top (main) switch, and one N‑channel MOSFET for the

bottom (synchronous) switch.

Duty Factor [I_RMS≈ 0.3 (∆I_O(P–P))]

Accepting larger values of ∆I allows the use of low in‑

L

ductances, but can result in higher output voltage ripple.

A reasonable starting point for setting ripple current is

Thepeak‑to‑peakdrivelevelsaresetbytheINTV voltage.

Thisvoltageistypically5Vduringstart‑up(seeEXTV Pin

CC

∆I = 0.4(I )/N, where N is the number of channels and

L

OUT

L

OUT

CC

I

is the total load current. Remember, the maximum

Connection).Consequently,logic‑levelthresholdMOSFETs

must be used in most applications. The only exception

∆I occurs at the maximum input voltage. The individual

inductor ripple currents are constant determined by the

is if low input voltage is expected (V < 5V); then, sub‑

IN

GS(TH)

inductor, input and output voltages.

logic‑level threshold MOSFETs (V

< 3V) should be

speciﬁcation for

used. Pay close attention to the BV

DSS

Inductor Core Selection

the MOSFETs as well; most of the logic‑level MOSFETs

are limited to 30V or less.

Once the values for L1 and L2 are known, the type of

inductor must be selected. High efﬁciency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of more expensive

ferrite,molypermalloy,orKoolMµ^®cores.Actualcoreloss

is independent of core size for a ﬁxed inductor value, but it

is very dependent on inductance selected. As inductance

increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore cop‑

per losses will increase.

Selection criteria for the power MOSFETs include the

“ON” resistance R

RSS

, reverse transfer capacitance

DS(ON)

C

, input voltage, and maximum output current. When

the LTC3729 is operating in continuous mode the duty

factors for the top and bottom MOSFETs of each output

stage are given by:

V_OUT

Main SwitchDuty Cycle=

V_IN

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con‑

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc‑

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

Kool Mµ is a registered trademark of Magnetics, Inc.





V_IN– V_OUT

V_IN

Synchronous SwitchDuty Cycle=









The MOSFET power dissipations at maximum output

current are given by:

3729fb

13

LTC3729

APPLICATIONS INFORMATION

2

C and C

Selection

IN

OUT

V_OUT

V_IN

I



_MAX



P_MAIN

=

1+ d R

+

(

)





DS(ON)



In continuous mode, the source current of each top

N‑channel MOSFET is a square wave of duty cycle

N

I

₂ _MAX

k V

(

C

f

( )

V /V .AlowESRinputcapacitorsizedforthemaximum

OUT IN

)

(

)

IN 



RSS





N

RMS current must be used. The details of a close form

equation can be found in Application Note 77. Figure 4

showstheinputcapacitorripplecurrentfordifferentphase

conﬁgurationswiththeoutputvoltageﬁxedandinputvolt‑

age varied. The input ripple current is normalized against

the DC output current. The graph can be used in place of

tedious calculations. The minimum input ripple current

can be achieved when the product of phase number and

2

V_IN– V_OUT

V_IN

I



_MAX



P_SYNC

=

1+ d R

DS(ON)

(

)







N

where d is the temperature dependency of R

, k is a

DS(ON)

constant inversely related to the gate drive current and N

is the number of stages.

2

output voltage, N(V ), is approximately equal to the

input voltage V or:

OUT

Both MOSFETs have I R losses but the topside N‑channel

IN

equation includes an additional term for transition losses,

which peak at the highest input voltage. For V < 20V

IN

V_OUT

V_IN

k

N

the high current efﬁciency generally improves with larger

=

where k = 1, 2, …, N – 1

MOSFETs, while for V > 20V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

So the phase number can be chosen to minimize the input

capacitor size for the given input and output voltages.

with lower C

actual provides higher efﬁciency. The

RSS

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short‑circuit when the synchronous switch is on close

to 100% of the period.

In the graph of Figure 4, the local maximum input RMS

capacitor currents are reached when:

V_OUT

V_IN

2k − 1

2N

=

The term (1 + d) is generally given for a MOSFET in the

where k = 1, 2, …, N

form of a normalized R

vs. Temperature curve,

DS(ON)

but d = 0.005/°C can be used as an approximation for

0.6

0.5

0.4

0.3

0.2

0.1

0

low voltage MOSFETs. C is usually speciﬁed in the

RSS

MOSFET characteristics. The constant k = 1.7 can be used

to estimate the contributions of the two terms in the main

switch dissipation equation.

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

The Schottky diodes, D1 and D2 shown in Figure 1 conduct

duringthedead‑timebetweentheconductionofthetwolarge

power MOSFETs. This helps prevent the body diode of the

bottomMOSFETfromturningon, storingchargeduringthe

dead‑time, and requiring a reverse recovery period which

would reduce efﬁciency. A 1A to 3A (depending on output

current)Schottkydiodeisgenerallyagoodcompromisefor

bothregionsofoperationduetotherelativelysmallaverage

current. Larger diodes result in additional transition losses

due to their larger junction capacitance.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

3729 F04

Figure 4. Normalized Input RMS Ripple Current vs

Duty Factor for 1 to 6 Output Stages

These worst‑case conditions are commonly used for

design because even signiﬁcant deviations do not offer

much relief. Note that capacitor manufacturer’s ripple

current ratings are often based on only 2000 hours of life.

3729fb

14

LTC3729

APPLICATIONS INFORMATION

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design. Always consult

the capacitor manufacturer if there is any question.

capacitor type are signiﬁcantly different than an ideal

capacitor and therefore require accurate modeling or

bench evaluation during design.

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough‑

hole capacitors. The OS‑CON semiconductor dielectric

capacitor available from Sanyo and the Panasonic SP

surface mount types have the lowest (ESR)(size) product

of any aluminum electrolytic at a somewhat higher price.

An additional ceramic capacitor in parallel with OS‑CON

type capacitors is recommended to reduce the inductance

effects.

The graph shows that the peak RMS input current is

reduced linearly, inversely proportional to the number, N

of stages used. It is important to note that the efﬁciency

loss is proportional to the input RMS current squared

and therefore a 2‑stage implementation results in 75%

less power loss when compared to a single phase design.

Battery/inputprotectionfuseresistance(ifused),PCboard

trace and connector resistance losses are also reduced by

the reduction of the input ripple current in a PolyPhase

system.Therequiredamountofinputcapacitanceisfurther

reduced by the factor, N, due to the effective increase in

the frequency of the current pulses.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handling requirements of the application. Aluminum

electrolytic and dry tantalum capacitors are both available

in surface mount conﬁgurations. New special polymer

surface mount capacitors offer very low ESR also but

have much lower capacitive density per unit volume. In

the case of tantalum, it is critical that the capacitors are

surge tested for use in switching power supplies. Several

excellentchoicesaretheAVXTPS,AVXTPSVortheKEMET

T510 series of surface mount tantalums, available in case

heights ranging from 2mm to 4mm. Other capacitor types

include Sanyo OS‑CON, Nichicon PL series and Sprague

595D series. Consult the manufacturer for other speciﬁc

recommendations. A combination of capacitors will often

result in maximizing performance and minimizing overall

cost and size.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require‑

ment has been met, the RMS current rating generally far

exceeds the I

requirements. The steady state

RIPPLE(P‑P)

output ripple (∆V ) is determined by:

OUT









1

∆V_OUT≈ ∆I_RIPPLEESR+



8NfC_OUT



Where f = operating frequency of each stage, N is the

number of phases, C = output capacitance, and

OUT

∆I

= combined inductor ripple currents.

RIPPLE

The output ripple varies with input voltage since ∆I is a

L

INTV Regulator

CC

function of input voltage. The output ripple will be less than

50mV at max V with ∆I = 0.4I /N assuming:

An internal P‑channel low dropout regulator produces

IN

L

OUT(MAX)

5V at the INTV pin from the V supply pin. The INTV

CC

IN

CC

C

required ESR < 2N(R

) and

SENSE

OUT

regulator powers the drivers and internal circuitry of the

> 1/(8Nf)(R

)

LTC3729. The INTV pin regulator can supply up to

OUT

SENSE

CC

50mA peak and must be bypassed to power ground with

a minimum of 4.7µF tantalum or electrolytic capacitor. An

additional1µFceramiccapacitorplacedveryclosetotheIC

is recommended due to the extremely high instantaneous

currents required by the MOSFET gate drivers.

The emergence of very low ESR capacitors in small,

surface mount packages makes very physically small

implementations possible. The ability to externally

compensate the switching regulator loop using the

I

pin(OPTI‑LOOP compensation) allows a much

TH

wider selection of output capacitor types. OPTI‑LOOP

compensation effectively removes constraints on output

capacitor ESR. The impedance characteristics of each

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the

3729fb

15

LTC3729

APPLICATIONS INFORMATION

maximum junction temperature rating for the LTC3729 to

be exceeded. The supply current is dominated by the gate

charge supply current, in addition to the current drawn

from the differential ampliﬁer output. The gate charge is

dependent on operating frequency as discussed in the

Efﬁciency Considerations section. The supply current can

either be supplied by the internal 5V regulator or via the

with the LTC3729’s V pin and a Schottky diode between

IN

the EXTV and the V pin, to prevent current from

CC

IN

backfeeding V .

IN

Signiﬁcant efﬁciency gains can be realized by powering

INTV from the output, since the V current resulting

CC

IN

from the driver and control currents will be scaled by the

ratio: (Duty Factor)/(Efﬁciency). For 5V regulators this

EXTV pin. When the voltage applied to the EXTV pin

CC

means connecting the EXTV pin directly to V

.

OUT

CC

is less than 4.7V, all of the INTV load current is supplied

CC

However, for 3.3V and other lower voltage regulators,

by the internal 5V linear regulator. Power dissipation for

additional circuitry is required to derive INTV power

CC

the IC is higher in this case by (I )(V – INTV ) and

IN

CC

from the output.

efﬁciency is lowered. The junction temperature can be

The following list summarizes the four possible connec‑

estimated by using the equations given in Note 1 of the

tions for EXTV :

Electrical Characteristics. For example, the LTC3729 V

CC

IN

current is limited to less than 24mA from a 24V supply:

1. EXTV left open (or grounded). This will cause INTV

CC

to be powered from the internal 5V regulator resulting in

T = 70°C + (24mA)(24V)(95°C/W) = 125°C

J

a signiﬁcant efﬁciency penalty at high input voltages.

Use of the EXTV pin reduces the junction temperature

CC

2. EXTV connected directly to V . This is the normal

to:

CC

OUT

connection for a 5V regulator and provides the highest

T = 70°C + (24mA)(5V)(95°C/W) = 81.4°C

J

efﬁciency.

The input supply current should be measured while

thecontrollerisoperatingincontinuousmodeatmaximum

IN

prevent the maximum junction temperature from being

exceeded.

3. EXTV connected to an external supply. If an external

CC

supply is available in the 5V to 7V range, it may be used to

V

and the power dissipation calculated in order to

powerEXTV providing itis compatible withthe MOSFET

CC

gate drive requirements. V must be greater than or equal

IN

to the voltage applied to the EXTV pin.

CC

EXTV Connection

4. EXTV connected to an output‑derived boost network.

CC

For 3.3V and other low voltage regulators, efﬁciency gains

The LTC3729 contains an internal P‑channel MOSFET

can still be realized by connecting EXTV to an output‑

CC

switch connected between the EXTV and INTV pins.

CC

derived voltage which has been boosted to greater than

4.7V but less than 7V. This can be done with either the

inductive boost winding as shown in Figure 5a or the

capacitive charge pump shown in Figure 5b. The charge

pump has the advantage of simple magnetics.

When the voltage applied to EXTV rises above 4.7V,

the internal regulator is turned off and the switch closes,

connecting the EXTV pin to the INTV pin thereby

CC

supplying internal and MOSFET gate driving power. The

switch remains closed as long as the voltage applied to

EXTV remains above 4.5V. This allows the MOSFET

CC

Topside MOSFET Driver Supply (CB,DB) (Refer to

Functional Diagram)

driver and control power to be derived from the output

during normal operation (4.7V < V

< 7V) and from

EXTVCC

External bootstrap capacitors C and C connected

the internal regulator when the output is out of regulation

(start‑up, short‑circuit). Do not apply greater than 7V

to the EXTV pin and ensure that EXTV < V + 0.3V

B1

B2

to the BOOST1 and BOOST2 pins supply the gate drive

voltages for the topside MOSFETs. Capacitor C in the

B

CC

IN

Functional Diagram is charged though diode D from

when using the application circuits shown. If an external

voltage source is applied to the EXTV pin when the V

supply is not present, a diode can be placed in series

B

INTV whentheSWpinislow.WhenthetopsideMOSFET

CC

IN

turns on, the driver places the C voltage across the

B

3729fb

16

LTC3729

APPLICATIONS INFORMATION

+

V

OPTIONAL EXTV CONNECTION

CC

+

IN

1µF

C

V

5V < V

< 7V

V

IN

SEC

+

IN

C

IN

LTC3729

IN

BAT85

0.22µF

BAT85

LTC3729

V

IN

1N4148

6.8V

TG1

V

SEC

TG1

+

N-CH

VN2222LL

1mF

V

EXTV

CC

N-CH

EXTV

R

CC

SENSE

R

SENSE

V

SW1

BG1

OUT

SW1

BG1

OUT

L1

T1

+

C

OUT

C

OUT

N-CH

PGND

3729 F05b

3729 F05a

Figure 5a. Secondary Output Loop and EXTV_CCConnection

Figure 5b. Capacitive Charge Pump for EXTV_CC

gate‑source of the desired MOSFET. This enhances the

MOSFET and turns on the topside switch. The switch node

current. The output voltage is set by an external resistive

divider according to the following formula:

voltage, SW, rises to V and the BOOST pin rises to V +

IN

V

. The value of the boost capacitor C needs to be

R1

R2







INTVCC

B

V_OUT= 0.8V 1+







30 to 100 times that of the total input capacitance of the

topside MOSFET(s). The reverse breakdown of D must

B

be greater than V

.

where R1 and R2 are deﬁned in the Functional Diagram.

IN(MAX)

Theﬁnalarbiterwhendeﬁningthebestgatedriveamplitude

level will be the input supply current. If a change is made

that decreases input current, the efﬁciency has improved.

If the input current does not change then the efﬁciency

has not changed either.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut‑

down,2)soft‑startand3)adefeatableshort‑circuitlatchoff

timer. Soft‑start reduces the input power sources’ surge

currents by gradually increasing the controller’s current

Differential Ampliﬁer/Output Voltage

limit I

. The latchoff timer prevents very short, ex‑

TH(MAX)

treme load transients from tripping the overcurrent latch.

A small pull‑up current (>5µA) supplied to the RUN/SS

pin will prevent the overcurrent latch from operating.

The following explanation describes how the functions

operate.

The LTC3729 has a true remote voltage sense capablity.

Thesensingconnectionsshouldbereturnedfromtheload

backtothedifferentialampliﬁer’sinputsthroughacommon,

tightly coupled pair of PC traces. The differential ampliﬁer

rejects common mode signals capacitively or inductively

radiated into the feedback PC traces as well as ground

loop disturbances. The differential ampliﬁer output signal

is divided down and compared with the internal precision

0.8V voltage reference by the error ampliﬁer.

An internal 1.2µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS reaches 1.5V, the

controllerispermittedtostartoperating. Asthevoltageon

RUN/SS increases from 1.5V to 3.0V, the internal current

limit is increased from 25mV/R

to 75mV/R

.

SENSE

The differential ampliﬁer utilizes a set of internal preci‑

sion resistors to enable precision instrumentation‑type

measurement of the output voltage. The output is an NPN

emitter follower without any internal pull‑down current.

A DC resistive load to ground is required in order to sink

The output current limit ramps up slowly, taking an ad‑

ditional 1.4µs/µF to reach full current. The output current

thus ramps up slowly, reducing the starting surge current

required from the input power supply. If RUN/SS has been

3729fb

17

LTC3729

APPLICATIONS INFORMATION

pulled all the way to ground there is a delay before starting

of approximately:

V

INTV

IN

CC

R

3.3V OR 5V

RUN/SS

*

R

SS

*

SS

D1

RUN/SS

1.5V

1.2µA

D1*

t_DELAY

=

C = 1.25s / µF C

SS SS

(

)

C

SS

C

SS

The time for the output current to ramp up is then:

3V − 1.5V

1.2µA

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

3729 F06

t_RAMP

=

C = 1.25s / µF C

SS SS

(

)

Figure 6. RUN/SS Pin Interfacing

By pulling the RUN/SS pin below 0.8V the LTC3729 is

condition. When deriving the 5µA current from V as

IN

put into low current shutdown (I < 40µA). RUN/SS can

in the ﬁgure, current latchoff is always defeated. Diode‑

Q

be driven directly from logic as shown in Figure 6. Diode

connecting this pull‑up resistor to INTV , as in Figure 6,

CC

D1 in Figure 6 reduces the start delay but allows C to

eliminates any extra supply current during shutdown

SS

ramp up slowly providing the soft‑start function. The

RUN/SSpinhasaninternal6Vzenerclamp(seeFunctional

Diagram).

while eliminating the INTV loading from preventing

CC

controller start‑up.

Why should you defeat current latchoff? During the pro‑

totyping stage of a design, there may be a problem with

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short‑circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com‑

plete whether to rely solely on foldback current limiting

or to enable the latchoff feature by removing the pull‑up

resistor.

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the

controllers when an overcurrent condition is detected.

The RUN/SS capacitor, C , is used initially to limit the

SS

inrush current of both controllers. After the controllers

have been started and been given adequate time to charge

up the output capacitors and provide full load current, the

RUN/SS capacitor is used for a short‑circuit timer. If the

output voltage falls to less than 70% of its nominal value

after C reaches 4.1V, C begins discharging on the as‑

SS

The value of the soft‑start capacitor C may need to

SS

sumption that the output is in an overcurrent condition. If

be scaled with output voltage, output capacitance and

load current characteristics. The minimum soft‑start

capacitance is given by:

theconditionlastsforalongenoughperiodasdetermined

by the size of C , the controller will be shut down until

SS

the RUN/SS pin voltage is recycled. If the overload occurs

‑4

during start‑up, the time can be approximated by:

C

SS

> (C

)(V )(10 )(R

)

OUT

SENSE

5

t

≈ (C • 0.6V)/(1.2µA) = 5 • 10 (C )

The minimum recommended soft‑start capacitor of C

0.1µF will be sufﬁcient for most applications.

=

LO1

SS

If the overload occurs after start‑up, the voltage on C

will continue charging and will provide additional time

SS

Phase-Locked Loop and Frequency Synchronization

before latching off:

The LTC3729 has a phase‑locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn‑on to be locked to the

rising edge of an external source. The frequency range

of the voltage controlled oscillator is ±50% around the

6

t

≈ (C • 3V)/(1.2µA) = 2.5 • 10 (C )

LO2

SS

This built‑in overcurrent latchoff can be overridden by

providing a pull‑up resistor, R , to the RUN/SS pin as

shown in Figure 6. This resistance shortens the soft‑

start period and prevents the discharge of the RUN/SS

capacitor during a severe overcurrent and/or short‑circuit

SS

center frequency f . A voltage applied to the PLLFLTR

O

pin of 1.2V corresponds to a frequency of approximately

3729fb

18

LTC3729

APPLICATIONS INFORMATION

400kHz. The nominal operating frequency range of the

LTC3729 is 250kHz to 550kHz.

a voltage that will guarantee the slave oscillator(s) ability

to lock onto the master’s frequency. A DC voltage of

0.7V to 1.7V applied to the master oscillator’s PLLFLTR

pin is recommended in order to meet this requirement.

The resultant operating frequency will be approximately

500kHz.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the ex‑

ternal and internal oscillators. This type of phase detector

willnotlockuponinputfrequenciesclosetotheharmonics

The loop ﬁlter components (C , R ) smooth out the cur‑

of the VCO center frequency. The PLL hold‑in range, ∆f ,

LP LP

H

rent pulses from the phase detector and provide a stable

is equal to the capture range, ∆f :

C

input to the voltage controlled oscillator. The ﬁlter compo‑

∆f = ∆f = ±0.5 f (250kHz‑550kHz)

H

C

O

nents C and R determine how fast the loop acquires

LP

Theoutputofthephasedetectorisacomplementarypairof

current sources charging or discharging the external ﬁlter

network on the PLLFLTR pin. A simpliﬁed block diagram

is shown in Figure 7.

lock. Typically R =10k and C is 0.01µF to 0.1µF.

LP

Minimum On-Time Considerations

Minimum on‑time t is the smallest time duration

ON(MIN)

that the LTC3729 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on‑time

limit and care should be taken to ensure that:

2.4V

R

10k

LP

PHASE

DETECTOR

C

LP

EXTERNAL

OSC

PLLFLTR

PLLIN

DIGITAL

PHASE/

OSC

FREQUENCY

DETECTOR

V_OUT

V f

_IN( )

50k

t_{ON MIN}

<

(

)

If the duty cycle falls below what can be accommodated

by the minimum on‑time, the LTC3729 will begin to skip

cycles resulting in nonconstant frequency operation. The

output voltage will continue to be regulated, but the ripple

current and ripple voltage will increase.

3729 F07

Figure 7. Phase-Locked Loop Block Diagram

If the external frequency (f

) is greater than the os‑

PLLIN

cillator frequency f , current is sourced continuously,

The minimum on‑time for the LTC3729 is approximately

100ns. However, as the peak sense voltage decreases

the minimum on‑time gradually increases. This is of

particular concern in forced continuous applications with

low ripple current at light loads. If the duty cycle drops

below the minimum on‑time limit in this situation, a

signiﬁcant amount of cycle skipping can occur with cor‑

respondingly larger current and voltage ripple.

0SC

pullingupthePLLFLTRpin.Whentheexternalfrequencyis

less than f , current is sunk continuously, pulling down

0SC

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. Thus the voltage on the PLLFLTR

pin is adjusted until the phase and frequency of the ex‑

ternal and internal oscillators are identical. At this stable

operating point the phase comparator output is open and

Ifanapplicationcanoperateclosetotheminimumon‑time

limit, an inductor must be chosen that has a low enough

inductance to provide sufﬁcient ripple amplitude to meet

the minimum on‑time requirement. As a general rule,

keep the inductor ripple current of each phase equal to or

the ﬁlter capacitor C holds the voltage. The LTC3729

LP

PLLIN pin must be driven from a low impedance source

such as a logic gate located close to the pin. When us‑

ing multiple LTC3729’s for a phase‑locked system, the

PLLFLTR pin of the master oscillator should be biased at

greater than 15% of I

/N at V

.

OUT(MAX)

IN(MAX)

3729fb

19

LTC3729

APPLICATIONS INFORMATION

Voltage Positioning

2

2) INTV regulator current, 3) I R losses and 4) Topside

CC

MOSFET transition losses.

Voltage positioning can be used to minimize peak‑to‑peak

output voltage excursions under worst‑case transient

loading conditions. The open‑loop DC gain of the control

loop is reduced depending upon the maximum load step

speciﬁcations. Voltage positioning can easily be added to

1) The V current has two components: the ﬁrst is the

IN

DC supply current given in the Electrical Characteristics

table,whichexcludesMOSFETdriverandcontrolcurrents;

the second is the current drawn from the differential

the LTC3729 by loading the I pin with a resistive divider

ampliﬁer output. V current typically results in a small

TH

IN

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage range of the error ampliﬁer, or

1.2V (see Figure 8).

(<0.1%) loss.

2) INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high

INTV

CC

R

T2

to low again, a packet of charge dQ moves from INTV

to ground. The resulting dQ/dt is a current out of INTV

CC

I

TH

LTC3729

R

T1

R

C

that is typically much larger than the control circuit cur‑

rent. In continuous mode, I = (Q + Q ), where

C

GATECHG

T

B

3729 F08

Q and Q are the gate charges of the topside and bottom

T

B

side MOSFETs.

Figure 8. Active Voltage Positioning Applied to the LTC3729

Supplying INTV power through the EXTV switch input

CC

The resistive load reduces the DC loop gain while main‑

taining the linear control range of the error ampliﬁer.

The maximum output voltage deviation can theoretically

be reduced to half or alternatively the amount of output

capacitance can be reduced for a particular application.

A complete explanation is included in Design Solutions

10. (See www.linear‑tech.com)

from an output‑derived source will scale the V current

IN

requiredforthedriverandcontrolcircuitsbytheratio(Duty

Factor)/(Efﬁciency).Forexample,ina20Vto5Vapplication,

10mA of INTV current results in approximately 3mA of

CC

V current. This reduces the mid‑current loss from 10%

IN

or more (if the driver was powered directly from V ) to

IN

only a few percent.

2

3) I R losses are predicted from the DC resistances of the

Efﬁciency Considerations

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

R

, but is “chopped” between the topside MOSFET

SENSE

and the synchronous MOSFET. If the two MOSFETs have

approximately the same R

, then the resistance of

DS(ON)

one MOSFET can simply be summed with the resistances

2

of L, R

if each R

and ESR to obtain I R losses. For example,

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

SENSE

=10mΩ, R =10mΩ, and R

=5mΩ,

DS(ON)

L

SENSE

where L1, L2, etc. are the individual losses as a percent‑

age of input power.

then the total resistance is 25mΩ. This results in losses

ranging from 2% to 8% as the output current increases

from 3A to 15A per output stage for a 5V output, or a 3%

to 12% loss per output stage for a 3.3V output. Efﬁciency

varies as the inverse square of V

componentsandoutputpowerlevel.Thecombinedeffects

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of

the losses in LTC3729 circuits: 1) LTC3729 V current

(including loading on the differential ampliﬁer output),

for the same external

IN

OUT

3729fb

20

LTC3729

APPLICATIONS INFORMATION

of increasingly lower output voltages and higher currents

required by high performance digital systems is not

doubling but quadrupling the importance of loss terms

in the switching regulator system!

estimated using the percentage of overshoot seen at this

pin.Thebandwidthcanalsobeestimatedbyexaminingthe

rise time at the pin. The I external components shown

TH

in the Figure 1 circuit will provide an adequate starting

point for most applications.

4) Transition losses apply only to the topside MOSFET(s),

and only when operating at high input voltages (typically

20V or greater). Transition losses can be estimated from:

The I series R ‑C ﬁlter sets the dominant pole‑zero

TH

C

loop compensation. The values can be modiﬁed slightly

(from 0.2 to 5 times their suggested values) to maximize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined.Theoutputcapacitorsneedtobedecidedupon

because the various types and values determine the loop

feedback factor gain and phase. An output current pulse

of 20% to 80% of full‑load current having a rise time of

2

Transition Loss = (1.7) V

I

C

f

IN O(MAX) RSS

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and input fuse

resistance losses can be minimized by making sure that

<2µs will produce output voltage and I pin waveforms

TH

C has adequate charge storage and a very low ESR at the

that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step

resulting from the step change in output current may not

be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

is why it is better to look at the Ith pin signal which is in

the feedback loop and is the ﬁltered and compensated

control loop response. The gain of the loop will be in‑

IN

switching frequency. A 50W supply will typically require

a minimum of 200µF to 300µF of capacitance having

a maximum of 10mΩ to 20mΩ of ESR. The LTC3729

PolyPhase architecture typically halves to quarters this

input capacitance requirement over competing solutions.

Other losses including Schottky conduction losses during

dead‑time and inductor core losses generally account for

less than 2% total additional loss.

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

Checking Transient Response

the same factor that C is decreased, the zero frequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed‑loop system and will demonstrate

the actual overall supply performance.

The regulator loop response can be checked by look‑

ing at the load transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

, where ESR is the effective

LOAD(ESR)

seriesresistanceofC (∆I

)alsobeginstochargeor

OUT

LOAD

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

discharge C

generating the feedback error signal that

OUT

forces the regulator to adapt to the current change and

return V to its steady‑state value. During this recovery

OUT

with C

, causing a rapid drop in V

. No regulator can

OUT

time V

can be monitored for excessive overshoot or

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

control loop behavior but also provides a DC coupled and

AC ﬁltered closed loop response test point. The DC step,

rise time, and settling at this test point truly reﬂects the

closed loop response. Assuming a predominantly second

ordersystem, phasemarginand/or dampingfactorcanbe

C

to C

is greater than1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

3729fb

21

LTC3729

APPLICATIONS INFORMATION

Design Example (Using Two Phases)

The power dissipation on the topside MOSFET can be

easily estimated. Using a Siliconix Si4420DY for example;

As a design example, assume V = 5V (nominal), V = 5.5V

IN

R

= 0.013Ω, C

= 300pF. At maximum input

DS(ON)

RSS

(max), V

= 1.8V, I

= 20A, T = 70°C and f = 300kHz.

MAX A

OUT

voltage with T (estimated) = 110°C at an elevated ambient

j

Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the PLLFLTR

temperature:

1.8V

5.5V

²

10 1+ 0.005 110°C− 25°C



P_MAIN

=

( ) )(

(

)





pin to a resistive divider using the INTV pin to generate

CC

1V for 300kHz operation. The minimum inductance for

2

0.013Ω + 1.7 5.5V 10A 300pF

(

) (

)(

)

30% ripple current is:

310kHz = 0.61W

(

)





V_OUT

f ∆I

( )

V_OUT

V_IN

L ≥

1−









The worst‑case power disipated by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction

temperature rise is:

1.8V

5.5V





≥

1−









300kHz 30% 10A

)( )(

(

)

≥ 1.35µH

5.5V − 1.8V

2

P_SYNC

=

10A 1.48 0.013Ω

(

) (

)(

)

A 2µH inductor will produce 20% ripple current. The peak

inductor current will be the maximum DC value plus one

half the ripple current, or 11.5A. The minimum on‑time

5.5V

= 1.29W

occurs at maximum V :

IN

A short‑circuit to ground will result in a folded back

current of:

V_OUT

V_INf

1.8V

t_{ON MIN}

=

= 1.1µs

(

)

5.5V 300kHz

(

)(

)













200ns 5.5V

25mV

0.005Ω 2

1

(

)

I_SC=

+

= 5.28A

2µH

The R

resistors value can be calculated by using the

SENSE

maximum current sense voltage speciﬁcation with some

accomodation for tolerances:

The worst‑case power disipated by the synchronous

MOSFET under short‑circuit conditions at elevated ambi‑

ent temperature and estimated 50°C junction temperature

rise is:

50mV

R_SENSE

=

≈ 0.005Ω

11.5A

5.5V − 1.8V

2

Choosing 1% resistors: R1 = 16.5k and R2 = 13.2k yields

an output voltage of 1.80V.

P_SYNC

=

5.28A 1.48 0.013Ω

(

) (

)(

)

5.5V

= 360mW

3729fb

22

LTC3729

APPLICATIONS INFORMATION

1) Are the signal and power grounds segregated? The

LTC3729signalgroundpinshouldreturntothe(–)plateof

OUT

which is much less than normal, full‑load conditions.

Incidentally, since the load no longer dissipates power in

the shorted condition, total system power dissipation is

decreased by over 99%.

C

separately. The power ground returns to the sources

ofthebottomN‑channelMOSFETs,anodesoftheSchottky

diodes, and (–) plates of C , which should have as short

IN

The duty cycles when the peak RMS input current occurs

is at D = 0.25 and D = 0.75 according to Figure 4. Calculate

the worst‑case required RMS input current rating at the

input voltage, which is 5.5V, that provides a duty cycle

nearest to the peak.

lead lengths as possible.

+

2) Does the LTC3729 V

pin connect to the (+) plate(s)

OS

–

of C ? Does the LTC3729 V

pin connect to the (–)

OUT

OS

plate(s) of C ? The resistive divider R1, R2 must be

OUT

connected between the V

and signal ground and

DIFFOUT

From Figure 4, C will require an RMS current rating of:

IN

any feedforward capacitor across R1 should be as close

as possible to the LTC3729.

C_INrequiredI_RMS= 20A 0.23

(

)(

)

–

+

3) Are the SENSE and SENSE leads routed together with

minimum PC trace spacing? The ﬁlter capacitors between

= 4.6A_RMS

+

–

The output capacitor ripple current is calculated by using

theinductorripplealreadycalculatedforeachinductorand

multiplyingbythefactorobtainedfromFigure3alongwith

the calculated duty factor. The output ripple in continuous

mode will be highest at the maximum input voltage. From

Figure 3, the maximum output current ripple is:

SENSE and SENSE pin pairs should be as close as

possible to the LTC3729. Ensure accurate current sensing

with Kelvin connections to the sense resistors.

4)Dothe(+)platesofC connecttothedrainsofthetopside

IN

MOSFETs as closely as possible? This capacitor provides

the AC current to the MOSFETs. Keep the input current path

formed by the input capacitor, top and bottom MOSFETs,

and the Schottky diode on the same side of the PC board in

a tight loop to minimize conducted and radiated EMI.

V_OUT

fL

∆I_COUT

=

0.34

(

)

1.8 0.34

300kHz 2µH

)(

(

)

∆I_COUTMAX

=

= 1A

5) Is the INTV 1µF ceramic decoupling capacitor con‑

CC

(

)

nectedcloselybetweenINTV andthepowergroundpin?

CC

This capacitor carries the MOSFET driver peak currents.

A small value is used to allow placement immediately

adjacent to the IC.

Note that the PolyPhase technique will have its maximum

beneﬁtforinputandoutputripplecurrentswhenthenumber

of phases times the output voltage is approximately equal

to or greater than the input voltage.

6) Keep the switching nodes, SW1 (SW2), away from sen‑

sitive small‑signal nodes. Ideally the switch nodes should

be placed at the furthest point from the LTC3729.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3729. These items are also illustrated graphically

in the layout diagram of Figure 11. Check the following

in your layout:

7)Usealowimpedancesourcesuchasalogicgatetodrive

the PLLIN pin and keep the lead as short as possible.

8) Minimize the capacitive load on the CLKOUT pin to

minimize excess phase shift. Buffer if necessary with an

NPN emitter follower.

3729fb

23

LTC3729

APPLICATIONS INFORMATION

The diagram in Figure 9 illustrates all branch currents in

a 2‑phase switching regulator. It becomes very clear after

studying the current waveforms why it is critical to keep

the high‑switching‑current paths to a small physical size.

High electric and magnetic ﬁelds will radiate from these

“loops” just as radio stations transmit signals. The output

capacitor ground should return to the negative terminal of

the input capacitor and not share a common ground path

with any switched current paths. The left half of the circuit

givesrisetothe“noise”generatedbyaswitchingregulator.

The ground terminations of the sychronous MOSFETs and

Schottkydiodesshouldreturntothebottomplate(s)ofthe

input capacitor(s) with a short isolated PC trace since very

high switched currents are present. A separate isolated

path from the bottom plate(s) of the input capacitor(s)

should be used to tie in the IC power ground pin (PGND)

and the signal ground pin (SGND). This technique keeps

inherent signals generated by high current pulses from

taking alternate current paths that have ﬁnite impedances

during the total period of the switching regulator. External

OPTI‑LOOP compensation allows overcompensation for

PC layouts which are not optimized but this is not the

recommended design procedure.

L1

SW1

R

SENSE1

D1

V

OUT

IN

R

IN

C

OUT

+

C

R

L

IN

SW2

L2

R

SENSE2

D2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3729 F09

Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

3729fb

24

LTC3729

APPLICATIONS INFORMATION

Simpliﬁed Visual Explanation of How a 2-Phase

Controller Reduces Both Input and Output RMS Ripple

Current

illustrate how the input and output currents are reduced by

using an additional phase. The input current peaks drop in

half and the frequency is doubled for a 2‑phase converter.

Theinputcapacityrequirementisreducedtheoreticallybya

factor of four! A ceramic input capacitor with its unbeatably

low ESR characteristic can be used.

Amultiphasepowersupplysigniﬁcantlyreducestheamount

of ripple current in both the input and output capacitors.

The RMS input ripple current is divided by, and the effective

ripple frequency is multiplied up by the number of phases

used (assuming that the input voltage is greater than the

numberofphasesusedtimestheoutputvoltage).Theoutput

ripple amplitude is also reduced by, and the effective ripple

frequencyisincreasedbythenumberofphasesused.Figure

10 graphically illustrates the principle.

Figure 4 illustrates the RMS input current drawn from the

input capacitance versus the duty cycle as determined

by the ratio of input and output voltage. The peak input

RMS current level of the single phase system is reduced

by 50% in a 2‑phase solution due to the current splitting

between the two stages.

An interesting result of the multi‑phase solution is that the

IN

SINGLE PHASE

SW V

V which produces worst‑case ripple current for the input

capacitor, V =V /2, inthesinglephasedesignproduces

OUT

IN

zero input current ripple in the 2‑phase design.

I

CIN

The output ripple current is reduced signiﬁcantly when

compared to the single phase solution using the same

I

COUT

inductance value because the V /L discharge current

OUT

term from the stage(s) that has its bottom MOSFET on

DUAL PHASE

subtracts current from the (V ‑ V )/L charging current

SW1 V

SW2 V

IN

OUT

resulting from the stage which has its top MOSFET on.

The output ripple current is:

I

L1













1− 2D 1− D

1− 2D + 1

2V_OUT

fL

(

)

I_RIPPLE

=

I

L2

where D is duty factor.

I

CIN

The input and output ripple frequency is increased by

the number of stages used, reducing the output capacity

I

COUT

3729 F10

RIPPLE

requirements. When V is approximately equal to NV

IN

OUT

as illustrated in Figures 3 and 4, very low input and output

ripple currents result.

Figure 10. Single and PolyPhase Current Waveforms

Again, the interesting result of 2‑phase operation results

Theworst‑caseRMSripplecurrentforasinglestagedesign

peaks at twice the value of the output voltage . The worst‑

case RMS ripple current for a two stage design results in

peaks at 1/4 and 3/4 of input voltage. When the RMS cur‑

rent is calculated, higher effective duty factor results and

the peak current levels are divided as long as the currents

in each stage are balanced. Refer to Application Note 19 for

a detailed description of how to calculate RMS current for

the single stage switching regulator. Figures 3 and 4 help to

in no output ripple at V

= V /2. The addition of more

OUT

IN

phases by phase locking additional controllers always

results in no net input or output ripple at V /V ratios

OUT IN

equal to the number of stages implemented. Designing a

systemwithamultipleofstagesclosetotheV /V ratio

OUT IN

will signiﬁcantly reduce the ripple voltage at the input and

outputs and thereby improve efﬁciency, physical size, and

heat generation of the overall switching power supply.

3729fb

25

LTC3729

TYPICAL APPLICATIONS

OPTIONAL

SYNC

CLOCK IN

L1

0.003Ω

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1000pF

RUN/SS

SENSE1

EAIN

CLKOUT

TG1

+

–

0.33µF

0.47µF

D7

M1

M2

M3

3

D1

MBRS

340T3

SW1

8.06k, 1%

4

BOOST1

10Ω

1µF

5

PLLFLTR

V

IN

BG1

6

LTC3729

0.3µF

47k

PLLIN

7

3X330µF, 6.3V

POSCAP

5V

PHASMD

EXTV

CC

1µF,6.3V

6800pF

100pF

25.5k, 1%

8

22µF

6.3V

2X150µF

16V

GND

I

INTV

TH

SGND

CC

9

V

OUT

3.3V/90A

PGND

BG2

10

11

12

13

14

V

DIFFOUT

–

BOOST2

SW2

OS

D2

MBRS

340T3

D8

470pF

+

OS

–

SENSE2

TG2

0.47µF

M4

M5

M6

+

PGOOD

1000pF

L2

L3

0.003Ω

24k

75k

0.003Ω

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1000pF

RUN/SS

SENSE1

EAIN

CLKOUT

TG1

+

–

0.47µF

M7

M8

M9

3

D3

MBRS

340T3

SW1

4

47pF

10k

D9

BOOST1

10Ω

1µF

5

PLLFLTR

V

IN

BG1

6

3X330µF, 6.3V

POSCAP

LTC3729

1nF

PLLIN

0.01µF

7

5V

PHASMD

EXTV

CC

1µF,6.3V

22µF

6.3V

8

2X150µF

16V

GND

I

INTV

TH

SGND

CC

9

100pF

V

IN

12V

PGND

BG2

10

11

12

13

14

NC

V

DIFFOUT

–

BOOST2

SW2

OS

D4

MBRS

340T3

D10

+

OS

–

SENSE2

TG2

0.47µF

M10

M11

M12

+

PGOOD

1000pF

L4

L5

0.003Ω

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1000pF

RUN/SS

SENSE1

EAIN

CLKOUT

TG1

+

–

0.47µF

M13

M14

M15

3

D5

MBRS

340T3

SW1

4

47pF

D11

BOOST1

10Ω

1µF

10k

1nF

5

PLLFLTR

V

IN

BG1

6

3X330µF, 6.3V

POSCAP

LTC3729

PLLIN

0.01µF

7

5V

PHASMD

EXTV

CC

1µF,6.3V

22µF

6.3V

8

2X150µF

16V

GND

I

INTV

TH

SGND

CC

9

100pF

PGND

BG2

10

11

12

13

14

NC

V

DIFFOUT

–

BOOST2

SW2

OS

D6

MBRS

340T3

D12

+

OS

–

SENSE2

TG2

0.47µF

M16

M17

M18

+

PGOOD

1000pF

L6

0.003Ω

V

: 12V

MI – M18: Si7440DP

L1 – L6: 1µH PANASONIC ETQP6F1R0S

D7 – D12: CENTROL CMDSH-3TR

OUTPUT CAPACITORS: SANYO 6TPB330M

IN

: 3.3V/90A

OUT

3729 TA03

SWITCHING FREQUENCY = 400kHz

Figure 11. High Current 3.3V/90A 6-Phase Application

3729fb

26

LTC3729

(For purposes of clarity, drawings are not to scale)

PACKAGE DESCRIPTION

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05‑08‑1640)

9.90 – 10.50*

(.390 – .413)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

1.25 0.12

5.3 – 5.7

7.8 – 8.2

7.40 – 8.20

(.291 – .323)

0.42 0.03

0.65 BSC

5

7

8

1

2

3

4

6

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0° – 8°

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

3729fb

27

LTC3729

(For purposes of clarity, drawings are not to scale)

PACKAGE DESCRIPTION

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05‑08‑1693 Rev D)

0.70 ±0.05

5.50 ±0.05

4.10 ±0.05

3.45 ± 0.05

3.50 REF

(4 SIDES)

3.45 ± 0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ± 0.05

5.00 ± 0.10

(4 SIDES)

31 32

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

3.50 REF

(4-SIDES)

3.45 ± 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ± 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3729fb

28

LTC3729

REVISION HISTORY ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

03/11 Updated Absolute Maximum Ratings section

Replaced Graph G09

2

5

Updated text and equation in Differential Ampliﬁer/Output Voltage section

Updated Figure 11, Figure 12

17

26, 30

30

Updated Related Parts

3729fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa‑

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

LTC3729

TYPICAL APPLICATION

L1

0.003Ω

D1

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1000pF

RUN/SS

CLKOUT

TG1

2

3

+

–

0.1µF

SENSE1

EAIN

0.47µF

D3

M1

M2

SW1

4

UPS840

BOOST1

10Ω

5

13.2k

PLLFLTR

PLLIN

V

IN

BG1

6

0.1µF

7

C

1000pF

IN

5V

PHASMD

EXTV

CC

3.3k

33pF

1µF,6.3V

4.7µF

6.3V

8

I

INTV

TH

SGND

CC

C

OUT

9

V

LTC3729

IN

PGND

BG2

6V TO

16V

16.5k

10

11

12

13

14

V

DIFFOUT

–

BOOST2

SW2

OS

D2

UPS840

D4

+

100k

OS

100pF

POWER

GOOD

–

SENSE2

TG2

0.47µF

M3

M4

+

PGOOD

V

OUT

1000pF

3.3V/30A

L2

0.003Ω

V

: 5V TO 16V

MI, M3: IRF7811

M2, M4: IRF7809

L1, L2: 1µH SUMIDA CEP125-1R0MC-H

C

: OS CON 2-16SP270M

IN

: 3.3V/30A

OUT

: KEMET 3-T510 470mF

OUT

3729TA02

SWITCHING FREQUENCY = 250kHz

D3, D4: CENTRAL CMDSH-3TR

Figure 12. 3.3V/30A Power Supply with Active Voltage Positioning

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC3856

Single Output 2‑Channel Polyphase Synchronous Step‑Down PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,

IN

DC/DC Controller with Diff Amp and up to 12‑Phase Operation 0.8V≤ V

≤ 5V

OUT

2

LTC3880/LTC3880‑1 Dual Output PolyPhase Step‑Down DC/DC Controller with

Digital Power System Management

I C/PMBus Interface with EEPROM and 16‑Bit ADC, V Up to 24V,

IN

0.5V ≤ V

≤ 5.5V, Analog Control Loop

OUT

LTC3829

Single Output 3‑Channel Polyphase Synchronous Step‑Down PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,

IN

DC/DC Controller with Diff Amp and up to 6‑Phase Operation

0.8V ≤ V

≤ 5V

OUT

LTC3869/LTC3869‑2 Dual Output, 2‑Phase Synchronous Step‑Down DC/DC

Controller, with Accurate Current Share

PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V,

IN

OUT3

V

Up to 12.5V

LTC3850/LTC3850‑1 Dual Output, 2‑Phase Synchronous Step‑Down DC/DC

PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V,

IN

LTC3850‑2

Controller, R

or DCR Current Sensing

0.8V ≤ V

≤ 5.25V

OUT

SENSE

LTC3855

Dual Output, 2‑phase, Synchronous Step‑Down DC/DC

PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V,

IN

Controller with Diff Amp and DCR Temperature Compensation 0.8V ≤ V

≤ 12V

OUT

LTC3853

LTC3860

Triple Output, Multiphase Synchronous Step‑Down DC/DC

Controller, R or DCR Current Sensing and Tracking

PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 24V,

IN

V

Up to 13.5V

OUT3

SENSE

Dual, Multiphase, Synchronous Step‑Down DC/DC Controller

with Diff Amp and Three‑State Output Drive

Operates with Power Blocks, DRMOS Devices or External

MOSFETs 3V ≤ V ≤ 24V, t = 20ns

IN

ON(MIN)

LTC3857/LTC3857‑1 Low I , Dual Output 2‑Phase Synchronous Step‑Down DC/DC Phase‑Lockable Fixed Operating Frequency 50kHz to 900kHz,

Q

Controller with 99% Duty Cycle

4V ≤ V ≤ 38V, 0.8V ≤ V

≤ 24V, I = 50µA

OUT Q

IN

3729fb

0311 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035‑7417

30

●

 LINEAR TECHNOLOGY CORPORATION 2001

(408) 432‑1900 FAX: (408) 434‑0507 www.linear.com


型号：	LTC3880-1
厂家：	Linear
描述：	550kHz, PolyPhase, High Efficiency, Synchronous Step-Down Switching Regulator 的550kHz ，多相，高效率，同步降压型开关稳压器稳压器开关
文件：	总30页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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