LTC3882-1_技术文档

LTC3870-1

PolyPhase Step-Down

Slave Controller for Digital

Power System Management

DescripTion

FeaTures

TheLTC^®3870-1isaPolyPhase^®step-downslavecontrol-

ler specially designed for multiphase operation with LTC's

digital power system management DC/DC controllers. It

provides a small and cost effective solution for supply-

ing very large currents by cascading it with a LTC3887-1

controller. A peak current mode architecture provides the

LTC3870-1 with excellent current sharing from phase to

phase and from chip to chip.

n

LTC3887-1 Phase Extender

n

Operates with Power Blocks, DrMOS or External

Gate Drivers and MOSFETs

n

Cascade with Multiple Chips for Very Large Current

Applications

n

Accurate PolyPhase Current Sharing

n

EXTV Capable of 5V to 14V Input

CC

n

Wide V Range: 4.5V to 60V

IN

Wide Output Voltage Range : 0.5V to 14V

Wide SYNC Frequency Range: 100kHz to 1MHz

Pin Programmable CCM/DCM Operation

Pin Programmable Phase-Shift Control

Coherently working with the LTC3887-1, the LTC3870-1

2

doesnotrequireadditionalI Caddresses, anditsupports

all programmable features as well as fault protection.

The constant switching frequency can be synchronized

to an external clock from the LTC3887-1 over a range of

100kHz to 1MHz.

Available in a 24-Pin (4mm × 4mm) QFN Package

L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787,

6580258, 5408150

applicaTions

n

High Power Distributed Power Systems

Telecom Systems

n

Industrial Applications

Typical applicaTion

Load Transient Response of a

2-Phase Master (3887-1)/Slave

(3870-1) Converter

V

IN

7V TO 14V

22µF

4.7µF

V

INTV

CC

I

IN

LOAD

20A/DIV

10A TO 20A TO 10A

V

CC1

CC0

LTC3870-1

I

LTC3887–1

(CH0)

10A/DIV

L

V

OUT0

3.3V, 30A

OUT1

1.8V, 40A

1.0µH

0.56µH

DrMOS

PWM0

PWM1

DrMOS

I

LTC3870–1

(CH0)

10A/DIV

L

2.15k

0.2µF

1.74k

530µF

0.2µF

V

I

+

I

+

OUT

SENSE0

SENSE1

200mV/DIV

I

-

I

-

SENSE0

SENSE1

AC–COUPLED

38701 TA01b

100µs/DIV

EXTV

CC

LTC3887-1

RUN0

V

= 12V

OUT

RUN0

IN

= 1.8V

RUN1

GPIO0

GPIO1

RUN1

82.5k

3.3V

V

+

FAULT0

FAULT1

FREQ

PHASMD

SENSE0

1.8V

V

+

I

LIM

SENSE1

TH0

TH1

I

MODE0

MODE1

GND

TH1

SYNC

* REFER TO LTC3887-1 DATA SHEET

FOR MASTER SETUP

38701 TA01a

38701f

1

For more information www.linear.com/LTC3870-1

LTC3870-1

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

V ............................................................. –0.3V to 65V

IN

V

, V .................................................... –0.3V to 6V

CC0 CC1

I

+, I

−, I

+, I

−....... –0.3V to 15V

SENSE0

SENSE1 SENSE1

24 23 22 21 20 19

+

INTV , RUN0/RUN1 .................................. –0.3V to 6V

CC

I

1

2

3

4

5

6

18

17

16

V

SENSE0

CC0

IN

EXTV .................................................... –0.3V to 14V

–

CC

SENSE0

MODE0/MODE1,

RUN0

RUN1

GND

25

GND

FREQ, PHASMD, I ........................–0.3V to INTV

15 EXTV

14

LIM

CC

–

I

INTV

FAULT0/FAULT1, I /I , SYNC .............. –0.3V to 3.6V

SENSE1

CC

TH0 TH1

+

13

V

CC1

SENSE1

INTV , EXTV Peak Current (Note 7) ...............100mA

CC

7

8

9 10 11 12

Operating Junction

Temperature Range............................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

T

= 125°C, θ = 46.9°C/W, θ = 4.5°C/W

JMAX

JA

JC_BOT

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

LTC3870EUF-1#PBF

LTC3870IUF-1#PBF

TAPE AND REEL

PART MARKING*

38701

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3870EUF-1#TRPBF

LTC3870IUF-1#TRPBF

–40°C to 125°C

24-Lead (4mm × 4mm) Plastic QFN

38701

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) V_IN= 15V, V_RUN0,V_RUN1= 3.3V, f_SYNC= 350kHz

(externally driven) unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

(Note 3)

MIN

4.5

TYP

MAX

60

UNITS

V

Input Voltage Range

Output Voltage Range

V

IN

(Note 4)

0.5

14

OUT

I

Q

Input Voltage Supply Current

Normal Operation

V

, V = 0V

RUN0 RUN1

1.1

2.6

mA

V

, V

= 3.3V

RUN0 RUN1

V

UVLO

Undervoltage Lockout Threshold

V

Falling

Rising

3.7

4.0

V

INTVCC

when V > 4.2V

IN

CONTROL LOOP

l

I

+,

+

Current Sense + Pin Current

Current Sense – Pin Current

V

+ = 3.3V

– = 3.3V

0.1

1

µA

ISENSE0

ISENSE1

ISENSE0,1

I

–,

–

ISENSE0

ISENSE1

ISENSE0,1

38701f

2

For more information www.linear.com/LTC3870-1

LTC3870-1

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) V_IN= 15V, V_RUN0,V_RUN1= 3.3V, f_SYNC= 350kHz

(externally driven) unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN

70

TYP

75

MAX

80

UNITS

mV

l

V

Maximum Current Sense Threshold (High Range)

Maximum Current Sense Threshold (Low Range)

V

ITH

V

ITH

= 2.22V, I = INTV

LIM CC

IILIMIT

= 2.22V, I = GND

45

50

55

mV

LIM

PWM Outputs

l

PWM

PWM Output High Voltage

PWM Output Low Voltage

PWM Output Current in Hi-Z State

I

= 500µA

= –500µA

V

– 0.2

CC

V

µA

LOAD

0.2

5

–5

t

Minimum On-Time

(Note 5)

90

ns

ON(MIN)

INTV Regulator

CC

V

Internal V Voltage No Load

6.0V < V < 60V, V = 0V

EXTVCC

4.85

4.65

5.1

0.8

5.1

0.5

4.8

200

5.35

2

V

%

V

INTVCC_VIN

CC

IN

INT

INTV Load Regulation

I

CC

= 0mA to 50mA, V = 0V

EXTVCC

LDO

CC

Internal V Voltage No Load

V

= 8.5V (Note 6)

EXTVCC

5.35

2

INTVCC_EXT

CC

EXT

EXTV Load Regulation

I

CC

= 0mA to 20mA, V = 8.5V

EXTVCC

%

V

LDO

CC

EXTV Switchover Voltage

V Ramping Positive (Note 6)

EXTVCC

4.95

EXTVCC

CC

EXTV Hysteresis

mV

HYS_EXTVCC

CC

Oscillator and Phase-Locked Loop

l

f

Oscillator SYNC Range

SYNC Input Threshold

100

9

1000

11

kHz

SYNC

V

Falling (Note 7)

Rising

0.4

2.0

V

TH,SYNC

f

I

Nominal Frequency

V

FREQ

= 1.0V

500

10

kHz

µA

NOM

FREQ Setting Current

FREQ

SYNC to Ch0 Phase Relationship Based on the

Falling Edge of SYNC and Rising Edge of PWM0

PHASMD =0

180

60

Deg

θ

-θ

SYNC

0

PHASMD = 1/3 INTV

PHASMD = 2/3 INTV

CC

120

90

PHASMD = INTV

CC

SYNC to Ch1 Phase Relationship Based on the

Falling Edge of SYNC and Rising Edge of PWM1

PHASMD = 0

0

Deg

θ

SYNC

1

PHASMD = 1/3 INTV

PHASMD = 2/3 INTV

300

240

270

CC

PHASMD = INTV

CC

Digital Inputs RUN0/RUN1, MODE0/MODE1, FAULT0/FAULT1

l

V

Input High Threshold Voltage

Input Low Threshold Voltage

2.0

V

IH

IL

1.4

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

impedance and other environmental factors. The junction temperature T

J

is calculated from the ambient temperature T and power dissipation P

A

D

according to the following formula:

T = T + (P • 46.9°C/W)

J

A

D

Note 2: The LTC3870-1 is tested under pulsed load conditions such that

Note 3: When V >15V, EXTV is recommended to reduce IC Temperature.

Note 4: Output voltage is set and controlled by the master controller in

multiphase operations.

Note 5: The minimum on-time condition corresponds to an inductor

IN

CC

T ≈ T . The LTC3870E-1 is guaranteed to meet specifications from

J

A

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3870I-1 is guaranteed over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the related package thermal

peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 6: EXTV is enabled only if V is higher than 6.5V.

CC

IN

Note 7: Guaranteed by design.

38701f

3

For more information www.linear.com/LTC3870-1

LTC3870-1

Typical perForMance characTerisTics

Efficiency vs Load Current

100

85

70

55

40

25

10

100

90

80

70

60

50

40

30

20

10

CCM

DCM

CCM

DCM

V

= 12V

OUT

IN

V

= 12V

OUT

= 350kHz

IN

V

= 1.8V

V

= 3.3V

L = 0.56µH

f

SW

DCR = 1.61mΩ

L = 1µH

f

= 350kHz

SW

DCR = 2.4mΩ

0.1

1

10

100

0.1

1

10

100

LOAD CURRENT (A)

3874 G01

38701 G02

Full Load (I_LOAD= 20A/Phase)

Efficiency and Power Loss vs

Input Voltage

Load Step (Discontinuous Conduction

Mode) 4-Phase Operation

LTC3887-1 and LTC3870-1

93.5

93.0

92.5

92.0

91.5

91.0

3.0

I

LOAD

EFFICIENCY

POWER LOSS

50A/DIV

0A TO 20A TO 0A

2.9

2.8

2.7

2.6

2.5

INDUCTOR CURRENT

LTC3887–1 (CH0)

10A/DIV

INDUCTOR CURRENT

LTC3870–1 (CH0)

10A/DIV

V

OUT

50mV/DIV

AC–COUPLED

38701 G04

V

= 1.8V

50µs/DIV

OUT

L = 0.56µH

V

= 12V

OUT

IN

DCR = 1.61mΩ

= 1.0V

5

6

7

8

9

10 11 11 12 13 14 15 16

INPUT VOLTAGE (V)

38701 G03

Load Step (Forced Continuous

Mode) 4-Phase Operation

LTC3887-1 and LTC3870-1

Inductor Current at Light Load

I

LOAD

I

L

50A/DIV

LTC3870–1 (CH1)

FORCED

0A TO 20A TO 0A

CONTINUOUS

MODE

INDUCTOR CURRENT

LTC3887–1 (CH0)

10A/DIV

5A/DIV

INDUCTOR CURRENT

LTC3870–1 (CH0)

10A/DIV

I

L

LTC3870–1 (CH1)

DISCONTINUOUS

MODE

V

OUT

5A/DIV

50mV/DIV

AC–COUPLED

38701 G05

38701 G06

50µs/DIV

1µs/DIV

V

= 12V

OUT

IN

= 1.0V

38701f

4

For more information www.linear.com/LTC3870-1

LTC3870-1

Typical perForMance characTerisTics

Start-Up into a Pre-Biased Load

2-Phase Operation LTC3887-1

and LTC3870-1

Current Sense Threshold

vs I_THVoltage

80

RANGE HIGH

RANGE LOW

RUN

ALL RUN PINS

TIED TOGETHER

2V/DIV

60

40

V

OUT

20

LTC3870–1

IN DCM

500mV/DIV

0

V

= 12V

IN

OUT

= 1.8V

38701 G07

–20

–40

2ms/DIV

0

0.5

1

V

1.5

(V)

2

2.5

ITH

38701 G08

DC Output Current Matching in

a 4-Phase Operation

LTC3887-1 and LTC3870-1

INTV_CCLine Regulation

6.0

5.0

4.0

3.0

2.0

1.0

0

30

25

20

15

10

5

LTC3887–1 CH0

LTC3887–1 CH1

LTC3870–1 CH0

LTC3870–1 CH1

0

10

20

30

40

50

60

0

10 20 30 40 50 60 70 80 90 100

INPUT VOLTAGE (V)

TOTAL OUTPUT CURRENT (A)

38701 G09

38701 G10

Dynamic Current Sharing During a

Load Transient in a 4-Phase System

LTC3887-1 and LTC3870-1

Quiescent Current vs Input

Voltage without EXTV_CC

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

LTC3887–1 CH0

10A/DIV

LTC3887–1 CH1

10A/DIV

LTC3870–1 CH0

10A/DIV

LTC3870–1 CH1

10A/DIV

38701 G11

50µs/DIV

V

= 12V

IN

= 1.0V

OUT

I

= 0A TO 32A TO 0A

LOAD

0

10

20

30

40

50

60

INPUT VOLTAGE (V)

38701 G12

38701f

5

For more information www.linear.com/LTC3870-1

LTC3870-1

pin FuncTions

SENSE0 SENSE1

positive inputs, normally connected to the positive node

of the DCR sensing networks or current sensing resistors.

I

+/I

+(Pin1/Pin6):CurrentSenseComparator

PHASMD (Pin 11): Phase Set Pin. This pin can be tied to

GND,INTV oraresistordividerfromINTV toGND.This

pin determines the relative phases between the external

clock on the SYNC pin and the internal controllers. See

Table 1 in the Operation Section for details.

CC

I

−/I

−(Pin2/Pin5):CurrentSenseComparator

SENSE0 SENSE1

negative inputs, normally connected to the negative node

of the DCR sensing network or current sensing resistors.

PWM0/PWM1(Pin19/Pin12):(Top)GateSignalOutputs.

ThissignalgoestothePWMortopgateinputoftheexternal

driver, integrated driver MOSFET or Power Block. This is

a three-state compatible output. To support three-state

mode, an external resistive divider is typically used from

RUN0/RUN1 (Pin 3/Pin 4): Enable Run Input Pins. A logic

high on these pins enables the corresponding channel.

In multiphase operation, these pins are connected to

LTC3887-1's RUN pins.

V

/V

to ground.

CC0 CC1

MODE0/MODE1 (Pin 24/Pin 7): DCM/CCM Mode Control

Pins. Channel0/Channel1 operate in forced continuous

modeifMODE0/MODE1pinislogichigh.Thereisa500kΩ

pull-down resistor on MODE0/MODE1 internally. The

default operation mode in each channel is discontinuous

mode operation unless these pins are actively driven high.

V

/V

(Pin 18/Pin 13): PWM Pin Driver Supplies.

CC0 CC1

Decouple these pins to GND with a capacitor (0.1µF) or tie

these pins to the INTV pin. PWM0/PWM1 signal swing

is from ground to V /V

CC

CC0 CC1

.

INTV (Pin14):InternalRegulator5VOutput.Theinternal

CC

controlcircuitsarepoweredfromthisvoltage. Bypassthis

I

/I

(Pin 23/Pin 8): Current Control Threshold.

TH0 TH1

pin to GND with a minimum of 4.7µF low ESR tantalum

Each associated channel’s current comparator tripping

or ceramic capacitor. INTV is enabled as soon as V

CC

IN

threshold increases with its I voltage. In multiphase

TH

is powered. The INTV pin is not short circuit proof. If

CC

operation, these pins are connected to the master con-

overloaded, this will disrupt internal operation that can

troller's I pins for current sharing.

TH

damage the part.

I

(Pin 9): Programs Current Comparators' Sense

LIM

EXTV (Pin 15): External power input to an internal LDO

CC

Voltage Range. This pin can be tied to GND or INTV

CC

connected to INTV . This LDO supplies INTV power

CC

to select the maximum current sense threshold for each

bypassing the internal LDO powered from V whenever

IN

current comparator. GND sets both channels' current low

EXTV is higher than 4.8V. See EXTV connection in the

CC

range with maximum 50mV sensing voltage. INTV sets

CC

Applications Information Section. Do not exceed 14V on

both channels' current high range with maximum 75mV

this pin. Bypass this pin to GND with a minimum of 4.7µF

sensing voltage. For equal current sharing, the setup on

low ESR tantalum or ceramic capacitor. If the EXTV pin

CC

the I

pin has to be same as the setup on the bit 7 of

LIM

is not used, leave it open or tie it to ground. EXTV can

MFR_PWM_MODE_3887-1registerinthemastercontrol-

ler. See Table 2 in the Operation Section for details.

be present before V . However, EXTV is enabled only

IN

CC

if V is higher than 6.5V.

IN

SYNC(Pin10):ExternalClockSynchronizationInput.Ifan

externalclockispresentatthispin,theswitchingfrequency

will be synchronized to the falling edge of the external

clock. In multiphase operation, this pin is connected to

LTC3887-1 SYNC pin for frequency synchronization. Do

not float the SYNC Pin.

GND (Pin 16/Exposed Pad Pin 25): Signal ground. All

small-signal and compensation components should con-

nect to this ground. The exposed pad must be soldered

38701f

6

For more information www.linear.com/LTC3870-1

LTC3870-1

pin FuncTions

to the PCB ground for electrical connection and rated

thermal performance.

resistor on FAULT0/FAULT1 internally. These pins have to

be driven high externally for normal operation.

V (Pin 17): Main Input Supply. Bypass this pin to GND

FREQ (Pin 22): Frequency Set Pin. There is a precision

10µA current flowing out of this pin. A resistor to ground

sets a voltage which in turn programs the frequency. This

pin sets the default switching frequency when there is no

externalclockontheSYNCpin.Settingthefrequencyclose

to the external clock helps the internal PLL sync to the

SYNC pin clock quickly and smoothly. See the Application

Section for the detailed information.

IN

with a capacitor (0.1µF to 1µF).

FAULT0/FAULT1(Pin21/Pin20):FaultInputPins.Connect

these pins to the master chip GPIO pins to respond to

fault signals from the master controller. If this pin is low,

the PWM pin is in three-state. There is a 500kΩ pull-down

block DiagraM

(CH0 Shown)

10

11

PHASMD

15

EXTV

SYNC

CC

10µA

SYNC

DET

4.8V

PHASE

V

PROGRAM

OSC

IN

FREQ

17

14

V

IN

PFD

VCO

27

+

C

IN

5.0V

LDO

EN

5.0V

LDO

EN

S

R

Q

I

INTV

3K

CMP

REV

CC

+

–

+

ON

V

CC0

18

19

REV

UVLO

FAULT

FCNT

RUN

L

PWM0

SWITCH

LOGIC

V

DrMOS

OUT0

I

RANGE SELECT

HI: 1:1

LO: 1:1.5

LIM

I

C

LIM

C

9

R

C

UVLO

INTV

+

CC

C

OUT0

+

I

SENSE0

SLOPE

COMPENSATION

1

2

–

SENSE0

INTV

CC

1

+

–

71.1k

1.7V

REF

500k

I

23

MODE0

24

RUN0

FAULT0

GND

16

TH0

3

21

38701 BD

38701f

7

For more information www.linear.com/LTC3870-1

LTC3870-1

operaTion

Main Control Loop

Start-Up and Shutdown (RUN0, RUN1)

The LTC3870-1 is a constant frequency, current mode

step-down slave controller for parallel operation with the

LTC3887-1. During normal operation, each top MOSFET

is turned on when the clock for that channel sets the RS

latch, and turned off when the main current comparator,

ThetwochannelsoftheLTC3870-1canindependentlystart

up and shut down using the RUN0 and RUN1 pins. Pulling

either of these pins below 1.4V shuts down the control

circuitsforthatchannel. Duringshutdown, thePWMpinis

in three-state mode. Pulling either of these pins above 2V

enables the corresponding channel and internal circuits.

During startup, the RUN0/RUN1 pins are actively pulled

I

, resets the RS latch. The peak inductor current at

CMP

which I

resets the RS latch is controlled by the voltage

CMP

TH

on the I pin, which is tied directly to the corresponding

down until the INTV voltage passes the undervoltage

CC

I

pin of the master controllers (LTC3887-1). When the

lockoutthresholdof4V. Formultiphaseparalleloperation,

the RUN0/RUN1 pins have to be connected and driven by

the RUN pins of the master controller. Do not exceed the

Absolute Maximum Rating of 6V on these pins.

TH

load current increases, LTC3887-1 master controllers

drive and increase the I voltage, which in turn causes

TH

the peak current in the corresponding slave channels to

increase, until the average inductor current matches the

new load current. After the top MOSFET has been turned

off, the bottom MOSFET is turned on until the beginning

of the next cycle in Continuous Conduction Mode (CCM)

or until the inductor current starts to reverse, as indicated

The start-up of each channel’s output voltage V

is

OUT

controlled and programmed by the master controller.

After the RUN pins are released, the master controller

drives the output based on the programmed delay time

and rise time, and the slave controller LTC3870-1 just

follows the master to supply equivalent current to the

output during start-up.

by the reverse current comparator I , in Discontinuous

REV

ConductionMode(DCM).LTC3870-1slavecontrollersDO

NOT regulate the output voltage but regulate the current in

each channel for current sharing with master controllers.

Output voltage regulation is achieved through the voltage

feedback loops in the master controller.

Light Load Current Operation (Discontinuous

Conduction Mode, Continuous Conduction Mode)

The LTC3870-1 can be set to operate either in Discontinu-

ous Conduction Mode (DCM) or forced Continuous Con-

duction Mode (CCM). To select forced Continuous Mode

of operation, tie the MODE pin to a DC voltage above 2V

INTV /EXTV Power

CC

PowerformostinternalcircuitryisderivedfromtheINTV

CC

pin. Normally an internal 5.0V linear regulator supplies

INTV power from V . In high V applications, if a high

(e.g., INTV ). To select Discontinuous Conduction Mode

CC

IN

of operation, tie the MODE pin to a DC voltage below 1.4V

(e.g., SGND). In forced continuous operation, the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current is

efficiencyexternalvoltagesourceisavailablefortheEXTV

CC

pin, another internal 5.0V linear regulator is enabled and

supplies INTV power from EXTV . To enable the linear

CC

regulator driven by the EXTV pin, V needs to be higher

CC

IN

determined by the voltage on the I pin. In this mode,

TH

than 6.5V and EXTV pin voltage has to be higher than

CC

the efficiency at light loads is lower than in discontinu-

ous mode operation. However, continuous mode has the

advantages of lower output ripple and less interference

with audio circuitry. When the MODE pin is connected to

4.8V. Do not exceed 14V on the EXTV pin.

CC

38701f

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For more information www.linear.com/LTC3870-1

LTC3870-1

operaTion

GND, the LTC3870-1 operates in discontinuous mode at

light loads. At very light loads, the current comparator

Single Output Multiphase Operation

TheLTC3870-1isdesignedformultiphaseconverterswith

the LTC3887-1 by making these connections:

I

may remain tripped for several cycles and force the

CMP

external top MOSFET to stay off for the same number of

cycles (i.e., skipping pulses). This mode provides higher

light load efficiency than forced continuous mode and

the inductor current is not allowed to reverse. There are

500kΩ pull-down resistors internally connected to the

MODE0/MODE1 pins. If MODE0/MODE1 pins are floating,

bothchannelsdefaulttoDiscontinuousConductionMode.

•ꢀ Tie all the I pins of paralleled channels together for

TH

current sharing between masters and slaves. Note that

I

setup on slaves has to match MFR_PWM_MODE

LIM

current range setup in masters.

•ꢀ Tie all SYNC pins together between master and slaves

for same switching frequency synchronization; one

and only one of the LTC3887-1 controllers has to be

programmed as master to generate clock signal on

the SYNC pin.

Multichip Operation (PHASMD and SYNC Pins)

The PHASMD pin determines the relative phases between

theinternalchannelsaswellastheexternalclocksignalon

the SYNC pin, as shown in Table 1. The phases tabulated

are relative to zero degree phase being defined as the

falling edge of the clock on SYNC.

•ꢀ Tie all the RUN pins of paralleled channels together

between master and slaves for startup and shutdown

sequences.

•ꢀ Tie the GPIO pin of the master controller to the FAULT

pin of slave controller and program the master GPIO

as fault sharing for fault protection.

Table 1.

PHASMD

Channel 0 Phase

Channel 1 Phase

GND

180°

60°

0°

Examples of single output multiphase converters are

shown in Figure 1.

1/3 INTV

300°

240°

270°

CC

2/3 INTV or Float

120°

90°

CC

INTV

CC

Inductor Current Sensing

The SYNC pin is used to synchronize switching frequency

between master and slave controllers. Input capacitance

ESR requirements and efficiency losses are substantially

reduced because the peak current drawn from the input

capacitor is effectively divided by the number of phases

used and power loss is proportional to the RMS current

squared. A two-phase, single output voltage implementa-

tion can reduce input path power loss by 75% and radi-

cally reduce the required RMS current rating of the input

capacitor(s).

Like the LTC3887-1, the LTC3870-1 can use either induc-

tor DCR or R

to sense the inductor current. Inductor

SENSE

DCR current sensing provides a lossless method of sens-

ing the instantaneous current. Therefore, it can provide

higherefficiencyforapplicationswithhighoutputcurrents.

However, the DCR of a copper inductor typically has 10%

tolerance.Forprecisecurrentsensing,aprecisionsensing

resistor R

can be used to sense the inductor current.

SENSE

Itisimportanttomatchthecurrentsensingcircuitbetween

master controllers and slave controllers to guarantee bal-

anced load sharing and overcurrent protection.

38701f

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LTC3870-1

operaTion

2 + 2 OPERATION

1 + 3 OPERATION

CH0 CH1

CH0

120°

CH1

240°

CH0

0°

CH1

180°

0°

180°

LTC3870-1

PHASMD = 2/3 INTV OR FLOAT

LTC3887-1

CC

CH0 CH1

180° 0°

LTC3870-1

PHASMD = GND

4 PHASE OPERATION

6 PHASE OPERATION

CH0

90°

CH1

270°

CH0

0°

CH1

180°

CH0

CH1

180°

CH0

60°

CH1

300°

CH0

120°

CH1

240°

0°

LTC3870-1

PHASMD = INTV

LTC3887-1

LTC3870-1

PHASMD = 1/3 INTV

LTC3870-1

PHASMD = 2/3 INTV

CC

38701 F01

Figure 1. Examples of Single/Dual Output Multiphase Converters

Frequency Selection and Phase-Locked Loop (FREQ

and SYNC Pins)

integrated inside the LTC3870-1. The phase-locked loop

is capable of locking to any frequency within the range of

100kHz to 1MHz.

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching fre-

quency of the LTC3870-1 controllers can be synchronized

to the falling edge of the external clock on the SYNC pin

or selected using the FREQ pin. A phase-locked loop

(PLL) is integrated in the LTC3870-1 to synchronize the

internal oscillator to an external clock source that is con-

nected to the SYNC pin; this source is normally provided

by the master controllers. The PLL loop filter network is

If the SYNC pin is not being driven by an external clock

source, the FREQ pin can be used to program the

LTC3870-1’s operating frequency from 100kHz to 1MHz.

There is a precision 10µA current flowing out of the FREQ

pin, so the user can program the controller’s switching

frequency with a single resistor to SGND. A curve is pro-

vided later in the application section showing the relation-

ship between the voltage on the FREQ pin and switching

frequency.Thefrequencysettingresistorshouldalwaysbe

present to set the controller’s initial switching frequency

before locking to the external clock.

38701f

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LTC3870-1

applicaTions inForMaTion

INTV Regulators and EXTV

The Typical Application on the first page of this data sheet

is a basic LTC3870-1 application circuit featuring the

LTC3887-1 as a slave controller. In paralleled operation,

the current sensing scheme as well as the power stage

parameters in LTC3870-1 must be the same as the master

controller to achieve balanced current sharing between

masters and slaves. Finally, input and output capacitors

are selected based on RMS current rating, ripple, and

transient specs.

CC

The LTC3870-1 includes a PMOS LDO that supplies power

to INTV from the V supply. INTV powers most of the

CC

IN

CC

LTC3870-1’sinternalcircuitry.Thelinearregulatorregulates

the voltage at the INTV pin to 5.0V when V is greater

CC

IN

than6V.EXTV connectstoINTV throughanotherPMOS

CC

LDO and can supply the needed power when its voltage

is higher than 4.8V and V is higher than 6.5V. Each of

IN

these LDOs can supply a peak current of 100mA and must

be bypassed to ground with a minimum of 4.7µF ceramic

capacitororlowESRelectrolyticcapacitor. Nomatterwhat

type of bulk capacitor is used, an additional 0.1µF ceramic

Current Limit Programming

To match the master controller current limit, each channel

oftheLTC3870-1canbeprogrammedseparatelywithtwo

capacitor placed directly adjacent to the INTV and PGND

CC

currentranges. TheI pinofLTC3870-1isa4-levellogic

pins is highly recommended. Good bypassing is needed

LIM

inputwhichsetsthecurrentlimitofLTC3870-1.WhenI

to prevent interaction between the channels.

LIM

is grounded, both channel0 and channel1 are set to be low

TheINTV pinisnotshort-circuitproof.Ifoverloaded,this

CC

current range. When I is tied to INTV , both channel0

LIM

CC

will disrupt internal operation that can damage the part.

and channel1 are set to be high current range. Here, low

When the voltage applied to EXTV rises above 4.8V and

current range means the current sense threshold linearly

CC

V above 6.5V, the INTV linear regulator is turned off

increases from 0mV to 50mV as I voltage is increased

IN

CC

TH

and the EXTV linear regulator is turned on. Using the

from0.5Vto2.22Vwithoutslopecompensation.Highcur-

CC

EXTV allows the control power to be derived from other

rentrangemeansthecurrentsensethresholdincreasesto

CC

high efficiency sources such as +5V or +12V rails in the

75mV as I voltage is increased to 2.22V without slope

TH

system. Do not apply more than 14V to the EXTV pin.

compensation. Set I to one-third INTV for channel0

CC

LIM

CC

high current range and channel1 low current range. Set

For applications where the main input power is 5V, tie the

I

to two-thirds INTV or float for channel0 low current

LIM

CC

V and INTV pins together and tie the combined pins

IN

CC

range and channel1 high current range. The summary of

pin setups is shown in Table 2. For balanced load

to the 5V input with a 1Ω or 2.2Ω resistor as shown in

I

LIM

Figure 2 to minimize the voltage drop. This will override

current sharing, use the same current range setting as in

the master controller. Note that the LTC3870-1 does not

the INTV linear regulator and will prevent INTV from

CC

dropping too low due to the dropout voltage. Make sure

have active clamping circuit on the I pin for peak current

TH

theINTV voltageisatorexceedstheR testvoltage

CC

DS(ON)

limit and over current protection. Over current protection

for the external power MOSFETs which is typically 4.5V

relies on the master controller to drive and clamp the I

TH

for logic-level devices.

pinvoltagenottoexceedtheprogrammedvoltagethrough

the PMBus command.

Table 2. Current Limit Programming

V

IN

R

VIN

LTC3870-1

1Ω

Channel 0

Current limit

Channel 1

Current limit

INTV

5V

CC

I

LIM

+

GND

C

INTVCC

4.7µF

C

IN

GND

Range Low

Range High

Range Low

Range High

Range Low

Range High

1/3 INTV

CC

38701 F04

2/3 INTV or Float

CC

INTV

CC

Figure 2. Setup for a 5V Input

38701f

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LTC3870-1

applicaTions inForMaTion

Undervoltage Lockout

1400

1200

1000

800

600

400

200

0

The LTC3870-1 has a precision UVLO comparator con-

stantly monitoring the INTV voltage. It locks out the

CC

switching action and pulls down the RUN pins when

INTV is below 3.7V. To prevent oscillation when there

CC

is a disturbance on the INTV , the UVLO comparator has

CC

300mV of precision hysteresis. In multiphase operation,

when LTC3870-1 is in undervoltage lockout, the RUN0

and RUN1 pins are pulled down to disable the master’s

switching action.

0

0.5

1

1.5

2

2.5

FREQ PIN VOLTAGE (V)

38701 F02

Phase-Locked Loop and Frequency Synchronization

Figure 3. Relationship Between Oscillator

Frequency and Voltage at the FREQ Pin

The LTC3870-1 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the internal clock to be locked

to the falling edge of an external clock signal applied to

the SYNC pin. The turn-on of channel 0/channel 1’s top

MOSFET is synchronized or out-of-phase with the falling

edge of the external clock. The phase detector is an edge

sensitive digital type that provides zero degree phase shift

between the external and internal oscillators. This type of

phase detector does not exhibit false lock to harmonics

of the external clock.

2.4V 5V

10µA

R

SET

FREQ

SYNC

DIGITAL

PHASE/

SYNC

EXTERNAL

OSCILLATOR

FREQUENCY

DETECTOR

VCO

Theoutputofthephasedetectorisapairofcomplementary

current sources that charge or discharge the internal filter

network.Thereisaprecision10µAofcurrentflowingoutof

the FREQ pin. This allows the user to use a single resistor

to GND to set the switching frequency when no external

clock is applied to the SYNC pin. The voltage on the FREQ

pin is equal to the resistance multiplied by 10µA current

(e.g. the voltage is 1V with a 100k resistor from the FREQ

pin to SGND). The internal switch between FREQ pin and

the integrated PLL filter network is ON, allowing the filter

network to be pre-charged to the same voltage potential

as the FREQ pin. The relationship between the voltage

on the FREQ pin and the operating frequency is shown

in Figure 3 and specified in the Electrical Characteristics

table. If an external clock is detected on the SYNC pin, the

internalswitchmentionedabovewillturnoffandisolatethe

influence of FREQ pin. Note that the LTC3870-1 can only

be synchronized to an external clock whose frequency is

38701 F03

Figure 4. Phase-Locked Loop Block Diagram

within the range of the LTC3870-1’s internal VCO. This is

guaranteed to be between 100kHz and 1MHz. A simplified

block diagram is shown in Figure 4.

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than f , current is sunk continuously, pulling down

OSC

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

38701f

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For more information www.linear.com/LTC3870-1

LTC3870-1

applicaTions inForMaTion

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

balanced current sharing between master and slave, it is

recommended that each slave channel copy the design

from the master channel. Select same inductors, same

MOSFET driver, same current sensing circuit and same

output capacitors between the master channel and slave

channels. Control loop and compensation design on the

Typically, the external clock (on the SYNC pin) input high

threshold is 2V, while the input low threshold is 0.4V.

I

pin should start with the single phase operation of the

TH

master controller. If the master and slave channels are

exactly the same, then the transient response and loop

stability of the multiphase design is almost the same as

Fault Protection and Responses

LTC3887-1 master controllers monitor system voltage,

current, and temperature and provide many protection

features during fault conditions. LTC3870-1 slave con-

trollers do not provide as many fault monitors as master

controllers and have to respond to fault signals from the

master controller. FAULT0 and FAULT1 pins are designed

to share fault signals between masters and slaves. In a

typical parallel application, connect the FAULT pins on

LTC3870-1 to the master GPIO pins of the correspond-

ing paralleled channels and program the master GPIO as

fault sharing, so that the slave controller can respond to

all fault protections from the master. When the FAULT pin

is pulled below 1.4V, the PWM pin in the corresponding

channel is in three-state. When the FAULT pin voltage is

above 2V, the corresponding channel returns to normal

operation. During fault conditions, all internal circuits in

LTC3870-1 are still running so the slave controllers can

immediately go back to normal operation when the FAULT

pin is released.

the single phase operation of the master by tying the I

TH

pins together between the master and slaves. For example,

designthecompensationforasinglephase1.8V/20Aoutput

usingLTC3887-1witha0.56µHinductorand530µFoutput

capacitors. Toextendtheoutputto1.8V/40A, simplyparal-

lel one channel of LTC3870-1 with the same inductor and

output capacitors (total output capacitors are 1060µF) and

tie the I pin of LTC3870-1 to the master I . The loop

TH

stabilityandtransientresponsesofthetwophaseconverter

areverysimilartothesinglephasedesignwithoutanyextra

compensator on the I pin of LTC3870-1 slave controller.

TH

Furthermore, LTpowerCAD is provided on the LTC website

as a free download for transient and stability analysis.

To minimize the high frequency noise on the I trace

TH

between master and slave I pins, a small filter capacitor

TH

in the range of tens of pF can be placed closely at each I

TH

pin of the slave controller. This small capacitor normally

doesnotsignificantlyaffecttheclosedloopbandwidthbut

increases the gain margin at high frequency.

LTC3870-1 has internal thermal shutdown protection

which forces the PWM pin three-state when the junction

temperature is higher than 160°C. In thermal shutdown,

FAULT0 and FAULT1 pins are also pulled low. There is a

500kΩ pull-down resistor on each FAULT pin which sets

the default voltage on FAULT pins low if FAULT pins are

left floating.

Mode Selection and Pre-Biased Startup

There may be situations that require the power supply to

start up with a pre-bias on the output capacitors. In this

case, it is desirable to start up without discharging the

output capacitors. The LTC3870-1 can be configured to

DCM mode for pre-biased start-up. If a PGOOD signal is

available on the master controller, the PGOOD pin can be

connected to MODE pins of LTC3870-1 to ensure DCM

operation at startup and CCM operation at steady state.

Transient Response and Loop Stability

In a typical parallel operation, LTC3870-1 cooperates with

master controllers to supply more current. To achieve

38701f

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LTC3870-1

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Minimum On-Time Considerations

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. Figure 5 illustrates the current waveforms pres-

ent in the various branches of the 2-phase synchronous

regulators operating in the continuous mode. Check the

following in the PC layout:

Minimumon-timet

isthesmallesttimedurationthat

ON(MIN)

the LTC3870-1 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

1. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return of

t

< T

V /V

ON(MIN)

SW OUT IN

where T is the switching period.

SW

C

mustreturntothecombinedC (–)terminals.

INTVCC

OUT

The I traces should be as short as possible. The C

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase. The

minimum on-time for the LTC3870-1 is approximately

90ns, with reasonably good PCB layout, minimum 30%

inductor current ripple and at least 10mV ripple on the

current sense signal. The minimum on-time can be af-

fected by PCB switching noise in the current loop. As

the peak sense voltage decreases, the minimum on-time

gradually increases to 130ns. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-timelimitinthissituation, asignificantamountofcycle

skipping can occur with correspondingly larger current

and voltage ripple.

TH

IN

capacitor should have short leads and PC trace lengths.

The output capacitor (–) terminals should be connected

as close as possible to the (–) terminals of the input

capacitor by placing the capacitors next to each other.

+

–

2. Are the I

and I

leads routed together with

SENSE

minimumPCtracespacing?Thefiltercapacitorbetween

+

–

I

and I

should be as close as possible to

SENSE

the IC. Ensure accurate current sensing with Kelvin

connectionsatthesenseresistororinductor,whichever

is used for current sensing.

3. Is the INTV bypassing capacitor connected close to

CC

the IC, between the INTV and the ground pins? An

CC

additional 1µF ceramic capacitor placed immediately

next to the INTV and PGND pins can help improve

CC

noise performance substantially.

PWM Pins

4. Keep the switching nodes (SW1, SW0), away from

sensitive small-signal nodes, especially from the op-

posite channel’s current sensing feedback pins. All of

these nodes have very large and fast moving signals

and therefore should be kept on the “output side” of

the LTC3870-1 and occupy minimum PC trace area.

If DCR sensing is used, place the right resistor (Block

The PWM output pins are three-state compatible outputs,

designedtodriveMOSFETdrivers, DrMOSs, etc. whichdo

not represent a heavy capacitive load. An external resistor

divider may be used to set the voltage to mid-rail while in

the high impedance state.

The V pin is the corresponding PWM pin driver supply.

CC

Diagram, “R ”) close to the switching node.

C

Decouple this pin to GND with a capacitor (0.1µF) or tie

this pin to the INTV pin.

CC

5. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

MOSFET Driver Selection

capacitors with tie-ins for the bottom of the INTV

GatedriverICs,DrMOSsandpowerblockswithaninterface

compatiblewiththeLTC3870-1’sthree-statePWMoutputs

can be used.

CC

bypassingcapacitor,thebottomofthevoltagefeedback

resistive divider and the GND pin of the IC.

38701f

14

For more information www.linear.com/LTC3870-1

LTC3870-1

applicaTions inForMaTion

PC Board Layout Debugging

with high input voltages and low output currents, look for

capacitive coupling between the BOOST, SW, TG, and pos-

sibly BG connections and the sensitive voltage and current

pins. The capacitor placed across the current sensing pins

needs to be placed immediately adjacent to the pins of the

IC.Thiscapacitorhelpstominimizetheeffectsofdifferential

noise injection due to high frequency capacitive coupling. If

problems are encountered with high current output loading

at lower input voltages, look for inductive coupling between

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switchingnode(SWpin)tosynchronizetheoscilloscopeto

the internal oscillator and probe the actual output voltage

as well. Check for proper performance over the operating

voltageandcurrentrangeexpectedintheapplication. The

frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10% of the maximum designed current level in

Burst Mode operation.

C , Schottky and the top MOSFET components to the

IN

sensitive current and voltage sensing traces. In addition,

investigate common ground path voltage pickup between

these components and the SGND pin of the IC.

Design Example

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a sub-harmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controllerischeckedforitsindividualperformanceshould

bothcontrollersbeturnedonatthesametime.Aparticularly

difficultregionofoperationiswhenonecontrollerchannel

is nearing its current comparator trip point when the other

channel is turning on its top MOSFET. This occurs around

50% duty cycle on either channel due to the phasing of

the internal clocks and may cause minor duty cycle jitter.

As a design example using master chip LTC3887-1 and

slave chip LTC3870-1 for a 4-phase high current regula-

tor, assume V = 12V (nominal), V = 14V (maximum),

IN

V

= 1.0V, I

= 120A, and f = 425kHz (see Typical

OUT

Applications).

MAX

The master chip LTC3887-1 design can be found in the

LTC3887-1 data sheet Design Example section.

LTC3887-1's SYNC pin is connected to LTC3870-1's

SYNC pin and LTC3870-1's PHASMD is connected to

LTC3870-1’s GND.

Slave chip LTC3870-1 should use the same inductor,

DrMOS, C , and C

as the master chip. DCR sensing

IN

OUT

is also used for the slave chip.

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

LTC3870-1's I pin is forced to 0V to match the master

LIM

dervoltage lockout circuit by further lowering V while

IN

chip's 50mV current limit. Both chips' V , V , RUN,

IN OUT

monitoring the outputs to verify operation.

I

pins are connected together. LTC3887-1's GPIO pins

TH

are connected to LTC3870-1's FAULT pins so the slave

Investigatewhetheranyproblemsexistonlyathigheroutput

currentsoronlyathigherinputvoltages.Ifproblemscoincide

controller will be disabled during fault conditions.

38701f

15

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LTC3870-1

applicaTions inForMaTion

SW1

L1

V

OUT1

C

R

L1

D1

OUT1

V

IN

R

IN

C

IN

SW0

L0

V

OUT0

C

R

L0

D0

OUT0

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38701 F05

Figure 5. Branch Current Waveforms

38701f

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For more information www.linear.com/LTC3870-1

LTC3870-1

Typical applicaTions

High Efficiency 350kHz 2-Phase 3.3V and 2-Phase 1.8V Step-Down Converters

2 Ω

V

IN

7V TO 14V

4.7µF

0.1µF

0.22µF

V

INTV

IN

CC

V

OUT1

OUT0

SENSE1

SENSE0

CC0

100nF

0Ω

+

–

CC1

–

+

I

V

IN

BOOT PHASE

2k

1µF

SENSE0

IN

22µF x 2

25V

WP

I

10nF

L1

1.0µH

FDMF6820A GH

GL

TSNS0

PWM0

PWM

V

OUT0

VSWH

THWN#

PGND

V

DRV

3.3V/30A

C

10nF

OUT1

LTC3887-1

TSNS1

10k

100µF x 2

6.3V

DISB#

VCIN

2k

10Ω

V

DR

5V

C

OUT2

330µF

6.3V

+

SMOD#

CGND

5k

SHARE_CLK

SCL

1µF

I

–

+

SENSE1

ALERT

I

SENSE1

100nF

PWM1

SDA

100nF

BOOT PHASE

0Ω

VDD33

V

DD25

5k

V

IN

V

1.58k

1µF

4.7µF

IN

OUT0_CFG

22µF x 2

25V

GPIO0

GPIO1

RUN0

RUN1

SYNC

15.8k

10k

FDMF6820A

L2

0.56µH

GH

GL

5k

V

PWM

V

OUT1

OUT1_CFG

ASEL1

ASEL0

VSWH

THWN#

PGND

17.4k

3.57k

16.2k

30.1k

1.8V/40A

5k

V

DRV

C

OUT3

10k

4700pF

100µF x 2

6.3V

DISB#

VCIN

10Ω

2.55k

V

C

+

DR

5V

OUT4

SMOD#

CGND

330µF

6.3V

2k

1µF

FREQ_CFG

PHAS_CFG

180pF

I

TH0

1µF

I

TH1

GND

1500pF

13.7k

75pF

0.22µF

100nF

0Ω

2 Ω

V

BOOT PHASE

IN

7V TO 14V

2k

1µF

IN

22µF x 2

25V

4.7µF

L3

1.0µH

0.1µF

FDMF6820A GH

V

INTV

IN

CC

GL

PWM

V

RUN0

RUN1

SYNC

CC0

VSWH

THWN#

PGND

V

DRV

C

OUT5

CC1

–

10k

100µF x 2

6.3V

I

SENSE0

DISB#

VCIN

10Ω

V

DR

5V

C

+

I

+

I

OUT6

SMOD#

CGND

TH0

330µF

6.3V

I

TH1

180pF

2k

1µF

PWM0

LTC3870-1

75pF

FAULT0

FAULT1

I

–

+

SENSE1

100nF

PWM1

FREQ

EXTV

CC

100nF

BOOT PHASE

0Ω

82.5k

V

1.58k

L4

0.56µH

1.58k

1µF

IN

22µF x 2

25V

PHASMD

FDMF6820A

GH

GL

I

LIM

PWM

MODE0

MODE1

GND

VSWH

THWN#

PGND

V

DRV

C

OUT7

10k

100µF x 2

6.3V

DISB#

10Ω

V

DR

5V

C

+

OUT8

VCIN SMOD# CGND

330µF

6.3V

2k

1µF

C

:

Murata GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)

SANYO 6TPE330MFL (330µF, 6.3V)

OUT1,3,5,7

OUT2,4,6,8

38701 TA02

L1, L3: VISHAY IHLP-4040DZ-11 (1.0µH, DCR = 2.4mΩ)

L2, L4: VISHAY IHLP-4040DZ-11 (0.56µH, DCR = 1.61mΩ)

38701f

17

For more information www.linear.com/LTC3870-1

LTC3870-1

Typical applicaTions

High Efficiency 425kHz 4-Phase 1.0V Step-Down Converter

2 Ω

V

IN

7V TO 14V

4.7µF

0.1µF

100nF

V

INTV

CC0

CC1

SENSE0

IN

CC

V

I

V

OUT

SENSE1

SENSE0

100nF

0Ω

+

–

I

–

+

V

IN

BOOT PHASE

1.78k

1µF

SENSE0

WP

IN

22µF x 2

25V

L1

0.16µH

FDMF5820DC

V

OUT

GL

1.0V/120A

10nF

PWM0

PWM

PV

SW

TMON

PGND

AGND

CC

EN/FAULT#

C

TSNS0

OUT1

10k

100µF x 6

6.3V

25k

V

C

+

LTC3887-1

DR

5V

OUT2

V

CC

10k

ZCD#

10nF

470µF

2.5V

0.1µF

1µF

TSNS1

SDA

5k

I

–

+

SENSE1

SCL

I

100nF

PWM1

ALERT

100nF

0Ω

V

DD25

V

IN

BOOT PHASE

SHARE_CLK

VDD33

V

1.78k

1µF

IN

OUT0_CFG

22µF x 2

25V

7.32k

24.9k

OUT1_CFG

ASEL1

ASEL0

FDMF5820DC

L2

0.16µH

4.7µF

GL

PWM

5k

SW

TMON

PGND

AGND

17.8k

4.32k

1.96k

20k

PV

GPIO0

GPIO1

RUN0

RUN1

SYNC

CC

C

OUT3

10k

100µF x 6

6.3V

EN/FAULT#

FREQ_CFG

PHAS_CFG

V

DR

5V

C

OUT4

470µF

2.5V

24.9k

30.1k

+

25k

V

CC

ZCD#

10k

0.1µF

1µF

I

TH0

TH1

4700pF

GND

1µF

2.55k

47pF

100nF

0Ω

2 Ω

V

IN

BOOT PHASE

IN

1.78k

1µF

IN

22µF x 2

25V

7V TO 14V

4.7µF

L3

0.16µH

0.1µF

FDMF5820DC

V

INTV

IN

CC

GL

PWM

PV

V

RUN0

RUN1

SYNC

CC0

SW

TMON

PGND

AGND

CC

C

OUT5

CC1

–

10k

100µF x 6

6.3V

I

SENSE0

EN/FAULT#

V

25k

V

DR

5V

C

+

I

+

I

OUT6

TH0

ZCD#

CC

470µF

2.5V

I

TH1

47pF

10k

0.1µF

1µF

PWM0

LTC3870-1

I

–

+

SENSE1

FAULT0

FAULT1

100nF

PWM1

FREQ

100nF

0Ω

EXTV

CC

100k

V

BOOT PHASE

1.78k

1µF

IN

22µF x 2

25V

PHASMD

FDMF5820DC

L4

0.16µH

I

LIM

GL

PWM

PV

MODE0

MODE1

GND

SW

TMON

PGND

AGND

CC

EN/FAULT#

C

OUT7

10k

100µF x 6

6.3V

V

DR

5V

C

+

25k

OUT8

V

CC

10k

ZCD#

470µF

2.5V

0.1µF

1µF

C

:

Murata GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)

SANYO 2R5TPE470M9 (470µF, 2.5V)

OUT1,3,5,7

OUT2,4,6,8

38701 TA03

C

L1-4: COILCRAFT XAL7070-161 (0.16µH, DCR = 0.75mΩ)

38701f

18

For more information www.linear.com/LTC3870-1

LTC3870-1

package DescripTion

Please refer to http://www.linear.com/product/LTC3870-1#packaging for the most recent package drawings.

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-ꢀ697 Rev B)

0.70 0.05

4.50 0.05

3.ꢀ0 0.05

2.45 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN ꢀ N

R = 0.20

0.35 × 4

R = 0.ꢀꢀ5

TYP

0.75 0.05

4.00 0.ꢀ0

(4 SIDES)

23 24

PIN ꢀ

TOP MARK

(NOTE 6)

0.40 0.ꢀ0

ꢀ

2

2.45 0.ꢀ0

(4-SIDES)

(UF24) QFN 0ꢀ05 REV B

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

38701f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

19

For more information www.linear.com/LTC3870-1

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3870-1

Typical applicaTion

4-Phase 1.5V/80A Step-Down Converter with Sensing Resistors

V

IN

7V TO 14V

4.7µF

V

INTV

CC

IN

DrMOS: FAIRCHILD FDMF6820A

V

CC1

CC0

LTC3870-1

PWM0 PWM1

0.42µH

0.0015Ω

V

1.5V

80A

OUT

DrMOS

+

530µF

100Ω

I

+

I

+

SENSE0

SENSE1

1000pF

100Ω

I

-

I

-

SENSE0

SENSE1

EXTV

CC

LTC3887-1

RUN0

84.5k

RUN1

GPIO0

GPIO1

RUN1

1.5V

V

+

FAULT0

FAULT1

FREQ

PHASMD

SENSE0

V

+

I

LIM

SENSE1

TH0

TH1

I

MODE0

MODE1

GND

TH1

SYNC

* REFER TO LTC3887-1 DATA SHEET

FOR MASTER SETUP

38701 TA04

relaTeD parTs

PART

NUMBER

DESCRIPTION

COMMENTS

4.5V ≤ V ≤ 17V, 0.5V ≤ V

2

LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator

with Digital Power System Management

( 0.5ꢀ) ≤ 5.5V, I C/PMBus Interface,

OUT

IN

16mm × 16mm × 5mm, BGA Package

2

LTM4675

LTM4677

LTC3884

Dual 9A or Single 18A μModule Regulator

with Digital Power System Management

4.5V ≤ V ≤1 7V; 0.5V ≤ V ( 0.5ꢀ) ≤ 5.5V, I C/PMBus Interface,

IN

OUT

11.9mm × 16mm × 5mm, BGA Package

2

Dual 18A or Single 18A μModule Regulator

with Digital Power System Management

4.5V ≤ V ≤ 16V; 0.5V ≤ V ( 0.5ꢀ) ≤ 1.8V, I C/PMBus Interface,

IN

OUT

16mm × 16mm × 5.01mm, BGA Package

2

Dual Output Multiphase Step-Down Controller with Sub MilliOhm DCR 4.5V ≤ V ≤ 38V, 0.5V ≤ V

( 0.5ꢀ) ≤ 5.5V, 70ms Start-Up, I C/PMBus

Sensing Current Mode Control and Digital Power System Management Interface, Programmable Analog Loop Compensation, Input Current Sense

IN

OUT

2

LTC3887/ Dual Output Multiphase Step-Down DC/DC Controller

LTC3887-1 with Digital Power System Management, 70ms Start-Up

4.5V ≤ V ≤ 24V, 0.5V ≤ V

( 0.5ꢀ) ≤ 5.5V, 70ms Start-Up, I C/

IN

OUT0,1

PMBus Interface, –1 Version Uses DrMOS and Power Blocks

LTC3882/ Dual Output Multiphase Step-Down DC/DC Voltage Mode

LTC3882-1 Controller with Digital Power System Management

3V ≤ V ≤ 38V, 0.5V ≤ V

≤ 5.25V, 0.5ꢀ V

Accuracy

IN

OUT1,2

OUT

2

I C/PMBus Interface, Uses DrMOS or Power Blocks

LTC3886

60V Dual Output Step-Down Controller

with Digital Power System Management

4.5V ≤ V ≤ 60V, 0.5V ≤ V

( 0.5ꢀ) ≤ 13.8V, 70ms Start-Up,

IN

OUT0,1

2

I C/PMBus Interface, Input Current Sense

LTC3883/ Single Phase Step-Down DC/DC Controller

LTC3883-1 with Digital Power System Management

V

Up to 24V, 0.5V ≤ V

≤ 5.5V, Input Current Sense Amplifier,

IN

OUT

2

I C/PMBus Interface with EEPROM and 16-Bit ADC, 0.5ꢀ V

Accuracy

OUT

LTC3815

6A Monolithic Synchronous DC/DC Step-Down Converter

with Digital Power System Management

2.25V ≤ V ≤ 5.5V, 0.4V ≤ V

≤ 0.72V , Programmable V

Range

IN

OUT

IN

OUT

25ꢀ with 0.1ꢀ Resolution, Up to 3MHꢁ Operation with 13-bit ADC

LTC3874

Multiphase Step-Down Synchronous Slave Controller

with Sub MilliOhm DCR Sensing

4.5V ≤ V ≤ 38V, V Up to 5.5V, Very High Output Current,

IN

OUT

Accurate Current Sharing, Current Mode Applications

LTC3880/ Dual Output Multiphase Step-Down DC/DC Controller

LTC3880-1 with Digital Power System Management

4.5V ≤ V ≤ 24V, 0.5V ≤ V

( 0.5ꢀ) ≤ 5.4V, 145ms Start-Up,

IN

OUT0

2

I C/PMBus Interface with EEPROM and 16-Bit ADC

38701f

LT 1115 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

For more information www.linear.com/LTC3870-1

●

 LINEAR TECHNOLOGY CORPORATION 2015

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3870-1


型号：	LTC3882-1
厂家：	Linear
描述：	PolyPhase Step-Down Slave Controller for Digital Power System Management
文件：	总20页 (文件大小：1057K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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