LTC3884_技术文档

LTC3884/LTC3884-1

Dual Output PolyPhase

Step-Down Controller with Sub-Milliohm DCR Sensing

and Digital Power System Management

FEATURES

DESCRIPTION

2

PMBus/I CCompliantSerialInterface

The LTC^®3884/LTC3884-1 are dual output PolyPhase DC/

DCsynchronousstep-downswitchingregulatorcontrollers

n

–TelemetryRead-BackIncludesV ,I ,V ,I

TemperatureandFaults

,

IN IN OUT OUT

2

with an I C-based PMBus compliant serial interface. The

–ProgrammableVoltage,CurrentLimit,DigitalSoft-

Start/Stop,Sequencing,Margining,OV/UV/OC

Sub-Milliohm DCR Current Sensing

Digitally Adjustable Loop Compensation Parameters

±±0.5OutputVoltageAccuracyOverTemperature

IntegratedInputCurrentSenseAmplifier

controllers employ a constant-frequency current mode

architecture, together with a unique scheme to provide

excellent performance for sub-milliohm DCR applica-

tions. The LTC3884/LTC3884-1 are supported by the

LTpowerPlay^®software development tool with graphical

user interface (GUI).

n

InternalEEPROMwithECCandFaultLogging

IntegratedN-ChannelMOSFETGateDrivers(LTC3884)

Programmable loop compensation allows the controller

to be compensated digitally. Switching frequency, channel

phasing, output voltage, and device address can be pro-

grammed both by the digital interface as well as external

configuration resistors. Additionally, parameters can be set

via the digital interface or stored in EEPROM. Both outputs

haveindependentpowergoodindicatorsandFAULTfunction.

The LTC3884 has integrated gate drivers. The LTC3884-1

has three-state PWM pins to drive power blocks or DrMOS

power stages.

PowerConversion

n

WideV Range:4.5Vto38V

IN

n

V

Range:0.5Vto3.5V(withLowDCRSetting);

OUT

0.5Vto5.5V(withoutLowDCRSetting)

AccuratePolyPhase^®CurrentSharingforUpto6Phases

Availablein48-Lead7mm×7mmQFNand

5mm×6mmGQFNPackages.

n

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners. Protected

by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150,

7420359, 8648623, 8786265, 8823352, 7000125. Licensed under U.S. Patent 7000125 and

other related patents worldwide.

n

Telecom, Datacom, and Storage Systems

n

Industrial and Point-of-Load Applications

TYPICAL APPLICATION

1µF

1Ω

2mΩ

V

IN

Efficiency and Power Loss

vs Load Current

6V TO 15V

10µF

×2

10µF

×2

4.7µF

+

–

270µF

×2

INTV

TG0

V

IN

I

CC

IN

TG1

ꢀꢁꢁ

ꢀꢁ

8ꢀ

ꢀꢁ

4ꢀ

ꢀ

4

3

ꢀ

0.1µF

BOOST0

SW0

BOOST1

SW1

DCR=0.32mΩ

L=0.33µH

DCR=0.32mΩ

L=0.33µH

ꢀ

ꢀ ꢁꢂꢃ

ꢀꢁ

BG0

BG1

ꢀ

ꢀ ꢁꢂ8ꢃ

LTC3884*

ꢀꢁꢂ

ꢀꢁꢂꢃ ꢀꢁ

SDA

SCL

FAULT0

FAULT1

ꢀꢀ

3ꢀꢁꢂꢃꢄ

f

ꢀꢁꢂ

FAULT MANAGEMENT

PMBus

ALERT

RUN0

RUN1

PGOOD0

PGOOD1

INTERFACE

TO/FROM

SHARE_CLK

OTHER LTC DEVICES

EXTV

CC

931Ω

+

I

SENSE0

SENSE1

0.22µF

ꢀꢁꢁꢂꢃꢂꢀꢄꢃꢅ

ꢀꢁꢂꢃꢄ ꢅꢁꢆꢆ

–

I

V

SENSE0

SENSE1

OUT1

OUT0

1.8V

30A

+

–

1V

V

SENSE0

SENSE1

–

ꢀ

ꢀꢁ

3ꢀ

30A

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ

TSNS0

TSNS1

TH1

THR1

DD25

3884 ꢀꢁꢂꢃꢄ

I

V

I

TH0

THR0

DD33

330µF

×2

330µF

×2

I

PGND SGND V

10nF

4700pF

220pF

2200pF

1µF 220pF

10nF

1µF

*SOME DETAILS OMITTED FOR CLARITY

3884 TA01a

3884fe

1

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TABLE OF CONTENTS

Features00000000000000000000000000000000000000000000000000000 1

Applications 000000000000000000000000000000000000000000000000 1

Typical Application 0000000000000000000000000000000000000000 1

Description00000000000000000000000000000000000000000000000000 1

Table of Contents 000000000000000000000000000000000000000000 2

Absolute Maximum Ratings000000000000000000000000000000 4

Pin Configuration 000000000000000000000000000000000000000000 4

Order Information000000000000000000000000000000000000000000 .

Electrical Characteristics000000000000000000000000000000000 6

Typical Performance Characteristics 00000000000000000012

Pin Functions000000000000000000000000000000000000000000000017

Block Diagram00000000000000000000000000000000000000000000019

Operation0000000000000000000000000000000000000000000000000002±

Overview.................................................................20

Main Control Loop..................................................21

EEPROM .................................................................21

Power-Up and Initialization .....................................22

Soft-Start................................................................23

Time-Based Sequencing.........................................23

Voltage-Based Sequencing.....................................23

Shutdown ...............................................................24

Light-Load Current Operation .................................24

Switching Frequency and Phase.............................25

PWM Loop Compensation......................................25

Output Voltage Sensing ..........................................25

Device Addressing..................................................32

Responses to V , I and I

Faults...................32

OUT IN

OUT

Output Overvoltage Fault Response ...................33

Output Undervoltage Response..........................33

Peak Output Overcurrent Fault Response...........33

Responses to Timing Faults....................................33

Responses to V OV Faults....................................34

IN

Responses to OT/UT Faults.....................................34

Internal Overtemperature Fault Response ..........34

External Overtemperature and

Undertemperature Fault Response .....................34

Responses to Input Overcurrent and Output

Undercurrent Faults................................................34

Responses to External Faults..................................34

Fault Logging..........................................................34

Bus Timeout Protection..........................................35

Similarity Between PMBus, SMBus and

2

I C 2-Wire Interface................................................35

PMBus Serial Digital Interface................................35

PMBus Command Summary 00000000000000000000000000004±

PMBus Commands.................................................40

*Data Format..........................................................45

Applications Information 0000000000000000000000000000000046

Current Limit Programming....................................46

I

and I

Pins......................................46

SENSE0

SENSE1

INTV /EXTV Power...........................................25

Inductor DCR Sensing........................................47

CC

Output Current Sensing and Sub Milliohm DCR

Inductor Value Calculation ......................................48

Inductor Core Selection ..........................................48

Low Value Resistor Current Sensing.......................48

Slope Compensation and Inductor Peak Current ....49

Power MOSFET and Optional Schottky Diode

Selection.................................................................50

Variable Delay Time, Soft-Start and Output

Current Sensing......................................................26

Input Current Sensing.............................................27

PolyPhase Load Sharing.........................................27

External/Internal Temperature Sense......................27

RCONFIG (Resistor Configuration) Pins..................28

Fault Detection and Handling..................................29

Status Registers and ALERT Masking.................29

Mapping Faults to FAULT Pins ............................31

Power Good Pins................................................31

CRC Protection and ECC.....................................31

Serial Interface .......................................................32

Communication Protection.................................32

Voltage Ramping ....................................................50

Digital Servo Mode................................................. 51

Soft Off (Sequenced Off)........................................52

INTV /EXTV Power...........................................52

CC

Topside MOSFET Driver Supply (C , D ) ................53

B

Undervoltage Lockout.............................................54

C and C

IN

Selection ...........................................54

OUT

3884fe

2

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TABLE OF CONTENTS

Fault Indication .......................................................55

Open-Drain Pins .....................................................55

Phase-Locked Loop and Frequency

Input Voltage and Limits.....................................81

Output Voltage and Limits..................................82

Output Current and Limits ......................................85

Input Current and Limits ....................................87

Temperature............................................................88

External Temperature Calibration........................88

Timing ....................................................................89

Timing—On Sequence/Ramp.............................89

Timing—Off Sequence/Ramp ............................90

Precondition for Restart .....................................91

Fault Response .......................................................91

Fault Responses All Faults..................................91

Fault Responses Input Voltage ...........................92

Fault Responses Output Voltage.........................92

Fault Responses Output Current.........................95

Fault Responses IC Temperature ........................96

Fault Responses External Temperature...............97

Fault Sharing...........................................................98

Fault Sharing Propagation ..................................98

Fault Sharing Response.................................... 100

Scratchpad ........................................................... 100

Identification......................................................... 101

Fault Warning and Status...................................... 102

Telemetry.............................................................. 109

NVM Memory Commands .................................... 113

Store/Restore ................................................... 113

Fault Log Operation .......................................... 114

Fault Logging.................................................... 114

Block Memory Write/Read................................ 118

Typical Applications000000000000000000000000000000000000 119

Package Description 00000000000000000000000000000000000 12.

Revision History 0000000000000000000000000000000000000000 127

Typical Application 0000000000000000000000000000000000000 128

Related Parts00000000000000000000000000000000000000000000 128

Synchronization .....................................................56

Minimum On-Time Considerations..........................56

External Temperature Sense...................................57

Input Current Sense Amplifier.................................58

External Resistor Configuration Pins (RCONFIG)....58

Voltage Selection................................................59

Frequency Selection ...........................................59

Phase Selection..................................................60

Address Selection Using RCONFIG.....................60

Efficiency Considerations .......................................61

Programmable Loop Compensation .......................62

Checking Transient Response.................................63

PolyPhase Configuration ....................................64

Master Slave Operation ......................................64

PC Board Layout Checklist .....................................67

PC Board Layout Debugging...................................67

Design Example......................................................68

Additional Design Checks .......................................69

2

Connecting the USB to I C/SMBus/PMBus

Controller to the LTC3884 in System......................69

LTpowerPlay: An Interactive GUI for

Digital Power ..........................................................70

PMBus Communication and Command

Processing..............................................................70

PMBus Command Details 000000000000000000000000000000073

Addressing and Write Protect.................................73

General Configuration Commands..........................75

On/Off/Margin ........................................................76

PWM Configuration ................................................78

Voltage....................................................................81

3884fe

3

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ABSOLUTE MAXIMUM RATINGS

(Note 1)

+

–

V , I , I .............................................. –0.3V to 40V

V

, V

................................... –0.3V to 0.3V

SENSE1

IN IN IN

SENSE0

+

–

(V – I ), (I – I ) ............................. –0.3V to 0.3V

EXTV , INTV ........................................... –0.3V to 6V

IN

CC CC

BOOST0, BOOST1 (LTC3884) .................... –0.3V to 46V

(EXTV – V ) ........................................................5.5V

CC IN

Switch Transient Voltage (SW0, SW1)

PGOOD0, PGOOD1.................................... –0.3V to 3.6V

(LTC3884)................................................. –5V to 40V

(BOOST0-SW0), (BOOST1-SW1)

RUN0, RUN1, SDA, SCL, ALERT ................ –0.3V to 5.5V

ASEL0, ASEL1, V

, V

,

OUT0_CFG0 OUT1_CFG

(LTC3884)................................................ –0.3V to 6V

Top Gate Transient Voltage TG0, TG1

FREQ_CFG, PHASE_CFG .................... –0.3V to 2.75V

FAULT0, FAULT1, SHARE_CLK, WP, SYNC –0.3V to 3.6V

TSNS0, TSNS1.......................................... –0.3V to 3.6V

TH0 TH1 THR0 THR1

Operating Junction Temperature Range

(Notes 2, 17, 18).......................................–40°C to 125°C

Storage Temperature Range ................ –65°C to 150°C*

*See Derating EEPROM Retention at Temperature in Applications Informa-

tion section for junction temperatures in excess of 125°C.

(LTC3884)................................................–5V TO 46V

V

, V

(LTC3884-1) ............................... –0.3V to 6V

I

, I , I

, I

.............................. –0.3V to 3.6V

CC0 CC1

Top Gate Transient Voltage PWM0, PWM1

(LTC3884-1)............................................. –0.3V to 6V

+

–

+

–

I

, I

, I ,

SENSE0 SENSE0

SENSE1 SENSE1

+

V

, V

...................................... –0.3V to 6V

SENSE0

SENSE1

PIN CONFIGURATION

LTC3884

ꢀꢁꢂ ꢃꢄꢅꢆ

ꢙ

ꢂꢉꢁꢁꢋꢚ ꢛ

38 ꢡꢉꢛ

3ꢟ ꢡꢁꢁꢈꢀꢛ

3ꢖ ꢀꢉꢛ

3ꢔ ꢈꢆꢛ

34 ꢂꢉꢁꢁꢋꢛ

ꢃ

ꢄ

ꢚ

ꢜ

3

4

ꢟ

ꢠ

ꢓ

8

3ꢠ ꢢꢁꢁꢈꢀꢚ

3ꢟ ꢀꢉꢚ

34 ꢈꢆꢚ

ꢈꢅꢊꢈꢅꢘ

ꢈꢅꢊꢈꢅꢚ

ꢜ

ꢃ

ꢝ

3

4

ꢔ

ꢖ

ꢟ

8

ꢇ

ꢛ

ꢙ

ꢛ

ꢈꢅꢊꢈꢅꢚ

ꢈꢅꢊꢈꢅꢛ

ꢞ

ꢜ

ꢞ

ꢃ

ꢄ

4ꢇ

ꢄ

33 ꢂꢉꢁꢁꢋꢚ

ꢈꢅꢊꢈꢅꢚ

ꢄ

ꢈꢅꢊꢈꢅꢛ

ꢄ

ꢙ

ꢜ

ꢞ

3ꢜ ꢃ

3ꢚ ꢃ

ꢀꢝꢞꢘ

ꢈꢅꢊꢈꢅꢚ

33 ꢃ

3ꢝ ꢃ

3ꢛ ꢄꢀꢍꢌꢛ

3ꢚ ꢄꢀꢍꢛ

ꢝꢇ ꢃ

ꢀꢍꢌꢚ

ꢈꢅꢊꢈꢅꢛ

ꢛ

ꢄ

4ꢇ

ꢈꢉꢊꢋ

ꢄ

4ꢇ

ꢈꢉꢊꢋ

ꢀꢝꢘ

ꢈꢅꢊꢈꢅꢚ

ꢀꢍꢚ

ꢜ

ꢞ

ꢙ

ꢈꢅꢊꢈꢅꢘ

ꢛ

ꢄ

3ꢘ ꢄꢀꢝꢞꢚ

ꢜꢇ ꢄꢀꢝꢚ

ꢈꢅꢊꢈꢅꢚ

ꢈꢅꢊꢈꢅꢘ

ꢀꢈꢊꢈꢛ ꢛꢚ

ꢀꢈꢊꢈꢚ ꢛꢛ

ꢈꢠꢊꢏ ꢛꢝ

ꢈꢏꢒ ꢛ3

ꢋꢋ33

ꢀꢈꢊꢈꢚ ꢇ

ꢜ8 ꢃ

ꢋꢋ33

ꢝ8 ꢈꢍꢎꢌꢅꢢꢏꢒꢐ

ꢝꢟ ꢆꢂ

ꢀꢈꢊꢈꢘ ꢚꢘ

ꢈꢡꢊꢏ ꢚꢚ

ꢈꢏꢑ ꢚꢜ

ꢜꢓ ꢈꢝꢎꢞꢅꢣꢏꢑꢍ

ꢜꢠ ꢆꢂ

ꢝꢖ ꢃ

ꢋꢋꢝꢔ

ꢜꢟ ꢃ

ꢋꢋꢜꢟ

ꢈꢋꢎ ꢛ4

ꢝꢔ ꢂꢍꢎꢈꢅꢢꢏꢙꢉ

ꢌꢍ ꢂꢎꢏꢍꢎꢉꢅ

48ꢐꢑꢅꢎꢋ ꢒꢓꢔꢔ × ꢓꢔꢔꢕ ꢂꢑꢎꢈꢀꢄꢏ ꢖꢗꢊ

ꢌꢍꢅ ꢂꢎꢏꢐꢎꢉꢅ

48ꢑꢒꢅꢎꢋ ꢓꢔꢕꢕ × ꢖꢕꢕꢗ ꢂꢒꢎꢈꢀꢄꢏ ꢉꢘꢙꢊ

T

= 125°C, θ = 31°C/W, θ = 3°C/W

T

= 125°C, θ = 31°C/W, θ = 3.7°C/W

JMAX JA JC

JMAX

JA

JC

EXPOSED PAD (PIN 49) IS SGND, MUST BE SOLDERED TO PCB

EXPOSED PADS (PIN 49) ARE SGND, MUST BE SOLDERED TO PCB

3884fe

4

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PIN CONFIGURATION

LTC3884-1

ꢀꢁꢂ ꢃꢄꢅꢆ

ꢂꢉꢁꢁꢋꢚ ꢛ

ꢜ

38 ꢊꢏ

3ꢟ ꢃ

3ꢖ ꢂꢆꢡꢛ

3ꢔ ꢊꢏ

34 ꢂꢉꢁꢁꢋꢛ

ꢃ

ꢄ

ꢝ

3

4

ꢔ

ꢖ

ꢟ

8

ꢇ

ꢈꢅꢊꢈꢅꢚ

ꢈꢅꢊꢈꢅꢛ

ꢏꢏꢛ

ꢞ

ꢜ

ꢞ

4ꢇ

ꢄ

ꢈꢅꢊꢈꢅꢛ

ꢄ

ꢜ

ꢞ

33 ꢃ

3ꢝ ꢃ

3ꢛ ꢄꢀꢍꢌꢛ

3ꢚ ꢄꢀꢍꢛ

ꢝꢇ ꢃ

ꢀꢍꢌꢚ

ꢈꢅꢊꢈꢅꢛ

ꢄ

4ꢇ

ꢈꢉꢊꢋ

ꢀꢍꢚ

ꢜ

ꢞ

ꢄ

ꢈꢅꢊꢈꢅꢚ

ꢀꢈꢊꢈꢛ ꢛꢚ

ꢀꢈꢊꢈꢚ ꢛꢛ

ꢈꢠꢊꢏ ꢛꢝ

ꢈꢏꢒ ꢛ3

ꢋꢋ33

ꢝ8 ꢈꢍꢎꢌꢅꢢꢏꢒꢐ

ꢝꢟ ꢆꢂ

ꢝꢖ ꢃ

ꢋꢋꢝꢔ

ꢈꢋꢎ ꢛ4

ꢝꢔ ꢂꢍꢎꢈꢅꢢꢏꢙꢉ

ꢌꢍꢅ ꢂꢎꢏꢐꢎꢉꢅ

48ꢑꢒꢅꢎꢋ ꢓꢔꢕꢕ × ꢖꢕꢕꢗ ꢂꢒꢎꢈꢀꢄꢏ ꢉꢘꢙꢊ

T

= 125°C, θ = 31°C/W, θ = 3.7°C/W

JA JC

JMAX

EXPOSED PADS (PIN 49) ARE SGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION ^{(http://www0linear0com/product/LTC3884#orderinfo)}

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3884EUK#PBF

LTC3884IUK#PBF

LTC3884ERHE#PBF

LTC3884IRHE#PBF

LTC3884ERHE-1#PBF

LTC3884IRHE-1#PBF

LTC3884EUK#TRPBF

LTC3884IUK#TRPBF

LTC3884ERHE#TRPBF

LTC3884IRHE#TRPBF

LTC3884ERHE-1#TRPBF LTC3884-1

LTC3884IRHE-1#TRPBF LTC3884-1

LTC3884 UK

LTC3884

48-Lead (7mm × 7mm) Plastic QFN

48-Lead (5mm × 6mm) Plastic GQFN

–40°C to 125°C

LTC3884

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

3884fe

5

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2.°C (Notes 2, 3)0 V_IN= 12V, EXTV_CC= ±V, V_RUN±,1= 303V,

f_SYNC= .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

Input Voltage

l

V

IN

Input Voltage Range

(Note 11)

4.5

38

V

I

Q

Input Voltage Supply Current

V

= 3.3V (Note 16)

= 0V (Note 16)

25

23

mA

RUN0,1

V

Undervoltage Lockout Threshold

V

Falling

Rising

3.55

3.90

V

UVLO

INTVCC

When V > 4.3V

IN

t

Initialization Time

Time from V Applied Until the TON_DELAY

35

ms

INIT

IN

Timer Starts

Short Cycle Retry Time

120

ms

OFF(MIN)

Control Loop

l

V

Full-Scale Voltage Range

Set Point Accuracy (0.6V ~ 2.5V)

Resolution

VOUT_COMMAND = 2.75V,

MFR_PWM_MODE[1] = 1

(Notes 9, 10, 13)

2.7

–0.5

2.8

0.5

V

%

Bits

mV

OUTRL

12

0.688

LSB Step Size

l

V

Full-Scale Voltage Range

Set Point Accuracy (0.6V ~ 5.0V)

Resolution

VOUT_COMMAND = 5.5V,

MFR_PWM_MODE[1] = 0

(Notes 9, 10, 13)

5.40

–0.5

5.60

0.5

V

%

Bits

mV

OUTRH

12

1.375

LSB Step Size

l

V

Line Regulation

Load Regulation

6V < V < 38V

0.02

%/V

LINEREG

IN

l

∆V = 1.35V ~ 0.7V

0.01

–0.01

0.1

–0.1

%

LOADREG

ITH

∆V = 1.35V ~ 2V

ITH

l

I

Input Pin Bias Current

0V ≤ V ≤ 5.5V

1

50

12

3

µA

kΩ

ISENSE0,1

V

Input Resistance to GND

0V ≤ V ≤ 5.5V

SENSERIN0,1

SENSE

(Note 15)

Steps

ILIMIT

l

V

MFR_PWM_MODE[7],[2]=0, 1, I [3:0]=1100, V ≤ 3.5V

14.5

27.0

35

16.5

9.5

18.5

31.0

49

mV

ILIM_HIGH

ILIM_LOW

REV

LIM

OUT

MFR_PWM_MODE[7],[2]=0, 1, I [3:0]=0001, V ≤ 3.5V

LIM

OUT

MFR_PWM_MODE[7],[2]=0, 1, V ≥ V

–7.5

OUT

OV

V

MFR_PWM_MODE[7],[2]=1, 1, I [3:0]=1100,V ≤ 3.5V

29.5

17.0

–15

mV

ILIM_HIGH

ILIM_LOW

REV

LIM

OUT

MFR_PWM_MODE[7],[2]=1, 1, I [3:0]=0001,V ≤ 3.5V

LIM

OUT

MFR_PWM_MODE[7],[2]=1, 1, V ≥ V

OUT

OV

V

MFR_PWM_MODE[7],[2]=0, 0, I [3:0]=1100

41.38

25

–18.8

mV

ILIM_HIGH

ILIM_LOW

REV

LIM

MFR_PWM_MODE[7],[2]=0, 0, I [3:0]=0001

LIM

MFR_PWM_MODE[7],[2]=0, 0, V ≥ V

OUT

OV

V

MFR_PWM_MODE[7],[2]=1, 0, I [3:0]=1100

67.5

74.5

43.5

–37.5

81.5

mV

ILIM_HIGH

ILIM_LOW

REV

LIM

MFR_PWM_MODE[7],[2]=1, 0, I [3:0]=0001

LIM

MFR_PWM_MODE[7],[2]=1, 0, V ≥ V

OUT

OV

g

Resolution

I

= 1.35V, MFR_PWM_COMP[7:5] = 0 to 7

3

Bits

mmho

m0,1

TH0,1

Error Amplifier g

LSB Step Size

5.76

1

m(MAX)

m(MIN)

0.68

R

Resolution

Compensation Resistor R

MFR_PWM_COMP[4:0] = 0 to 31 (See Figure 37)

5

62

0

Bits

kΩ

TH0, 1

TH(MAX)

TH(MIN)

Gate Drivers (LTC3884)

TG R

BG R

TG Pull-Up R

TG High

TG Low

BG High

2.6

1.5

2.4

Ω

UP

DS(ON)

TG Pull-Down R

DOWN

UP

DS(ON)

BG Pull-Up R

3884fe

6

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2.°C (Notes 2, 3)0 V_IN= 12V, EXTV_CC= ±V, V_RUN±,1= 303V,

f_SYNC= .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0

SYMBOL

PARAMETER

CONDITION

BG Low

MIN

TYP

MAX

UNITS

BG R

BG Pull-Down R

1.1

Ω

DOWN

DS(ON)

TG

TG Transition Time:

Rise Time

Fall Time

(Note 4)

LOAD

t

C

= 3300pF

30

ns

r

f

t

BG

BG Transition Time:

Rise Time

Fall Time

(Note 4)

LOAD

t

C

= 3300pF

30

ns

r

f

t

TG/BG, t

Top Gate Off to Bottom Gate on

Delay Time

(Note 4) C

= 3300pF at Each Driver

30

60

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate on

Delay Time

(Note 4) C

= 3300pF at Each Driver

2D

LOAD

t

Minimum On-Time

ON(MIN)

PWM±/PWM1 Outputs (LTC3884-1)

PWM

PWM Output High Voltage

PWM Output Low Voltage

PWM Output in Hi-Z State

I

= 500µA

= –500µA

V

CC

– 0.2

V

µA

LOAD

0.2

5

–5

OV/UV Output Voltage Supervisor Channel ±/1

N

Resolution

9

Bits

mV

V

LSB Step Size

MFR_PWM_MODE[1] = 1 (Note 13)

MFR_PWM_MODE[1] = 0 (Note 13)

MFR_PWM_MODE[1] = 1

5.6

11.2

OUSTPSP_RL

OUSTPSP_RH

RANGE_RL

RANGE_RH

THAC0_RL

THAC1_RH

PROPOV

LSB Step Size

Voltage Monitoring Range

0.5

1

2.7

5.6

1.5

MFR_PWM_MODE[1] = 0

V

l

Threshold Accuracy 1V < V

< 2.5V MFR_PWM_MODE[1] = 1

%

OUT

Threshold Accuracy 2V < V < 5.5V MFR_PWM_MODE[1] = 0

%

OUT

t

OV Comparator Response Time

UV Comparator Response Time

V

OD

V

OD

= 10% of Threshold

100

µs

PROPUV

V

IN

Voltage Supervisor

N

Resolution

9

Bits

mV

V

LSB Step Size

Full-Scale Voltage

76

INSTP

IN

4.5

38

Threshold Accuracy 9V < V < 38V

Threshold Accuracy 4.5V < V ≤ 9V

3

6.0

%

INTHACCM

IN

t

Comparator Response Time

(VIN_ON and VIN_OFF)

V

= 10% of threshold

= 0 (Note 8)

100

µs

PROPVIN

OD

Output Voltage Readback

N

Resolution

16

244

8

Bits

µV

V

LSB Step Size

OUTSTP

F/S

Full-Scale Sense Voltage

Total Unadjusted Error

Zero-Code Offset Voltage

Update Rate

V

RUNn

l

> 0.6V (Note 8)

OUT

–0.5

0.5

%

OUT_TUE

OS

500

µV

ms

t

(Note 6)

(Note 5)

90

10

CONVERT

V

Voltage Readback

IN

N

Resolution

Bits

3884fe

7

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2.°C (Notes 2, 3)0 V_IN= 12V, EXTV_CC= ±V, V_RUN±,1= 303V,

f_SYNC= .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

V

Full-Scale Input Voltage

Total Unadjusted Error

(Note 11)

43

V

F/S

V

VIN

> 4.5V (Note 8)

0.5

2

%

INTUE

l

t

Update Rate

(Note 6)

90

10

ms

CONVERT

Output Current Readback

N

Resolution

(Note 5)

Bits

+

–

V

LSB Step Size

0V ≤ |V

– V

| < 16mV

15.63

31.25

62.5

µV

IOUTSTP

ISENSE

+

–

16mV ≤ |V

32mV ≤ |V

64mV ≤ |V

– V

| < 32mV

| < 64mV

| < 128mV

ISENSE

+

–

125

I

Full-Scale Input Current

Total Unadjusted Error

Zero-Code Offset Voltage

Update Rate

(Note 7) DCR or R

= 1mΩ

128

A

%

F/S

ISENSE

–

+

l

V

– V

> 6mV (Note 8)

1.25

50

OUT_TUE

ISENSE

V

µV

ms

OS

t

(Note 6)

90

10

CONVERT

Input Current Readback

Resolution

N

(Note 5)

Bits

+

–

V

IINSTP

LSB Step Size Full-Scale Range = 16mV Gain = 8, 0V ≤ |V

LSB Step Size Full-Scale Range = 32mV Gain = 4, 0V ≤ |V

LSB Step Size Full-Scale Range = 64mV Gain = 2, 0V ≤ |V

– V | ≤ 5mV

15.26

30.52

61

µV

IIN

–

– V | ≤ 20mV

IIN

– V | ≤ 50mV

IIN

+

–

l

I

Total Unadjusted Error

Gain = 8, 2.5mV ≤ |V

– V | V = 8V (Note 8)

2

1.3

1.2

%

IN_TUE

IIN

IN

+

–

Gain = 4, 4mV ≤ |V

Gain = 2, 6mV ≤ |V

– V | V = 8V (Note 8)

IIN

IN

+

–

IIN

IN

V

Zero-Code Offset Voltage

Update Rate

50

µV

OS

t

(Note 6)

(Note 5)

90

ms

CONVERT

Supply Current Readback

N

Resolution

10

Bits

µV

V

LSB Step Size Full-Scale Range =

256mV

244

ICHIPSTP

+

l

I

t

Total Unadjusted Error

Update Rate

|V

– V | ≤ 150mV (Note 19)

3

%

CHIPTUE

IIN

IN

(Note 6)

90

ms

CONVERT

Temperature Readback (T±, T1)

T

Resolution

0.25

°C

RES_T

T0_TUE

External Temperature Total

Unadjusted Readback Error

TSNS0, TSNS1 ≤ 1.85V (Note 8)

MFR_PWM_MODE_[5] = 0

MFR_PWM_MODE_[5] = 1 (Note 14)

–3

–10

3

10

°C

T1_TUE

Internal TSNS TUE

Update Rate

V

= 0.0, f

= 0kHz (Note 8)

SYNC

1

°C

RUN0,1

t

(Note 6)

90

ms

CONVERT

INTV Regulator/EXTV

CC

V

Internal V Voltage No Load

6V ≤ V ≤ 38V

5.25

4.5

5.5

0.5

4.7

290

50

5.75

2

V

%

INTVCC

CC

IN

INTV Load Regulation

I = 0mA to 20mA, 6V ≤ V ≤ 38V

CC IN

LDO_INT

EXTVCC

CC

EXTV Switchover Voltage

V

IN

≥ 7V, EXTV Rising

V

CC

EXTV Hysteresis

mV

LDO_HYS

LDO_EXT

CC

EXTV Voltage Drop

I

CC

= 20mA, V = 5.5V

EXTVCC

100

CC

3884fe

8

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2.°C (Notes 2, 3)0 V_IN= 12V, EXTV_CC= ±V, V_RUN±,1= 303V,

f_SYNC= .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0

SYMBOL

PARAMETER

Threshold to Enable EXTV

CONDITION

MIN

TYP

MAX

UNITS

V

IN

Rising

7

V

IN_THR

IN

CC

Switchover

V

Threshold to Disable EXTV

V

IN

Falling

6.5

V

IN_THF

IN

CC

Switchover

V

Regulator

DD33

LIM

V

Internal V

Voltage

4.5V < V

or 4.8V < V

EXTVCC

3.2

3.3

100

3.5

3.1

3.4

V

mA

V

DD33

INTVCC

I

V

Current Limit

V

DD33

= GND, V = INTV = 4.5V

IN CC

DD33

V

Overvoltage Threshold

DD33_OV

DD33_UV

Undervoltage Threshold

V

Regulator

DD2.

DD25

LIM

Internal V

Voltage

2.5

80

V

DD25

I

V

Current Limit

V

DD25

= GND, V = INTV = 4.5V

mA

DD25

IN

CC

Oscillator and Phase-Locked Loop

l

f

PLL SYNC Range

Syncronized with Falling Edge of SYNC

Frequency Switch = 250.0 to 1000.0 kHz

200

1000

7.5

kHz

%

RANGE

OSC

Oscillator Frequency Accuracy

SYNC Input Threshold

V

SYNC

V

SYNC

Falling

Rising

1

1.5

V

TH(SYNC)

V

SYNC Low Output Voltage

I

= 3mA

0.2

0.4

5

V

OL(SYNC)

LOAD

I

SYNC Leakage Current in Slave Mode 0V ≤ V ≤ 3.6V

µA

LEAK(SYNC)

θSYNC-θ0

SYNC to Ch0 Phase Relationship

Based on the Falling Edge of Sync

and Rising Edge of TG0

MFR_PWM_CONFIG[2:0] = 0,2,3

0

Deg

MFR_PWM_CONFIG[2:0] = 5

MFR_PWM_CONFIG[2:0] = 1

MFR_PWM_CONFIG[2:0]= 4,6

60

90

120

θSYNC-θ1

SYNC to Ch1 Phase Relationship

Based on the Falling Edge of Sync

and Rising Edge of TG1

MFR_PWM_CONFIG[2:0] = 3

MFR_PWM_CONFIG[2:0] = 0

MFR_PWM_CONFIG[2:0] = 2,4,5

MFR_PWM_CONFIG[2:0] = 1

MFR_PWM_CONFIG[2:0] = 6

120

180

240

270

300

Deg

EEPROM Characteristics

l

Endurance

Retention

(Note 12)

0°C < T < 85°C EEPROM Write Operations

10,000

10

Cycles

Years

ms

J

T < 125°C

J

Mass_Write Mass Write Operation Time

STORE_USER_ALL, 0°C < T < 85°C

440

4100

J

During EEPROM Write Operation

Leakage Current SDA, SCL, ALERT, RUN

l

I

Input Leakage Current

Leakage Current FAULTn, PGOODn

Input Leakage Current

Digital Inputs SCL, SDA, RUNn, GPI0n

OV ≤ V ≤ 5.5V

5

2

µA

OL

I

GL

OV ≤ V ≤ 3.6V

l

V

C

Input High Threshold Voltage

Input Low Threshold Voltage

Input Hysteresis

1.35

V

IH

0.8

IL

SCL, SDA

WP

0.08

10

V

HYST

Input Capacitance

10

pF

Digital Input WP

Input Pull-Up Current

I

µA

PUWP

3884fe

9

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 2.°C (Notes 2, 3)0 V_IN= 12V, EXTV_CC= ±V, V_RUN±,1= 303V,

f_SYNC= .±±kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified0

SYMBOL

Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn

Output Low Voltage = 3mA

Digital Inputs SHARE_CLK, WP

PARAMETER

CONDITION

MIN

TYP

MAX

UNITS

V

OL

I

0.4

V

SINK

l

V

IH

V

IL

Input High Threshold Voltage

Input Low Threshold Voltage

1.5

1

1.8

V

0.6

Digital Filtering of FAULTn

Input Digital Filtering FAULTn

Digital Filtering of PGOODn

Output Digital Filtering PGOODn

Digital Filtering of RUNn

Input Digital Filtering RUN

PMBus Interface Timing Characteristics

I

3

µs

FLTG

I

60

10

FLTG

I

FLTG

l

f

t

Serial Bus Operating Frequency

10

400

kHz

µs

SCL

BUF

Bus Free Time Between Stop and

Start

1.3

l

t

Hold Time After Repeated Start

Condition After This Period, the First

Clock is Generated

0.6

µs

HD(STA)

l

t

Repeated Start Condition Setup Time

Stop Condition Setup Time

0.6

10000

0.9

µs

SU(STA)

SU(ST0)

HD(DAT)

Date Hold Time

Receiving Data

Transmitting Data

l

0

0.3

µs

t

Data Setup Time

Receiving Data

SU(DAT)

l

0.1

µs

Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event

Stuck PMBus Timer Block Reads

32

255

ms

TIMEOUT_SMB

l

t

Serial Clock Low Period

Serial Clock High Period

1.3

0.6

10000

µs

LOW

HIGH

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: All currents into device pins are positive; all currents out of device pins

are negative. All voltages are referenced to ground unless otherwise specified

Note 4: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels. C

design.

= 3500pF is guaranteed by

LOAD

Note 2: The LTC3884/LTC3884-1 is tested under pulsed load conditions

such that T ≈ T . The LTC3884E/LTC3884E-1 is guaranteed to meet

J

A

Note .: The data format in PMBus is 5 bits exponent (signed) and 11 bits

mantissa (signed). This limits the output resolution to 10 bits though the

internal ADC is 16 bits and the calculations use 32-bit words.

Note 6: The data conversion is done by default in round robin fashion. All

inputs signals are continuously converted for a typical latency of 90ms.

Setting MFR_ADC_CONTRL value to be 0 to 12, LTC3884 can do fast data

conversion with only 8ms to 10ms. See section PMBus Command for

details.

performance specifications from 0°C to 85°C. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3884I/LTC3884I-1 is guaranteed over the full –40°C to 125°C operating

junction temperature range. T is calculated from the ambient temperature

J

T and power dissipation P according to the following formula:

A

D

T = T + (P • θ )

JA

J

A

D

The maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board layout,

the rated package thermal impedance and other environmental factors.

Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as

read from READ_IOUT in Amperes.

3884fe

10

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

ELECTRICAL CHARACTERISTICS

Note 8: Part tested with PWM disabled. Evaluation in application

demonstrates capability. TUE(%) = ADC Gain Error (%) +100 •

(Zero code Offset + ADC Linearity Error)/Actual Value.

Note 14: MFR_PWM_MODE_[5] = 0 or 1 sets the temperature

measurement method through ∆V , or through 2V

.

BE

Note 1.: MFR_PWM_MODE[2] = 1 or 0 sets device in low DCR mode or

regular DCR mode respectively. MFR_PWM_MODE[7]=1 or 0 sets device in

high output current range or low current range. See “Output Current Sensing

and sub milliohm DCR Current Sensing” in Operation Section for details.

Note 9: All V

commands assume the ADC is used to auto zero the

OUT

output to achieve the stated accuracy. LTC3884/LTC3884-1 is tested in a

feedback loop that servos V to a specified value.

OUT

Only V

codes 2–8 are supported for DCR sensing.

ILIMIT

Note 1±: The maximum programmable V

voltage is 5.5V when the

OUT

output voltage range is High and 2.75V when the output voltage range is

Low.

Note 16: The LTC3884/LTC3884-1 quiescent current (I ) equals the I of

Q Q

V

IN

plus the I of EXTV .

Q CC

Note 11: The maximum V voltage is 38V.

Note 17: The LTC3884/LTC3884-1 includes overtemperature protection

that is intended to protect the device during momentary overload

conditions. Junction temperature will exceed 125°C when overtemperature

protection is active. Continuous operation above the specified maximum

operating junction temperature may impair device reliability.

IN

Note 12: EEPROM endurance and retention are guaranteed by design,

characterization and correlation with statistical process controls. Data

retention is production tested via a high temperature at wafer level. The

minimum retention specification applies for devices whose EEPROM

has been cycled less than the minimum endurance specification. The

RESTORE_USER_ALL command (NVM read) is valid over the entire

operating junction temperature range.

Note 18: Write operations above T = 85°C or below 0°C are possible

J

although the Electrical Characteristics are not guaranteed and the EEPROM

will be degraded. Read operations performed at temperatures below 125°C

will not degrade the EEPROM. Writing to the EEPROM above 85°C will

result in a degradation of retention characteristics.

Note 13: MFR_PWM_MODE[1]=1 or 0 sets the output voltage range Low

or High.

Note 19: Properly adjust the input current sensing resistor R to set the

VIN

sensing voltage within the maximum voltage of 150mV.

ꢀꢁ

43

3ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

3ꢀ

ꢀꢁꢂꢃ

3884 ꢀꢁꢂ

Figure 10 Programmable R_TH

3884fe

11

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_IN= 12V, L = 0 .33µH, DCR = 0 .32mΩ, EXTV_CC= 0 V unless otherwise noted.

Efficiency vs Load Current

ꢀꢁ

8ꢀ

83

ꢀꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁ

8ꢀ

83

ꢀꢀ

ꢀꢁ

ꢀꢀ

ꢀꢁ

f

ꢀ 3ꢁꢂꢃꢄꢅ

ꢀꢁ

f

ꢀ ꢁꢂꢂꢃꢄꢅ

ꢀꢁ

ꢀ

ꢀꢁꢂ8ꢃ

ꢀ

ꢀꢁꢂ8ꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀꢁ

3ꢀ

ꢀ

ꢀꢁ

3ꢀ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ

3884 ꢀꢁꢂ

Power Loss vs Load Current

Power Loss vs Output Current

ꢀ

4

3

ꢀ

4

3

ꢀ

f

ꢀ ꢁꢂꢂꢃꢄꢅ

f

ꢀ 3ꢁꢂꢃꢄꢅ

ꢀꢁ

ꢀ

ꢀꢁꢂ8ꢃ

ꢀ

ꢀꢁꢂ8ꢃ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀꢁ

3ꢀ

ꢀ

ꢀꢁ

3ꢀ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ

3884 ꢀꢁ4

3884 ꢀꢁ3

Load Step

(Forced Continuous Mode)

Load Step

(Discontinuous Mode)

3884

8

3

3884fe

12

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_IN= 12V, L = 0 .33µH, DCR = 0 .32mΩ, EXTV_CC= 0 V unless otherwise noted.

Inductor Current at Light Load

Soft-Start Ramp

ꢀꢁꢂ

ꢃꢄꢅꢆꢇꢄ

ꢈꢄ

ꢀꢁꢂꢃꢄꢅ

ꢃꢁꢆꢇꢈꢆꢉꢁꢉꢊ

ꢋꢁꢅꢄ

ꢌꢍꢎꢅꢈꢏ

ꢄ

ꢉꢁꢊ

ꢋꢄꢅꢆꢇꢄ

ꢈꢄ

ꢅꢈꢊꢃꢁꢆꢇꢈꢆꢉꢁꢉꢊ

ꢋꢁꢅꢄ

ꢌꢍꢎꢅꢈꢏ

3884 ꢖꢗꢘ

3884 ꢗꢈ8

ꢏ

ꢕꢁꢍꢅ

ꢓ ꢐꢔ8ꢏ

ꢓ ꢐꢍ

ꢐꢑꢒꢎꢅꢈꢏ

ꢏ

ꢒ ꢋꢈꢍꢎ

ꢌꢍꢎꢅꢆꢇꢄ

ꢁꢉꢇ

ꢀꢇꢐꢑ

ꢈ

ꢒ ꢌꢍꢎ

ꢒ ꢋꢖ8ꢄ

ꢆꢑꢓꢔꢕ

ꢄ

ꢉꢁꢊ

Start-Up Into a Prebiased Output

Soft-Off Ramp

ꢀꢁꢂ

ꢃꢄꢅꢆꢇꢄ

ꢈꢄ

ꢀꢁꢂ

ꢃꢄꢅꢆꢇꢄ

ꢈꢄ

ꢄ

ꢉꢁꢊ

ꢋꢄꢅꢆꢇꢄ

ꢈꢄ

ꢋꢄꢅꢆꢇꢄ

ꢈꢄ

3884 ꢔꢈꢕ

3884 ꢖꢋꢈ

ꢏ

ꢒ ꢋꢈꢍꢎ

ꢒ ꢋꢓ8ꢄ

ꢌꢍꢎꢅꢆꢇꢄ

ꢀꢇꢐꢑ

ꢉꢁꢊ

ꢏ

ꢓ ꢌꢍꢎ

ꢆꢔꢒꢑꢕ

ꢌꢍꢎꢅꢆꢇꢄ

ꢐꢑꢒꢒ

ꢄ

ꢓ ꢋꢈꢍꢎ

Dynamic Current Sharing During

a Load Transient in a 2-Phase

System

Dynamic Current Sharing During

a Load Transient in a 2-Phase

System

ꢀꢁꢂꢃꢄꢅꢆ

ꢅ

ꢇ

ꢌ

ꢁꢂ

3884 ꢋꢀꢀ

3884 ꢊꢀꢋ

ꢈꢉꢊꢃꢄꢅꢆ

ꢇꢈꢉꢃꢄꢅꢆ

3884fe

13

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_IN= 12V, L = 0 .33µH, DCR = 0 .32mΩ, EXTV_CC= 0 V unless otherwise noted.

Dynamic Current Sharing During

a Load Transient in a 4-Phase

System

Dynamic Current Sharing During

a Load Transient in a 4-Phase

System

ꢅ

ꢉ

ꢅ

ꢉ

ꢈꢊꢋꢃꢄꢅꢆ

ꢊꢋ

3884 ꢇꢈ3

3884 ꢇꢈ4

ꢀꢁꢂꢃꢄꢅꢆ

Current Limit During an Output

Short Condition

Phase Current Matching in Two

Phase Systems

ꢀꢁꢂꢀ

ꢀ8ꢁꢂ

ꢀꢁꢂꢃ

ꢀ4ꢁꢀ

ꢀꢁꢂꢀ

ꢀꢁꢂꢁ

8ꢀꢁ

ꢇꢐꢑꢒꢍꢈꢎꢉ ꢎꢅꢓꢅꢉ ꢔ 4ꢌꢍꢕ

ꢅꢎꢑꢖꢗꢍꢘ ꢔ 4ꢙꢍ

ꢆ

ꢇꢈꢉ

ꢊꢋꢄ

ꢅ

ꢎ

ꢏꢌꢍꢃꢄꢅꢆ

ꢀꢁꢂ

ꢌꢍ

3ꢀꢁ

ꢀꢁꢂ

3884 ꢊꢏꢀ

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀ

8

ꢀꢁ

ꢀ4

3ꢀ

4ꢀ

ꢀꢁꢂꢃꢁꢂ ꢄꢁꢅꢅꢆꢇꢂ ꢈꢉꢊ

3884 ꢀꢁꢂ

Current Sense Threshold

vs Duty Cycle

INTV_CCLine Regulation

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂ8

ꢀꢁꢂ4

ꢀꢁꢂꢁ

ꢀꢁꢂ

ꢀꢁ8

ꢀꢁꢀ

ꢀꢁꢂ

4ꢀꢁ

4ꢀ3

4ꢀꢁ

ꢀꢁꢀꢂꢃꢄꢀꢂꢀꢅꢆꢇꢈꢉꢊꢈꢋꢊ ꢌ ꢍꢎꢏ

ꢀꢁꢂꢃꢄꢁꢅꢄꢆꢇꢂꢈꢃꢄꢈꢀꢉꢀꢃꢊ 3ꢋꢌꢍꢇ

ꢀꢁꢂ

8ꢀ8

8ꢀ4

8ꢀꢁ

ꢀ

ꢀꢁ

4ꢀ

ꢀꢁ

8ꢀ

ꢀꢁꢁ

ꢀ

ꢀꢁ

ꢀꢁꢂ

3ꢀ

4ꢀ

ꢀꢁꢂꢃ ꢄꢃꢄꢅꢆ ꢇꢈꢉ

ꢀ

ꢀꢁ

3884 ꢀꢁ8

3884 ꢀꢁꢂ

3884fe

14

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_IN= 12V, L = 0 .33µH, DCR = 0 .32mΩ, EXTV_CC= 0 V unless otherwise noted.

SHARE_CLK Frequency

vs Input Voltage

Quiescent Current

vs Input Voltage

Supply Current Measurement

Error vs Supply Current

ꢀꢁꢂ

ꢀꢁꢁ

ꢀ8

3ꢀꢁꢀ

ꢀꢁꢂꢃ

ꢀꢀꢁꢂ

ꢀꢁꢂꢁ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂ

= 2Ω

ꢀꢁ8

ꢀꢁꢂ

ꢀꢁ4

ꢀꢁꢂ

ꢀꢁꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ4

ꢀꢁꢂꢃ

ꢀꢁꢂ8

ꢀꢁꢂꢃ

ꢀꢁ

ꢀ3

4

ꢀꢁ

ꢀꢀ

ꢃꢀꢄ

ꢀ8

34

4ꢀ

ꢀꢁ

4ꢀ

ꢀꢁ

8ꢀ

ꢀꢁꢁ

ꢀꢁꢂ

4

ꢀ3

ꢀꢀ

ꢀꢁꢂ

3ꢀ

4ꢀ

ꢀ

ꢀꢁꢂꢂꢃꢄ ꢅꢁꢆꢆꢇꢈꢉ ꢊꢋꢌꢍ

ꢀ

ꢁꢂ

ꢀꢁ

3884 ꢀꢁꢂ

V_OUTOvervoltage Threshold

vs Temperature (Target 1V)

V_REFvs Temperature

V_OUTvs Temperature

ꢀꢁꢂꢂꢂꢃ

ꢀꢁꢂꢂꢀ8

ꢀꢁꢂꢂꢀꢃ

ꢀꢁꢂꢂꢀ3

ꢀꢁꢂꢂꢀꢃ

ꢀꢁꢂꢂꢃ8

ꢀꢁꢂꢂꢃꢄ

ꢀꢁꢂꢂꢃ3

ꢀꢁꢂꢂꢃꢃ

ꢀꢁꢂꢀꢃ8

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂꢀꢃ3

ꢀꢁꢂꢀꢃꢄ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢂ4

ꢀꢁꢂꢂ3

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢂꢀ

ꢀꢁꢂꢂꢂ

ꢀꢁꢂꢂ8

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢀꢃ

ꢀꢁꢂꢀꢂ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢂꢂ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂꢂꢀ

ꢀꢁꢂ8ꢃ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

3884 ꢀꢁꢁ

3884 ꢀꢁ3

3884 ꢀꢁ4

V

_OUTOvervoltage Threshold

V

_OUTOvervoltage Threshold

vs Temperature (Target 2V)

vs Temperature (Target 4V)

SHARE_CLK vs Temperature

4ꢀꢁꢂ

4ꢀꢁ4

4ꢀꢁꢂ

4ꢀꢁꢁ

3ꢀꢁ8

3ꢀꢁꢂ

3ꢀꢁ4

ꢀꢁꢂ

ꢀꢁ4

ꢀꢁ3

ꢀꢁꢀ

ꢀꢁꢁ

ꢀꢀ

ꢀꢁꢂ3ꢂ

ꢀꢁꢂꢀꢂ

ꢀꢁꢂꢃꢂ

ꢀꢁꢂꢂꢂ

ꢀꢁꢂꢂꢃ

ꢀꢁꢂ8ꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁ

ꢀ4

ꢀ3

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

3884 ꢀꢁꢂ

3884fe

15

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_IN= 12V, L = 0 .33µH, DCR = 0 .32mΩ, EXTV_CC= 0 V unless otherwise noted.

Underlock Voltage vs Temperature

V_OUTCommand DNL

V_OUTCommand INL

4ꢀꢁꢁ

3ꢀꢁꢂ

3ꢀ8ꢁ

3ꢀꢁꢂ

3ꢀꢁꢁ

3ꢀꢁꢂ

ꢀꢁ3ꢀ

ꢀꢁꢂ3

ꢀꢁꢂꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂ

ꢀꢁꢂꢀ

ꢀ

ꢀꢁꢂꢁꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁꢀ8

ꢀꢁꢀꢀ

ꢀꢁꢂꢁꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂ3ꢁ

ꢀꢁꢂꢃꢁ

ꢀꢁꢂꢂꢃꢄꢅ

ꢀꢁꢂꢃꢃ

ꢀꢁꢁ

ꢀꢁꢂ

3ꢀ

8ꢀ

ꢀꢁꢂ

3ꢀꢁ

ꢄꢀꢅ

4ꢀꢁ

ꢀꢁꢀ

ꢀꢁꢂꢀ

ꢀꢁꢂꢃ

3ꢀꢁꢂ

ꢄꢀꢅ

4ꢀꢁꢂ

ꢀꢁꢀꢂ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

ꢀ

ꢁꢂꢃ

3884 ꢀꢁ8

3884 ꢀꢁꢂ

3884 ꢀ3ꢁ

V_OUTError vs V_OUT

I_OUTError vs I_OUT

Input Current Error vs Input Current

ꢀꢁ4ꢀ

ꢀꢁ3ꢀ

ꢀꢁꢂꢁꢁ

ꢀꢁꢂ4

ꢀ

= 5mΩ

ꢀꢀꢁꢂꢁꢂ

ꢀ

ꢀꢁꢂꢀ

4ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢀ

ꢀꢁ43

ꢀ

ꢀꢁꢀꢀ

ꢀꢁꢂ43

ꢀ4ꢁꢂꢃ

ꢀꢁꢂꢃ4

ꢀꢁꢂꢃꢂꢂ

ꢀꢁ

ꢀ3

ꢀꢁꢂꢃꢁ

ꢀꢁꢂ3ꢁ

ꢀꢁꢂ

3ꢀꢁ

ꢄꢀꢅ

4ꢀꢁ

ꢀꢁꢀ

ꢀꢁꢂ

8ꢀꢁ

ꢀꢁꢂꢃ

ꢀ4ꢁꢂ

ꢀꢁꢂ

3ꢀꢁꢂ

4ꢀꢁꢀ

ꢀ

3

ꢀ

8

ꢀꢁ

ꢀ

ꢀꢁꢂꢃꢄ ꢅꢃꢆꢆꢇꢁꢄꢈꢉꢊ

ꢁꢂꢃ

ꢀꢁꢂ

3884 ꢀ3ꢁ

3884 ꢀ33

3884fe

16

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PIN FUNCTIONS ^{(UK, RHE)}

+

V

/V

(Pin 1/Pin 32, Pin 2/Pin 33): Positive

ASEL0 /ASEL1 (Pin 19/Pin 20 , Pin 20 /Pin 21): Serial Bus

SENSE0

SENSE1

Output Voltage Sense Inputs.

Address Select Inputs. Connect optional 1% resistor

dividers between V

and SGND to these pins to select

–

DD25

V

/V

(Pin 2/Pin 31, Pin 3/Pin 32): Negative

SENSE1

SENSE0

the serial bus interface address. Refer to the Applications

Informationsectionformoredetails.Minimizecapacitance

when the pin is open to assure accurate detection of the

pin state.

Output Voltage Sense Inputs.

I

/I (Pin 6/Pin 29, Pin 7/Pin 30 ): Current Control

TH0 TH1

ThresholdandErrorAmplifierCompensationNodes. Each

associatedchannel’scurrentcomparatortrippingthreshold

increases with its I voltage.

V

/V

(Pin 21/Pin 22, Pin 22/Pin 23):

OUT0 _CFG OUT1_CFG

TH

OutputVoltageSelectPins.Connectoptional 1%resistor

divider between V VOUT_CFG and SGND in order to

I

/I

(Pin 5/Pin 30 , Pin 6/Pin 31): Loop Compen-

THR0 THR1

sation Nodes.

DD25

select output voltage for each channel. If the pin is left

open, the IC will use the value programmed in EEPROM.

Refer to the Applications Information section for more

details. Minimize capacitance when the pin is open to

assure accurate detection of the pin state.

+

I

/I

(Pin7/Pin3,Pin8/Pin4):Currentsense

SENSE0 SENSE1

comparator positive inputs, normally connected to DCR

sensing networks or current sensing resistors.

–

I

/I

(Pin 8/Pin 4, Pin 9/Pin 5): Current

SENSE0 SENSE1

FREQ_CFG (Pin 23, Pin 24): Frequency Select Pin. Con-

sense comparator negative inputs, normally connected

to outputs.

nect optional 1% resistor divider between V

and

DD25

FREQ_CFG SGND in order to select PWM switching fre-

quency. Refer to the Applications Information section for

more details. Minimize capacitance when the pin is open

to assure accurate detection of the pin state.

SYNC (Pin 11, Pin 12): External Clock Synchronization

Input and Open-Drain Output Pin. If an external clock is

present at this pin, the switching frequency will be syn-

chronized to the external clock. If clock master mode is

enabled, this pin will pull low at the switching frequency

with a 500ns pulse to ground. A resistor pull-up to 3.3V

is required in the application if the LTC3884 is the master.

PHASE_CFG (Pin 24, Pin 25): Phase Select Pin. Connect

1% resistor divider between V

PHASE_CFG SGND

DD25

to this pin to configure the phase of each PWM channel

relative to SYNC. If the pin is left open, the IC will use the

value programmed in the NVM. Refer to the Applications

Informationsectionformoredetails.Minimizecapacitance

when the pin is open to assure accurate detection of the

pin state.

SCL (Pin 12, Pin 13): Serial Bus Clock Input. Open-drain

outputcanholdtheoutputlowifclockstretchingisenabled.

A pull-up resistor to 3.3V is required in the application.

SDA (Pin 13, Pin 14): Serial Bus Data Input and Output.

A pull-up resistor to 3.3V is required in the application.

V

(Pin 25, Pin 26): Internally Generated 2.5V Power

DD25

Supply Output Pin. Bypass this pin to SGND with a low

ESR 1μF capacitor. Do not load this pin with external cur-

rent except for the 1% resistor dividers required for the

configuration pins.

ALERT (Pin 14, Pin 15): Open-Drain Digital Output. Con-

nect the SMBALERT signal to this pin. A pull-up resistor

to 3.3V is required in the application.

FAULT0/FAULT1 (Pin 15/Pin 16, Pin 16/Pin 17): Digital

ProgrammableFAULTInputsandOutputs.Open-drainout-

put.Apull-upresistorto3.3Visrequiredintheapplication.

WP (Pin 26, Pin 27): Write Protect Pin Active High. An

internal 10μA current source pulls the pin to V

is high, the PMBus writes are restricted.

. If WP

DD33

RUN0 /RUN1 (Pin 17/Pin 18, Pin 18/Pin 19): Enable Run

Input and Output. Logic high on these pins enables the

controller. An open-drain output holds the pin low until

the LTC3884 is out of reset. This pin should be driven by

an open-drain digital output. A pull-up resistor to 3.3V is

required in the application.

SHARE_CLK (Pin 27, Pin 28): Share Clock, Bidirectional

Open-DrainClockSharingPin.Nominally100kHz.Usedto

synchronizethetimingbetweenmultipleLTC3884s.Tieall

SHARE_CLK pins together. All LTC3884s will synchronize

to the fastest clock. A pull-up resistor to 3.3V is required.

3884fe

17

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PIN FUNCTIONS ^{(UK, RHE)}

V

(Pin 28, Pin 29): Internally Generated 3.3V Power

SW0 /SW1 (LTC3884) (Pin 45/Pin 34, Pin 46/Pin 35):

Switch Node Connections to Inductors. Voltage swings

at the pins are from a diode (internal body diode) voltage

DD33

Supply Output Pin. Bypass this pin to SGND with a low

ESR 1μF capacitor. Do not load this pin with external cur-

rent except for the pull-up resistors required for FAULTn,

SCLK, SYNC and possibly RUNn, SDA and SCL, PGOODn.

drop below ground to V .

IN

TSNS0 /TSNS1 (Pin 10 /Pin 9, Pin 11/Pin 10 ): External

DiodeTemperatureSense. Connecttotheanodeofadiode

connected PNP transistor and star-connect the cathode

to GND (Pin 49) in order to sense remote temperature. A

bypass capacitor between the anode and cathode must

be located in close proximity to the transistor. If external

temperature sense elements are not installed, short pin

to ground and set the UT_FAULT_LIMIT to –275°C and

the UT_FAULT_RESPONSE to ignore.

INTV (Pin 38, Pin 39): Internal Regulator 5.5V Output.

CC

The control circuits are powered from this voltage. De-

couple this pin to PGND with a minimum of 4.7μF low ESR

tantalum or ceramic capacitor. This regulator is mainly

designed for internal circuits, not to be used as supply

for the other ICs.

EXTV (Pin 40 , Pin 41): External Power Input to an

CC

Internal Switch Connected to INTV . This switch closes

CC

+

andsuppliestheICpower,bypassingtheinternalregulator

I

IN

(Pin 46, Pin 47): Positive Current Sense Comparator

whenever EXTV is higher than 4.7V and V is higher

Input. If the input current sense amplifier is not used, this

pin must be shorted to the I and V pins.

CC

IN

–

than 7V. EXTV also powers up V

when EXTV is

CC

DD33

CC

IN

higher than 4.7V and INTV is lower than 3.8V. Do not

–

CC

I

IN

(Pin 47, Pin 48): Negative Current Sense Comparator

exceed 6V on this pin. Decouple this pin to PGND with a

Input. If the input current sense amplifier is not used, this

pin must be shorted to the I and V pins.

minimumof4.7μFlowESRtantalumorceramiccapacitor.

+

IN

If the EXTV pin is not used to power INTV , the EXTV

CC

PGOOD0 /PGOOD1 (Pin 48/Pin 33, Pin 1/ Pin 34): Power

Good Indicator Outputs. Open-drain logic output that is

pulled to ground when the output exceeds the UV and

OV regulation window. The output is deglitched by an

internal 60µs filter. A pull-up resistor to 3.3V is required

in the application.

pin must be tied GND. The EXTV pin may be connected

CC

to a higher voltage than the V pin.

IN

V

(Pin 39, Pin 40 ): Main Input Supply. Decouple this

IN

pin to PGND with a capacitor (1µF to 10µF). For applica-

tions where the main input power is 6V or below, tie the

V

IN

and INTV pins together. If the input current sense

CC

+

PGND (Pin 41/Pin 42): Power Ground.

amplifier is not used, this pin must be shorted to the I

IN

–

and I pins.

IN

V

/V (LTC3884-1) (Pin 44/Pin 37): Supply to PWM.

CC0 CC1

Connected to INTV or V

. Bypass to PGND with a

BG0 /BG1 (LTC3884) (Pin 42/Pin 37, Pin 43/Pin 38):

Bottom Gate Driver Outputs. These pins drive the gates

of the bottom N-channel MOSFETs between PGND and

CC

DD33

1µF capacitor.

PWM0 /PWM1(LTC3884-1)(Pin45/Pin36):PWMOutputs.

INTV .

CC

These are the three-state control outputs with a voltage

swing of GND to V .

BOOST0/BOOST1 (LTC3884) (Pin 43/Pin 36, Pin 44/Pin 37):

Boosted Floating Driver Supplies. The (+) terminal of the

booststrap capacitors connect to these pins. These pins

CC

SGND (Exposed Pad Pin 49): Internal Signal Ground.

All small-signal and compensation components should

connect to this ground, which in turn connects to PGND

at single point.

swing from a diode voltage drop below INTV up to

CC

V + INTV .

IN

CC

TG0 /TG1 (LTC3884) (Pin 44/Pin 35, Pin 45/Pin 36): Top

Gate Driver Outputs. These are the outputs of the floating

driverswithavoltageswingequaltoINTV superimposed

CC

on the switch node voltages.

3884fe

18

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

BLOCK DIAGRAM ^{(UK PACKAGE, LTC3884)}

ꢏ

ꢉꢄ

ꢤ

ꢏꢉꢄ

ꢏ

3ꢟ

ꢑꢗꢎꢎꢛꢡ

ꢀ

ꢉ

ꢉꢄ

ꢌ

ꢉꢄ

4ꢅꢤ

ꢤ

3ꢨꢤ

ꢤ

ꢏ

ꢉꢄ

ꢞꢄꢭꢞꢦꢦ

4ꢆ

ꢀ

ꢁ

ꢀ

^{ꢂ ꢃ ꢄ}ꢁ

ꢤ

ꢁ

ꢉꢉꢄꢑꢄꢑ

ꢉ

ꢉꢄ

4ꢣ

ꢒꢘꢊꢏ

4ꢕ

ꢞꢏ

ꢗꢏ

ꢌꢌ

ꢎꢠꢞꢞꢋꢕ

ꢎꢠꢞꢞꢋꢕ 48

ꢒꢘꢊꢏ

ꢉꢄꢊꢏ

ꢌꢌ

ꢨꢢꢨꢏꢤꢒꢠ

ꢟꢇꢈꢉꢊ ꢏ

ꢋꢂꢌ

ꢉꢄ

ꢉꢄꢊꢏ

38

ꢌꢌ

ꢏ

ꢋꢋ33

ꢙ8

3ꢢ3ꢏ

ꢑꢗꢈꢤꢒꢠ

ꢏ

ꢋꢋ33

ꢑ

ꢤ

ꢎꢓꢔꢐꢌꢛꢞꢌꢥ

ꢋ

ꢈ

ꢈꢞꢞꢑꢊꢕ

43

ꢧ

ꢦꢌꢄꢊ

ꢉ

ꢨꢩ

ꢌꢔꢎ

ꢤꢒꢏ

ꢁ

ꢀ

ꢊꢠꢕ

44

ꢎꢤꢒꢈꢉꢂꢑ

ꢞꢄ

ꢀ

ꢁ

ꢔꢅ

ꢔꢙ

ꢌ

ꢈ

ꢑꢓꢕ

4ꢨ

ꢑꢓꢉꢊꢌꢍ

ꢛꢞꢠꢉꢌ

ꢂꢄꢋ

ꢂꢄꢊꢉꢇ

ꢑꢍꢞꢞꢊꢇ

ꢊꢍꢤꢞꢗꢠꢍ

ꢤꢒꢏ

ꢗꢏ

ꢗꢏꢛꢞ

ꢑꢑ

ꢏ

ꢞꢗꢊꢕ

ꢌ

ꢞꢗꢊ

ꢈꢠꢕ

4ꢙ

ꢤꢗꢄ

ꢉ

ꢤꢂꢄꢠꢒ ꢑꢒꢛꢒꢌꢊ

ꢍꢉꢖ ꢅꢖꢅ

ꢎꢠꢄꢋ

4ꢅ

ꢌ

ꢛꢉꢔ

ꢏꢌꢌ

ꢞꢏ

ꢛꢞꢖ ꢅꢖꢅꢢ8

ꢅ

ꢨꢩ

ꢀ

ꢉ

ꢑꢒꢄꢑꢒꢕ

ꢣ

ꢁ

ꢑꢒꢄꢑꢒꢕ

8

ꢑꢛꢞꢎꢒ

ꢌꢞꢔꢎꢒꢄꢑꢂꢊꢉꢞꢄ

ꢀ

ꢁ

ꢀ

ꢠꢔ

ꢀ

ꢁ

ꢀ

ꢉꢄꢊꢏ

ꢌꢌ

ꢗꢏꢛꢞ

ꢣꢤ

ꢅꢅꢤ

_ꢅꢕꢖꢅꢁ

ꢀ

ꢉ

ꢙ

ꢊꢍꢕ

ꢉ

ꢏꢉꢄꢐꢑꢄꢑꢅ

^ꢔꢗꢘꢁ

ꢂꢌꢊꢉꢏꢒ

ꢌꢛꢂꢔꢎ

ꢉ

ꢋꢂꢌ

ꢁ

ꢛꢉꢔ

ꢏ

ꢆ

ꢑꢒꢄꢑꢒꢕ

ꢀ

ꢁ

ꢀ

ꢁ

ꢜ3 ꢈꢉꢊꢑꢝ

ꢀ

ꢅꢆꢇꢈꢉꢊ

ꢂꢋꢌ

ꢑꢒꢄꢑꢒꢅ

ꢌ

ꢌꢊꢎ

^ꢂꢋꢀ

ꢁ

ꢀ

ꢁ

ꢀ

ꢉ

ꢑꢒꢄꢑꢒꢅ

ꢏ

ꢎꢓꢔꢕ

ꢉ

ꢀ

ꢉ

ꢀ

ꢁ

ꢊꢍꢤꢕ

ꢨ

ꢤ

ꢑꢒꢄꢑꢒꢕ

ꢅ

ꢊꢍ

ꢑꢒꢄꢑꢒꢅ

ꢣꢤ

ꢅꢅꢤ

ꢊꢍ

ꢁ

ꢀ

ꢙꢚꢂ

3ꢙꢚꢂ

ꢌꢍꢉꢎ

ꢁ

ꢒꢂ

ꢗꢏ

ꢞꢏ

ꢁ

ꢀ

ꢊꢑꢄꢑꢕ

ꢅꢕ

ꢏ

ꢑꢊꢈꢡ

ꢊꢔꢗꢘ

ꢅꢕꢤ

ꢤꢒꢦ

ꢑꢠꢄꢋ

4ꢤ

ꢑꢠꢄꢋ

ꢅꢢꢙꢙꢏ

ꢎꢍꢂꢑꢒ ꢋꢒꢊ

ꢅꢅ ꢑꢡꢄꢌ

ꢅꢙꢇꢈꢉꢊ

ꢑꢒꢊ ꢎꢞꢉꢄꢊ

ꢋꢂꢌ

ꢟꢇꢈꢉꢊ

ꢗꢏ

ꢋꢂꢌ

ꢟꢇꢈꢉꢊ

ꢞꢏ

ꢋꢂꢌ

ꢏ

ꢌꢞ

ꢎꢓꢔ

ꢌꢛꢞꢌꢥ

ꢎꢍꢂꢑꢒ ꢑꢒꢛꢒꢌꢊꢞꢤ

ꢌꢛꢞꢌꢥ ꢋꢉꢏꢉꢋꢒꢤ

ꢏ

ꢋꢋ33

ꢏ

ꢋꢋ33

ꢏ

ꢋꢋꢙꢨ

ꢑꢌꢛ

ꢅꢙ

ꢙꢢꢨꢏ

ꢎꢔꢈꢫꢬ

ꢏ

ꢋꢋ33

ꢑꢛꢂꢏꢒ

ꢔꢉꢑꢞ

ꢙꢨ

ꢏ

ꢋꢋꢙꢨ

ꢑꢋꢂ ꢅ3

ALERT ꢅ4

ꢓꢎ ꢙꢆ

ꢑꢗꢈꢤꢒꢠ

ꢉꢄꢊꢒꢤꢦꢂꢌꢒ

ꢜ4ꢕꢕꢩꢍꢪ

ꢌꢞꢔꢎꢂꢤꢒ

ꢌꢞꢔꢎꢂꢊꢉꢈꢛꢒꢝ

ꢌꢛꢥ ꢔꢞꢑꢉ

ꢔꢂꢑꢊꢒꢤ

ꢔꢂꢉꢄ

ꢌꢞꢄꢊꢤꢞꢛ

ꢞꢑꢌ

ꢜ3ꢙꢔꢍꢪꢝ

3

ꢂꢑꢒꢛꢕ

ꢂꢑꢒꢛꢅ

ꢏ

ꢅꢟ

ꢙꢕ

ꢙꢅ

ꢙ3

ꢙ4

ꢑꢉꢄꢌ

ꢗꢏꢛꢞ

FAULT0

ꢤꢗꢄꢕ

ꢅꢨ

ꢅꢣ

ꢙꢣ

ꢌꢍꢂꢄꢄꢒꢛ

ꢊꢉꢔꢉꢄꢠ

ꢔꢂꢄꢂꢠꢒꢔꢒꢄꢊ

ꢌꢞꢄꢦꢉꢠ

ꢋꢒꢊꢒꢌꢊ

ꢞꢗꢊꢕꢐꢌꢦꢠ

ꢦꢤꢒꢧꢐꢌꢦꢠ

ꢑꢍꢂꢤꢒꢐꢌꢛꢥ

ꢎꢤꢞꢠꢤꢂꢔ

ꢤꢞꢔ

ꢤꢂꢔ

ꢒꢒꢎꢤꢞꢔ

ꢎꢍꢂꢑꢒꢐꢌꢦꢠ

3884 ꢦꢕꢙ

Figure 2. Block Diagram, One of Two Channels (Channel 0 Shown)

3884fe

19

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

OVERVIEW

n

Programmable Output Voltage

Programmable Input Voltage On and Off Threshold

Voltage

The LTC3884-1 has all the features that LTC3884 has,

except the LTC3884 includes MOSFET gate drivers while

the LTC3884-1 does not. LTC3884 is used in applications

where the gate driver is required while the LTC3884-1

is used in applications where the gate driver is external,

for example a DrMOS power stage. In the remainder of

this document, all the descriptions, features, operation

and applications of LTC3884 apply to LTC3884-1, unless

otherwise specified.

n

Programmable Current Limit

Programmable Switching Frequency

Programmable OV and UV Threshold voltage

Programmable ON and Off Delay Times

Programmable Output Rise/Fall Times

Phase-Locked Loop for Synchronous PolyPhase

Operation (2, 3, 4 or 6 Phases).

The LTC3884 is a dual channel/dual phase, constant-

frequency,analogcurrentmodecontrollerforDC/DCstep-

down applications with a digital interface. The LTC3884

digitalinterfaceiscompatiblewithPMBuswhichsupports

bus speeds of up to 400kHz. A Typical Application circuit

is shown on the first page of this data sheet.

n

Integrated Gate Drivers (LTC3884)

Nonvolatile Configuration Memory with ECC

Optional External Configuration Resistors for Key

Operating Parameters

LTC3884 is very similar to LTC3880, but has numerous

new features as shown in bold:

n

Optional Timebase Interconnect for Synchronization

Between Multiple Controllers

Major features include:

n

WP Pin to Protect Internal Configuration

n

Sub-Milliohm DCR Sensing

StandAloneOperationAfterUserFactoryConfiguration

PMBus, Version 1.2, 400kHz Compliant Interface

n

Dedicated Power Good Indicators

n

Direct Input and Chip Current Sensing

The PMBus interface provides access to important power

management data during system operation including:

n

Programmable Loop Compensation Parameters

n

T

Start-Up Time: 35ms

INIT

n

Internal Controller Temperature

n

PWM Synchronization Circuit, (See Frequency and

Phasing Section for Details)

n

External System Temperature via Optional Diode Sense

Elements

MFR_ADC_CONTROL for Fast ADC Sampling of One

Parameter (as Fast as 8ms) (See PMBus Command

for Details)

n

Average Output Current

n

Average Output Voltage

n

Fully Differential Output Sensing for Both Channels;

VOUT0 /1 Both Programmable Up to 5.5V

n

Average Input Voltage

n

Average Input Current

n

Power-Up and Program EEPROM with EXTV

Input Voltage Up to 38V

CC

n

Average Chip Input Current from V

IN

n

Configurable, Latched and Unlatched Individual Fault

and Warning Status

Dual Diode Temperature Sensing

SYNC Contention Circuit (Refer to Frequency and

Phase Section for Details)

IndividualchannelsareaccessedthroughthePMBususing

the PAGE command, i.e., PAGE 0 or 1.

n

Fault Logging

3884fe

20

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

Fault reporting and shutdown behavior are fully con-

figurable. Two individual FAULT0, FAULT1 outputs are

provided, both of which can be masked independently.

Three dedicated pins for ALERT, PGOOD0/1 functions are

provided. The shutdown operation also allows all faults

to be individually masked and can be operated in either

unlatched (hiccup) or latched modes.

command will typically have a latency less than 10ms. The

user is encouraged to refer to the PMBus Power System

Management Protocol Specification to understand how to

program the LTC3884.

http://www.pmbus.org/specs.html

Continuing the basic operation description, the current-

mode controller will turn off the top gate when the peak

current is reached. If the load current increases, sense

voltagewillslightlydroopwithrespecttotheDACreference.

Individual status commands enable fault reporting over

the serial bus to identify the specific fault event. Fault or

warning detection includes the following:

This causes the I voltage to increase until the average

TH

n

Output Undervoltage/Overvoltage

inductor current matches the new load current. After the

top MOSFET has turned off, the bottom MOSFET is turned

on. In continuous conduction mode, the bottom MOSFET

stays on until the end of the switching cycle.

n

Input Undervoltage/Overvoltage

n

Input and Output Overcurrent

n

Internal Overtemperature

n

External Overtemperature

EEPROM

n

Communication, Memory or Logic (CML) Fault

The LTC3884 contains internal EEPROM (nonvolatile

memory)withErrorCorrectionCoding(ECC)tostoreuser

configuration settings and fault log information. EEPROM

endurance retention and mass write operation time are

specified in the Electrical Characteristics and Absolute

MAIN CONTROL LOOP

The LTC3884 is a constant-frequency, current mode step-

down controller containing two channels operating with

user-defined relative phasing. During normal operation the

top MOSFET is turned on when the clock for that channel

sets the RS latch, and turned off when the main current

Maximum Ratings sections. Write operations above T =

J

85°C are possible although the Electrical Characteristics

are not guaranteed and the EEPROM will be degraded.

Read operations performed at temperatures between

–40°C and 125°C will not degrade the EEPROM. Writing

to the EEPROM above 85°C will result in a degradation of

retentioncharacteristics.Thefaultloggingfunction,which

is useful in debugging system problems that may occur

at high temperatures, only writes to fault log EEPROM

locations. If occasional writes to these registers occur

above 85°C, the slight degradation in the data retention

characteristics of the fault log will not take away from the

usefulness of the function.

comparator, I , resets the RS latch. The peak inductor

CMP

current at which I

resets the RS latch is controlled by

CMP

the voltage on the I pin which is the output of each er-

TH

ror amplifier, EA. The EA negative terminal is equal to the

+

–

differential voltage between V

and V

divided

SENSE

by 5.5 (or 2.75 if MFR_PWM_MODE[1] = 1). The positive

terminal of the EA is connected to the output of a 12-bit

DAC with values ranging from 0V to 1.024V. The output

voltage, through feedback of the EA, will be regulated to

5.5 times the DAC output (or 2.75 times). The DAC value

is calculated by the part to synthesize the user's desired

output voltage. The output voltage is programmed by the

user either with the resistor configuration pins detailed

It is recommended that the EEPROM not be written

when the die temperature is greater than 85°C. If the die

temperature exceeds 130°C, the LTC3884 will disable all

EEPROM write operations. All EEPROM write operations

will be re-enabled when the die temperature drops below

125°C. (The controller will also disable all the switching

when the die temperature exceeds the internal overtem-

perature fault limit 160°C with a 10°C hysteresis)

in Table 3 or by the PMBus V

command (either from

OUT

EEPROM or by PMBus command). Refer to the PMBus

commandsectionofthedatasheetorthePMBusspecifica-

tion for more details. The PMBus VOUT_COMMAND can

be executed at any time while the device is running. This

3884fe

21

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

The degradation in EEPROM retention for temperatures

>125°C can be approximated by calculating the dimen-

sionless acceleration factor using the following equation:

programming, including bulk EEPROM Programming,

which the LTC3884 also supports.

POWER-UP AND INITIALIZATION

⎡

⎤

⎥

⎦

⎛

⎞

Ea

k

1

⎛

⎞

•

–

⎢

⎜

⎟

⎠

⎜

⎟

AF = e^⎣⎝

where:

T

_USE+273 T_STRESS+273

⎝

⎠

The LTC3884 is designed to provide standalone supply

sequencing and controlled turn-on and turn-off operation.

It operates from a single input supply (4.5V to 38V) while

three on-chip linear regulators generate internal 2.5V, 3.3V

AF = acceleration factor

Ea = activation energy = 1.4eV

K = 8.617 • 10 eV/°K

and 5.5V. If V does not exceed 6V, and the EXTV pin

IN

CC

is not driven by an external supply, the INTV and V

CC

IN

–5

pins must be tied together. The controller configuration is

T

= 125°C specified junction temperature

= actual junction temperature in °C

USE

initialized by an internal threshold based UVLO where V

IN

must be approximately 4V and the 5.5V, 3.3V and 2.5V

linear regulators must be within approximately 20% of

the regulated values. In addition to power supply,a PMBus

RESTORE_USER_ALL or MFR_RESET command can

initialize the part too.

STRESS

Example: Calculate the effect on retention when operating

at a junction temperature of 135°C for 10 hours.

T

= 130°C

STRESS

= 125°C,

–5

([(1.4/8.617 • 10 ) • (1/398 – 1/403)] )

USE

TheEXTV pinisdrivenbyanexternalregulatortoimprove

CC

efficiency of the circuit and minimize power loss on the

AF = e

= 16.6

LTC3884 when V is high. The EXTV pin must exceed

IN

CC

The equivalent operating time at 125°C = 16.6 hours.

approximately 4.7V, and V must exceed approximately

IN

7V before the INTV LDO operates from the EXTV pin.

Thus the overall retention of the EEPROM was degraded by

16.6hoursasaresultofoperatingatajunctiontemperatureof

130°Cfor 10 hours. The effect of the overstress is negligible

when compared to the overall EEPROM retention rating of

87,600 hours at a maximum junction temperature of 125°C.

CC

To minimize application power, the EXTV pin can be

CC

supplied by a switching regulator.

During initialization, the external configuration resistors

are identified and/or contents of the NVM are read into the

controller’scommandsandtheBGn,TGnpinsareheldlow

forLTC3884.TheRUNnandFAULTnandPGOODnareheld

lowfortheLTC3884,orPWMpinsareinthree-stateforthe

LTC3884-1. The LTC3884 will use the contents of Table 3

to Table 6 to determine the resistor defined parameters.

See the Resistor Configuration section for more details.

The resistor configuration pins only control some of the

preset values of the controller. The remaining values are

programmed in NVM either at the factory or by the user.

TheintegrityoftheentireonboardEEPROMischeckedwith

a CRC calculation each time its data is to be read, such as

after a power-on reset or execution of a RESTORE_USER_

ALL command. If a CRC error occurs, the CML bit is set in

the STATUS_BYTE and STATUS_WORD commands, the

EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC

command is set, and the ALERT and RUN pins pulled

low (PWM channels off). At that point the device will only

respond at special address 0x7C, which is activated only

after an invalid CRC has been detected. The chip will also

respond at the global addresses 0x5A and 0x5B, but use

of these addresses when attempting to recover from a

CRC issue is not recommended. All power supply rails

associated with either PWM channel of a device reporting

an invalid CRC should remain disabled until the issue is

resolved. See the application Information section or con-

tact the factory for details on efficient in-system EEPROM

Iftheconfigurationresistorsarenotinsertedoriftheignore

RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL

configuration command), the LTC3884 will use only the

contentsofNVMtodeterminetheDC/DCcharacteristics.The

ASEL0/1valuereadatpower-uporresetisalwaysrespected

unless the pin is open. The ASEL0/1 will set the MSB and

the LSB from the detected threshold. See the Applications

Information section for more details.

3884fe

22

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

Aftertheparthasinitialized,anadditionalcomparatormoni-

TON_RISE operation. In discontinuous mode, the bottom

gate is turned off as soon as reverse current is detected in

the inductor. This will allow the regulator to start up into

a pre-biased load. When the TON_MAX_FAULT_LIMIT is

reached, the part transitions to continuous mode, if so

programmed. If TON_MAX_FAULT_LIMIT is set to zero,

there is no time limit and the part transitions to the desired

tors V . The VIN_ON threshold must be exceeded before

IN

the output power sequencing can begin. After V is initially

IN

applied, the part will typically require 35ms to initialize and

begin the TON_DELAY timer. The readback of voltages and

currents may require an additional 0ms to 90ms.

conduction mode after TON_RISE completes and V

has

OUT

SOFT-START

exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is

not present. However setting TON_MAX_FAULT_LIMIT to

a value of 0 is not recommended.

The method of start-up sequencing described below is time

based. The part must enter the run state prior to soft-start.

The run pins are released by the LTC3884 after the part is

initialized and V is greater than the VIN_ON threshold. If

IN

TIME-BASED SEQUENCING

multiple LTC3884s are used in an application, they all hold

their respective run pins low until all devices are initialized

The default mode for sequencing the outputs on and off is

timebased.EachoutputisenabledafterwaitingTON_DELAY

amount of time following either a RUN pin going high,

and V exceeds the VIN_ON threshold for every device.

IN

The SHARE_CLK pin assures all the devices connected to

the signal use the same time base. The SHARE_CLK pin is

a PMBus command to turn on or the V rising above a

IN

held low until the part has been initialized after V is ap-

preprogrammed voltage. Off sequencing is handled in a

similar way. To assure proper sequencing, make sure all

ICs connect the SHARE_CLK pin together and RUN pins

together. If the RUN pins cannot be connected together

for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1.

This bit requires the SHARE_CLK pin to be clocking before

the power supply output can start. When the RUN pin is

pulled low, the LTC3884 will hold the pin low for the MFR_

RESTART_DELAY. The minimum MFR_RESTART_ DELAY

is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures

proper sequencing of all rails. The LTC3884 calculates this

delayinternallyandwillnotprocessashorterdelay.However,

a longer commanded MFR_RESTART_DELAY will be used

by the part. The maximum allowed value is 65.52 seconds.

IN

plied. The LTC3884 can be set to turn-off (or remain off)

if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to

1). This allows the user to assure synchronization across

numerous ADI ICs even if the RUN pins cannot be con-

nected together due to board constraints. In general, if the

user cares about synchronization between chips it is best

not only to connect all the respective RUN pins together

but also to connect all the respective SHARE_CLK pins

together and pull up to V

sures all chips begin sequencing at the same time and use

the same time base.

with a 10k resistor. This as-

DD33

After the RUN pins release and prior to entering a constant

output voltage regulation state, the LTC3884 performs a

monotonicinitialrampor“soft-start”.Soft-startisperformed

byactivelyregulatingtheloadvoltagewhiledigitallyramping

the target voltage from 0V to the commanded voltage set-

point. Once the LTC3884 is commanded to turn on (after

power up and initialization), the controller waits for the

user specified turn-on delay (TON_DELAY) prior to initiat-

ing this output voltage ramp. The rise time of the voltage

ramp can be programmed using the TON_RISE command

to minimize inrush currents associated with the start-up

voltage ramp. The soft-start feature is disabled by setting

the value of TON_RISE to any value less than 0.25ms. The

LTC3884PWMalwaysusesdiscontinuousmodeduringthe

VOLTAGE-BASED SEQUENCING

The sequence can also be voltage based. As shown in

Figure3,ThePGOODnpinisassertedwhentheUVthreshold

isexceededforeachoutput. ItispossibletofeedthePGOOD

pin from one LTC3884 into the RUN pin of the next LTC3884

in the sequence, especially across multiple LTC3884s. The

PGOODnhasa60μsfilter.IftheV voltagebouncesaround

OUT

the UV threshold for a long period of time it is possible for

the PGOODn output to toggle more than once. To minimize

this problem, set the TON_RISE time under 100ms.

3884fe

23

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

If a fault in the string of rails is detected, only the faulted

rail and downstream rails will fault off. The rails in the

string of devices in front of the faulted rail will remain on

unless commanded off.

the output is disabled. The retry delay time is determined

by the longer of the MFR_RETRY_ DELAY command or

the time required for the regulated output to decay below

12.5% of the programmed value. If multiple outputs are

controlled by the same FAULTn pin, the decay time of the

faultedoutputdeterminestheretrydelay.Ifthenaturaldecay

time of the output is too long, it is possible to remove the

voltagerequirementoftheMFR_RETRY_DELAYcommand

by asserting bit 0 of MFR_CHAN_CONFIG. Alternatively,

latched off mode means the controller remains latched-off

followingafaultandclearingrequiresuserinterventionsuch

as toggling RUNn or commanding the part OFF then ON.

Voltage-Based Sequencing by Cascading PGs Into RUN Pins

ꢃꢄꢅ ꢇ

ꢈꢉꢊꢊꢋꢇ

ꢌꢁꢍꢃꢁ

ꢀꢁꢂ3884

ꢃꢄꢅ ꢆ

ꢈꢉꢊꢊꢋꢆ

ꢃꢄꢅ ꢇ

ꢃꢄꢅ ꢆ

ꢈꢉꢊꢊꢋꢇ

ꢈꢉꢊꢊꢋꢆ

ꢀꢁꢂ3884

LIGHT-LOAD CURRENT OPERATION

3884 ꢎꢇ3

ꢁꢊ ꢅꢏꢐꢁ ꢂꢑꢍꢅꢅꢏꢀ

ꢒꢅ ꢁꢑꢏ ꢌꢏꢓꢄꢏꢅꢂꢏ

The LTC3884 has two modes of operation: high efficiency

discontinuous conduction mode or forced continuous

conduction mode. Mode selection is done using the

MFR_PWM _MODE command (discontinuous conduc-

tion is always the start-up mode, forced continuous is the

default running mode).

Figure 3. Event (Voltage) Based Sequencing

SHUTDOWN

The LTC3884 supports two shutdown modes. The first

mode is closed-loop shutdown response, with user de-

fined turn-off delay (TOFF_DELAY) and ramp down rate

(TOFF_FALL). The controller will maintain the mode of

operationforTOFF_FALL.Thesecondmodeisdiscontinu-

ous conduction mode, the controller will not draw current

from the load and the fall time will be set by the output

capacitance and load current, instead of TOFF_FALL.

If a controller is enabled for discontinuous operation, the

inductorcurrentisnotallowedtoreverse.Thereversecurrent

comparator’s output, I , turns off the bottom gate of the

REV

external MOSFET just before the inductor current reaches

zero, preventing it from reversing and going negative.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. Thepeakinductorcurrentisdeterminedsolely

The shutdown occurs in response to a fault condition or

loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set

toa1)orV fallingbelowtheVIN_OFFthresholdorFAULT

pulled low externally (if the MFR_FAULT_ RESPONSE is

set to inhibit). Under these conditions the power stage

is disabled in order to stop the transfer of energy to the

load as quickly as possible. The shutdown state can be

entered from the soft-start or active regulation states or

through user intervention.

by the voltage on the I pin. In this mode, the efficiency at

TH

IN

light loads is lower than in discontinuous mode operation.

However, continuous mode exhibits lower output ripple

andlessinterferencewithaudiocircuitry, butmayresultin

reverseinductorcurrent,whichcancausetheinputsupply

to boost. The VIN_OV_FAULT_LIMIT can detect this and

turn off the offending channel. However, this fault is based

on an ADC read and can take up to t

to detect. If

CONVERT

there is a concern about the input supply boosting, keep

the part in discontinuous conduction mode.

Therearetwowaystorespondtofaults;whichareretrymode

andlatchedoffmode.Inretrymode,thecontrollerresponds

to a fault by shutting down and entering the inactive state

foraprogrammabledelaytime(MFR_RETRY_DELAY).This

delayminimizesthedutycycleassociatedwithautonomous

retriesifthefaultthatcausestheshutdowndisappearsonce

If the part is set to discontinuous mode operation, as the

inductor average current increases, the controller will

automatically modify the operation from discontinuous

mode to continuous mode.

3884fe

24

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

SWITCHING FREQUENCY AND PHASE

The phase relationships and frequency are independent

of each other, providing numerous application options.

Multiple LTC3884 ICs can be synchronized to realize

a PolyPhase array. In this case the phases should be

separated by 360/n degrees, where n is the number of

phases driving the output voltage rail.

The switching frequency of the PWM can be established

with an internal oscillator or an external time base. The

internal phase-locked loop (PLL) synchronizes PWM

controltothistimingreferencewithproperphaserelation,

whether the clock is provided internally or externally. The

device can also be configured to provide the master clock

to other ICs through PMBus command, NVM setting, or

external configuration resistors as outlined in Table 4.

PWM LOOP COMPENSATION

The internal PWM loop compensation resistors R

ITHn

of the LTC3884 can be adjusted using bit[4:0] of the

MFR_PWM_COMP command.

As clock master, the LTC3884 will drive its open-drain SYNC

pinattheselectedratewithapulsewidthof500ns.Anexternal

pull-up resistor between SYNC and V

is required in this

DD33

ThetransconductanceoftheLTC3884PWMerroramplifier

can be adjusted using bit[7:5] of the MFR_PWM_COMP

command. These two loop compensation parameters

can be programmed when device is in operation. Refer

to the Programmable Loop Compensation subsection in

the Applications Information section for further details.

case.OnlyonedeviceconnectedtoSYNCshouldbedesignated

to drive the pin. But if multiple LTC3884s programmed as

clock masters are wired to the same SYNC line with a pull-

up resistor, just one of the devices is automatically elected to

provide clocking, and the others disable their SYNC outputs.

TheLTC3884willautomaticallyreverttoanexternalSYNC

input, disabling its own SYNC, as long as the external

SYNC frequency is greater than 80% of the programmed

SYNC frequency. The external SYNC input shall have a

duty cycle between 20% and 80%.

OUTPUT VOLTAGE SENSING

Both channels in LTC3884 have differential amplifiers,

which allow the remote sensing of the load voltage be-

+

–

tween V

and V

pins. The telemetry ADC is

SENSEn

Whether configured to drive SYNC or not, the LTC3884

can continue PWM operation using its own internal

oscillator if an external clock signal is subsequently lost.

The device can also be programmed to always require

an external oscillator for PWM operation by setting bit

4 of MFR_CONFIG_ALL. The status of the SYNC driver

circuit is indicated by bit 10 of MFR_PADS.

also fully differential and makes measurements between

+

–

V

and V

pins respectively. The maximum

SENSEn

allowed sense voltages for both channels is 5.5V.

INTV /EXTV POWER

CC

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV pin.

CC

The MFR_PWM_CONFIG command can be used to

configure the phase of each channel. Desired phase

can also be set from EEPROM or external configuration

resistors as outlined in Table 5. Designated phase is

the relationship between the falling edge of SYNC and

the internal clock edge that sets the PWM latch to turn

on the top power switch. Additional small propagation

delays to the PWM control pins will also apply. Both

channels must be off before the FREQUENCY_SWITCH

and MFR_PWM_CONFIG commands can be written to

the LTC3884.

When the EXTV pin is shorted to GND or tied to a voltage

CC

less than 4.7V, an internal 5.5V linear regulator supplies

INTV power from V . If EXTV is taken above approxi-

CC

IN

CC

mately4.7V and V ishigherthan 7.0V, the 5.5V regulator

IN

isturnedoffandaninternalswitchisturnedon,connecting

EXTV to INTV . Using the EXTV allows the INTV

CC

power to be derived from a high efficiency external source

such as a switching regulator output.

EXTV can provide power to the internal 3.3V linear

CC

regulator even when V is not present, which allows the

IN

LTC3884 to be initialized and programmed even without

main power being applied.

3884fe

25

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

ꢀꢁꢂ3884 ꢃ ꢄꢅꢆꢇꢈ ꢉꢁꢊꢋꢇ

ꢀꢐꢓꢂꢈ

ꢈ

ꢌ

ꢁꢍꢏ

ꢁꢍꢎ

ꢃ

ꢜ

ꢁꢍꢈꢏ

ꢁꢍꢈꢎ

ꢎꢏꢝ 4ꢣꢤꢤꢝ ꢎꢏꢝ ꢎꢏꢝ ꢎꢏꢝ

ꢌ

ꢒ

ꢉꢇꢔꢉꢇꢏ

ꢂ

FAULT0

ꢃ

ꢜ

ꢉꢇꢔꢉꢇꢏ

ꢈꢛꢔ

ꢈꢛꢔꢏ

ꢈꢛꢔꢎ

ꢀꢐꢓꢂꢈ

ꢈ

ALERT

FAULT

ꢉꢘꢔꢂ

ALERT

FAULT1

ꢉꢘꢔꢂ ꢞꢇꢔꢊꢙꢀꢇꢓꢟ

ꢉꢍꢊꢈꢇꢠꢂꢀꢡ

ꢃ

ꢜ

ꢃ

ꢜ

ꢌ

ꢒ

ꢉꢇꢔꢉꢇꢎ

ꢉꢍꢊꢈꢇꢠꢂꢀꢡ

ꢒ

ꢓꢓ33

ꢎꢢꢗ

ꢒ

ꢉꢋꢔꢓ

ꢄꢋꢔꢓ

ꢔꢅꢁꢇꢕ ꢉꢅꢖꢇ ꢂꢅꢔꢔꢇꢂꢁꢅꢈꢉ

ꢊꢔꢓ ꢂꢅꢖꢄꢅꢔꢇꢔꢁꢉ ꢅꢖꢌꢁꢁꢇꢓ

ꢗꢅꢈ ꢂꢀꢊꢈꢌꢁꢘ

ꢙꢅꢁꢍ ꢂꢍꢌꢄꢉ ꢍꢊꢒꢇ ꢁꢍꢇ ꢌꢔꢁꢇꢈꢔꢊꢀ

ꢗꢈꢇꢚꢛꢇꢔꢂꢘ ꢂꢅꢖꢖꢊꢔꢓ ꢉꢇꢁ ꢁꢅ ꢁꢍꢇ

ꢉꢊꢖꢇ ꢓꢇꢉꢌꢈꢇꢓ ꢄꢆꢖ ꢗꢈꢇꢚꢛꢇꢔꢂꢘ

ꢎꢐꢑ ꢀꢁꢂ3884 ꢃ ꢄꢅꢆꢇꢈ ꢉꢁꢊꢋꢇ

ꢀꢐꢓꢂꢈ

ꢈ

ꢌ

ꢁꢍꢏ

ꢒ

ꢓꢓ33

ꢎꢢꢗ

ꢃ

ꢜ

ꢌ

ꢈꢛꢔꢏ

ꢉꢇꢔꢉꢇꢏ

ꢂ

ALERT

FAULT0

ꢃ

ꢜ

ꢒ

ꢉꢇꢔꢉꢇꢏ

ꢉꢘꢔꢂ ꢞꢓꢌꢉꢊꢙꢀꢇꢓꢟ

ꢉꢍꢊꢈꢇꢠꢂꢀꢡ

ꢀꢅꢊꢓ

ꢉꢋꢔꢓ

ꢋꢔꢓ

3884 ꢗꢏ4

Figure 4. Load Sharing Connections for 3-Phase Operation

EachtopMOSFETdriverisbiasedfromthefloatingbootstrap

thus represents the current flowing through the inductor.

In addition to this regular current sensing, the LTC3884

employs a unique architecture to enhance the signal-to-

noiseratioby14dB,enablingittooperatewithasmallsense

signal(aslowas2mV)viaasub-milliohmvalueofinductor

DCR (such as 0.2mΩ) to improve the power efficiency for

capacitor,C ,whichnormallyrechargesduringeachoffcycle

B

through an external diode when the bottom MOSFET turns

on. If the input voltage V decreases to a voltage close to

IN

V

OUT

, the loop may enter dropout and attempt to turn on

thetopMOSFETcontinuously.Thedropoutdetectordetects

this and forces the top MOSFET off for about one-twelfth

of the clock period plus 100ns every three cycles to allow

the heavy load applications while V

≤ 3.5V. As shown

OUT

in Figure 4, externally the new architecture only requires

reducing R by 4/5, i.e., R = 1/5Rnomdcr. Better

C to recharge. However, it is recommended that a load

B

LOWDCR

be present or the IC operates at low frequency during the

signal-to-noise ratio helps to reduce jitter at the output

with as low as 2mV sensing signal. Low DCR improves

power efficiency in heavy system loads. So the new DCR

sensing scheme provides a perfect solution for larger

power, and noise sensitive systems. In the meantime, the

current limit threshold is still a function of the inductor

peak current and its DCR value, and can be accurately set

with the MFR_PWM_MODE[2], MFR_PWM_MODE[7].

See Figure 26.

drop-out transition to ensure C is recharged.

B

OUTPUT CURRENT SENSING AND SUB MILLIOHM

DCR CURRENT SENSING

ForDCRcurrentsenseapplications,aresistorinserieswith

a capacitor is placed across the inductor. In this configu-

ration, the resistor is tied to the FET side of the inductor

while the capacitor is tied to the load side of the inductor

as shown in Figure 4. If the RC values are chosen such that

the RC time constant matches the inductor time constant

(L/DCR, where DCR is the inductor series resistance), the

resultantvoltageappearingacrossthecapacitorequalsthe

The RC calculations are based on the room temperature

DCR of the inductor. The RC time constant should remain

constant as a function of temperature. This assures the

transient response of the circuit is the same regardless

of the temperature. The DCR of the inductor has a large

voltage across the inductor series resistance (V ) and

DCR

3884fe

26

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

temperature coefficient, approximately 3900ppm/°C. The

temperature coefficient of the inductor must be written to

the MFR_IOUT_CAL_GAIN_TC register. The external tem-

perature is sensed near the inductor and used to modify

the internal current limit circuit to maintain an essentially

PolyPhase LOAD SHARING

Multiple LTC3884s can be arrayed in order to provide a

balanced load-share solution by bussing the necessary

pins. Figure 4 illustrates the shared connections required

for load sharing.

constant current limit with temperature. In this application,

+

Ifanexternaloscillatorisnotprovided,theSYNCpinshould

only be enabled on one of the LTC3884s. The other(s)

should be programmed to disable SYNC using bit 4 of

MFR_CONFIG_ALL. If an external oscillator is present, the

chip with the SYNC pin enabled will detect the presence

of the external clock and disable its output.

the I

pin is connected to the FET side of the DCR

SENSEn

–

sensing filter capacitor while the I

pin is placed on

SENSEn

the load side of the capacitor. The current sensed from the

input is then given by the expression V /DCR. V is

digitized by the LTC3884’s telemetry ADC with an input

range of 128mV, a noise floor of 7μV , and a peak-peak

noise of approximately 46.5μV. The LTC3884 computes

the inductor current using the DCR value stored in the

IOUT_CAL_GAINcommandandthetemperaturecoefficient

storedincommandMFR_IOUT_CAL_GAIN_TC.Theresult-

ing current value is returned by the READ_IOUT command.

DCR

RMS

+

MultiplechipsneedtotiealltheV

pinstogether, and

SENSE

–

all the V

as well.

pins together, and I

and I together

SENSE

THR TH

EXTERNAL/INTERNAL TEMPERATURE SENSE

Externaltemperaturecanbestbemeasuredusingaremote,

diode-connected PNP transistor such as the MMBT3906.

The emitter should be connected to a TSNS pin while the

base and collector terminals of the PNP transistor should

be returned directly to the LTC3884 SGND pin. Two dif-

ferent currents are applied to the diode (nominally 2μA

INPUT CURRENT SENSING

TosensethetotalinputcurrentconsumedbytheLTC3884

and the power stage, a resistor is placed between the sup-

ply voltage and the drain of the top N-channel MOSFET.

+

–

The I and I pins are connected to the sense resistor.

IN

The filtered voltage is amplified by the internal high side

current sense amplifier and digitized by the LTC3884’s

telemetry ADC. The input current sense amplifier has

three gain settings of 2x, 4x, and 8x set by the bit[6:5] of

the MFR_PWM_CONFIG command. The maximum input

sense voltage for the three gain settings is 50mV, 20mV,

and 5mV respectively. The LTC3884 computes the input

current using the R value stored in the IIN_CAL_GAIN

command. The resulting measured power stage current

is returned by the READ_IIN command.

and 32μA) and the temperature is calculated from a ∆V

BE

measurement made with the internal 16-bit monitor ADC

(see Figure 5).

ꢀꢁꢂꢁ

ꢈꢀꢉ3884

ꢁꢍꢂꢎ

ꢊꢆꢋꢌ

ꢃꢃꢄꢀ3ꢅꢆꢇ

ꢁꢍꢂꢎ

3884 ꢌꢆꢏ

Figure 5. Temperature Sense Circuit

The LTC3884 uses the RVIN resistor to measure the V_IN

pin supply current being consumed by the LTC3884. This

valueisreturnedbytheMFR_READ_ICHIPcommand.The

chipcurrentiscalculatedbyusingtheRvaluestoredinthe

MFR_RVINcommand. RefertothesubsectiontitledInput

Current Sense Amplifier in the Applications Information

section for further details.

The LTC3884 also supports direct V based external

BE

temperature measurements. In this case the diode or di-

ode network is trimmed to a specific voltage at a specific

current and temperature. In general this method does not

yield as accurate result as the single PNP transistor ∆V

BE

method, but may function better in a noisy application.

Refer to MFR_PWM_MODE in the PMBus Command De-

tails section for additional information on programming

the LTC3884 for these two external temperature sense

3884fe

27

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

configurations. The calculated temperature is returned by

the PMBus READ_TEMPERATURE_1 command. Refer to

the Applications Information section for details on proper

layoutofexternaltemperaturesenseelementsandPMBus

commands that can be used to improve the accuracy of

calculated temperatures. The READ_TEMPERATURE_2

command returns the internal junction temperature of the

during a power-up reset or after a MFR_RESET or after a

RESTORE_USER_ALL command is executed.

The V

pin settings are described in Table 3. These

OUTn_CFG

pins select the output voltages for the LTC3884’s analog

PWMcontrollers. Ifthepinisopen, theVOUT_COMMAND

command is loaded from NVM to determine the output

voltage. The default setting is to have the switcher off

unless the voltage configuration pins are installed.

LTC3884 using an on-chip diode with a ∆V measure-

ment and calculation.

BE

The following parameters are set as a percentage of the

output voltage if the RCONFIG pins are used to determine

the output voltage:

The slope of the external temperature sensor can be

modified with the temperature slope coefficient stored in

MFR_TEMP_1_GAIN. Typical PNPs require temperature

slopeadjustmentsslightlylessthan1.TheMMBT3906has

a recommended value in this command of approximately

MFR_TEMP_1_GAIN = 0.991 based on the ideality factor

of 1.01. Simply invert the ideality factor to calculate the

MFR_TEMP_1_GAIN. Different manufacturers and differ-

entlotsmayhavedifferentidealityfactors.Consultwiththe

manufacturer to set this value. The offset of the external

temperaturesensecanbeadjustedbyMFR_TEMP_1_OFF-

SET. Avalueof0inthisregistersetsthetemperatureoffset

to –273.15°C.

n

VOUT_OV_FAULT_LIMIT.....................................+10%

n

VOUT_OV_WARN_LIMIT...................................+7.5%

n

VOUT_MAX.......................................................+7.5%

n

VOUT_MARGIN_HIGH..........................................+5%

n

VOUT_MARGIN_LOW...........................................–5%

n

VOUT_UV_WARN_LIMIT...................................–6.5%

n

VOUT_UV_FAULT_LIMIT.......................................–7%

The FREQ_CFG pin settings are described in Table 4. This

pinselectstheswitchingfrequency.Thephaserelationships

betweenthetwochannelsandSYNCpinaredeterminedby

the PHASE_CFG pin described in Table 5. To synchronize

to an external clock, the part should be put into external

clock mode (SYNC output disabled but frequency set to

thenominalvalue).Ifnoexternalclockissupplied,thepart

will clock at the programmed frequency. If the application

is multiphase and the SYNC signal between chips is lost,

the parts will not operate at the designed phase even if

theyareprogrammedandtrimmedtothesamefrequency.

This may increase the ripple voltage on the output, pos-

sibly produce undesirable operation. If the external SYNC

signal is being generated internally and external SYNC is

not selected, bit 10 of MFR_PADS will be asserted. If no

frequency is selected and the external SYNC frequency is

not present, a PLL_FAULT will occur. If the user does not

wish to see the ALERT from a PLL_FAULT even if there is

not a valid synchronization signal at power-up, the ALERT

mask for PLL_FAULT must be written. See the description

on SMBALERT_MASK for more details. If the SYNC pin is

connectedbetweenmultipleICsonlyoneoftheICsshould

have the SYNC pin enabled, and all other ICs should be

configured to have the SYNC pin disabled.

If the PNP cannot be placed in direct contact with the

inductor, the slope or offset can be increased to account

for temperature mismatches. If the user is adjusting the

slope, theinterceptpointisatabsolutezero, –273.15°C, so

small adjustments in slope can change the apparent mea-

sured temperature significantly. Another way to artificially

increase the slope of the temperature term is to increase

the MFR_IOUT_CAL_GAIN_TC term. This will modify the

temperature slope with respect to room temperature.

RCONFIG (RESISTOR CONFIGURATION) PINS

There are six input pins utilizing 1% resistor dividers

between V

and SGND to select key operating param-

DD25

eters. The pins are ASEL0, ASEL1, FREQ_CFG, V

,

OUT0_CFG

V , PHASE_CFG. If pins are floated, the value

OUT1_CFG

stored in the corresponding NVM command is used. If

bit 6 of the MFR_CONFIG_ALL configuration command

is asserted in NVM, the resistor inputs are ignored upon

power-up except for ASEL0 and ASEL1 which are always

respected.Theresistorconfigurationpinsareonlymeasured

3884fe

28

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

The ASEL0,1 pin settings are described in Table 6. ASEL1

selects the top 3 bits of the slave address for the LTC3884.

ASEL0 selects the bottom 4 bits of the slave address for

the LTC3884. If ASEL1 is floating, the 3 most significant

bits are retrieved from the NVM MFR_ADDRESS com-

mand. If ASEL0 is floating, the 4 LSB bits stored in NVM

MFR_ADDRESScommandareusedtodeterminethe4LSB

bits of the slave address. For more detail, refer to Table 6.

Any fault or warning event will always cause the ALERT

pin to assert low unless the fault or warning is masked by

the SMBALERT_MASK. The pin will remain asserted low

until the CLEAR_FAULTS command is issued, the fault bit

is written to a 1 or bias power is cycled or a MFR_RESET

command is issued, or the RUN pins are toggled OFF/ON

or the part is commanded OFF/ON via PMBus or an ARA

command operation is performed. The MFR_FAULT_

PROPAGATE command determines if the FAULT pins are

pulled low when a fault is detected.

Note: Per the PMBus specification, pin programmed

parameters can be overridden by commands from the

digital interface with the exception of ASEL which is

always honored. Do not set any part address to 0x5A or

0x5B because these are global addresses and all parts

will respond to them.

Output and input fault event handling is controlled by the

corresponding fault response byte as specified in Tables 7

to 12. Shutdown recovery from these types of faults can

either be autonomous or latched. For autonomous recov-

ery, the faults are not latched, so if the fault conditions

not present after the retry interval has elapsed, a new

soft-start is attempted. If the fault persists, the controller

will continue to retry. The retry interval is specified by the

MFR_RETRY_DELAY command and prevents damage to

the regulator components by repetitive power cycling,

assuming the fault condition itself is not immediately

destructive. The MFR_RETRY_DELAY must be greater

than 120ms. It can not exceed 83.88 seconds.

FAULT DETECTION AND HANDLING

A variety of fault and warning reporting and handling

mechanisms are available. Fault and warning detection

capabilities include:

n

Input OV FAULT Protection and UV Warning

Average Input OC Warn

Output OV/UV Fault and Warn Protection

Output OC Fault and Warn Protection

Status Registers and ALERT Masking

Figure 6 summarizes the internal LTC3884 status reg-

isters accessible by PMBus command. These contain

indication of various faults, warnings and other important

operating conditions. As shown, the STATUS_BYTE and

STATUS_WORD commands also summarize contents of

other status registers. Refer to PMBus Command Details

for specific information.

Internal and External Overtemperature Fault and Warn

Protection

n

External Undertemperature Fault and Warn Protection

CML Fault (Communication, Memory or Logic)

External Fault Detection via the Bidirectional FAULTn

Pins.

NONE OF THE ABOVE in STATUS_BYTE indicates that

one or more of the bits in the most-significant nibble of

STATUS_WORD are also set.

In addition, the LTC3884 can map any combination of

fault indicators to their respective FAULTn pin using the

propagate FAULTn response commands, MFR_FAULT_

PROPAGATE. Typical usage of a FAULTn pin is as a driver

foranexternalcrowbardevice,overtemperaturealert,over-

voltage alert or as an interrupt to cause a microcontroller

to poll the fault commands. Alternatively, the FAULTn pins

canbeusedasinputstodetectexternalfaultsdownstream

of the controller that require an immediate response.

In general, any asserted bit in a STATUS_x register also

pulls the ALERT pin low. Once set, ALERT will remain low

until one of the following occurs.

n

ACLEAR_FAULTSorMFR_RESETCommandIsIssued

n

The Related Status Bit Is Written to a One

n

The Faulted Channel Is Properly Commanded Off and

Back On

3884fe

29

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

STATUS_WORD

STATUS_VOUT*

ꢇꢈ ꢎꢏꢕꢬ

ꢇ4 ꢙꢏꢕꢬ

ꢇ3 ꢙꢡꢁꢕꢬ

ꢇꢉ ꢱꢐꢞꢪꢟꢁꢄꢝꢙꢐꢙꢝ

ꢇꢇ ꢁꢏꢩꢄꢞꢪꢃꢏꢏꢅꢹ

ꢇꢊ ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢎꢏꢕꢬꢪꢏꢎ ꢐꢑꢒꢓꢔ

ꢎꢏꢕꢬꢪꢏꢎ ꢩꢑꢖꢚꢜꢚꢭ

ꢎꢏꢕꢬꢪꢕꢎ ꢩꢑꢖꢚꢜꢚꢭ

ꢎꢏꢕꢬꢪꢕꢎ ꢐꢑꢒꢓꢔ

ꢎꢏꢕꢬꢪꢱꢂꢷ ꢩꢑꢖꢚꢜꢚꢭ

ꢬꢏꢡꢪꢱꢂꢷ ꢐꢑꢒꢓꢔ

ꢬꢏꢐꢐꢪꢱꢂꢷ ꢩꢑꢖꢚꢜꢚꢭ

ꢀꢖeꢑꢗꢘ ꢊꢆ

STATUS_INPUT

ꢎꢙꢡꢪꢏꢎ ꢐꢑꢒꢓꢔ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢎꢙꢡꢪꢕꢎ ꢩꢑꢖꢚꢜꢚꢭ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢕꢚꢜꢔ ꢏff fꢢꢖ ꢙꢚꢘꢒffꢣꢜeꢚꢔ ꢎꢙꢡ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢋ

8

ꢀꢖeꢑꢗꢘ ꢊꢆ

STATUS_BYTE

ꢀꢁꢂꢃꢄꢅꢆ

ꢙꢙꢡꢪꢏꢝ ꢩꢑꢖꢚꢜꢚꢭ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢰꢕꢟꢠ

ꢏꢐꢐ

ꢎꢏꢕꢬꢪꢏꢎ

ꢙꢏꢕꢬꢪꢏꢝ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢬꢄꢱꢁꢄꢞꢂꢬꢕꢞꢄ

ꢝꢱꢫ

ꢡꢏꢡꢄ ꢏꢐ ꢬꢳꢄ ꢂꢰꢏꢎꢄ

STATUS_IOUT

STATUS_MFR_SPECIFIC

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢙꢏꢕꢬꢪꢏꢝ ꢐꢑꢒꢓꢔ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢙꢏꢕꢬꢪꢏꢝ ꢩꢑꢖꢚꢜꢚꢭ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢙꢚꢔeꢖꢚꢑꢓ ꢬeꢶꢯeꢖꢑꢔꢒꢖe ꢐꢑꢒꢓꢔ

ꢙꢚꢔeꢖꢚꢑꢓ ꢬeꢶꢯeꢖꢑꢔꢒꢖe ꢩꢑꢖꢚꢜꢚꢭ

ꢄꢄꢁꢞꢏꢱ ꢝꢞꢝ ꢄꢖꢖꢢꢖ

ꢙꢚꢔeꢖꢚꢑꢓ ꢁꢫꢫ ꢕꢚꢓꢢꢣꢤeꢗ

ꢐꢑꢒꢓꢔ ꢫꢢꢭ ꢁꢖeꢘeꢚꢔ

ꢎꢅꢅ33 ꢕꢎ ꢢꢖ ꢏꢎ ꢐꢑꢒꢓꢔ

ꢎꢏꢕꢬ ꢟꢨꢢꢖꢔ ꢝꢦꢣꢓeꢗ

FAULT ꢁꢒꢓꢓeꢗ ꢫꢢꢮ ꢰꢦ ꢄꢧꢔeꢖꢚꢑꢓ ꢅeꢛꢜꢣe

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢖeꢑꢗꢘ ꢊꢆ

MFR_COMMON

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢝꢨꢜꢯ ꢡꢢꢔ ꢅꢖꢜꢛꢜꢚꢭ ALERT ꢫꢢꢮ

ꢝꢨꢜꢯ ꢡꢢꢔ ꢰꢒꢘꢦ

ꢀꢁꢂꢃꢄꢅꢆ

ꢙꢚꢔeꢖꢚꢑꢓ ꢝꢑꢓꢣꢒꢓꢑꢔꢜꢢꢚꢘ ꢡꢢꢔ ꢁeꢚꢗꢜꢚꢭ

ꢏꢒꢔꢯꢒꢔ ꢡꢢꢔ ꢙꢚ ꢬꢖꢑꢚꢘꢜꢔꢜꢢꢚ

ꢄꢄꢁꢞꢏꢱ ꢙꢚꢜꢔꢜꢑꢓꢜꢲeꢗ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢟꢳꢂꢞꢄꢪꢝꢫꢴꢪꢫꢏꢩ

ꢩꢁ ꢁꢜꢚ ꢳꢜꢭꢨ

STATUS_TEMPERATURE

MFR_PADS

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢏꢬ ꢐꢑꢒꢓꢔ

ꢇꢈ ꢎꢅꢅ33 ꢏꢎ ꢐꢑꢒꢓꢔ

ꢇ4 ꢎꢅꢅ33 ꢕꢎ ꢐꢑꢒꢓꢔ

ꢇ3 ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢇꢉ ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢇꢇ ꢙꢚꢛꢑꢓꢜꢗ ꢂꢅꢝ ꢞeꢘꢒꢓꢔꢀꢘꢆ

ꢇꢊ ꢟꢠꢡꢝ ꢝꢓꢢꢣꢤeꢗ ꢥꢦ ꢄꢧꢔeꢖꢚꢑꢓ ꢟꢢꢒꢖꢣe

ꢏꢬ ꢩꢑꢖꢚꢜꢚꢭ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢕꢬ ꢐꢑꢒꢓꢔ

ꢀꢖeꢑꢗꢘ ꢊꢆ

MFR_INFO

ꢇꢈ ꢞeꢘeꢖꢛeꢗ

ꢇ4 ꢞeꢘeꢖꢛeꢗ

ꢇ3 ꢞeꢘeꢖꢛeꢗ

ꢇꢉ ꢞeꢘeꢖꢛeꢗ

ꢇꢇ ꢞeꢘeꢖꢛeꢗ

ꢇꢊ ꢞeꢘeꢖꢛeꢗ

ꢋ

8

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢋ

8

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢝꢨꢑꢚꢚeꢓ ꢇ ꢜꢘ ꢁꢏꢩꢄꢞꢪꢃꢏꢏꢅ

ꢝꢨꢑꢚꢚeꢓ ꢊ ꢜꢘ ꢁꢏꢩꢄꢞꢪꢃꢏꢏꢅ

ꢫꢬꢝ3884 ꢐꢢꢖꢣꢜꢚꢭ ꢞꢕꢡꢇ ꢫꢢꢮ

ꢫꢬꢝ3884 ꢐꢢꢖꢣꢜꢚꢭ ꢞꢕꢡꢊ ꢫꢢꢮ

ꢞꢕꢡꢇ ꢁꢜꢚ ꢟꢔꢑꢔe

ꢀꢁꢂꢃꢄꢅꢆ

STATUS_CML

ꢌ

ꢍ

ꢈ

4

3

ꢉ

ꢇ

ꢊ

ꢙꢚꢛꢑꢓꢜꢗꢸꢕꢚꢘꢒꢯꢯꢢꢖꢔeꢗ ꢝꢢꢶꢶꢑꢚꢗ

ꢙꢚꢛꢑꢓꢜꢗꢸꢕꢚꢘꢒꢯꢯꢢꢖꢔeꢗ ꢅꢑꢔꢑ

ꢁꢑꢣꢤeꢔ ꢄꢖꢖꢢꢖ ꢝꢨeꢣꢤ ꢐꢑꢜꢓeꢗ

ꢱeꢶꢢꢖꢦ ꢐꢑꢒꢓꢔ ꢅeꢔeꢣꢔeꢗ

ꢁꢖꢢꢣeꢘꢘꢢꢖ ꢐꢑꢒꢓꢔ ꢅeꢔeꢣꢔeꢗ

ꢀꢖeꢑꢗꢘ ꢊꢆ

ꢞꢕꢡꢊ ꢁꢜꢚ ꢟꢔꢑꢔe

ꢞeꢘeꢖꢛeꢗ

ꢄꢄꢁꢞꢏꢱ ꢄꢝꢝ ꢟꢔꢑꢔꢒꢘ

ꢞeꢘeꢖꢛeꢗ

ꢫꢬꢝ3884 ꢐꢢꢖꢣꢜꢚꢭ FAULT1 ꢫꢢꢮ

ꢫꢬꢝ3884 ꢐꢢꢖꢣꢜꢚꢭ FAULT0 ꢫꢢꢮ

FAULT1 ꢁꢜꢚ ꢟꢔꢑꢔe

FAULT0 ꢁꢜꢚ ꢟꢔꢑꢔe

3884 ꢐꢊꢍ

ꢏꢔꢨeꢖ ꢝꢢꢶꢶꢒꢚꢜꢣꢑꢔꢜꢢꢚ ꢐꢑꢒꢓꢔ

ꢏꢔꢨeꢖ ꢱeꢶꢢꢖꢦ ꢢꢖ ꢫꢢꢭꢜꢣ ꢐꢑꢒꢓꢔ

ꢞeꢘeꢖꢛeꢗ

DESCRIPTION

MASKABLE GENERATES ALERT BIT CLEARABLE

ꢃeꢚeꢖꢑꢓ ꢐꢑꢒꢓꢔ ꢢꢖ ꢩꢑꢖꢚꢜꢚꢭ ꢄꢛeꢚꢔ

ꢃeꢚeꢖꢑꢓ ꢡꢢꢚꢵꢱꢑꢘꢤꢑꢥꢓe ꢄꢛeꢚꢔ

ꢅꢦꢚꢑꢶꢜꢣ

ꢠeꢘ

ꢡꢢ

ꢠeꢘ

ꢡꢢ

ꢠeꢘ

ꢡꢢ

ꢟꢔꢑꢔꢒꢘ ꢅeꢖꢜꢛeꢗ fꢖꢢꢶ ꢏꢔꢨeꢖ ꢰꢜꢔꢘ

ꢡꢢꢔ ꢅꢜꢖeꢣꢔꢓꢦ

ꢡꢢ

Figure 6. LTC3884 Status Register Summary

3884fe

30

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

n

TheLTC3884SuccessfullyTransmitsItsAddressDuring

a PMBus ARA

low until either the RUN pin is toggled OFF/ON or the part

is commanded OFF/ON. The toggling of the RUN either

by the pin or OFF/ON command will clear faults associ-

ated with the channel. If it is desired to have all faults

cleared when either RUN pin is toggled or, set bit 0 of

MFR_CONFIG_ALL to a 1.

n

Bias Power Is Cycled

With some exceptions, the SMBALERT_MASK command

can be used to prevent the LTC3884 from asserting

ALERT for bits in these registers on a bit-by-bit basis.

These mask settings are promoted to STATUS_WORD

and STATUS_BYTE in the same fashion as the status bits

themselves. For example, if ALERT is masked for all bits

in Channel 0 STATUS_VOUT, then ALERT is effectively

masked for the VOUT bit in STATUS_WORD for PAGE 0.

The status of all faults and warnings is summarized in the

STATUS_WORD and STATUS_BYTE commands.

Additional fault detection and handling capabilities are:

Power Good Pins

The PGOODn pins of the LTC3884 are connected to the

open drains of internal MOSFETs. The MOSFETs turn on

and pull the PGOODn pins low when the channel output

voltageisnotwithinthechannel’sUVandOVvoltagethresh-

olds. During TON_DELAY and TON_RISE sequencing, the

PGOODn pin is held low. The PGOODn pin is also pulled

low when the respective RUNn pin is low. The PGOODn

pin response is deglitched by an internal 60μs digital filter.

The PGOODn pin and PGOOD status may be different at

times due to communication latency of up to 10µs.

The BUSY bit in STATUS_BYTE also asserts ALERT low

and cannot be masked. This bit can be set as a result of

various internal interactions with PMBus communication.

This fault occurs when a command is received that cannot

be safely executed with one or both channels enabled. As

discussed in Application Information, BUSY faults can

be avoided by polling MFR_COMMON before executing

some commands.

If masked faults occur immediately after power up, ALERT

may still be pulled low because there has not been time

to retrieve all of the programmed masking information

from EEPROM.

CRC Protection and ECC

TheLTC3884containsinternalEEPROMwitherrorcorrec-

tion coding (ECC) to store user configuration settings and

faultloginformation.EEPROMenduranceandretentionfor

userspaceandfaultlogpagesarespecifiedintheAbsolute

Maximum Ratings and Electrical Characteristics tables.

Status information contained in MFR_COMMON and

MFR_PADS can be used to further debug or clarify the

contents of STATUS_BYTE or STATUS_WORD as shown,

but the contents of these registers do not affect the state

of the ALERT pin and may not directly influence bits in

STATUS_BYTE or STATUS_WORD.

The integrity of the NVM memory is checked after a power

on reset. A CRC error will prevent the controller from leav-

ing the inactive state. If a CRC error occurs, the CML bit is

setintheSTATUS_BYTEandSTATUS_WORDcommands,

the appropriate bit is set in the STATUS_MFR_SPECIFIC

command, and the ALERT pin will be pulled low. NVM

repair can be attempted by writing the desired configura-

tion to the controller and executing a STORE_USER_ALL

command followed by a CLEAR_FAULTS command.

Mapping Faults to FAULT Pins

Channel-to-channelfault(includingchannelsfrommultiple

LTC3884s) dependencies can be created by connecting

FAULTn pins together. In the event of an internal fault, one

or more of the channels is configured to pull the bussed

FAULTn pins low. The other channels are then configured

to shut down when the FAULTn pins are pulled low. For

autonomous group retry, the faulted channel is config-

ured to let go of the FAULTn pin(s) after a retry interval,

assuming the original fault has cleared. All the channels

in the group then begin a soft-start sequence. If the fault

responseisLATCH_OFF, theFAULTnpinremainsasserted

The LTC3884 manufacturing section of the NVM is mir-

rored. If both copies are corrupted, the “NVM CRC Fault”

in the STATUS_MFR_SPECIFIC command is set. If this bit

remainssetafterbeingclearedbyissuingaCLEAR_FAULTS

or writing a 1 to this bit, an irrecoverable internal fault has

3884fe

31

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

occurred. The user is cautioned to disable both output

power supply rails associated with this specific part.

There are no provisions for field repair of NVM faults in

the manufacturing section.

or both of these global addresses. Reading from global

addresses is strongly discouraged.

Device addressing provides the standard means of the

PMBus master communicating with a single instance of

an LTC3884. The value of the device address is set by a

combination of the ASEL0 and ASEL1 configuration pins

andtheMFR_ADDRESScommand.Whenthisaddressing

meansisused,thePAGEcommanddeterminesthechannel

being acted upon. Device addressing can be disabled by

writing a value of 0x80 to the MFR_ADDRESS.

SERIAL INTERFACE

The LTC3884 serial interface is a PMBus compliant slave

device and can operate at any frequency between 10kHz

and 400kHz. The address is configurable using either the

NVMoranexternalresistordivider.InadditiontheLTC3884

always responds to the global broadcast address of 0x5A

(7 bit) or 0x5B (7 bit).

Rail addressing provides a means for the bus master to

simultaneouslycommunicatewithallchannelsconnected

together to produce a single output voltage (PolyPhase).

While similar to global addressing, the rail address can

be dynamically assigned with the paged MFR_RAIL_

ADDRESS command, allowing for any logical grouping of

channelsthatmightberequiredforreliablesystemcontrol.

Reading from rail addresses is also strongly discouraged.

The serial interface supports the following protocols de-

fined in the PMBus specifications: 1) send command, 2)

write byte, 3) write word, 4) group, 5) read byte, 6) read

word and 7) read block. 8) write block. All read operations

will return a valid PEC if the PMBus master requests it. If

the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL

command, the PMBus write operations will not be acted

upon until a valid PEC has been received by the LTC3884.

All four means of PMBus addressing require the user to

employdisciplinedplanningtoavoidaddressingconflicts.

Communication to LTC3884 devices at global and rail ad-

dresses should be limited to command write operations.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts

to access unsupported commands, or writing invalid data

to supported commands will result in a CML fault. The

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_CML

command, and the ALERT pin is pulled low.

RESPONSES TO V , I and I

FAULTS

OUT

OUT IN

V

OVandUVconditionsaremonitoredbycomparators.

OUT

The OV and UV limits are set in three ways.

n

As a Percentage of the V

Configuration Pins

if Using the Resistor

OUT

DEVICE ADDRESSING

n

In NVM if Either Programmed at the Factory or Through

the GUI

The LTC3884 offers five different types of addressing over

the PMBus interface, specifically: 1) global, 2) device, 3)

rail addressing and 4) alert response address (ARA).

By PMBus Command

The I and I

overcurrent monitors are performed by

IN

OUT

Global addressing provides a means of the PMBus master

to address all LTC3884 devices on the bus. The LTC3884

global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and

cannot be disabled. Commands sent to the global address

act the same as if PAGE is set to a value of 0xFF. Com-

mands sent are written to both channels simultaneously.

Global command 0x5B (7 bit) or 0xB6 (8 bit) is paged and

allows channel specific command of all LTC3884 devices

on the bus. Other ADI device types may respond at one

ADC readings and calculations. Thus these values are

based on average currents and can have a time latency

of up to t

. The I

calculation accounts for the

CONVERT

OUT

DCR or sense resistor and their temperature coefficient.

The input current is equal to the voltage measured across

the R

resistor divided by the resistors value as set

IINSNS

with the MFR_RVIN command. If this calculated input

current exceeds the IN_OC_WARN_LIMIT the ALERT pin

3884fe

32

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

is pulled low and the IIN_OC_WARN bit is asserted in the

STATUS_INPUT command.

Peak Output Overcurrent Fault Response

Due to the current mode control algorithm, peak output

currentacrosstheinductorisalwayslimitedonacycle-by-

cycle basis. The value of the peak current limit is specified

in sense voltage in the EC table. The current limit circuit

The digital processor within the LTC3884 provides the

ability to ignore the fault, shut down and latch off or shut

down and retry indefinitely (hiccup). The retry interval

is set in MFR_RETRY_ DELAY and can be from 120ms

to 83.88 seconds in 1ms increments. The shutdown for

OV/UV and OC can be done immediately or after a user

selectable deglitch time.

operatesbylimitingtheI maximumvoltage.IfDCRsens-

TH

ing is used, the I maximum voltage has a temperature

TH

dependency directly proportional to the TC of the DCR

of the inductor. The LTC3884 automatically monitors the

external temperature sensors and modifies the maximum

Output Overvoltage Fault Response

allowed I to compensate for this term.

TH

A programmable overvoltage comparator (OV) guards

against transient overshoots as well as long-term over-

voltages at the output. In such cases, the top MOSFET is

turned off and the bottom MOSFET is turned on. However,

the reverse output current is monitored while device is in

OV fault. When it reaches the limit, both top and bottom

MOSFETs are turned off. The top and bottom MOSFETs will

keep their state until the overvoltage condition is cleared

regardless of the PMBus VOUT_OV_FAULT_RESPONSE

command byte value. This hardware level fault response

delay is typically 2μs from the overvoltage condition to BG

asserted high. Using the VOUT_OV_FAULT_RESPONSE

command,theusercanselectanyofthefollowingbehaviors:

The overcurrent fault processing circuitry can execute the

following behaviors:

n

Current Limit Indefinitely

n

Shut Down Immediately—Latch Off

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY.

Theovercurrentresponsescanbedeglitchedinincrements

of (0-7) • 16ms. See Table 9

RESPONSES TO TIMING FAULTS

TON_MAX_FAULT_LIMIT is the time allowed for V

to

OUT

n

OV Pull-Down Only (OV Cannot Be Ignored)

rise and settle at start-up. The TON_MAX_FAULT_LIMIT

condition is predicated upon detection of the VOUT_UV_

FAULT_LIMIT as the output is undergoing aSOFT_START

sequence. The TON_MAX_ FAULT_LIMIT time is started

after TON_DELAY has been reached and a SOFT_START

sequence is started. The resolution of the TON_MAX_

FAULT_LIMIT is 10μs. If the VOUT_UV_FAULT _LIMIT

is not reached within the TON_MAX_FAULT_LIMIT time,

the response of this fault is determined by the value of

the TON_MAX_FAULT_RESPONSE command value. This

response may be one of the following:

n

Shut Down (Stop Switching) Immediately—Latch Off

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY

Either the Latch Off or Retry fault responses can be de-

glitched in increments of (0-7) • 10μs. See Table 7.

Output Undervoltage Response

The response to an undervoltage comparator output can

be the following:

n

Ignore

n

Ignore

n

Shut Down (Stop Switching) Immediately—Latch Off

n

Shut Down Immediately—Latch Off

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY.

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY.

This fault response is not deglitched. A value of 0 in

TON_MAX_FAULT_LIMIT means the fault is ignored. The

The UV responses can be deglitched. See Table 8.

3884fe

33

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

n

Ignore

TON_MAX_FAULT_LIMIT should be set longer than the

TON_RISE time. It is recommended TON_MAX_FAULT_

LIMIT always be set to a non-zero value, otherwise the

output may never come up and no flag will be set to the

user. See Table 11.

Shut Down Immediately—Latch Off

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY. See Table 9.

RESPONSES TO INPUT OVERCURRENT AND OUTPUT

UNDERCURRENT FAULTS

RESPONSES TO V OV FAULTS

IN

V overvoltage is measured with the ADC. The response

IN

Input overcurrent and output undercurrent are measured

with the ADC. The fault responses are:

is naturally deglitched by the 90ms typical response time

of the ADC. The fault responses are:

n

Ignore

n

Ignore

n

Shut Down Immediately—Latch Off

n

Shut Down Immediately—Latch Off

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY

n

ShutDownImmediately—RetryIndefinitelyattheTime

IntervalSpecifiedinMFR_RETRY_DELAY.SeeTable11.

See Table 11.

RESPONSES TO OT/UT FAULTS

RESPONSES TO EXTERNAL FAULTS

Internal Overtemperature Fault Response

When either FAULTn pin is pulled low, the OTHER bit is

set in the STATUS_WORD command, the appropriate bit

is set in the STATUS_MFR_SPECIFIC command, and the

ALERT pin is pulled low. Responses are not deglitched.

Each channel can be configured to ignore or shut down

then retry in response to its FAULTn pin going low by

modifying the MFR_FAULT_RESPONSE command. To

avoid the ALERT pin asserting low when FAULT is pulled

low, assert bit 1 of MFR_CHAN_CONFIG, or mask the

ALERT using the SMBALERT_MASK command.

An internal temperature sensor protects against NVM

damage.Above85°C,nowritestoNVMarerecommended.

Above130°C,theinternalovertemperaturewarnthreshold

isexceededandthepartdisablestheNVManddoesnotre-

enable until the temperature has dropped to 125°C. When

thedietemperatureexceed160°Ctheinternaltemperature

fault response is enabled and the PWM is disabled until

the die temperature drops below 150°C. Temperature is

measured by the ADC. Internal temperature faults cannot

beignored. Internaltemperaturelimitscannotbeadjusted

by the user. See Table 10.

FAULT LOGGING

External Overtemperature and Undertemperature

Fault Response

The LTC3884 has fault logging capability. Data is logged

into memory in the order shown in Table 13. The data is

stored in a continuously updated buffer in RAM. When a

fault event occurs, the fault log buffer is copied from the

RAM buffer into NVM. Fault logging is allowed at tem-

peratures above 85°C; however, retention of 10 years is

not guaranteed. When the die temperature exceeds 130°C

the fault logging is delayed until the die temperature drops

below 125°C. The fault log data remains in NVM until a

MFR_FAULT _LOG_CLEAR command is issued. Issuing

this command re-enables the fault log feature. Before

Two external temperature sensors can be used to sense

the temperature of critical circuit elements like inductors

and power MOSFETs. The OT_FAULT_ RESPONSE and

UT_FAULT_ RESPOSE commands are used to determine

theappropriateresponsetoanovertemperatureandunder

temperature condition, respectively. If no external sense

elementsareused(notrecommended)settheUT_FAULT_

RESPONSE to ignore and set the UT_FAULT_LIMIT to

–275°C. The fault responses are:

3884fe

34

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

re-enabling fault log, be sure no faults are present and a

CLEAR_FAULTS command has been issued.

PMBus/SMBus protocols are more robust than simple

2

I C byte commands because PMBus/SMBus provide

timeouts to prevent persistent bus errors and optional

packet error checking (PEC) to ensure data integrity.

When the LTC3884 powers-up or exits its reset state, it

checks the NVM for a valid fault log. If a valid fault log

exists in NVM, the “Valid Fault Log” bit in the STATUS_

MFR_SPECIFIC command will be set and an ALERT event

will be generated. Also, fault logging will be blocked until

the LTC3884 has received a MFR_FAULT_LOG_CLEAR

command before fault logging will be re-enabled.

2

In general, a master device that can be configured for I C

communication can be used for PMBus communication

with little or no change to hardware or firmware. Repeat

2

start (restart) is not supported by all I C controllers but

is required for SMBus/PMBus reads. If a general purpose

2

I C controller is used, check that repeat start is supported.

The information is stored in EEPROM in the event of

any fault that disables the controller on either channel. A

FAULTn being externally pulled low will not trigger a fault

logging event.

The LTC3884 supports the maximum SMBus clock speed

of 100kHz and is compatible with the higher speed PM-

Bus specification (between 100kHz and 400kHz) if MFR_

COMMONpollingorclockstretchingisenabled.Forrobust

communication and operation refer to the Note section in

thePMBuscommandsummary.Clockstretchingisenabled

by asserting bit 1 of MFR_CONFIG_ALL.

BUS TIMEOUT PROTECTION

The LTC3884 implements a timeout feature to avoid per-

sistent faults on the serial interface. The data packet timer

begins at the first START event before the device address

write byte. Data packet information must be completed

within 35ms or the LTC3884 will three-state the bus and

ignorethegivendatapacket.Ifmoretimeisrequired,assert

bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts

of 255ms. Data packet information includes the device

address byte write, command byte, repeat start event

(if a read operation), device address byte read (if a read

operation), all data bytes and the PEC byte if applicable.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.2: Paragraph 5: Transport.

For a description of the differences between SMBus and

2

I C, refer to System Management Bus (SMBus) Speci-

fication Version 2.0: Appendix B—Differences Between

2

SMBus and I C.

PMBus SERIAL DIGITAL INTERFACE

TheLTC3884allowslongerPMBustimeoutsforblockread

data packets. This timeout is proportional to the length of

the block read. The additional block read timeout applies

primarilytotheMFR_FAULT_LOGcommand.Thetimeout

period defaults to 32ms.

TheLTC3884communicateswithahost(master)usingthe

standardPMBusserialbusinterface.TheTimingDiagram,

Figure 7, shows the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The LTC3884

is a slave device. The master can communicate with the

LTC3884 using the following formats:

Theuserisencouragedtouseashighaclockrateaspossible

tomaintainefficientdatapackettransferbetweenalldevices

sharing the serial bus interface. The LTC3884 supports the

full PMBus frequency range from 10kHz to 400kHz.

n

Master Transmitter, Slave Receiver

n

Master Receiver, Slave Transmitter

2

SIMILARITY BETWEEN PMBus, SMBus AND I C

The following PMBus protocols are supported:

2-WIRE INTERFACE

n

Write Byte, Write Word, Send Byte

The PMBus 2-wire interface is an incremental extension

2

n

of the SMBus. SMBus is built upon I C with some minor

Read Byte, Read Word, Block Read, Block Write

differences in timing, DC parameters and protocol. The

n

Alert Response Address

3884fe

35

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

Figures 8-25 illustrate the aforementioned PMBus pro-

tocols. All transactions support PEC and GCP (group

command protocol). The Block Read supports 255 bytes

of returned data. For this reason, the PMBus timeout may

be extended when reading the fault log.

the slave receiver) the master transmitter becomes a

master receiver and the slave receiver becomes a slave

transmitter.

n

Combined format. During a change of direction within

a transfer, the master repeats both a start condition and

the slave address but with the R/W bit reversed. In this

case, the master receiver terminates the transfer by

generating a NACK on the last byte of the transfer and

a STOP condition.

Figure 8 is a key to the protocol diagrams in this section.

PEC is optional.

A value shown below a field in the following figures is

mandatory value for that field.

Refer to Figure 8 for a legend.

The data formats implemented by PMBus are:

Handshakingfeaturesareincludedtoensurerobustsystem

communication.PleaserefertothePMBusCommunication

and Command Processing subsection of the Applications

Information section for further details.

n

Master transmitter transmits to slave receiver. The

transfer direction in this case is not changed.

n

Master reads slave immediately after the first byte. At

the moment of the first acknowledgment (provided by

ꢀꢁꢂ

ꢅ

ꢔ

ꢅ

ꢀꢊꢇꢁꢂꢈꢉ

ꢅ

ꢀꢍ

ꢅ

ꢆꢁꢇꢀꢁꢂꢉ

ꢔ

ꢅ

f

ꢎꢊꢏ

f

ꢄꢋꢌ

ꢀꢃꢄ

ꢅ

ꢀꢊꢇꢀꢈꢋꢉ

ꢆꢁꢇꢀꢈꢂꢉ

ꢀꢊꢇꢀꢈꢂꢉ

ꢅ

ꢆꢒꢕꢆ

ꢆꢁꢇꢁꢂꢈꢉ

3884 ꢏꢖꢗ

ꢀꢈꢂꢐꢈ

ꢃꢋꢑꢁꢒꢈꢒꢋꢑ

ꢐꢓꢍꢓꢂꢈꢓꢁ ꢀꢈꢂꢐꢈ

ꢃꢋꢑꢁꢒꢈꢒꢋꢑ

ꢀꢈꢋꢍ

ꢀꢈꢂꢐꢈ

ꢃꢋꢑꢁꢒꢈꢒꢋꢑ ꢃꢋꢑꢁꢒꢈꢒꢋꢑ

Figure 7. Timing Diagram

Table 1. Abbreviations of Supported Data Formats

PMBus

SPECIFICATION

ADI

TERMINOLOGY

L11 Linear

REFERENCE TERMINOLOGY DEFINITION

EXAMPLE

N

Part II ¶7.1

Linear_5s_1s Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x9807 = 10011_000_0000_0111

–13

where N = b[15:1] and Y = b[10:0], both

two’s compliment binary integers.

value = 7 • 2 = 854E-6

–12

L16 Linear VOUT_MODE

CF DIRECT

Part II ¶8.2

Part II ¶7.2

Linear_16u

Varies

Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x4C00 = 0100_1100_0000_0000

–12

where Y = b[15:0], an unsigned integer.

value = 19456 • 2 = 4.75

16-bit data with a custom format

defined in the detailed PMBus command

description.

Often an unsigned or two’s compliment

integer.

Reg register bits

Part II ¶10.3

Reg

Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.

command description.

ASC text characters

Part II ¶22.2.1

ASCII

ISO/IEC 8859-1 [A05]

LTC (0x4C5443)

3884fe

36

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

ꢂ

ꢂꢃꢄꢅꢃ ꢆꢇꢈꢉꢊꢃꢊꢇꢈ

ꢂꢋ

ꢅꢌꢍꢌꢄꢃꢌꢉ ꢂꢃꢄꢅꢃ ꢆꢇꢈꢉꢊꢃꢊꢇꢈ

ꢅꢎ ꢅꢌꢄꢉ ꢏꢐꢊꢃ ꢑꢄꢒꢓꢌ ꢇꢀ ꢔꢕ

ꢖꢋ ꢖꢅꢊꢃꢌ ꢏꢐꢊꢃ ꢑꢄꢒꢓꢌ ꢇꢀ ꢁꢕ

ꢄ

ꢄꢆꢗꢈꢇꢖꢒꢌꢉꢘꢌ ꢏꢃꢙꢊꢂ ꢐꢊꢃ ꢍꢇꢂꢊꢃꢊꢇꢈ ꢚꢄꢛ ꢐꢌ ꢁ

ꢀꢇꢅ ꢄꢈ ꢄꢆꢗ ꢇꢅ ꢔ ꢀꢇꢅ ꢄ ꢈꢄꢆꢗꢕ

ꢍ

ꢂꢃꢇꢍ ꢆꢇꢈꢉꢊꢃꢊꢇꢈ

ꢍꢌꢆ ꢍꢄꢆꢗꢌꢃ ꢌꢅꢅꢇꢅ ꢆꢇꢉꢌ

ꢚꢄꢂꢃꢌꢅ ꢃꢇ ꢂꢒꢄꢑꢌ

ꢂꢒꢄꢑꢌ ꢃꢇ ꢚꢄꢂꢃꢌꢅ

ꢜꢜꢜ

ꢆꢇꢈꢃꢊꢈꢓꢄꢃꢊꢇꢈ ꢇꢀ ꢍꢅꢇꢃꢇꢆꢇꢒ

3884 ꢀꢁ8

Figure 8. PMBus Packet Protocol Diagram Element Key

ꢐ

ꢏ

ꢐ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢇꢈꢉꢊ

ꢂ

ꢋ

3884 ꢌꢍꢎ

Figure 9. Quick Command Protocol

ꢏ

ꢑ

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢍ

3884 ꢎꢏꢐ

Figure 10 . Send Byte Protocol

ꢏ

ꢐ

ꢏ

8

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢌꢍ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢋꢄꢇ

ꢂ

ꢋ

3884 ꢎꢏꢏ

Figure 11. Send Byte Protocol with PEC

ꢒ

ꢔ

ꢒ

8

ꢒ

8

ꢒ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢎꢏ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ

ꢂ

ꢐ

3884 ꢑꢒꢓ

Figure 12. Write Byte Protocol

ꢒ

ꢓ

ꢒ

8

ꢒ

8

ꢒ

8

ꢒ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢎꢏ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ

ꢂ

ꢐꢄꢇ

ꢂ

ꢐ

3884 ꢑꢒ3

Figure 13. Write Byte Protocol with PEC

ꢒ

ꢓ

ꢒ

8

ꢒ

8

ꢒ

8

ꢒ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢎꢏ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ ꢁꢈꢎ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ ꢔꢕꢖꢔ

ꢂ

ꢐ

3884 ꢑꢒ4

Figure 14. Write Word Protocol

ꢒ

ꢔ

ꢒ

8

ꢒ

8

ꢒ

8

ꢒ

8

ꢒ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢎꢏ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ ꢁꢈꢎ

ꢂ

ꢅꢂꢋꢂ ꢌꢍꢋꢄ ꢕꢖꢗꢕ

ꢂ

ꢐꢄꢇ

ꢂ

ꢐ

3884 ꢑꢒꢓ

Figure 15. Write Word Protocol with PEC

3884fe

37

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

ꢏ

ꢑ

ꢏ

8

ꢏ

ꢑ

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢕ

ꢂ

ꢅꢂꢒꢂ ꢓꢔꢒꢄ

ꢂ

ꢍ

3884 ꢎꢏꢐ

Figure 16. Read Byte Protocol

ꢏ

ꢐ

ꢏ

8

ꢏ

ꢐ

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢔ

ꢂ

ꢅꢂꢑꢂ ꢒꢓꢑꢄ

ꢂ

ꢍꢄꢇ

ꢂ

ꢍ

3884 ꢎꢏꢐ

Figure 17. Read Byte Protocol with PEC

ꢏ

ꢐ

ꢏ

8

ꢏ

ꢐ

ꢏ

8

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢗ

ꢂ

ꢅꢂꢑꢂ ꢒꢓꢑꢄ ꢁꢈꢋ

ꢂ

ꢅꢂꢑꢂ ꢒꢓꢑꢄ ꢔꢕꢖꢔ

ꢂ

ꢍ

3884 ꢎꢏ8

Figure 18. Read Word Protocol

ꢏ

ꢑ

ꢏ

8

ꢏ

ꢑ

ꢏ

8

ꢏ

8

ꢏ

8

ꢏ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢘ

ꢂ

ꢅꢂꢒꢂ ꢓꢔꢒꢄ ꢁꢈꢋ

ꢂ

ꢅꢂꢒꢂ ꢓꢔꢒꢄ ꢕꢖꢗꢕ

ꢂ

ꢍꢄꢇ

ꢂ

ꢍ

3884 ꢎꢏꢐ

Figure 19. Read Word Protocol with PEC

ꢎ

ꢍ

ꢎ

8

ꢎ

ꢍ

ꢎ

8

ꢎ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢔ

ꢂ

ꢏꢐꢑꢄ ꢇꢈꢒꢊꢑ ꢓ ꢊ

ꢂ

ꢕ

8

ꢎ

8

ꢎ

ꢕ

8

ꢎ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ

ꢂ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢘ

ꢂ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢊ

ꢂ

ꢖ

3884 ꢗꢘꢘ

Figure 20 . Block Read Protocol

ꢎ

ꢍ

ꢎ

8

ꢎ

ꢍ

ꢎ

8

ꢎ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢋꢌ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢀꢌ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢔ

ꢂ

ꢏꢐꢑꢄ ꢇꢈꢒꢊꢑ ꢓ ꢊ

ꢂ

ꢕ

8

ꢎ

8

ꢎ

ꢕ

8

ꢎ

8

ꢎ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ

ꢂ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢖ

ꢂ

ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢊ

ꢂ

ꢗꢄꢇ

ꢂ

ꢗ

3884 ꢘꢖꢎ

Figure 21. Block Read Protocol with PEC

3884fe

38

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

OPERATION

ꢓ

ꢒ

ꢓ

8

ꢓ

8

ꢓ

8

ꢓ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢐꢑ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢋꢌꢍꢄ ꢇꢈꢎꢊꢍ ꢏ ꢉ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢓ

ꢂ

ꢔ

8

ꢓ

8

ꢓ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢕ

ꢂ

ꢔ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢉ

ꢂ

ꢔ

ꢓ

ꢒ

ꢓ

8

ꢓ

8

ꢓ

ꢀꢑ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢖ

ꢂ

ꢋꢌꢍꢄ ꢇꢈꢎꢊꢍ ꢏ ꢊ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢓ

ꢂ

ꢔ

8

ꢓ

ꢔ

8

ꢓ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢕ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢊ

ꢂ

ꢗ

3884 ꢘꢕꢕ

Figure 22. Block Write – Block Read Process Call

ꢓ

ꢒ

ꢓ

8

ꢓ

8

ꢓ

8

ꢓ

ꢀ

ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢐꢑ

ꢂ

ꢇꢈꢉꢉꢂꢊꢅ ꢇꢈꢅꢄ

ꢂ

ꢋꢌꢍꢄ ꢇꢈꢎꢊꢍ ꢏ ꢉ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢓ

ꢂ

ꢔ

8

ꢓ

8

ꢓ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢕ

ꢂ

ꢔ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢉ

ꢂ

ꢔ

ꢓ

ꢒ

ꢓ

8

ꢓ

8

ꢓ

ꢀꢑ ꢀꢁꢂꢃꢄ ꢂꢅꢅꢆꢄꢀꢀ ꢆꢖ

ꢂ

ꢋꢌꢍꢄ ꢇꢈꢎꢊꢍ ꢏ ꢊ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢓ

ꢂ

ꢔ

8

ꢓ

ꢔ

8

ꢓ

8

ꢓ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢕ

ꢂ

ꢅꢂꢍꢂ ꢋꢌꢍꢄ ꢊ

ꢂ

ꢗꢄꢇ

ꢂ

ꢗ

3884 ꢘꢕ3

Figure 23. Block Write – Block Read Process Call with PEC

ꢎ

ꢍ

ꢎ

8

ꢎ

ꢀꢁꢂꢃꢄ ꢃꢂꢅꢆꢇꢈꢅꢂ

ꢀꢉꢉꢃꢂꢅꢅ

ꢅ

ꢃꢊ

ꢀ

ꢉꢂꢏꢐꢑꢂ ꢀꢉꢉꢃꢂꢅꢅ

ꢀ

ꢆ

3884 ꢋꢌ4

Figure 24. Alert Response Address Protocol

ꢌ

ꢋ

ꢌ

8

ꢌ

8

ꢌ

ꢀꢁꢂꢃꢄ ꢃꢂꢅꢆꢇꢈꢅꢂ

ꢀꢉꢉꢃꢂꢅꢅ

ꢅ

ꢃꢊ

ꢀ

ꢉꢂꢍꢎꢏꢂ ꢀꢉꢉꢃꢂꢅꢅ

ꢀ

ꢆꢂꢏ

ꢀ

ꢆ

3884 ꢐꢑꢒ

Figure 25. Alert Response Address Protocol with PEC

3884fe

39

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

PMBus COMMANDS

plicitly not supported by the manufacturer. Attempting to

access non-supported or reserved commands may result

in a CML command fault event. All output voltage settings

ThefollowingtableslistsupportedPMBuscommandsand

manufacturerspecificcommands.Acompletedescription

of these commands can be found in the “PMBus Power

System Mgt Protocol Specification – Part II – Revision

1.2”. Usersareencouragedtoreferencethisspecification.

Exceptions or manufacturer specific implementations are

listed below in Table 2. Floating point values listed in the

“DEFAULT VALUE” column are either Linear 16-bit Signed

(PMBus Section 8.3.1) or Linear_5s_11s (PMBus Sec-

tion7.1)format,whicheverisappropriateforthecommand.

All commands from 0xD0 through 0xFF not listed in this

table are implicitly reserved by the manufacturer. Users

should avoid blind writes within this range of commands

to avoid undesired operation of the part. All commands

from 0x00 through 0xCF not listed in this table are im-

and measurements are based on the VOUT_MODE setting

–12

of 0x14. This translates to an exponent of 2

.

If PMBus commands are received faster than they are be-

ing processed, the part may become too busy to handle

new commands. In these circumstances the part follows

the protocols defined in the PMBus Specification v1.2,

Part II, Section 10.8.7, to communicate that it is busy.

The part includes handshaking features to eliminate busy

errors and simplify error handling software while ensur-

ing robust communication and system behavior. Please

refer to the subsection titled PMBus Communication and

Command Processing in the Applications Information

section for further details.

Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.)

CMD

DATA

DEFAULT

VALUE PAGE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

PAGE

0x00 Provides integration with multi-page PMBus

devices.

R/W Byte

N

Y

Reg

0x00

0x80

0x1E

NA

73

77

OPERATION

0x01 Operating mode control. On/off, margin high

and margin low.

R/W Byte

Y

ON_OFF_CONFIG

0x02 RUN pin and PMBus bus on/off command

configuration.

CLEAR_FAULTS

0x03 Clear any fault bits that have been set.

Send Byte

W Block

N

102

69

PAGE_PLUS_WRITE

PAGE_PLUS_READ

WRITE_PROTECT

0x05 Write a command directly to a specified page.

0x06 Read a command directly from a specified page. Block R/W

73

0x10 Level of protection provided by the device

against accidental changes.

R/W Byte

Reg

Y

0x00

74

STORE_USER_ALL

RESTORE_USER_ALL

CAPABILITY

0x15 Store user operating memory to EEPROM.

Send Byte

N

NA

113

101

0x16 Restore user operating memory from EEPROM. Send Byte

0x19 Summary of PMBus optional communication

protocols supported by this device.

R Byte

0xB0

SMBALERT_MASK

VOUT_MODE

0x1B Mask ALERT activity

Block R/W

R Byte

Y

Reg

Y

see CMD 103

–12

0x20 Output voltage format and exponent (2 ).

2

83

84

83

84

0x14

VOUT_COMMAND

VOUT_MAX

0x21 Nominal output voltage set point.

R/W Word

Y

L16

V

Y

1.0

0x1000

0x24 Upper limit on the commanded output voltage

including VOUT_MARGIN_HI.

2.75

0x2C00

VOUT_MARGIN_HIGH

VOUT_MARGIN_LOW

0x25 Margin high output voltage set point. Must be

greater than VOUT_COMMAND.

1.05

0x10CD

0x26 Margin low output voltage set point. Must be

less than VOUT_COMMAND.

0.95

0x0F33

3884fe

40

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

VALUE PAGE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

VOUT_TRANSITION_

RATE

0X27 Rate the output changes when VOUT

commanded to a new value.

R/W Word

Y

N

Y

L11

V/ms

kHz

V

Y

0.25

90

81

82

85

0xAA00

FREQUENCY_SWITCH

0x33 Switching frequency of the controller.

R/W Word

425k

0xFB52

VIN_ON

0x35 Input voltage at which the unit should start

power conversion.

6.5

0xCB40

VIN_OFF

0x36 Input voltage at which the unit should stop

power conversion.

V

6.0

0xCB00

IOUT_CAL_GAIN

0x38 The ratio of the voltage at the current sense

pins to the sensed current. For devices using a

fixed current sense resistor, it is the resistance

value in mΩ.

mΩ

0.32

0xAA8F

VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit.

R/W Word

Y

N

Y

N

Y

L16

Reg

L16

Reg

L11

Reg

L11

Reg

L11

Reg

L11

Reg

L11

V

Y

1.1

83

92

83

84

93

86

95

87

88

97

88

89

97

81

92

82

87

0x119A

VOUT_OV_FAULT_

RESPONSE

0x41 Action to be taken by the device when an output R/W Byte

overvoltage fault is detected.

0xB8

VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit.

VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit.

VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit.

R/W Word

V

1.075

0x1133

0.925

0x0ECD

0.9

0x0E66

VOUT_UV_FAULT_

RESPONSE

0x45 Action to be taken by the device when an output R/W Byte

undervoltage fault is detected.

0xB8

IOUT_OC_FAULT_LIMIT

0x46 Output overcurrent fault limit.

R/W Word

A

45.0

0xE2D0

IOUT_OC_FAULT_

RESPONSE

0x47 Action to be taken by the device when an output R/W Byte

overcurrent fault is detected.

0x00

IOUT_OC_WARN_LIMIT

0x4A Output overcurrent warning limit.

R/W Word

R/W Byte

R/W Word

R/W Byte

R/W Word

R/W Byte

R/W Word

A

C

35.0

0xE230

OT_FAULT_LIMIT

0x4F External overtemperature fault limit.

100.0

0xEB20

OT_FAULT_RESPONSE

OT_WARN_LIMIT

0x50 Action to be taken by the device when an

external overtemperature fault is detected,

0xB8

0x51 External overtemperature warning limit.

C

85.0

0xEAA8

UT_FAULT_LIMIT

0x53 External undertemperature fault limit.

–40.0

0xE580

UT_FAULT_RESPONSE

VIN_OV_FAULT_LIMIT

0x54 Action to be taken by the device when an

external undertemperature fault is detected.

0xB8

0x55 Input supply overvoltage fault limit.

V

15.5

0xD3E0

VIN_OV_FAULT_

RESPONSE

0x56 Action to be taken by the device when an input

overvoltage fault is detected.

0x80

VIN_UV_WARN_LIMIT

IIN_OC_WARN_LIMIT

TON_DELAY

0x58 Input supply undervoltage warning limit.

V

A

6.3

0xCB26

0x5D Input supply overcurrent warning limit.

10.0

0xD280

0x60 Time from RUN and/or Operation on to output

rail turn-on.

ms

0.0

0x8000

89

3884fe

41

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

VALUE PAGE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

TON_RISE

0x61 Time from when the output starts to rise

until the output voltage reaches the VOUT

commanded value.

R/W Word

Y

L11

ms

Y

8.0

0xD200

89

TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for R/W Word

VOUT to cross the VOUT_UV_FAULT_LIMIT.

Y

L11

Reg

L11

ms

Y

10.00

90

95

90

91

0xD280

TON_MAX_FAULT_

RESPONSE

0x63 Action to be taken by the device when a TON_

MAX_FAULT event is detected.

R/W Byte

0xB8

TOFF_DELAY

0x64 Time from RUN and/or Operation off to the start R/W Word

of TOFF_FALL ramp.

ms

0.0

0x8000

TOFF_FALL

0x65 Time from when the output starts to fall until

the output reaches zero volts.

R/W Word

8.00

0xD200

TOFF_MAX_WARN_

LIMIT

0x66 Maximum allowed time, after TOFF_FALL

completed, for the unit to decay below 12.5%.

R/W Word

150.0

0xF258

STATUS_BYTE

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

STATUS_INPUT

0x78 One byte summary of the unit’s fault condition. R/W Byte

0x79 Two byte summary of the unit’s fault condition. R/W Word

Y

N

Y

Reg

NA

104

105

106

0x7A Output voltage fault and warning status.

0x7B Output current fault and warning status.

0x7C Input supply fault and warning status.

R/W Byte

STATUS_TEMPERATURE 0x7D External temperature fault and warning status

for READ_TEMERATURE_1.

STATUS_CML

0x7E Communication and memory fault and warning R/W Byte

status.

N

Y

Reg

NA

107

STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state

information.

R/W Byte

READ_VIN

READ_IIN

0x88 Measured input supply voltage.

0x89 Measured input supply current.

0x8B Measured output voltage.

0x8C Measured output current.

R Word

N

Y

L11

L16

L11

V

A

V

A

C

NA

110

READ_VOUT

READ_IOUT

READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This

is the value used for all temperature related

processing, including IOUT_CAL_GAIN.

READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not

affect any other commands.

R Word

N

L11

C

NA

110

READ_FREQUENCY

READ_POUT

0x95 Measured PWM switching frequency.

0x96 Measured output power

R Word

R Byte

Y

N

L11

Reg

Hz

W

NA

N/A

110

111

101

READ_PIN

0x97 Calculated input power

N/A

PMBus_REVISION

0x98 PMBus revision supported by this device.

Current revision is 1.2.

0x22

MFR_ID

0x99 The manufacturer ID of the LTC3884 in ASCII.

0x9A Manufacturer part number in ASCII.

R String

R Word

N

Y

ASC

L16

LTC

101

MFR_MODEL

MFR_VOUT_MAX

LTC3884 101

0xA5 Maximum allowed output voltage including

VOUT_OV_FAULT_LIMIT.

V

5.7

0x5B33

85

MFR_PIN_ACCURACY

USER_DATA_00

0xAC Returns the accuracy of the READ_PIN command

R Byte

N

%

5.0%

NA

111

101

0xB0 OEM RESERVED. Typically used for part

serialization.

R/W Word

Reg

Y

3884fe

42

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

COMMAND NAME

USER_DATA_01

USER_DATA_02

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

VALUE PAGE

0xB1 Manufacturer reserved for LTpowerPlay.

R/W Word

Y

N

Reg

Y

NA

101

0xB2 OEM RESERVED. Typically used for part

serialization.

USER_DATA_03

USER_DATA_04

MFR_INFO

0xB3 An NVM word available for the user.

0xB4 An NVM word available for the user.

0xB6 Manufacturing specific information.

0xBD Contact factory.

R/W Word

R Word

Y

N

Reg

Y

0x0000 101

109

MFR_EE_UNLOCK

118

MFR_EE_ERASE

0xBE Contact factory.

118

MFR_EE_DATA

0xBF Contact factory.

118

MFR_CHAN_CONFIG

MFR_CONFIG_ALL

0xD0 Configuration bits that are channel specific.

0xD1 General configuration bits.

R/W Byte

R/W Word

Y

N

Y

Reg

Y

0x1D

0x21

75

76

98

MFR_FAULT_

PROPAGATE

0xD2 Configuration that determines which faults are

propagated to the FAULT pin.

0x6993

MFR_PWM_COMP

MFR_PWM_MODE

0xD3 PWM loop compensation configuration

0xD4 Configuration for the PWM engine.

R/W Byte

Y

Reg

Y

0xAE

0xC7

0xC0

79

78

MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the

FAULT pin is externally asserted low.

100

MFR_OT_FAULT_

RESPONSE

0xD6 Action to be taken by the device when an

internal overtemperature fault is detected.

R Byte

R Word

N

Y

N

Y

N

Y

Reg

L11

Reg

L11

L16

L11

0xC0

NA

96

111

112

91

MFR_IOUT_PEAK

0xD7 Report the maximum measured value of READ_

IOUT since last MFR_CLEAR_PEAKS.

A

MFR_ADC_CONTROL

MFR_RETRY_DELAY

MFR_RESTART_DELAY

MFR_VOUT_PEAK

MFR_VIN_PEAK

0xD8 ADC telemetry parameter selected for repeated

fast ADC read back

R/W Byte

R/W Word

R Word

0x00

0xDB Retry interval during FAULT retry mode.

ms

V

Y

350.0

0xFABC

0xDC Minimum time the RUN pin is held low by the

LTC3884.

500.0

0xFBE8

91

0xDD Maximum measured value of READ_VOUT

since last MFR_CLEAR_PEAKS.

NA

111

0xDE Maximum measured value of READ_VIN since

last MFR_CLEAR_PEAKS.

R Word

V

MFR_TEMPERATURE_1_ 0xDF Maximum measured value of external

PEAK

R Word

C

Temperature (READ_TEMPERATURE_1) since

last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN

command since last MFR_CLEAR_PEAKS

R Word

N

L11

A

NA

111

MFR_CLEAR_PEAKS

MFR_READ_ICHIP

MFR_PADS

0xE3 Clears all peak values.

Send Byte

R Word

N

NA

103

111

108

75

0xE4 Measured supply current of the LTC3884

0xE5 Digital status of the I/O pads.

L11

Reg

R Word

NA

2

MFR_ADDRESS

MFR_SPECIAL_ID

0xE6 Sets the 7-bit I C address byte.

R/W Byte

R Word

Y

0x4F

0xE7 Manufacturer code representing the LTC3884

and revision

0x4C0X 101

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current sense R/W Word

element in mΩ.

N

L11

mΩ

5.0

0xCA80

87

3884fe

43

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

CMD

DATA

DEFAULT

VALUE PAGE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

MFR_FAULT_LOG_

STORE

0xEA Command a transfer of the fault log from RAM

to EEPROM.

Send Byte

N

NA

115

MFR_FAULT_LOG_

CLEAR

0xEC Initialize the EEPROM block reserved for fault

logging.

Send Byte

N

118

MFR_FAULT_LOG

MFR_COMMON

0xEE Fault log data bytes.

R Block

R Byte

N

Reg

Y

NA

115

108

0xEF Manufacturer status bits that are common

across multiple ADI chips.

MFR_COMPARE_USER_ 0xF0 Compares current command contents with

ALL NVM.

Send Byte

R Word

N

Y

N

Y

NA

113

112

80

MFR_TEMPERATURE_2_ 0xF4 Peak internal die temperature since last MFR_

L11

Reg

CF

C

PEAK

CLEAR_PEAKS.

MFR_PWM_CONFIG

0xF5 Set numerous parameters for the DC/DC

controller including phasing.

R/W Byte

R/W Word

Y

0x10

MFR_IOUT_CAL_GAIN_

TC

0xF6 Temperature coefficient of the current sensing

element.

ppm/

˚C

3900

0x0F3C

85

MFR_RVIN

0xF7 The resistance value of the V pin filter element R/W Word

L11

CF

mΩ

1000

0x03E8

82

IN

in mΩ.

MFR_TEMP_1_GAIN

MFR_TEMP_1_OFFSET

MFR_RAIL_ADDRESS

0xF8 Sets the slope of the external temperature

sensor.

R/W Word

R/W Byte

1.0

0x4000

88

0xF9 Sets the offset of the external temperature

sensor with respect to –273.1°C

L11

Reg

CF

C

0.0

0x8000

88

0xFA Common address for PolyPhase outputs to

adjust common parameters.

0x80

75

MFR_REAL_TIME

MFR_RESET

0xFB 48-bit share-clock counter value.

R Block

N

NA

xx

0xFD Commanded reset without requiring a power

down.

Send Byte

77

Note 1: Commands indicated with Y in the NVM column indicate that these

commands are stored and restored using the STORE_USER_ALL and

RESTORE_USER_ALL commands, respectively.

Note 4: Some of the unpublished commands are read-only and will

generate a CML bit 6 fault if written.

Note 5: Writing to commands not published in this table is not permitted.

Note 2: Commands with a default value of NA indicate “not applicable”.

Commands with a default value of FS indicate “factory set on a per part

basis”.

Note 3: The LTC3884 contains additional commands not listed in this

table. Reading these commands is harmless to the operation of the IC;

however, the contents and meaning of these commands can change

without notice.

Note 6: The user should not assume compatibility of commands

between different parts based upon command names. Always refer to

the manufacturer’s data sheet for each part for a complete definition of a

command’s function.

ADI strives to keep command functionality compatible between all ADI

devices. Differences may occur to address specific product requirements.

3884fe

44

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND SUMMARY

*DATA FORMAT

L11 Linear_5s_11s

PMBus data field b[15:0]

N

Value = Y • 2

where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit

two’s complement integer

Example:

For b[15:0] = 0x9807 = ‘b10011_000_0000_0111

–13

–6

Value = 7 • 2 = 854 • 10

From “PMBus Spec Part II: Paragraph 7.1”

L16 Linear_16u

PMBus data field b[15:0]

N

Value = Y • 2

where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s

complement exponent that is hardwired to –12 decimal

Example:

For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000

–12

Value = 19456 • 2 = 4.75

From “PMBus Spec Part II: Paragraph 8.2”

Reg Register

PMBus data field b[15:0] or b[7:0].

Bit field meaning is defined in detailed PMBus Command Description.

I16 Integer Word

PMBus data field b[15:0]

Value = Y

where Y = b[15:0] is a 16 bit unsigned integer

Example:

For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111

Value = 38919 (decimal)

CF Custom Format

ASC ASCII Format

Value is defined in detailed PMBus Command Description.

This is often an unsigned or two’s complement integer scaled by an MFR specific

constant.

A variable length string of text characters conforming to ISO/IEC 8859-1 standard.

3884fe

45

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

The Typical Application on the back page is a common

LTC3884 application circuit. The LTC3884 is mainly

designed for low DCR application via PMBus command

thatcurrentlimit, anOCfaultwillbeissued. Eachrangein

Figure 26 affects the loop gain, and subsequently affects

the loop stability, so setting range of current limiting is

a part of loop design.

MFR_PWM_MODE[2] = 1 applicable when 0 ≤ V

≤

OUT

3.5V, but it can be also configured to be regular DCR or

regular resistor sensing by setting MFR_PWM_MODE[2]

ꢇꢆꢆ

8ꢆ

= 0 for 0≤ V

≤ 5.5V. The choice among them is largely

OUT

ꢍ

ꢗꢝꢒ

a design trade-off between cost, power consumption and

accuracy. DCR sensing is becoming popular because it

saves expensive current sensing resistors and is more

power efficient, especially in high current applications.

Low DCR provides the most power efficient solution, and

best signal-to-noise ratio of the input sensing voltage.

The accuracy of the current reading and current limit

are typically limited by the accuracy of the DCR resistor

(accounted for in the IOUT_CAL_GAIN parameter of the

LTC3884). Thus current sensing resistors provide the

most accurate current sensing and limiting for the ap-

plication. Other external component selection is driven

by the load requirement, and begins with the selection of

ꢒꢝ =

ꢈꢆ

4ꢆ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢉꢚꢛꢆ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢜꢚꢛꢇ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢉꢚꢛꢆ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢜꢚꢛꢆ

ꢉꢆ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢉꢚꢛꢇ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢜꢚꢛꢇ

ꢆ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢉꢚꢛꢇ

ꢎꢑꢒꢓꢔꢕꢎꢓꢎꢖꢗꢘꢙꢜꢚꢛꢆ

3ꢐꢐ4 ꢑꢉꢈ

ꢍ

ꢒꢝ =

ꢌ ꢞꢗꢝꢒ

ꢊꢉꢆ

ꢊ4ꢆ

ꢉ

3

ꢆ

ꢆꢋꢌ

ꢇ

ꢇꢋꢌ

ꢄꢀꢅ

ꢉꢋꢌ

ꢀ

ꢁꢂꢃ

Figure 26. V_ITHvs V_ILIMIT

The LTC3884 will account for the DCR of the inductor if

the device is configured for DCR sensing and automati-

cally updates the current limit as the inductor temperature

changes. The temperature coefficient of the DCR is stored

in the MFR_IOUT_TC register. The setting MFR_PWM_

MODE[2] = 1, MFR_PWM_MODE[7] = 0 allows for the use

of verylow DCR inductorsorsenseresistors. In thismode,

thepeakoutputcurrentisupto16.5mV/DCRandrepresents

the application the LTC3884 is mainly designed for. Keep

in mind this operation is on a cycle-by-cycle basis and is

only a function of the peak inductor current. The average

inductor current is monitored by the ADC converter and

can provide a warning if too much average output current

R

(if R

is used) and inductor value. Next, the

SENSE

power MOSFETs are selected. Then the input and output

capacitorsareselected.Tohaveastableloopperformance

and reliability, the loop compensation parameters such

as GM of error amplifier programmed by MFR_PWM_

COMP[7:5] and RTH by MFR_PWM_ COMP[4:0] together

with current limit value and Voltage range set by bit 1 of

MFR_ PWM_MODE have to be properly selected. All other

programmable parameters do not affect the loop gain, al-

lowing parameters to be modified without impacting the

transient response to load changes.

is detected. The overcurrent fault is detected when the I

TH

voltage hits the maximum value. The digital processor

within the LTC3884 provides the ability to either ignore

the fault, shut down and latch off or shut down and retry

indefinitely (hiccup). Refer to the overcurrent portion of

the Operation section for more details.

CURRENT LIMIT PROGRAMMING

Thecycle-by-cyclecurrentlimitthresholdvoltage,V

ILIMIT,

+

–

across the I

and I

pins is proportional to

SENSEn

V .TheV limitcanbeprogrammedfrom1.45Vto2.2V

ITH

using the PMBUS command IOUT_OC_FAULT_LIMIT.

See Figure 26. The LTC3884 has four ranges of cur-

rent limit programming. Properly setting the value of

MFR_PWM_MODE[2] and MFR_PWM_MODE[7], and

IOUT_OC_FAULT_LIMIT, see the section of the PMBus

commands,thedevicecanregulateoutputvoltagewiththe

peak current under the value of IOUT_OC_FAULT_LIMIT

in normal operation. In case of output current exceeding

±

I

AND I

PINS

SENSE0

SENSE1

+

–

The I

and I

pins are the inputs to the current

SENSE

comparator and the A/D. The common mode input volt-

age range of the current comparators is 0V to 5.5V and

0V to 3.5V in low DCR mode. Both the SENSE pins are

high impedance inputs with small input currents typically

3884fe

46

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

less than 1µA. The high impedance inputs to the current

comparators enable accurate DCR sensing. Do not float

these pins during normal operation.

where:

V

:Maximumsensevoltageacrosstheinduc-

SENSE(MAX)

tor DCR for a given I voltage

TH

Filter components connected to the I

traces should

SENSE

I

: Maximum load current

MAX

be placed close to the IC. The positive and negative traces

should be routed differentially and Kelvin connected to the

currentsenseelement;seeFigure27. Anon-Kelvinconnec-

tion or improper placement can add parasitic inductance

andcapacitancetothecurrentsenseelement,degradingthe

signal at the sense terminals and making the programmed

current limit perform poorly. In a PolyPhase system, poor

placement of the sensing element will result in sub-optimal

current sharing between power stages. If DCR sensing is

used(Figure28a), senseresistorR1shouldbeplacedclose

totheinductortopreventnoisefromcouplingintosensitive

∆I : Inductor ripple current

DCR: Inductor resistance

The RC sense filter time constant must be set by the fol-

L

lowing equations:

L

at MFR_PWM_MODE[2] = 1 for low DCR

RC =

5 • DCR

L

at MFR_PWM_MODE[2]=0 for normal DCR

RC =

DCR

During normal DCR sensing, the voltage ripple across C1 is

equal to the voltage ripple across the inductor DCR. During

low DCR sensing, the voltage ripple across C1 is equal to

the 5x the voltage ripple across the inductor DCR.

small-signalnodes.ThecapacitorC1shouldbeplacedclose

+

totheICpins.AnyimpedancedifferencebetweentheI

SENSE

–

andI

signalpathscanresultinlossofaccuracyinthe

SENSE

ꢀ

ꢁꢂ

current reading of the ADC. The current reading accuracy

ꢀ

ꢁꢂꢃꢀ

ꢁꢂ

ꢄꢄ

can be improved by matching the impedance of the two

ꢅꢆꢆꢇꢃ

ꢃꢈ

signal paths. To accomplish this add a series resistor R3

ꢁꢂꢊꢋꢄꢃꢆꢌ

ꢊꢄꢌ

–

between V

and I

equal to R1. A capacitor of 1µF

OUT

SENSE

ꢏ

ꢇꢉ

or greater should be placed in parallel with this resistor.

ꢀ

ꢆꢋꢃ

ꢏꢃꢄ3884

ꢃꢁ ꢄꢅꢆꢄꢅ ꢇꢈꢉꢃꢅꢊꢋ

ꢅꢈ

ꢆꢅꢌꢃ ꢃꢁ ꢃꢍꢅ ꢀꢁꢆꢃꢊꢁꢉꢉꢅꢊ

ꢄꢐ

ꢑꢒꢓꢔ

ꢈꢂꢊ

ꢌꢒ

ꢖ

ꢀ

ꢁ

ꢁꢂꢃ

ꢇꢕꢂꢇꢕ

ꢄꢒꢙ

ꢌ3

ꢈꢆꢎꢂꢀꢃꢁꢊ ꢁꢊ ꢊ

3884 ꢇꢏꢐ

ꢄꢅꢆꢄꢅ

ꢗ

ꢇꢕꢂꢇꢕ

ꢆꢍꢃꢁꢆꢂꢎꢏ

3884 ꢔꢐ8ꢘ

Figure 27. Sense Lines Placement with Inductor DCR

Figure 28a. Inductor DCR Current Sense Circuit (LTC3884)

Inductor DCR Sensing

V

IN

The DCR is the DC winding resistance of the inductor's

copper, which is often less than 1mΩ for high current

inductors. In high current and low output voltage applica-

tions, a conduction loss of a high DCR or a sense resistor

will cause a significant reduction in power efficiency. For a

specific output requirement, choose the inductor with the

DCR that satisfies the maximum desirable sense voltage,

and uses the relationship of the sense pin filters to output

inductor characteristics as depicted in the following:

INTV

V

CC

IN

SENSE RESISTOR

PLUS PARASITIC

INDUCTANCE

BOOST

TG

R

ESL

SW

S

V

OUT

LTC3884

BG

C • 2 ≤ ESL/R

F

RF

S

POLE-ZERO

GND

CANCELLATION

R

F

+

I

SENSE

C *

F

–

3884 F28b

SENSE

R

V_SENSE(MAX)

DCR=

*FILTER COMPONENTS

PLACED NEAR SENSE PINS

ΔI_L

I_MAX

+

2

Figure 28b. Resistor Current Sense Circuit (LTC3884)

3884fe

47

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

To ensure the load current will be delivered over the full

operating temperature range, the temperature coefficient

of DCR resistance, approximately 3900ppm/°C, should

be taken into consideration.

operation is obtained with a small ripple current, which

requires a large inductor.

A reasonable starting point is to choose a ripple current

that is about 40% of I . Note that the largest ripple

OUT(MAX)

Typically, C is selected in the range of 0.047µF to 0.47µF.

ThisforcesR1toaround2kΩ@MFR_PWM_MODE[2]=0,

400Ω@MFR_PWM_MODE[2]=1reducingerrorthatmight

current occurs at the highest input voltage. To guarantee

that the ripple current does not exceed a specified maxi-

mum, the inductor should be chosen according to:

have been caused by the I

pins’ 1µA current (R3

SENSE

V_OUTV – V

(

)

IN

OUT

and C2 are for reducing sensing error caused by input

current through R1).

L ≥

V •f •I_RIPPLE

IN

OSC

There will be some power loss in R that relates to the

duty cycle, and will be the most in continuous mode at

the maximum input voltage:

INDUCTOR CORE SELECTION

Once the inductor value is determined, the type of induc-

tor must be selected. Core loss is independent of core

size for a fixed inductor value, but it is very dependent on

inductance. As the inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses increase. Ferrite

designs have very low core loss and are preferred at high

switching frequencies, so design goals can concentrate

on copper loss and preventing saturation. Ferrite core

materials saturate hard, which means that the induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

V

_IN(MAX)– V_OUT•V

(

)

OUT

P

R =

_LOSS( )

R

Ensure that R1 has a power rating higher than this value.

However, DCR sensing eliminates the conduction loss of

senseresistor;itwillprovidebetterefficiencyatheavyloads.

To maintain a good signal-to-noise ratio for low current

sense signals, it is best to enable the LOW DCR sensing

network (MFR_PWM_MODE[2] = 1, RC = L/(5 • DCR)).

For a DCR sensing application, the ripple voltage will be

determined by the equation:

V_OUTV – V

IN

OUT

ΔV_SENSE

=

•

V

RC•f_OSC

IN

LOW VALUE RESISTOR CURRENT SENSING

Low DCR sensing can be used at ∆V

signals as low

SENSE

as 2mV.

A typical sensing circuit using a discrete resistor is shown

in Figure 28b. R

output current.

is chosen based on the required

SENSE

INDUCTOR VALUE CALCULATION

The current comparator has a maximum threshold

determined by the I setting. The input

common mode range of the current comparator is 0V to

5.5V. The current comparator threshold sets the peak of

the inductor current, yielding a maximum average output

Given the desired input and output voltages, the inductor

V

SENSE(MAX)

LIMIT

value and operating frequency, f , directly determine

OSC

the inductor peak-to-peak ripple current:

V_OUTV – V

(

)

IN

OUT

I_RIPPLE

=

current I

equal to the peak value less half the peak-

V •f_OSC•L

MAX

IN

to-peak ripple current ∆I . To calculate the sense resistor

L

value, use the equation:

Lower ripple current reduces core losses in the inductor,

ESR losses in the output capacitors, and output voltage

ripple. Thus, at a given frequency, the highest efficiency

V_SENSE(MAX)

R_SENSE

=

ΔI_L

I_MAX

+

2

3884fe

48

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

Due to possible PCB noise in the current sensing loop, the

check the sense resistor manufacturer’s data sheet for

information about parasitic inductance. In the absence of

data, measure the voltage drop directly across the sense

resistor to extract the magnitude of the ESL step and use

Equation1todeterminetheESL.However,donotoverfilter

the signal. Keep the RC time constant less than or equal to

the inductor time constant to maintain a sufficient ripple

AC current sensing ripple of ∆V

= ∆I • R

also

SENSE

L

SENSE

needs to be checked in the design to get a good signal-to-

noise ratio. In general, for a reasonably good PCB layout,

a 15mV minimum ∆V

voltage is recommended as a

SENSE

conservativenumbertostartwithforR

applications.

SENSE

For previous generation current mode controllers, the

maximum sense voltage was high enough (e.g., 75mV for

theLTC1628/LTC3728family)thatthevoltagedropacross

the parasitic inductance of the sense resistor represented

a relatively small error. In the newer and higher current

density solutions, the value of the sense resistor can be

less than 1mΩ and the peak sense voltage can be less than

20mV. Also, inductor ripple currents greater than 50%

with operation up to 750kHz are becoming more common.

Under these conditions, the voltage drop across the sense

resistor’s parasitic inductance is no longer negligible. A

typical sensing circuit using a discrete resistor is shown in

Figure 28b. In previous generations of controllers, a small

RC filter placed near the IC was commonly used to reduce

the effects of the capacitive and inductive noise coupled

in the sense traces on the PCB. A typical filter consists of

two series 100Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 200ns.

voltage on V

for optimal operation of the current

RSENSE

loop controller.

ꢇ

ꢈꢉꢊꢈꢉ

ꢋꢁꢌꢇꢄꢅꢆꢇ

3884 ꢍꢋꢎꢏ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

Figure 29a. Voltage Measured Directly Across R_SENSE

This same RC filter, with minor modifications, can be used

to extract the resistive component of the current sense

signalinthepresenceofparasiticinductance.Forexample,

Figure 29a illustrates the voltage waveform across a 2mΩ

resistor with a PCB footprint of 2010. The waveform is

the superposition of a purely resistive component and a

purely inductive component. It was measured using two

scope probes and waveform math to obtain a differential

measurement. Based on additional measurements of the

ꢇ

ꢈꢉꢊꢈꢉ

ꢋꢁꢌꢇꢄꢅꢆꢇ

3884 ꢍꢋꢎꢏ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

Figure 29b. Voltage Measured After the R_SENSEFilter

SLOPE COMPENSATION AND INDUCTOR PEAK

CURRENT

inductor ripple current and the on-time, t , and off-time,

ON

t

, ofthetopswitch, thevalueoftheparasiticinductance

was determined to be 0.5nH using the equation:

OFF

Slope compensation provides stability in constant-

frequency current-mode architectures by preventing

sub-harmonic oscillations at high duty cycles. This is ac-

complished internally by adding a compensation ramp to

the inductor current signal. The LTC3884 uses a patented

currentlimittechniquethatcounteractsthecompensating

ramp. This allows the maximum inductor peak current to

remain unaffected throughout all duty cycles.

V_ESL(STEP)

t_ON•t_OFF

t_ON+ t_OFF

ESL =

•

(1)

ΔI_L

If the RC time constant is chosen to be close to the para-

sitic inductance divided by the sense resistor (L/R), the

resultantwaveformlooksresistive,asshowninFigure 29b.

For applications using low maximum sense voltages,

3884fe

49

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

POWER MOSFET AND OPTIONAL SCHOTTKY DIODE

SELECTION

where δ is the temperature dependency of R

DR

at the MOSFET’s Miller threshold voltage. V

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

is

TH(MIN)

Two external power MOSFETs must be selected for each

controller in the LTC3884: one N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the bot-

tom (synchronous) switch. The peak-to-peak drive levels

the typical MOSFET minimum threshold voltage. Both

2

MOSFETs have I R losses while the topside N-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V < 20V

IN

are set by the INTV voltage. This voltage is typically 5.5V.

CC

the high current efficiency generally improves with larger

Consequently,logic-levelthresholdMOSFETsmustbeused

MOSFETs, while for V > 20V the transition losses rapidly

IN

in most applications. The only exception is if low input volt-

increasetothepointthattheuseofahigherR

device

DS(ON)

age is expected (V < 5V); then, sub-logic level threshold

IN

withlowerC

actuallyprovideshigherefficiency.The

MILLER

MOSFETs (V

< 3V) should be used. Pay close atten-

GS(TH)

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

tion to the BV

specification for the MOSFETs as well;

DSS

most of the logic-level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the on-

resistance, R , Miller capacitance, C , input

DS(ON) MILLER

The term (1 + d) is generally given for a MOSFET in the

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

form of a normalized R

vs Temperature curve, but

DS(ON)

C

MILLER

δ = 0.005/°C can be used as an approximation for low

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

voltage MOSFETs.

MILLER

along the horizontal axis while the curve is approximately

The optional Schottky diodes conduct during the dead

time between the conduction of the two power MOSFETs.

These prevent the body diodes of the bottom MOSFETs

from turning on, storing charge during the dead time and

requiringareverserecoveryperiodthatcouldcostasmuch

as 3% in efficiency at high V_IN. A 1A to 3A Schottky is

generally a good compromise for both regions of opera-

tion due to the relatively small average current. Larger

diodes result in additional transition losses due to their

larger junction capacitance.

flat divided by the specified change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

to the gate charge curve specified V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Main Switch Duty Cycle =

V

IN

V – V

IN

OUT

Synchronous Switch Duty Cycle =

V

IN

VARIABLE DELAY TIME, SOFT-START AND OUTPUT

VOLTAGE RAMPING

The MOSFET power dissipations at maximum output

current are given by:

The LTC3884 must enter the run state prior to soft-start.

The RUNn pin is released after the part initializes and V

V_OUT

2

IN

P_MAIN

=

I

(

1+δ •R

+

(

)

MAX

DS(ON)

V

isgreaterthantheVIN_ONthreshold.IfmultipleLTC3884s

are used in an application, they should be configured to

share the same RUNn pins. They all hold their respective

IN

I

2 ⎛

⎞

⎠

MAX

2

V

R

⎟

C

•

(

)

(

_DR)(

)

⎜

⎝

IN

MILLER

RUNn pins low until all devices initialize and V exceeds

IN

⎡

⎢

⎣

⎤

the VIN_ON threshold for all devices. The SHARE_CLK

pin assures all the devices connected to the signal use

the same time base.

1

+

•f

OSC

⎥

V

_INTVCC– V_TH(MIN)V_{TH(MIN) ⎥}

⎦

V – V

IN

OUT

P_SYNC

=

I

(

²• 1+δ •R

( )

MAX

DS(ON)

)

V

IN

3884fe

50

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

After the RUNn pin releases, the controller waits for the

user-specified turn-on delay (TON_DELAY) prior to ini-

tiating an output voltage ramp. Multiple LTC3884s and

other ADI parts can be configured to start with variable

delay times. To work correctly, all devices use the same

timing clock (SHARE_CLK) and all devices must share

the RUNn pin. This allows the relative delay of all parts

to be synchronized. The actual variation in the delay will

be dependent on the highest clock rate of the devices

connected to the SHARE_CLK pin (all Analog Devices ICs

are configured to allow the fastest SHARE_CLK signal to

control the timing of all devices). The SHARE_CLK signal

can be 10% in frequency, thus the actual time delays will

have proportional variance.

Themethodofstart-upsequencingdescribedaboveistime

based. For concatenated events it is possible to control

the RUNn pins based on the PGOODn pin of a different

controller. There is 60µs filtering to the PGOODn inside

the device. If unwanted transitions still occur on PGOODn,

place a capacitor to ground on the PGOODn pin to filter the

waveform. The RC time-constant of the filter should be set

sufficiently fast to assure no appreciable delay is incurred.

A value of 300μs to 500μs will provide some additional

filtering without significantly delaying the trigger event.

DIGITAL SERVO MODE

For maximum accuracy in the regulated output voltage,

enable the digital servo loop by asserting bit 6 of the

MFR_PWM_MODE command. In digital servo mode, the

LTC3884 will adjust the regulated output voltage based

on the ADC voltage reading. Every 90ms the digital servo

loop will step the LSB of the DAC (nominally 1.375mV or

0.688mV depending on the voltage range bit) until the

outputisatthecorrectADCreading.Atpower-upthismode

engagesafterTON_MAX_FAULT_LIMITunlessthelimitis

set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to

0 (infinite), the servo begins after TON_RISE is complete

Soft-startisperformedbyactivelyregulatingtheloadvolt-

age while digitally ramping the target voltage from 0.0V

to the commanded voltage set point. The rise time of the

voltage ramp can be programmed using the TON_RISE

commandtominimizeinrushcurrentsassociatedwiththe

start-up voltage ramp. The soft-start feature is disabled

by setting TON_RISE to any value less than 0.250ms.

The LTC3884 will perform the necessary math internally

to assure the voltage ramp is controlled to the desired

slope. However, the voltage slope cannot be any faster

thanthefundamentallimitsofthepowerstage.Theshorter

TON_RISE time is set, the larger the discrete steps in the

TON_RISE ramp will appear. The number of steps in the

ramp is equal to TON_RISE/0.1ms.

has exceeded the VOUT_UV_FAULT_LIMIT.

and V

OUT

This same point in time is when the output changes from

discontinuous to the programmed mode as indicated in

MFR_PWM_MODE bit 0. Refer to Figure 30 for details on

the V

waveform under time-based sequencing. If the

OUT

TON_MAX_FAULT_LIMIT is set to a value greater than 0

and the TON_MAX_FAULT_RESPONSE is set to ignore

0x00, the servo begins:

The LTC3884 PWM will always use discontinuous mode

during the TON_RISE operation. In discontinuous mode,

the bottom gate is turned off for LTC3884 or PWM is in

three-state for LTC3884-1 as soon as reverse current is

detected in the inductor. This will allow the regulator to

start up into a pre-biased load.

1. After the TON_RISE sequence is complete

2. AftertheTON_MAX_FAULT_LIMITtimeisreached;and

3. After the VOUT_UV_FAULT_LIMIT has been exceed or

the IOUT_OC_FAULT_LIMIT is no longer active.

There is no traditional tracking feature in the LTC3884.

However, two outputs can be given the same TON_RISE

and TON_DELAY times to effectively ramp up at the same

time. If the RUN pin is released at the same time and both

LTC3884s use the same time base, the outputs will track

very closely. If the circuit is in a PolyPhase configuration,

all timing parameters must be the same.

If the TON_MAX_FAULT_LIMIT is set to a value greater

than 0 and the TON_MAX_FAULT_RESPONSE is not set

to ignore 0X00, the servo begins:

1. After the TON_RISE sequence is complete;

3884fe

51

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

2. After the TON_MAX_FAULT_LIMIT time has expired

and both VOUT_UV_FAULT and IOUT_OC_FAULT are

not present.

VOUT will decay at the natural rate determined by the load

impedance. If the controller is in discontinuous mode, the

controller will not pull negative current and the output

will be pulled low by the load, not the power stage. The

maximum fall time is limited to 1.3 seconds. The shorter

TOFF_FALL time is set, the larger the discrete steps in the

TOFF_FALL ramp will appear. The number of steps in the

ramp is equal to TOFF_FALL/0.1ms.

The maximum rise time is limited to 1.3 seconds.

In a PolyPhase configuration it is recommended only one

of the control loops have the digital servo mode enabled.

Thiswillassurethevariousloopsdonotworkagainsteach

other due to slight differences in the reference circuits.

ꢀꢎꢇꢎꢆꢁꢅ ꢌꢈꢉꢃꢄ

ꢏꢄꢀꢈ ꢈꢋꢁꢗꢅꢈꢀ

ꢑꢎꢋꢁꢅ ꢄꢘꢆꢙꢘꢆ

ꢃꢄꢅꢆꢁꢇꢈ ꢉꢈꢁꢂꢚꢈꢀ

ꢆꢄꢋꢛꢏꢁꢜꢛꢑꢁꢘꢅꢆꢛꢅꢎꢏꢎꢆ

ꢌ

ꢁꢍꢀ

ꢆꢎꢏꢈ ꢀꢈꢅꢁꢐ ꢄꢑ

ꢒꢓꢓꢔ4ꢓꢓꢕꢖ

ꢀꢁꢂ ꢃꢄꢅꢆꢁꢇꢈ

ꢈꢉꢉꢄꢉ ꢊꢋꢄꢆ

ꢆꢄ ꢌꢂꢁꢅꢈꢍ

ꢃ

ꢄꢘꢆ

3884 ꢂ3ꢋ

ꢀꢉꢊꢇ

ꢀꢁꢂꢂꢃꢆꢇꢅꢄꢈ

ꢀꢁꢂꢂꢃꢂꢄꢅꢅ

Figure 31. TOFF_DELAY and TOFF_FALL

3884 ꢑ3ꢓ

ꢆꢎꢏꢈ

ꢆꢄꢋꢛꢉꢎꢌꢈ

ꢆꢄꢋꢛꢀꢈꢅꢁꢐ

INTV /EXTV POWER

Figure 30 . Timing Controlled V_OUTRise

CC

Power for the top and bottom MOSFET drivers and most

other internal circuitry are derived from the INTV pin.

SOFT OFF (SEQUENCED OFF)

CC

When the EXTV pin is shorted to GND or tied to a volt-

CC

In addition to a controlled start-up, the LTC3884 also sup-

portscontrolledturn-off.TheTOFF_DELAYandTOFF_FALL

functionsareshowninFigure31.TOFF_FALLisprocessed

when the RUN pin goes low or if the part is commanded

off. If the part faults off or FAULTn is pulled low externally

and the part is programmed to respond to this, the output

will three-state rather than exhibiting a controlled ramp.

The output will decay as a function of the load. The output

voltage will operate as shown in Figure 31 so long as the

part is in forced continuous mode and the TOFF_FALL

time is sufficiently slow that the power stage can achieve

the desired slope. The TOFF_FALL time can only be met if

the power stage and controller can sink sufficient current

to assure the output is at zero volts by the end of the fall

time interval. If the TOFF_FALL time is set shorter than

the time required to discharge the load capacitance, the

output will not reach the desired zero volt state. At the end

of TOFF_FALL, the controller will cease to sink current and

age less than 4.7V, or V is lower than 7V, an internal

IN

5.5V linear regulator supplies INTV power from V . If

CC

IN

EXTV is taken above 4.7V and V is higher than 7V,

CC

IN

the 5.5V regulator is turned off and an internal switch is

turned on connecting EXTV to INTV . EXTV can be

CC

appliedbeforeV .Theregulatorcansupplyapeakcurrent

IN

of 100mA. Both INTV and EXTV need to be bypassed

CC

to ground with a minimum of 1μF ceramic capacitor or

low ESR electrolytic capacitor. No matter what type of bulk

capacitor is used, an additional 0.1μF ceramic capacitor

placed directly adjacent to the INTV and GND pins is

CC

highly recommended. Good bypassing is needed to sup-

ply the high transient currents required by the MOSFET

gate drivers.

High input voltage application in which large MOSFETs

are being driven at high frequencies may cause the

maximum junction temperature rating for the LTC3884

3884fe

52

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

to be exceeded. The INTV current, of which a large

CC

V

percentage is due to the gate charge current, is supplied

IN

R

LTC3884

VIN

from either the V or EXTV pin. If the LTC3884 internal

IN

CC

1Ω

INTV

5V

CC

regulator is powered from the V pin, the power through

IN

+

C

PGND

INTVCC

C

IN

the IC is equal to V • I

. The gate charge current

IN

INTVCC

4.7µF

3884 F32

is dependent on operating frequency as discussed in the

EfficiencyConsiderationssection.Thejunctiontemperature

can be estimated by using the equations in Note 2 of the

Electrical Characteristics. For example, at 70°C ambient,

Figure 32. Setup for a 5V Input

V

IN

the LTC3884 INTV current is limited to less than 44mA

CC

1Ω TO 5Ω

C

BOOST

TG

from a 40V supply:

B

0.1µF

T = 70°C + 44mA • 40V • 31°C/W = 125°C

J

D

LTC3884

B

To prevent the maximum junction temperature from being

exceeded, theLTC3884internalLDOcanbepoweredfrom

SW

INTV

CC

C

INTVCC

4.7µF

the EXTV pin, providing significant system efficiency

BG

CC

improvement and thermal gains. If the EXTV pin is not

PGND

CC

3884 F33

used to power INTV , the EXTV pin must be tied to

CC

GND; do not float this pin. The V current resulting from

Figure 33. Boost Circuit to Minimize PWM Jitter

IN

the gate driver and control circuitry will be reduced to a

minimumbysupplyingtheINTV currentfromtheEXTV :

CC

TOPSIDE MOSFET DRIVER SUPPLY (C , D )

B

⎛

⎞

V_EXTVCC

⎛

1

⎞

Externalbootstrapcapacitors,C ,connectedtotheBOOSTn

B

⎜

⎟

⎜

⎟

⎝

⎠

V

Efficiency

⎝

⎠

pin supplies the gate drive voltages for the topside MOS-

IN

FETs.CapacitorC intheBlockDiagramischargedthrough

B

Tying the EXTV pin to a 5.5V supply reduces the junc-

CC

external diode D from INTV when the SWn pin is low.

CC

tion temperature in the previous example from 125°C to:

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate source of the

T = 70°C + 42mA • 5.5V • 31°C/W + 2mA • 40V • 31°C/W

B

J

desired MOSFET. This enhances the MOSFET and turns on

= 80°C

the topside switch. The switch node voltage, SWn, rises to

Do not tie INTV on the LTC3884 to an external supply

CC

V andtheBOOSTnpinfollows.WiththetopsideMOSFET

IN

because INTV will attempt to pull the external supply

CC

on, the boost voltage is above the input supply: V

=

BOOST

B

high and hit current limit, significantly increasing the die

V + V

IN

. The value of the boost capacitor, C , needs

INTVCC

temperature.

to be 100 times that of the total input capacitance of the

For applications where V is less than 6V, tie the V and

topsideMOSFET(s).Thereversebreakdownoftheexternal

IN

INTV pins together to the supply voltage through a 1Ω

Schottky diode must be greater than V

.

CC

IN(MAX)

or 2.2Ω resistor as shown in Figure 32. To minimize the

PWM jitter has been observed in some designs operating

at higher V /V ratios. This jitter does not substantially

affect the circuit accuracy. Referring to Figure 33, PWM

jitter can be removed by inserting a series resistor with a

value of 1Ω to 5Ω between the cathode of the diode and

the BOOSTn pin. A resistor case size of 0603 or larger is

recommended to reduce ESL and achieve the best results.

voltage drop caused by the gate charge current a low ESR

IN OUT

capacitor must be connected to the V /INTV pins. This

IN

CC

configuration will override the INTV linear regulator and

CC

will prevent INTV from dropping too low. Make sure the

CC

INTV voltage exceeds the R

test voltage for the

CC

DS(ON)

MOSFETs, which is typically 4.5V for logic level devices.

The UVLO on INTV is set to approximately 4V.

CC

3884fe

53

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

UNDERVOLTAGE LOCKOUT

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

The LTC3884 is initialized by an internal threshold-based

1/2

I_MAX

V

IN

UVLO where V must be approximately 4V and INTV ,

IN

DD25

CC

⎡

⎤

)

⎦

C_INRequiredI_RMS

≈

V

_OUT)(

V – V

IN

OUT

(

⎣

V

, and V

must be within approximately 20% of

DD33

their regulated values. In addition, V

must be within

DD33

This formula has a maximum at V = 2V , where

approximately 7% of the targeted value before the RUN

pin is released. After the part has initialized, an additional

IN

OUT

I

= I /2. This simple worst-case condition is com-

RMS

OUT

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturers’

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the capaci-

tor, or to choose a capacitor rated at a higher temperature

thanrequired.Severalcapacitorsmaybeparalleledtomeet

size or height requirements in the design. Due to the high

operating frequency of the LTC3884, ceramic capacitors

comparator monitors V . The VIN_ON threshold must be

IN

exceeded before the power sequencing can begin. When

V drops below the VIN_OFF threshold, the SHARE_CLK

IN

pin will be pulled low and V must increase above the

IN

VIN_ON threshold before the controller will restart. The

normalstart-upsequencewillbeallowedaftertheVIN_ON

threshold is crossed. If FAULTB is held low when V is

IN

applied, ALERT will be asserted low even if the part is

can also be used for C . Always consult the manufacturer

programmed to not assert ALERT when FAULTB is held

IN

2

if there is any question.

low. If I C communication occurs before the LTC3884 is

out of reset and only a portion of the command is seen by

the part, this can be interpreted as a CML fault. If a CML

fault is detected, ALERT is asserted low.

The benefit of using a LTC3884 in 2-phase operation can

be calculated by using the equation above for the higher

power controller and then calculating the loss that would

have resulted if both controller channels switched on at

the same time. The total RMS power loss is lower when

both controllers are operating due to the reduced overlap

of current pulses required through the input capacitor’s

ESR. This is why the input capacitor’s requirement cal-

culated above for the worst-case controller is adequate

for the dual controller design. Also, the input protection

fuse resistance, battery resistance, and PC board trace

resistance losses are also reduced due to the reduced

peak currents in a 2-phase system. The overall benefit of

a multiphase design will only be fully realized when the

source impedance of the power supply/battery is included

in the efficiency testing. The sources of the top MOSFETs

should be placed within 1cm of each other and share a

common C (s). Separating the sources and C may pro-

It is possible to program the contents of the NVM in the

application if the V

supply is externally driven directly

DD33

to V

or through EXTV . This will activate the digital

DD33

CC

portion of the LTC3884 without engaging the high volt-

age sections. PMBus communications are valid in this

supply configuration. If V has not been applied to the

IN

LTC3884, bit 3 (NVM Not Initialized) in MFR_COMMON

will be asserted low. If this condition is detected, the part

will only respond to addresses 5A and 5B. To initialize

the part issue the following set of commands: global ad-

dress 0x5B command 0xBD data 0x2B followed by global

address 5B command 0xBD and data 0xC4. The part will

now respond to the correct address. Configure the part as

desired then issue a STORE_USER_ALL. When V is ap-

IN

pliedaMFR_RESETcommandmustbeissuedtoallowthe

IN

duce undesirable voltage and current resonances at V .

PWM to be enabled and valid ADC conversions to be read.

IN

A small (0.1μF to 1μF) bypass capacitor between the chip

IN

C AND C

SELECTION

V pin and ground, placed close to the LTC3884, is also

IN

OUT

suggested. A 2.2Ω to 10Ω resistor placed between C

IN

Incontinuousmode,thesourcecurrentofthetopMOSFET

(C1) and the V pin provides further isolation between

IN

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

the two LTC3884s.

large voltage transients, a low ESR capacitor sized for the

3884fe

54

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

The selection of C

is driven by the effective series

OPEN-DRAIN PINS

OUT

resistance (ESR). Typically, once the ESR requirement

The LTC3884 has the following open-drain pins:

is satisfied, the capacitance is adequate for filtering. The

output ripple (∆V ) is approximated by:

3.3V Pins

OUT

1. FAULT

⎛

⎜

⎝

⎞

1

ΔV_OUT≈I_RIPPLEESR+

⎟

2. SYNC

8•f•C_OUT

⎠

3. SHARE_CLK

where f is the operating frequency, C

is the output

OUT

4. PGOODn

capacitance and I

is the ripple current in the induc-

RIPPLE

tor. The output ripple is highest at maximum input voltage

since I increases with input voltage.

5VPins(5Vpinsoperatecorrectlywhenpulledto3.3V.)

RIPPLE

1. RUNn

2. ALERT

3. SCL

FAULT INDICATION

The LTC3884 FAULT pins are configurable to indicate a

variety of faults including OV, UV, OC, OT, timing faults,

and peak over current faults. In addition, the FAULT pins

can be pulled low by external sources indicating a fault in

some other portion of the system. The fault response is

configurable and allows the following options:

4. SDA

All the above pins have on-chip pull-down transistors that

can sink 3mA at 0.4V. The low threshold on the pins is

0.8V; thus, there is plenty of margin on the digital signals

with 3mA of current. For 3.3V pins, 3mA of current is

a 1.1k resistor. Unless there are transient speed issues

associated with the RC time constant of the resistor pull-

up and parasitic capacitance to ground, a 10k resistor or

larger is generally recommended.

n

Ignore

n

Shut Down Immediately—Latch Off

n

ShutDownImmediately—RetryIndefinitelyattheTime

Interval Specified in MFR_RETRY_DELAY

For high speed signals such as the SDA, SCL and SYNC,

a lower value resistor may be required. The RC time con-

stant should be set to 1/3 to 1/5 the required rise time

to avoid timing issues. For a 100pF load and a 400kHz

PMBus communication rate, the rise time must be less

than 300ns. The resistor pull-up on the SDA and SCL pins

with the time constant set to 1/3 the rise time is:

Refer to the PMBus section of the data sheet and the

PMBus specification for more details.

The OV response is automatic. If an OV condition is de-

tected, TGn goes low and BGn is asserted.

Fault logging is available on the LTC3884. The fault log-

ging is configurable to automatically store data when a

fault occurs that causes the unit to fault off. The header

portion of the fault logging table contains peak values. It

is possible to read these values at any time. This data will

be useful while troubleshooting the fault.

t_RISE

3•100pF

R_PULLUP

=

=1k

The closest 1% resistor value is 1k. Be careful to minimize

parasitic capacitance on the SDA and SCL pins to avoid

communicationproblems. Toestimatetheloadingcapaci-

tance, monitor the signal in question and measure how

long it takes for the desired signal to reach approximately

63% of the output value. This is a one time constant. The

SYNC pin has an on-chip pull-down transistor with the

If the LTC3884 internal temperature is in excess of 85°C,

writes into the NVM (other than fault logging) are not

recommended. The data will still be held in RAM, unless

the 3.3V supply UVLO threshold is reached. If the die

temperature exceeds 130°C all NVM communication is

disabled until the die temperature drops below 120°C.

3884fe

55

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

output held low for nominally 500ns. If the internal oscil-

lator is set for 500kHz and the load is 100pF and a 3x time

constant is required, the resistor calculation is as follows:

fault can be cleared by writing a 1 to the bit. If the user

does not wish to see the ALERT pin assert if a PLL_FAULT

occurs, the SMBALERT_MASK command can be used to

prevent the alert.

2µs–500ns

3•100pF

R_PULLUP

=

= 5k

If the SYNC signal is not clocking in the application, the

nominal programmed frequency will control the internal

PWM circuitry. However, if multiple parts share the SYNC

pins and the signal is not clocking, the parts will not be

synchronized and excess voltage ripple on the output may

be present. Bit 10 of MFR_PADS will be asserted low if

this condition exists.

The closest 1% resistor is 4.99k.

If timing errors are occurring or if the SYNC frequency is

notasfastasdesired,monitorthewaveformanddetermine

if the RC time constant is too long for the application. If

possible reduce the parasitic capacitance. If not reduce

the pull-up resistor sufficiently to assure proper timing.

The SHARE_CLK pull-up resistor has a similar equation

with a period of 10µs and a pull-down time of 1μs. The

RC time constant should be approximately 3μs or faster.

If the TG/BG (LTC3884) or PWM (LTC3884-1) appear to

be running at too high a frequency, monitor the SYNC

pin. Extra transitions on the falling edge will result in the

PLL trying to lock on to noise versus the intended signal.

Review routing of digital control signals and minimize

crosstalktotheSYNCsignaltoavoidthisproblem.Multiple

LTC3884sarerequiredtoshareoneSYNCpininPolyPhase

configurations. For other configurations, connecting the

SYNC pins to form a single SYNC signal is optional. If the

SYNCpinissharedbetweenLTC3884s,onlyoneLTC3884

can be programmed with a frequency output. All the other

LTC3884s should be programmed to disable the SYNC

output. However their frequency should be programmed

to the nominal desired value.

PHASE-LOCKED LOOP AND FREQUENCY

SYNCHRONIZATION

The LTC3884 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. The PLL is locked to the falling edge of

the SYNC pin. The phase relationship between the PWM

controller and the falling edge of SYNC is controlled by

the lower 3 bits of the MFR_PWM_ CONFIG command.

For PolyPhase applications, it is recommended that all

the phases be spaced evenly. Thus for a 2-phase system

the signals should be 180° out of phase and a 4-phase

system should be spaced 90°.

MINIMUM ON-TIME CONSIDERATIONS

Minimum on-time, t

, is the smallest time duration

ON(MIN)

that the LTC3884 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn off the top MOSFET. Low duty

cycle applications may approach this minimum limit and

care should be taken to ensure that:

The phase detector is an edge-sensitive digital type that

provides a known phase shift between the external and

internal oscillators. This type of phase detector does not

exhibit false lock to harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the internal

filter network. The PLL lock range is guaranteed between

200kHzand1MHz.Nominalpartswillhavearangebeyond

this; however, operation to a wider frequency range is not

guaranteed.

V_OUT

t_ON(MIN)

<

V •f

IN

OSC

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The PLL has a lock detection circuit. If the PLL should lose

lockduringoperation,bit4oftheSTATUS_MFR_SPECIFIC

command is asserted and the ALERT pin is pulled low. The

3884fe

56

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

The minimum on-time for the LTC3884 is approximately

60ns.ReasonablygoodPCBlayout,minimum30%induc-

tor current ripple and at least 2mV for LOW DCR structure

or 10mV to 15mV for regular DCR ripple on the current

sensesignalarerequiredtoavoidincreasingtheminimum

on-time. The minimum on-time can be affected by PCB

switchingnoiseinthevoltageandcurrentloop.Asthepeak

current sense voltage decreases, the minimum on-time

gradually increases to 90ns. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-timelimitinthissituation, asignificantamountofcycle

skipping can occur with correspondingly larger current

and voltage ripple.

ꢀꢁꢂꢁ

ꢈꢀꢉ3884

ꢍꢂꢎ

ꢊꢆꢋꢌ

ꢃꢃꢄꢀ3ꢅꢆꢇ

ꢍꢂꢎ

3884 ꢌ34

Figure 34. External ∆V_BETemperature Sense

4ꢈꢉꢊꢋ

ꢀꢁꢂꢁ

ꢃꢀꢄ3884

ꢅꢆꢇ

ꢅꢌ3ꢉꢍ ꢋꢀ ꢎꢉꢏꢄ

ꢐꢂꢑ

3884 ꢇ3ꢉ

Figure 35. 2D+R Temperature Sense

EXTERNAL TEMPERATURE SENSE

dual diode network as shown in Figure 35. This second

measurement method is not generally as accurate as the

first, but it supports legacy power blocks or may prove

necessary if high noise environments prevent use of the

The LTC3884 is capable of measuring the power stage

temperature of each channel. Multiple methods using

silicon junction type remote sensors are supported. The

voltage produced by the remote sense circuit is digitized

by the internal ADC, and the computed temperature value

is returned by the paged READ_TEMPERATURE_1 telem-

etry command.

∆V approach with its lower signal levels.

BE

For either method, the slope of the external temperature

sensor can be modified with the coefficient stored in

MFR_TEMP_1_GAIN. With the ∆V approach, typical

BE

PNPs require temperature slope adjustments slightly

less than 1. The MMBT3906 has a recommended value

in this command of approximately MFR_TEMP_1_GAIN

= 0.991 based on the ideality factor of 1.01. Simply invert

the ideality factor to calculate the MFR_TEMP_1_GAIN.

Different manufacturers and different lots may have dif-

ferent ideality factors. Consult with the manufacturer to

set this value. Bench characterization over temperature is

recommended when adjusting MFR_TEMP_1_GAIN for

the direct p-n junction measurement.

The most accurate external temperature measurement

can be made using a diode-connected PNP transistor

such as the MMBT3906 as shown in Figure 34 with bit 5

of MFR_PWM_MODE should be set to 0 ∆V when using

BE

this sensor configuration. The transistor should be placed

in contact with or immediately adjacent to the power stage

inductor. ItsemittershouldbeconnectedtotheTSNSnpin

whilethebaseandcollectorterminalsofthePNPtransistor

should be returned to the LTC3884 GND paddle using a

Kevin connection. For best noise immunity, the connec-

tions should be routed differentially and a 10nF capacitor

should be placed in parallel with the diode-connected PNP.

Parasitic PCB trace inductance between the capacitor and

transistor should be minimized. Avoid placing PCB vias

between the transistor and capacitor.

Theoffsetoftheexternaltemperaturesensecanbeadjusted

by MFR_TEMP_1_OFFSET.

If an external temperature sense element is not used, the

TSNSn pinmustbeshortedtoGND.TheUT_FAULT_LIMIT

must be set to –275°C, and the UT_FAULT_RESPONSE

must be set to ignore. The user also needs to set the

IOUT_CAL_GAIN_TC to a value of 0.

The LTC3884 also supports direct junction voltage mea-

surements when bit 5 of MFR_PWM_MODE_LTC3884 is

set to 1. The factory defaults support a resistor trimmed

3884fe

57

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

To ensure proper use of these temperature adjustment

parameters, refer to the specific formulas given for the

two methods by the MFR_PWM_MODE command in the

later section covering PMBus command details.

transient input current. This will help prevent noise from

the top gate MOSFET from feeding into the input current

sense amplifier inputs and supply.

If the input current sense amplifier is not used, short the

+

–

V , I , and I pins together.

IN IN

IN

INPUT CURRENT SENSE AMPLIFIER

R

IINSNS

The LTC3884 input current sense amplifier can sense the

V

IN

supply current into the V pin using an external resis-

10µF

IN

tor as well as the power stage current using an external

sense resistor shown in Figure 36. Unless care is taken to

mitigate the frequency noise caused by the discontinuous

inputcurrent,significantinputcurrentmeasurementerror

may occur. The noise will be the greatest in high current

applications and at large step-down ratios. Careful layout

TG

M1

M2

LTC3884

I

-

IN

2Ω

+

SW

BG

IN

V

IN

10µF

3884 F36

and filtering at the V pin is recommended to minimize

IN

Figure 36. Low Noise Input Current Sense Circuit

measurement error. The V pin should be filtered with

IN

a resistor and a ceramic capacitor. The filter should be

EXTERNAL RESISTOR CONFIGURATION PINS

(RCONFIG)

located as close to the V pin as possible. The supply

IN

side of the V pin filter should be Kelvin connected to the

IN

supply side of the R

resistor. A 2Ω resistor should

IINSNS

The LTC3884 is factory programmed to use the external

resistor configuration. This allows output voltage, PWM

frequency, PWM phasing, and the PMBus address to be

set by the user without programming the part through the

PMBusinterfaceorpurchasingcustomprogrammedparts.

To use resistor programming, the RCONFIG pins require

be sufficient for most applications. The resistor will cause

an IR voltage drop from the supply to the V pin due to

IN

the current flowing into the V pin. To compensate for

IN

this voltage drop, the MFR_RVIN command value should

be set to the nominal resistor value. The LTC3884 will

multiplytheMFR_READ_ICHIPmeasurementvaluebythe

user defined MFR_RVIN value and add this voltage to the

a resistor divider between V

and GND. The RCONFIG

DD25

pins are only interrogated at initial power up and during a

reset, so modifying their values on the fly while the part

is powered will have no effect. However, this does mean

that RCONFIG pins on the same IC can be shared with a

single resistor divider if they require identical program-

ming. Resistors with a tolerance of 1% or better must be

used to assure proper operation. In the following tables,

measured voltage at the V pin. Therefore

IN

READ_VIN=V

+(MFR_READ_ICHIP•MFR_RVIN)

VIN_PIN

Therefore the READ_VIN command will return the value

of the voltage at the supply side of the V pin filter. If no

IN

V filter element is used, set MFR_RVIN = 0.

IN

R

is connected between V

and the RCONFIG pin

is connected between the pin and GND. Noisy

clock signals should not be routed near these pins.

The capacitor from the drain of M1 to ground should be

a low ESR ceramic capacitor. It should be placed as close

as possible to the drain of M1 to supply high frequency

TOP

while R

DD25

BOT

3884fe

58

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

Voltage Selection

Frequency Selection

When an output voltage is set using the VOUT_CFGn pins

(by Table 3) the following parameters are set as a percent-

age of the output voltage:

The PWM switching frequency is set according to Table 4.

The SYNC pins must be shared in PolyPhase configura-

tions where multiple LTC3884s or multiple LTC3884s and

LTC3874s are used to produce the output. If the configu-

ration is not PolyPhase the SYNC pins do not have to be

shared. If the SYNC pins are shared between LTC3884s

only one SYNC pin should be enabled; all other SYNC pins

n

VOUT_OV_FAULT_LIMIT....................................+10%

n

VOUT_OV_WARN_LIMIT...................................+7.5%

n

VOUT_MAX.......................................................+7.5%

n

VOUT_MARGIN_HIGH..........................................+5%

should be disabled. A pull-up resistor to V

on the SYNC pin.

is required

DD33

n

VOUT_MARGIN_LOW...........................................–5%

n

VOUT_UV_WARN_LIMIT..................................–6.5%

n

VOUT_UV_FAULT_LIMIT......................................–7%

Table 4. FREQ_CFG Resistor Programming

R

(kΩ)

R

(kΩ)

BOTTOM

FREQUENCY (kHz)

TOP

If V

is 2.5V or lower, low range is used. When V

is

OUT

0 or Open

10

Open

23.2

15.8

20.5

17.4

17.8

15

NVM

1000

750

set using the VOUT_CFGn pins, the part will turn on the

rail modifying the OPERATION command, if required, to

respond to PMBus commands.

10

16.2

20

Table 3. VOUT_CFGn Resistor Programming

R

(kΩ)

R

(kΩ)

V (V)

ON/OFF

NVM

ON

TOP

BOTTOM

OUT

0 or Open

10

Open

23.2

15.8

20.5

17.4

17.8

15

NVM

5.000

3.300

2.500

1.800

1.500

1.350

1.250

1.200

1.150

1.100

1.050

0.900

0.750

0.650

0.600

NVM

20

12.7

11

10

ON

20

16.2

20

ON

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

ON

650

ON

575

20

ON

500

20

12.7

11

ON

425

20

ON

350

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

ON

250

ON

External Clock

ON

OFF

3884fe

59

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

Phase Selection

Address Selection Using RCONFIG

The phase of the channels with respect to the falling edge

of SYNC is set using the values in Table 5.

TheLTC3884addressisselectedbasedontheprogramming

ofthetwoconfigurationpinsASEL0andASEL1accordingto

Table 6. ASEL0 programs the bottom four bits of the device

address for the LTC3884, and ASEL1 programs the three

most significant bits. Either portion of the address can also

be retrieved from the MFR_ADDRESS value in EEPROM. If

both pins are left open, the full 7-bit MFR_ADDRESS value

stored in EEPROM is used to determine the device address.

The LTC3884 always responds to 7-bit global addresses

0x5A and 0x5B. MFR_ADDRESS should not be set to either

of these values because these are global addresses and all

parts will respond to them.

Table 5. PHASE_CFG Resistor Programming

R

TOP

R

SYNC TO CH0 SYNC TO CH1

SYNC

BOTTOM

(kΩ)

0 or Open

10

(kΩ)

(DEGREES)

NVM

300

ENABLE

Open

23.2

15.8

20.5

17.4

17.8

15

NVM

120

60

NVM

10

16.2

20

240

120

0

240

20

120

DISABLE

Table 6. ASELn Resistor Programming

20

12.7

11

0

240

ASEL1

DEVICE ADDRESS DEVICE ADDRESS

BITS[6:4] BITS[3:0]

(kΩ) BINARY HEX BINARY HEX

EEPROM

1111

ASEL0

20

90

270

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

180

120

60

300

R

(kΩ)

R

BOTTOM

TOP

240

0 or Open

10

Open

120

0

240

23.2

15.8

20.5

17.4

17.8

15

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

10

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

120

ENABLE

16.2

20

0

240

EEPROM

90

270

0

180

20

Forexampleina4-phaseconfigurationclockedat500kHz,

all of the LTC3884s must be set to the desired frequency

and phase and only one LTC3884 should be set to the

desired frequency with the SYNC pin enabled. All phasing

is with respect to the falling edge of SYNC.

20

12.7

11

24.9

30.1

Open

11.3

9.09

7.32

5.76

4.32

3.57

1.96

0

111

7

6

5

4

3

2

1

0

110

101

100

011

010

001

000

For LTC3884 Chip 1, set the frequency to 500kHz with 90°

and 270° phase shift with the SYNC pin enabled:

Frequency R

Phase R

= 24.9kΩ and R

= 5.76kΩ

TOP

BOT

= 30.1kΩ and R

= 1.96kΩ

TOP

BOT

For LTC3884 Chip 2, set the frequency to 500kHz with

0°and 180° phase shift and the SYNC pin disabled:

Frequency 24.9kΩ and R

= 5.76kΩ

BOT

Phase R

= 24.9kΩ and R

= 11.3kΩ

TOP

BOT

3884fe

60

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

Table 6A¹. MFR_ADDRESS Command Examples

1. The V current is the DC supply current given in the

IN

Expressing Both 7- or 8-Bit Addressing

ElectricalCharacteristicstable,whichexcludesMOSFET

HEX DEVICE

driverandcontrolcurrents. V currenttypicallyresults

IN

ADDRESS

BIT BIT BIT BIT BIT BIT BIT BIT

in a small (<0.1%) loss.

DESCRIPTION 7 BIT 8 BIT

7

0

1

6

1

0

5

0

1

0

4

1

0

3

1

0

2

0

1

0

1

0

R/W

0

4

Rail

0x5A 0xB4

0x5B 0xB6

0x4F 0x9E

0x60 0xC0

0x61 0xC2

0

1

0

1

0

2. INTV current is the sum of the MOSFET driver and

CC

4

Global

0

controlcurrents(LTC3884).TheMOSFETdrivercurrent

resultsfromswitchingthegatecapacitanceofthepower

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

Default

0

Example 1

Example 2

0

2,3,5

Disabled

0

from INTV to ground. The resulting dQ/dt is a cur-

CC

Note 1: This table can be applied to the MFR_CHANNEL_ADDRESS,

and MFR_RAIL_ADDRESS commands as well as the MFR_ADDRESS

command.

rent out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

f(Q + Q ), where Q and Q are the gate charges of the

=

GATECHG

T

B

T

B

Note 2: A disabled value in one command does not disable the device, nor

does it disable the Global address.

topside and bottom side MOSFETs. For the LTC3884-1,

the gate driver is inside the DrMOS, which is powered

by some other supply. Similar power loss occurs with

that supply.

Note 3: A disabled value in one command does not inhibit the device from

responding to device addresses specified in other commands.

Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit),

or 0x5A or 0x5B(7 bit) to the MFR_ADDRESS, MFR_CHANNEL_

ADDRESS or the MFR_RAIL_ADDRESS commands.

2

3. I R losses are predicted from the DC resistances of

Note 5: To disable the address enter 0x80 in the MFR_ADDRESS

command. The 0x80 is greater than the 7-bit address field, disabling

the address.

the fuse (if used), MOSFET, inductor, and current sense

resistor.Incontinuousmode,theaverageoutputcurrent

flowsthroughtheinductorandR ,butis“chopped”

SENSE

between the topside MOSFET and the synchronous

MOSFET. If the two MOSFETs have approximately the

EFFICIENCY CONSIDERATIONS

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

same R

, then the resistance of one MOSFET can

DS(ON)

simply be summed with the resistances of the inductor

2

and R

DS(ON)

to obtain I R losses. For example, if each

SENSE

R

= 10mΩ, R = 10mΩ, R

= 5mΩ, then the

L

SENSE

total resistance is 25mΩ. This results in losses ranging

from 2% to 8% as the output current increases from

3A to 15A for a 5V output, or a 3% to 12% loss for a

3.3V output. Efficiency varies as the inverse square of

V

OUT

for the same external components and output

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

powerlevel. Thecombinedeffectsofincreasinglylower

output voltages and higher currents required by high

performance digital systems is not doubling but qua-

drupling the importance of loss terms in the switching

regulator system!

losses in LTC3884 circuits: 1) IC V current, 2) INTV

IN

CC

2

regulator current, 3) I R losses, 4) Topside MOSFET

transition losses.

3884fe

61

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

ꢂ

ꢁ

ꢀ

ꢃꢄꢅ

ꢍ

ꢎ

ꢅꢆ

2

ꢃ

ꢉꢊ

Transition Loss = (1.7) • V • I

• C

• f

IN

O(MAX)

RSS

ꢌ

ꢉꢊ

ꢉꢊꢃ

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

3884 ꢅ3ꢇ

ꢈ

ꢉꢊ

ꢈ

ꢉꢊꢋ

Figure 37. Programmable Loop Compensation

losses can be minimized by making sure that C has ad-

IN

equate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum

of 20μF to 40μF of capacitance having a maximum of

20mΩto50mΩofESR.TheLTC38842-phasearchitecture

typically halves this input capacitance requirement over

competingsolutions.OtherlossesincludingSchottkycon-

duction losses during dead time and inductor core losses

generally account for less than 2% total additional loss.

ꢎꢌꢏꢄ ꢀꢀ ꢂꢐꢑꢏꢄꢁꢆꢅꢎꢀꢐꢁ

ꢍꢅꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢄ ꢇ

ꢈ

ꢉꢃꢄꢊꢋꢄꢁꢂꢌ

PROGRAMMABLE LOOP COMPENSATION

3884 ꢉ38

The LTC3884 offers programmable loop compensation

to optimize the transient response without any hardware

Figure 38. Error Amp g_mAdjust

change. The error amplifier gain g varies from 1.0mmho

m

ꢇꢌꢏꢄ ꢀꢀ ꢂꢐꢑꢏꢄꢁꢆꢅꢇꢀꢐꢁ

to 5.73mmho, and the compensation resistor R varies

TH

ꢎꢅꢀꢁ

from0kΩto62kΩinsidethecontroller.Twocompensation

capacitors, C and C , are required in the design and

TH

THP

the typical ratio between C and C

is 10.

TH

THP

Byadjustingtheg andR only,theLTC3884canprovide

m

TH

a flexible type II compensation network to optimize the

ꢀꢁꢂꢃꢄꢅꢆꢄ ꢃ

loop over a wide range of output capacitors. Adjusting

ꢇꢈ

the g will change the gain of the compensation over the

m

whole frequency range without moving the pole and zero

ꢉꢃꢄꢊꢋꢄꢁꢂꢌ

3884 ꢉ3ꢍ

location, as shown in Figure 38.

Figure 39. R_THAdjust

Adjusting the R will change the pole and zero location,

TH

as shown in Figure 39. It is recommended that the user

determines the appropriate value for the g and R using

m

TH

the LTPowerCAD tool.

3884fe

62

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

CHECKING TRANSIENT RESPONSE

types and values determine the loop gain and phase. An

output current pulse of 20% to 80% of full-load current

having a rise time of 1μs to 10μs will produce output volt-

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

age and I pin waveforms that will give a sense of the

TH

overall loop stability without breaking the feedback loop.

PlacingapowerMOSFETwitharesistortogrounddirectly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

(ESR), where ESR is the effective

LOAD

series resistance of C . ∆I

also begins to charge or

OUT

LOAD

discharge C

generating the feedback error signal that

OUT

to a load step. The MOSFET + R

will produce output

SERIES

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recovery

currents approximately equal to V /R

. R

OUT SERIES

SERIES

OUT

valuesfrom0.1Ωto2Ωarevaliddependingonthecurrent

limit settings and the programmed output voltage. The

initial output voltage step resulting from the step change

in output current may not be within the bandwidth of the

feedback loop, so this signal cannot be used to determine

time V

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

availability of the I pin not only allows optimization of

TH

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phasemarginand/or dampingfactorcan be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

phase margin. This is why it is better to look at the I pin

TH

signal which is in the feedback loop and is the filtered and

compensated control loop response. The gain of the loop

will be increased by increasing R and the bandwidth

TH

of the loop will be increased by decreasing C . If R is

TH

increased by the same factor that C is decreased, the

TH

the rise time at the pin. The I

external capacitor shown

THR

zero frequency will be kept the same, thereby keeping the

phaseshiftthesameinthemostcriticalfrequencyrangeof

thefeedbackloop. Thegainoftheloopwillbeproportional

to the transconductance of the error amplifier which is

set using bits[7:5] of the MFR_PWM_COMP command.

The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance. A second, more

severe transient is caused by switching in loads with large

(>1μF) supply bypass capacitors. The discharged bypass

in the Typical Application circuit will provide an adequate

starting point for most applications. The programmable

parameters that affect loop gain are the voltage range,

bit[1] of the MFR_PWM_MODE command, the current

range, bit[2] and bit[7] of the MFR_PWM_MODE com-

mand, the g of the PWM channel amplifier bits [7:5] of

m

MFR_PWM_COMP, and the internal R compensation

TH

resistor, bits[4:0] of MFR_PWM_COMP. Be sure to es-

tablish these settings prior to compensation calculation.

The I series internal R external C filter sets the

capacitorsareeffectivelyputinparallelwithC , causing

TH

OUT

dominant pole-zero loop compensation. The internal R

a rapid drop in V . No regulator can alter its delivery of

TH

OUT

value can be modified (from 0Ω to 62kΩ) using bits[4:0]

currentquicklyenoughtopreventthissuddenstepchange

of the MFR_PWM_ COMP command. Adjust the value

in output voltage if the load switch resistance is low and

of R to optimize transient response once the final PCB

it is driven quickly. If the ratio of C

to C

is greater

TH

LOAD

OUT

layout is done and the particular C filter capacitor and

than1:50, theswitchrisetimeshouldbecontrolledsothat

the load rise time is limited to approximately 25 • C

TH

outputcapacitortypeandvaluehavebeendetermined.The

.

LOAD

output capacitors need to be selected because the various

Thus a 10μF capacitor would require a 250μs rise time,

limiting the charging current to about 200mA.

3884fe

63

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

PolyPhase Configuration

Master Slave Operation

WhenconfiguringaPolyPhaserailwithmultipleLTC3884s,

LTC3884(asMaster)canworkwithLTC3874(asslave)very

efficientlytodeliververylargeoutputcurrents.LTC3874is

a very small simple device, which has two current loops,

but no PMBus, and no voltage loops.

the user must share the SYNC, I , I , SHARE_CLK,

TH THR

FAULT, and ALERT pins of these parts. Be sure to use pull-

up resistors on FAULT, SHARE_CLK and ALERT. One of

the part’s SYNC pins must be set to the desired switching

frequency,andallotherFREQUENCY_SWITCHcommands

must be set to External Clock. If an external oscillator is

provided, set the FREQUENCY_SWITCH command to

External Clock for all parts. The relative phasing of all

the channels should be spaced equally. The MFR_RAIL_

ADDRESSofallthedevicesshouldbesettothesamevalue.

Both LTC3884 and LTC3874 devices are mainly designed

for low DCR applications, and with the same relationship

between V vs V

(see Figure 40).

ITH

ISENSE

Figure 40 is the schematic of a 3+1 application using a

LTC3884 and a LTC3874. LTC3884 channel 0 provides

V

of 1.5V and 30A output current, and channel 1

OUT0

together with channel 0 and channel 1 in the LTC3874

to provide V of 1.0V, with 90A output current. Both

WhenconnectingaPolyPhaserailwithLTC3884s,connect

OUT1

the V pins of the LTC3884s directly back to the supply

IN

chips are programmed to be LOW DCR configuration, and

channel1 of LTC3884 and channel 0/1 of the LTC3874 are

programmed to have the same current limit. Connecting

voltage through the V pin filter networks.

IN

I

of LTC3884 with I

and I

of LTC3874 together

TH1

TH0

TH1

forms three current loops. The voltage loop inside the

LTC3884 regulates I , which then regulates all three

TH1

current loops with the same gain and current limit, and

ultimately delivers the same amount of current per phase.

Programming the phase of each channel properly, these

three channels form a perfect PolyPhase configuration.

3884fe

64

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

3884fe

65

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

ꢑ

ꢉꢉꢅꢈꢅꢈ

ꢍ

ꢉꢅ

ꢊ

ꢌ

ꢉ

ꢉꢅ

ꢉ

ꢉꢅ

ꢁꢈꢅꢈ

ꢘꢗ

ꢀꢁꢂ3884

ꢌ

ꢀ

ꢑ

ꢈꢋꢅꢈꢋ

ꢉ

ꢈꢋꢅꢈꢋ

ꢍ

ꢖꢒꢁ

ꢁꢄ

ꢂꢗ

ꢑ

ꢍꢉꢅ

ꢊ

ꢈꢋꢅꢈꢋ

ꢈꢔ

ꢍ

ꢉꢅ

ꢂ

ꢕ

ꢂ

ꢕꢖꢖꢈꢁ

ꢕꢄ

ꢈꢓꢅꢂ

ꢙꢗ

ꢙꢎ

ꢍꢉꢅ

ꢆꢗ

ꢑꢒꢅ

ꢍ

ꢗꢚꢛ

ꢂꢋꢑꢜꢙꢉꢂ

ꢌ

ꢈꢋꢅꢈꢋ

ꢊ

ꢉ

ꢁꢐꢑ

ꢉ

ꢉꢅꢁꢍ

ꢂꢂ

ꢂ

ꢁꢐ

ꢌ

ꢖꢒꢁ

ꢌ

ꢂ

ꢉꢅ

ꢍ

ꢆꢆ33

ꢆꢆꢎꢏ

ꢂ

ꢉꢅꢁꢍꢂꢂ

ꢃꢄꢅꢆꢇꢈꢄꢅꢆ

3884 ꢛ4ꢝꢞ

Figure 41a. Recommended Printed Circuit Layout Diagram, Single Phase Shown

ꢄꢅꢂ

ꢁꢂ

ꢀ

ꢄꢆꢇꢄꢆꢂ

ꢈ

ꢉꢊꢋꢂ

ꢃꢂ

ꢌ

ꢉꢊꢋꢂ

ꢀ

ꢁꢂ

ꢈ

ꢍꢇ

ꢀ

ꢍꢇ

ꢌ

ꢍꢇ

ꢄꢅꢎ

ꢁꢎ

ꢀ

ꢄꢆꢇꢄꢆꢎ

ꢈ

ꢉꢊꢋꢎ

ꢃꢎ

ꢌ

ꢉꢊꢋꢎ

ꢀ

ꢁꢎ

ꢏꢉꢁꢃ ꢁꢍꢇꢆꢄ ꢍꢇꢃꢍꢌꢐꢋꢆ

ꢑꢍꢒꢑ ꢄꢅꢍꢋꢌꢑꢍꢇꢒ

ꢌꢊꢀꢀꢆꢇꢋꢓ ꢔꢆꢆꢕ ꢁꢍꢇꢆꢄ

ꢋꢉ ꢐ ꢖꢍꢇꢍꢖꢊꢖ ꢁꢆꢇꢒꢋꢑꢓ

3884 ꢗ4ꢎꢘ

Figure 41b. Branch Current Waveforms

3884fe

66

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

PC BOARD LAYOUT CHECKLIST

PC BOARD LAYOUT DEBUGGING

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 41a. Figure 41b illustrates the

current waveforms present in the various branches of a

synchronous regulator operating in continuous mode.

Check the following in your layout:

It is helpful to use a DC-50MHz current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SWn pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

output voltage as well. Check for proper performance

over the operating voltage and current range expected

in the application. The frequency of operation should be

maintained over the input voltage range down to dropout

and until the output load drops below the low current

operation threshold.

1. Is the top N-channel MOSFET, M1, located within 1cm

of C ?

IN

2. Aresignalgroundandpowergroundkeptseparate?The

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

ground return of C

OUT

must return to the combined

INTVCC

C

(–) terminals.

3. The I trace should be as short as possible.

TH

4. The loop formed by the top N-channel MOSFET,

Schottky diode and the C capacitor should have

IN

short leads and PC trace lengths.

5. Theoutputcapacitor(–)terminalsshouldbeconnected

as close as possible to the (–) terminals of the input

capacitor by placing the capacitors next to each other

and away from the Schottky loop described in item 4.

Reduce V from its nominal level to verify operation

IN

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

+

–

6. Are the I

and I

leads routed together

SENSE

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOSTn, SWn,

TGn, and possibly BGn connections and the sensitive volt-

age and current pins. The capacitor placed across the cur-

rentsensingpinsneedstobeplacedimmediatelyadjacent

to the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

with minimum PC trace spacing? The filter capacitor

+

–

between I

and I

should be as close as

SENSE

possibletotheIC.Ensureaccuratecurrentsensingwith

Kelvin connections at the sense resistor or inductor,

whichever is used for current sensing.

7. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins?ThiscapacitorcarriestheMOSFETdrivercurrent

peaks. An additional 1µF ceramic capacitor placed

immediately next to the INTV and GND pins can

CC

help improve noise performance substantially.

for inductive coupling between C , Schottky and the top

IN

8. Keep the switching nodes (SWn), top gate nodes

(TGn),andboostnodes(BOOSTn)awayfromsensitive

small-signal nodes, especially from the voltage and

current sensing feedback pins. All of these nodes

have very large and fast moving signals and therefore

should be kept on the “output side” of the LTC3884

and occupy minimum PC trace area. If DCR sensing

is used, place the top resistor (Figure 25a, R1) close

to the switching node.

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

GND pin of the IC.

3884fe

67

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

DESIGN EXAMPLE

⎡

⎤

V_OUT

f•L

V_OUT

ΔI_L(NOM)

=

1–

⎢

⎥

As a design example for a 2-channel medium current

V

⎢

⎣

IN(NOM) ⎥

⎦

regulator,assumeV =12Vnominal,V =20Vmaximum,

IN

V

OUT0

= 3.3V, V

= 1.5V, I = 30A and f = 500kHz.

OUT1

MAX0,1

Channel 0 will have 8.1A (27%) ripple, and channel 1 will

have 8.4A (28%) ripple. The peak inductor current will be

the maximum DC value plus one-half the ripple current or

34A for channel 0 and 34.2A for channel 1. The minimum

on time occurs on channel 1 at the maximum V , and

should not be less than 60ns:

The regulated output is established by the VOUT_

COMMAND stored in NVM or placing the following resis-

tor divider between V

the RCONFIG pin and SGND:

DD25

IN

1. V

2. V

, R

= 10k, R

= 20k, R

= 15.8k

= 17.8k

OUT0_CFG TOP

BOTTOM

, R

OUT1_CFG TOP

V_OUT

1.5V

t_ON(MIN)

=

=150ns

The frequency and phase are set by NVM or by setting

the resistor divider between V FREQ_CFG and SGND

V

_IN(MAX)•f 20V •500kHz

DD25

and V

PHASE_CFG and SGND.

DD25

The next design focuses on only Channel1.

Frequency R

= 24.9kΩ and R

= 5.76kΩ

TOP

BOTTOM

TheWürth7443010330.33μH(0.32mΩDCRTYPat25°C)

is used for channel 1. So IOUT_CAL_GAIN = 0.32mΩ.

Phase R

= open and R

= 0Ω

TOP

BOTTOM

Based on the output current and inductor value, it is con-

sideredtobeaperfectexampleoflowDCRapplication.Set:

TheaddressissettoXFwhereXistheMSBstoredinNVM.

The following parameters are set as a percentage of the

output voltage if the resistor configuration pins are used

to determined output voltage:

MFR_PWM_MODE[2] = 1

then choose C = 220nF, R1 = L/(DCR • C • 5) = 937Ω

Choose R1 = 931Ω.

n

VOUT_OV_FAULT_LIMIT.....................................+10%

n

VOUT_OV_WARN_LIMIT...................................+7.5%

The maximum power loss in R1 is related to the duty

cycle, and will occur in continuous mode at the maximum

input voltage:

n

VOUT_MAX.......................................................+7.5%

n

VOUT_MARGIN_HIGH..........................................+5%

n

VOUT_MARGIN_LOW...........................................–5%

n

VOUT_UV_WARN_LIMIT...................................–6.5%

V

_IN(MAX)– V_OUT•V

(

)

OUT

n

VOUT_UV_FAULT_LIMIT.......................................–7%

P

=

LOSSR1

R1

All other user defined parameters must be programmed

into the NVM. The GUI can be utilized to quickly set up

the part with the desired operating parameters.

20−1.5 •1.5

(

)

=

= 29.8mW

931

The current limit will be set 20% higher than the peak

value to assure variation in components and noise in the

system do not limit the average current.

The inductance values are based on a 28% maximum

ripple current assumption (8.4A). The highest value of

ripple current occurs at the maximum input voltage:

V

= I

• R

= (1 + 20%) • 34.2A • 0.32mΩ

DCR(MAX)

ILIMIT PEAK

⎡

⎢

⎣

⎤

V_OUT

f•ΔI_{L(MAX) ⎢}

V_OUT

= 13.1mV

L =

1–

⎥

V

IN(MAX) ⎥

⎦

Based on Figure 26, set MFR_PWM_MODE[2], [7] = 1,0

and IOUT_CAL_GAIN = 0.32mΩ in GUI, and enter the

valuewithIOUT_OC_FAULT_LIMIT=41.04A,theLTC3884

will automatically set the current limit to 40.64A, based

on the IOUT_FAULT_LIMIT table, (see PMBus command

Channel 0 will require 0.68μH and channel 1 will require

0.33μH.respectively.Atthenominalinputtheripplewillbe:

for details).

3884fe

68

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

The power dissipation on the topside MOSFET can be eas-

Tie SHARE_CLK high with a 4.99k resistor to V

and

DD33

ily estimated. Choose a INFINEON BSC050NE2LS topside

sharebetweenallADIPSMpartsintheapplication.Besurea

uniqueaddressforeachchipcanbedecodedwiththeASEL0

and ASEL1 pins. Refer to Table 6. For maximum flexibility,

MOSFET. R

= 7.1mΩ, C

= 35pF. At maximum

DS(ON)

MILLER

input voltage with T estimated = 75°C and a bottom side

MOSFET a INFINEON BSC010NE2LSI, R = 1.1mΩ:

allow board space for R and R for any parameter

DS(ON)

TOP

BOTTOM

that is set with resistors such as ASEL0 and ASEL1.

1.5V

20V

2

P_MAIN

=

• 30A •⎡1+ 0.005 75°C–25°C ⎤

( ) ( )

( )

⎣ ⎦

2

CONNECTING THE USB TO I C/SMBus/PMBus

2

•0.0071Ω+ 20V 30A /2 2Ω

) ( )(

(

)

CONTROLLER TO THE LTC3884 IN SYSTEM

2

1

⎛

⎞

The ADI USB-to-I C/SMBus/PMBus adapter (DC1613A or

+

35pF 500kHz = 751mW

)(

(

)

⎜

⎝

⎟

⎠

5.5–2.8 2.8

equivalent) can be interfaced to the LTC3884 on the user’s

board for programming, telemetry and system debug.

The adapter, when used in conjunction with LTpowerPlay,

provides a powerful way to debug an entire power sys-

tem. Faults are quickly diagnosed using telemetry, fault

status commands and the fault log. The final configura-

tion can be quickly developed and stored to the LTC3884

EEPROM. Figure 42 illustrates the application schematic

for powering, programming and communication with one

ormoreLTC3884sviatheADII C/SMBus/PMBusadapter

regardless of whether or not system power is present. If

system power is not present the dongle will power the

LTC3884 through the V

part when V is not applied and the V

The loss in the bottom side MOSFET is:

20V –1.5V

2

P_SYNC

=

• 30A •

( )

20V

ꢀ

ꢂ

1+ 0.005 75°Cº−25°C •0.001Ω

(

)

(

)

ꢃ

ꢁ

=11.04W

2

Both MOSFETS have I R losses while the PMAIN equation

includes an additional term for transition losses, which

are highest at high input voltages. C is chosen for an

RMS current rating of:

2

IN

supply pin. To initialize the

DD33

1/2

C Required I

= 34.2/12 • (3.3 • (12– 3.3)) = 15A

pin is powered

IN

RMS

IN

DD33

use global address 0x5B command 0xBD data 0x2B fol-

lowed by address 0x5B command 0xBD data 0xC4.The

LTC3884 can now communicate with, and the project file

can be updated. To write the updated project file to the

C

is chosen with an ESR of 0.006Ω for low output

OUT

ripple.Theoutputrippleincontinuousmodewillbehighest

at the maximum input voltage. The output voltage ripple

due to ESR is:

NVM issue a STORE_USER _ALL command. When V is

IN

V

= R • (∆I ) = 0.006Ω • 8.1 ≈ 48.6mV

ESR L

ORIPPLE

applied, a MFR_RESET must be issued to allow the PWM

to be enabled and valid ADCs to be read.

ADDITIONAL DESIGN CHECKS

Becauseoftheadapter’slimitedcurrentsourcingcapability,

only the LTC3884s, their associated pull-up resistors and

Tie FAULT0 and FAULT1 together and pull up to V

with

DD33

2

theI Cpull-upresistorsshouldbepoweredfromtheORed

a 10k resistor. Tie RUN0 and RUN1 together and pull up

2

3.3V supply. In addition any device sharing the I C bus

to V

with a 10k resistor.

DD33

connectionswiththeLTC3884shouldnothavebodydiodes

If there are other ADI PSM parts, connect the RUN pins

between the SDA/SCL pins and their respective V node

DD

betweenchipsandconnecttheFAULTpinsbetweenchips.

because this will interfere with bus communication in the

Be sure all PMBus pins have resistor pull-up to V

DD33

absence of system power. If V is applied, the DC1613A

IN

and connect these inputs across all ADI PSM parts in the

will not supply the power to the LTC3884s on the board. It

is recommended the RUNn pins be held low or no voltage

configuration resistors inserted to avoid providing power

to the load until the part is fully configured.

application.

3884fe

69

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

ꢀ

ꢁꢂ

ꢚꢏꢗ

ꢈꢓꢓꢙ

ꢗꢎꢂꢏꢘꢎꢚꢚꢑꢘ

ꢀ

ꢁꢂ

ꢐꢑꢇꢃꢑꢘ

ꢁꢆꢎꢚꢇꢏꢑꢃ

3ꢛ3ꢀ

ꢀ

ꢃꢃ33

ꢃꢃꢄꢅ

ꢏꢒꢓꢈꢓꢈꢔ

ꢆꢃꢇ

ꢆꢗꢚ

ꢈꢉꢊ

ꢚꢏꢗ3884

ꢈꢓꢙ

ꢆꢃꢇ

ꢆꢗꢚ

ꢡꢒ ꢒꢋꢂꢃꢞꢆꢋꢂꢃ

ꢏꢎ ꢚꢏꢗ ꢃꢗꢈꢖꢈ3

ꢄ

ꢜꢆꢝ ꢏꢎ ꢁ ꢗꢞꢆꢌꢝꢟꢠꢞꢒꢌꢝꢟꢠ

ꢗꢎꢂꢏꢘꢎꢚꢚꢑꢘ

ꢀ

ꢁꢂ

ꢀ

ꢃꢃꢄꢅ

ꢃꢃ33

ꢏꢒꢓꢈꢓꢈꢔ

ꢈꢉꢊ

ꢚꢏꢗ3884

ꢆꢃꢇ

ꢆꢗꢚ

ꢀꢋꢆ ꢌꢇꢍ ꢎꢂ ꢏꢐꢑ ꢏꢒꢓꢈꢓꢈꢔ ꢁꢆ 8ꢀ ꢁꢊ ꢀ ꢕ ꢈꢖꢀ

ꢁꢂ

ꢡꢒ ꢒꢋꢂꢃꢞꢆꢋꢂꢃ

ꢗꢐꢇꢂꢋꢑ ꢏꢐꢑ ꢘꢑꢆꢁꢆꢏꢎꢘ ꢃꢁꢀꢁꢃꢑꢘ ꢎꢂ ꢏꢐꢑ ꢒꢊꢑꢏ ꢋꢇꢏꢑ

3884 ꢊ4ꢈ

Figure 42. Controller Connection

TheLTC3884isfullyisolatedfromthehostPC’sgroundby

the DC1613A.The 3.3V from the adapter and the LTC3884

DD33

during board bring-up to program or tweak the power

system or to diagnose power issues when bring up rails.

2

V

pin must be driven to each LTC3884 with a separate

LTpowerPlayutilizesAnalogDevices’sUSB-to-I C/SMBus/

PFET. If both V and EXTV are not applied, the V

PMBus adapter to communication with one of the many

potential targets including the DC2165A demo board, the

DC2298A socketed programming board, or a customer

target system. The software also provides an automatic

update feature to keep the revisions current with the latest

set of device drivers and documentation.

IN

CC

DD33

pins can be in parallel because the on-chip LDO is off. The

controller 3.3V current limit is 100mA but typical V

DD33

currents are under 15mA. The V

does back drive the

DD33

INTV /EXTV pin. Normally this is not an issue if V

CC

IN

is open.

A great deal of context sensitive help is available with

LTpower Play along with several tutorial demos. Complete

information is available at:

LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL

POWER

LTpowerPlay (Figure 43) is a powerful Windows-based

development environment that supports Analog De-

vices digital power system management ICs including

the LTC3884. The software supports a variety of differ-

ent tasks. LTpowerPlay can be used to evaluate Analog

Devices ICs by connecting to a demo board or the user

application. LTpowerPlay can also be used in an offline

mode(withnohardwarepresent)inordertobuildmultiple

IC configuration files that can be saved and reloaded at a

latertime.LTpowerPlayprovidesunprecedenteddiagnostic

and debug features. It becomes a valuable diagnostic tool

http://www.linear.com/ltpowerplay

PMBus COMMUNICATION AND COMMAND

PROCESSING

The LTC3884 has a one deep buffer to hold the last data

written for each supported command prior to processing

as shown in Figure 44, Write Command Data Processing.

When the part receives a new command from the bus,

it copies the data into the Write Command Data Buffer,

indicates to the internal processor that this command

3884fe

70

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

Figure 43. LTpowerPlay Screen Shot

processing (fetch, convert, and execute) to ensure the

last data written to any command is never lost. Com-

mand data buffering handles incoming PMBus writes by

storing the command data to the Write Command Data

Buffer and marking these commands for future process-

ing. The internal processor runs in parallel and handles

the sometimes slower task of fetching, converting and

executing commands marked for processing. Some

computationallyintensivecommands(e.g.,timingparam-

eters, temperatures, voltages and currents) have internal

processor execution times that may be long relative to

PMBus timing. If the part is busy processing a command,

and new command(s) arrive, execution may be delayed

or processed in a different order than received. The part

indicateswheninternalcalculationsareinprocessviabit5

ꢂꢅꢀ

ꢍꢄꢆꢈꢁ ꢂꢃꢅꢅꢉꢇꢀ

ꢀꢉꢈꢉ ꢎꢏꢐꢐꢁꢄ

ꢋꢅꢎꢘꢙ

ꢍꢄꢆꢈꢁ

ꢀꢁꢂꢃꢀꢁꢄ

ꢆꢇꢈꢁꢄꢇꢉꢊ

ꢋꢉꢑꢁ

•

ꢒꢓꢒꢒ

ꢒꢓꢔꢕ

ꢋꢄꢃꢂꢁꢌꢌꢃꢄ

ꢂꢅꢀꢌ

ꢐꢁꢈꢂꢚꢛ

ꢂꢃꢇꢗꢁꢄꢈ

ꢀꢉꢈꢉ

ꢉꢇꢀ

ꢁꢜꢁꢂꢏꢈꢁ

ꢀꢉꢈꢉ

ꢅꢏꢜ

ꢗꢃꢏꢈꢖꢂꢃꢅꢅꢉꢇꢀ

•

ꢅꢐꢄꢖꢄꢁꢌꢁꢈ

ꢓꢕ

ꢒꢓꢐꢀ

ꢌ

ꢄ

ꢂꢉꢊꢂꢏꢊꢉꢈꢆꢃꢇꢌ

ꢋꢁꢇꢀꢆꢇꢑ

3884 ꢐ43

Figure 44. Write Command Data Processing

data needs to be fetched, and converts the command to

its internal format so that it can be executed. Two distinct

parallelblocksmanagecommandbufferingandcommand

3884fe

71

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

APPLICATIONS INFORMATION

of MFR_COMMON (‘calculations not pending’). When the

part is busy calculating, bit 5 is cleared. When this bit is

set, the part is ready for another command. An example

polling loop is provided in Figure 45 which ensures that

commands are processed in order while simplifying error

handling routines.

power off/on, moving to a new output voltage set point,

etc.) it will clear bit 4 of MFR_COMMON (‘output not in

transition’). When internal calculations are in process, the

part will clear bit 5 of MFR_COMMON (‘calculations not

pending’). These three status bits can be polled with a

PMBus read byte of the MFR_COMMON register until all

three bits are set. A command immediately following the

status bits being set will be accepted without NACKing or

generating a BUSY fault/ALERT notification. The part can

NACK commands for other reasons, however, as required

by the PMBus spec (for instance, an invalid command or

data). An example of a robust command write algorithm

fortheVOUT_COMMANDregisterisprovidedinFigure45.

When the part receives a new command while it is busy,

it will communicate this condition using standard PMBus

protocol. Depending on part configuration it may either

NACK the command or return all ones (0xFF) for reads. It

may also generate a BUSY fault and ALERT notification,

or stretch the SCL clock low. For more information refer

to PMBus Specification v1.1, Part II, Section 10.8.7 and

SMBusv2.0section4.3.3.Clockstretchingcanbeenabled

by asserting bit 1 of MFR_CONFIG_ ALL. Clock stretch-

ing will only occur if enabled and the bus communication

speed exceeds 100kHz.

It is recommended that all command writes (write byte,

write word, etc.) be preceded with a polling loop to avoid

the extra complexity of dealing with busy behavior and

unwantedALERTnotification. Asimplewaytoachievethis

is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_

WORD()subroutine.Theabovepollingmechanismallows

your software to remain clean and simple while robustly

communicating with the part. For a detailed discussion

of these topics and other special cases please refer to the

application note section located at:

// wait until chip is not busy

do

{

mfrCommonValue = PMBUS_READ_BYTE(0xEF);

partReady = (mfrCommonValue & 0x68) == 0x68;

}while(!partReady)

// now the part is ready to receive the next command

PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V

www.linear.com/designtools/app_notes

Figure 45. Example of a Command Write of VOUT_COMMAND

When communicating using bus speeds at or below

100kHz, the polling mechanism shown here provides a

simplesolutionthatensuresrobustcommunicationwithout

clock stretching. At bus speeds in excess of 100kHz, it is

strongly recommended that the part be configured to en-

able clock stretching. This requires a PMBus master that

supports clock stretching. System software that detects

and properly recovers from the standard PMBus NACK/

BUSYfaultsasdescribedinthePMBusSpecificationv1.1,

Part II, Section 10.8.7 is required to communicate The

LTC3884 is not recommended in applications with bus

speeds in excess of 400kHz.

PMBus busy protocols are well accepted standards, but

can make writing system level software somewhat com-

plex. The part provides three ‘hand shaking’ status bits

which reduce complexity while enabling robust system

level communication.

The three hand shaking status bits are in the MFR_

COMMON register. When the part is busy executing an

internal operation, it will clear bit 6 of MFR_COMMON

(‘chip not busy’). When the part is busy specifically be-

cause it is in a transitional V

state (margining hi/lo,

OUT

3884fe

72

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

ADDRESSING AND WRITE PROTECT

CMD

DATA

DEFAULT

COMMAND NAME

PAGE

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

0x00 Provides integration with multi-page PMBus devices.

R/W Byte

N

Reg

0x00

PAGE_PLUS_WRITE

PAGE_PLUS_READ

0x05 Write a supported command directly to a PWM channel. W Block

0x06 Read a supported command directly from a PWM

channel.

Block

R/W

WRITE_PROTECT

0x10 Level of protection provided by the device against

accidental changes.

R/W Byte

N

Y

0x00

2

MFR_ADDRESS

0xE6 Sets the 7-bit I C address byte.

R/W Byte

N

Y

Reg

Y

0x4F

0x80

MFR_RAIL_ADDRESS

0xFA Common address for PolyPhase outputs to adjust

common parameters.

PAGE

The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-

cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for

one PWM channel.

Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.

Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTC3884

will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).

This command has one data byte.

PAGE_PLUS_WRITE

The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send

the data for the command, all in one communication packet. Commands allowed by the present write protection level

may be sent with PAGE_PLUS_WRITE.

The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send

a non-paged command, the Page Number byte is ignored.

This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-

mand that has two data bytes is shown in Figure 46.

ꢗ

ꢖ

ꢗ

8

ꢗ

8

ꢗ

8

ꢗ

8

ꢗ

ꢀꢁꢂꢃꢄ

ꢂꢅꢅꢆꢄꢀꢀ

ꢇꢂꢈꢄꢉꢇꢁꢊꢀ

ꢋꢌꢍꢍꢂꢎꢅ ꢋꢌꢅꢄ

ꢏꢁꢌꢋꢐ ꢋꢌꢊꢎꢑ

ꢒꢓ 4ꢔ

ꢇꢂꢈꢄ

ꢎꢊꢍꢏꢄꢆ

ꢋꢌꢍꢍꢂꢎꢅ

ꢋꢌꢅꢄ

ꢀ

ꢕ

ꢂ

ꢘ

8

ꢗ

8

ꢗ

8

ꢗ

ꢁꢌꢕꢄꢆ ꢅꢂꢑꢂ

ꢏꢙꢑꢄ

ꢊꢇꢇꢄꢆ ꢅꢂꢑꢂ

ꢏꢙꢑꢄ

ꢂ

ꢇꢄꢋ ꢏꢙꢑꢄ

ꢂ

ꢇ

3884 ꢚ4ꢛ

Figure 46. Example of PAGE_PLUS_WRITE

PAGE_PLUS_READ

The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read

the data returned by the command, all in one communication packet .

3884fe

73

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access

data from a non-paged command, the Page Number byte is ignored.

This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown

in Figure 47.

ꢁ

ꢘ

ꢁ

8

ꢁ

8

ꢁ

8

ꢁ

8

ꢁ

ꢂꢃꢄꢅꢆ

ꢄꢇꢇꢈꢆꢂꢂ

ꢀꢄꢉꢆꢊꢀꢃꢋꢂ

ꢌꢍꢎꢎꢄꢏꢇ ꢌꢍꢇꢆ

ꢐꢃꢍꢌꢑ ꢌꢍꢋꢏꢒ

ꢓꢔ ꢕꢖ

ꢀꢄꢉꢆ

ꢏꢋꢎꢐꢆꢈ

ꢌꢍꢎꢎꢄꢏꢇ

ꢌꢍꢇꢆ

ꢂ

ꢗ

ꢄ

ꢙ

ꢁ

ꢘ

ꢁ

8

ꢁ

8

ꢁ

8

ꢁ

8

ꢁ

ꢂꢃꢄꢅꢆ

ꢄꢇꢇꢈꢆꢂꢂ

ꢐꢃꢍꢌꢑ ꢌꢍꢋꢏꢒ

ꢃꢍꢗꢆꢈ ꢇꢄꢒꢄ

ꢐꢚꢒꢆ

ꢋꢀꢀꢆꢈ ꢇꢄꢒꢄ

ꢐꢚꢒꢆ

ꢂꢛ

ꢈ

ꢄ

ꢀꢆꢌ ꢐꢚꢒꢆ

ꢏꢄ

ꢀ

ꢓꢔ ꢕꢖ

3884 ꢜ4ꢝ

Figure 47. Example of PAGE_PLUS_READ

Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another

PAGE_PLUS command. If this is attempted, the LTC3884 will NACK the entire PAGE_PLUS packet and issue a CML

fault for Invalid/Unsupported Data.

WRITE_PROTECT

The WRITE_PROTECT command is used to control writing to the LTC3884 device. This command does not indicate

the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the

value of this command.

BYTE MEANING

0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_

EE_UNLOCK, and STORE_USER_ALL commands.

0x40 Disable all writes except to the WRITE_PROTECT, PAGE,

MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,

OPERATION and CLEAR_FAULTS command. Individual fault

bits can be cleared by writing a 1 to the respective bits in the

STATUS commands.

0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,

MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,

PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_

ALL. Individual fault bits can be cleared by writing a 1 to the

respective bits in the STATUS commands.

0x10 Reserved, must be 0

0x08 Reserved, must be 0

0x04 Reserved, must be 0

0x02 Reserved, must be 0

0x01 Reserved, must be 0

Enable writes to all commands when WRITE_PROTECT is set to 0x00.

IfWPpinishigh,PAGE,OPERATION,MFR_CLEAR_PEAKS,MFR_EE_UNLOCK,WRITE_PROTECTandCLEAR_FAULTS

commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS

commands.

3884fe

74

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_ADDRESS

The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.

Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,

cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB

and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC3884 will use the

address value stored in NVM. If the ASEL0 pin is open, the LTC3884 will use the lower 4 bits of the MFR_ADDRESS

value stored in NVM to construct the effective address of the part. If the ASEL1 pin is open, the LTC3884 will use the

upper 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part.

This command has one data byte.

MFR_RAIL_ADDRESS

The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value

of this command should be common to all devices attached to a single power supply rail.

The user should only perform command writes to this address. If a read is performed from this address and the rail

devices do not respond with EXACTLY the same value, the LTC3884 will detect bus contention and may set a CML

communications fault.

Setting this command to a value of 0x80 disables rail device addressing for the channel.

This command has one data byte.

GENERAL CONFIGURATION COMMANDS

DATA

DEFAULT

VALUE

COMMAND NAME

MFR_CHAN_CONFIG

MFR_CONFIG_ALL

CMD CODE DESCRIPTION

TYPE

Configuration bits that are channel specific. R/W Byte

General configuration bits. R/W Byte

PAGED FORMAT UNITS NVM

0xD0

0xD1

Y

N

Reg

Y

0x1D

0x21

MFR_CHAN_CONFIG

General purpose configuration command common to multiple ADI products.

BIT MEANING

7

6

5

4

3

2

1

Reserved

Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.

Enable Short Cycle recognition if this bit is set to a 1.

SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.

No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are

propagated on FAULT.

0

Disables the V

decay value requirement for MFR_RETRY_TIME and t

processing. When this bit is set to a 0, the output must decay to

OUT

OFF(MIN)

less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from

high to low to high.

This command has one data byte.

3884fe

75

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

A shortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been

commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned

ON and OFF through either the RUN pin and or the PMBus OPERATION command.

If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:

1. Immediately tri-state the PWM channel output;

2. Start the retry delay timer as specified by the t

.

OFF(MIN)

3. After the t

value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_

OFF(MIN)

MFR_SPECIFIC bit #1 will assert.

If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:

1. Stop ramping down the PWM channel output;

2. Immediately tri-state the PWM channel output;

3. Start the retry delay timer as specified by the t

.

OFF(MIN)

4. After the t

value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_

OFF(MIN)

MFR_SPEFIFIC bit #1 will assert.

If the SHORT Cycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine

will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.

MFR_CONFIG_ALL

General purpose configuration command common to multiple ADI products.

BIT MEANING

7

6

5

4

3

2

1

0

Enable Fault Logging.

Ignore Resistor Configuration Pins.

Mask PMBus, PartII, Section 10.9.1 Violations.

Disable SYNC output.

Enable 255ms PMBus timeout.

PMBus command writes require a valid Packet Error Checking, PEC, byte to be accepted.*

Enable the use of PMBus clock stretching.

Execute CLEAR_FAULTS on rising edge of either RUN pin.

*PMBus command writes that have a valid PEC byte are always processed. PMBus command

writes that have an invalid PEC byte are not processed and set a CML status fault.

This command has one data byte.

ON/OFF/MARGIN

CMD

DATA

DEFAULT

VALUE

COMMAND NAME

ON_OFF_CONFIG

OPERATION

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte

Y

Reg

Y

0x1E

0x80

0x01 Operating mode control. On/off, margin high and margin R/W Byte

low.

MFR_RESET

0xFD Commanded reset without requiring a power-down.

Send Byte

N

NA

3884fe

76

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

ON_OFF_CONFIG

The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to

turn the PWM channel on and off.

Supported Values:

VALUE

0x1F

MEANING

OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.

OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.

RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.

RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.

0x1E

0x17

0x16

Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.

This command has one data byte.

OPERATION

The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It

is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in

the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin

instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET

or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed

to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation

command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor

IN

configuration pins are not installed, the outputs will be commanded off.

The part defaults to the Sequence Off state.

This command has one data byte.

Supported Values:

VALUE

0xA8

MEANING

Margin high.

Margin low.

0x98

0x80

On (V

back to nominal even if bit 3 of ON_OFF_CONFIG is not set).

OUT

0x40*

0x00*

Soft off (with sequencing).

Immediate off (no sequencing).

*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.

Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.

This command has one data byte.

MFR_RESET

This command provides a means to reset the LTC3884 from the serial bus. This forces the LTC3884 to turn off both

PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of

both PWM channels, if enabled.

This write-only command has no data bytes.

3884fe

77

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

PWM CONFIGURATION

DATA

DEFAULT

COMMAND NAME

MFR_PWM_COMP

MFR_PWM_MODE

MFR_PWM_CONFIG

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

0xD3

0xD4

0xF5

PWM loop compensation configuration

R/W Byte

Y

N

Reg

Y

0xAE

0xC7

0x10

Configuration for the PWM engine.

Set numerous parameters for the DC/DC controller

including phasing.

FREQUENCY_SWITCH

0x33

Switching frequency of the controller.

R/W

Word

N

L11

kHz

Y

425

0xFB52

MFR_PWM_MODE

The MFR_PWM_MODE command sets important PWM controls for each channel.

The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping

mode), or forced continuous conduction mode.

BIT

7

0b

1b

6

MEANING

Use High Range of I

Low Current Range

High Current Range

Enable Servo Mode

LIMIT

5

External temperature sense:

0: ∆V measurement.

BE

1: Direct voltage measurement.

Reserved

[4:3]

2

Enable ultra-low DCR current sense

1

V

Range

OUT

1b

0b

The maximum output voltage is 2.75V

The maximum output voltage is 5.5V

Bit[0] Mode

0b

1b

Discontinuous

Forced Continuous

Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.

Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the

channel output is active. Writing this bit when the channel is active will generate a CML fault.

Bit [6] The LTC3884 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo

is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC

and the VOUT_COMMAND (or the appropriate margined value).

When Bit[5] is cleared, the LTC3884 computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as

BE

T = (G • ∆V • q/(K • ln(16))) – 273.15 + O

BE

When Bit[5] is set, the LTC3884 computes temperature in °C from TSNSn voltage measured by the ADC as

T = (G • (1.35 – V

+ O)/4.3e-3) + 25

TSNSn

3884fe

78

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

For both equations,

–14

G = MFR_TEMP_1_GAIN • 2 , and

O = MFR_TEMP_1_OFFSET

Bit[2] determines if the part uses sub-milliohm DCR for sensing the output current. This is a very critical selection

in terms of overcurrent limit. It is highly recommend that Bit[2] should not be changed when device is in operation.

Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes

the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing

this bit when the channel is active will generate a CML fault.

B

it[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con-

duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of

this bit. This command has one data byte.

MFR_PWM_COMP

The MFR_PWM_COMP command sets the g of the PWM channel error amplifiers and the value of the internal R

m

ITHn

compensation resistors. This command affects the loop gain of the PWM output which may require modifications to

the external compensation network.

BIT

MEANING

BIT [7:5]

000b

Error Amplifier GM Adjust (mS)

1.00

1.68

2.35

3.02

3.69

4.36

5.04

5.73

001b

010b

011b

100b

101b

110b

111b

BIT [4:0 ]

00000b

00001b

00010b

00011b

00100b

00101b

00110b

00111b

01000b

01001b

01010b

01011b

01100b

01101b

01110b

R

ITH

(kΩ)

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.5

3

3.5

4

4.5

5

3884fe

79

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

01111b

10000b

10001b

10010b

10011b

10100b

10101b

10110b

10111b

11000b

11001b

11010b

11011b

11100b

11101b

11110b

11111b

5.5

6

7

8

9

11

13

15

17

20

24

28

32

38

46

54

62

This command has one data byte.

MFR_PWM_CONFIG

The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the

SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the

channels must be commanded off. If either channel is in the RUN state and this command is written, the command

will be NACK’d and a BUSY fault will be asserted.

BIT

MEANING

7

Reserved

[6:5]

00b

01b

10b

11b

Input current sense gain.

2x gain. 0mV to 50mV range.

4x gain. 0mV to 20mV range.

8x gain. 0mV to 5mV range.

Reserved

4

Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until

V

> VIN_ON. The SHARE_CLK pin will be

IN

pulled low when V < VIN_OFF. If this bit is 0, the

IN

SHARE_CLK pin will not be pulled low when VIN <

VIN_OFF except for the initial application of VIN.

BIT [2:0 ]

000b

001b

010b

011b

100b

101b

110b

CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)

0

90

0

180

270

240

120

240

300

0

120

60

120

3884fe

80

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

FREQUENCY_SWITCH

The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTC3884.

Supported Frequencies:

VALUE [15:0 ]

0x0000

0xF3E8

RESULTING FREQUENCY (TYP)

External Oscillator

250kHz

0xFABC

0xFB52

0xFBE8

0x023F

350kHz

425kHz

500kHz

575kHz

0x028A

0x02EE

0x03E8

650kHz

750kHz

1000kHz

The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be

commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY

fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be

detected as the PLL locks onto the new frequency.

This command has two data bytes and is formatted in Linear_5s_11s format.

VOLTAGE

Input Voltage and Limits

DATA

PAGED FORMAT

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

UNITS

NVM

VIN_OV_FAULT_LIMIT

0x55

0x58

0x35

0x36

0xF7

Input supply overvoltage fault limit.

R/W

N

L11

V

Y

15.5

Word

0xD3E0

VIN_UV_WARN_LIMIT

VIN_ON

Input supply undervoltage warning limit.

R/W

Word

V

Y

6.3

0xCB26

Input voltage at which the unit should start

power conversion.

R/W

Word

6.5

0xCB40

VIN_OFF

Input voltage at which the unit should stop

power conversion.

R/W

Word

V

6.0

0xCB00

MFR_RVIN

The resistance value of the V pin filter

R/W

Word

mΩ

1000

0x03E8

IN

element in milliohms

VIN_OV_FAULT_LIMIT

The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes

an input overvoltage fault.

This command has two data bytes in Linear_5s_11s format.

3884fe

81

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

VIN_UV_WARN_LIMIT

The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under-

voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON

command and the unit has been enabled. If the V Voltage drops below the VIN_OV_WARN_LIMIT the device:

IN

• Sets the INPUT Bit Is the STATUS_WORD

• Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command

IN

• Notifies the Host by Asserting ALERT, unless Masked

VIN_ON

The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.

This command has two data bytes and is formatted in Linear_5s_11s format.

VIN_OFF

The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_RVIN

The MFR_RVIN command is used to set the resistance value of the V pin filter element in milliohms. (See also

IN

READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.

This command has two data bytes and is formatted in Linear_5s_11s format.

Output Voltage and Limits

DATA

DEFAULT

VALUE

2

0x14

2.75

0x2C00

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

R Byte

PAGED FORMAT

Y

UNITS

NVM

–12

VOUT_MODE

0x20

Output voltage format and exponent

Reg

L16

–12

(2 ).

VOUT_MAX

0x24

Upper limit on the output voltage

the unit can command regardless of

any other commands.

R/W

Word

Y

V

Y

VOUT_OV_FAULT_ LIMIT

VOUT_OV_WARN_ LIMIT

VOUT_MARGIN_HIGH

0x40

0x42

0x25

Output overvoltage fault limit.

R/W

Y

L16

V

Y

1.1

Word

0x119A

Output overvoltage warning limit.

R/W

Word

R/W

Word

1.075

0x1133

1.05

0x10CD

Margin high output voltage set

point. Must be greater than VOUT_

COMMAND.

VOUT_COMMAND

0x21

0x26

Nominal output voltage set point.

R/W

Y

L16

V

Y

1.0

Word

0x1000

VOUT_MARGIN_LOW

Margin low output voltage set

point. Must be less than VOUT_

COMMAND.

R/W

Word

0.95

0x0F33

VOUT_UV_WARN_ LIMIT

VOUT_UV_FAULT_ LIMIT

MFR_VOUT_MAX

0x43

0x44

0xA5

Output undervoltage warning limit.

Output undervoltage fault limit.

Maximum allowed output voltage.

R/W

Y

L16

V

Y

0.925

Word

0x0ECD

R/W

Word

R Word

0.9

0x0E66

5.7

0x5B33

3884fe

82

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

VOUT_MODE

The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode

(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write

commands.

This read-only command has one data byte.

VOUT_MAX

The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-

mand regardless of any other commands or combinations. The maximum allowed value of this command is 5.8V.

The maximum output voltage the LTC3884 can produce is 5.5V including VOUT_MARGIN_HIGH. However, the

VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7V.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_OV_FAULT_LIMIT

The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara-

tor at the sense pins, in volts, which causes an output overvoltage fault.

If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi-

fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and

6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND

is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable

behavior and possible damage to the switcher.

If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT

is propagated. The LTC3884 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_OV_WARN_LIMIT

The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,

in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this

limit has been exceeded.

In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

This condition is detected by the ADC so the response time may be up to t

This command has two data bytes and is formatted in Linear_16u format.

.

CONVERT

3884fe

83

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

VOUT_MARGIN_HIGH

The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts,

when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The

maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5V.

ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE

will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_COMMAND

The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed

value on VOUT is 5.5V.

ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE

will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_MARGIN_LOW

The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,

when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.

ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE

will be used if this command is modified while the output is active and in a steady-state condition.

This command has two data bytes and is formatted in Linear_16u format.

VOUT_UV_WARN_LIMIT

The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,

in volts, which causes an output voltage low warning.

In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

This command has two data bytes and is formatted in Linear_16u format.

VOUT_UV_FAULT_LIMIT

The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-

parator at the sense pins, in volts, which causes an output undervoltage fault.

This command has two data bytes and is formatted in Linear_16u format.

3884fe

84

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_VOUT_MAX

The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_

LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX is 5.5V. If

the output voltage is set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX is 2.75V. Entering

a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped

to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.

This read only command has 2 data bytes and is formatted in Linear_16u format.

OUTPUT CURRENT AND LIMITS

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

IOUT_CAL_GAIN

0x38

The ratio of the voltage at the current R/W Word

sense pins to the sensed current. For

devices using a fixed current sense

resistor, it is the resistance value in

mΩ.

Y

L11

mΩ

Y

0.32

0xAA8F

MFR_IOUT_CAL_GAIN_TC

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

0xF6

0x46

0x4A

Temperature coefficient of the current R/W Word

sensing element.

Y

CF

Y

3900

0x0F3C

Output overcurrent fault limit.

R/W Word

L11

A

45.0

0xE2D0

Output overcurrent warning limit.

R/W Word

34.0

0xE230

IOUT_CAL_GAIN

The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see

also MFR_IOUT_CAL_GAIN_TC).

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_IOUT_CAL_GAIN_TC

TheMFR_IOUT_CAL_GAIN_TCcommandallowstheusertoprogramthetemperaturecoefficientoftheIOUT_CAL_GAIN

sense resistor or inductor DCR in ppm/°C.

This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •

–6

10 . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:

[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].

DCR sensing will have a typical value of 3900.

The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT,

MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.

3884fe

85

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

IOUT_OC_FAULT_LIMIT

The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control-

ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the

+

–

progammable peak output current limit value in mV between I

and I

. The actual value of current limit is

SENSE

+

–

(I

– I

)/IOUT_CAL_GAIN in Amperes.

SENSE

MFR_PWM_MODE[2]=1 (Sub-milli Ω DCR)

MFR_PWM_MODE[2]=0 (Normal Value of DCR)

L

RC =

5 • DCR

DCR

MFR_PWM_MODE[7]=1

High Current Range (mV)

MFR_PWM_MODE[7]=0

Low Current Range (mV)

MFR_PWM_MODE[7]=1

High Current Range (mV)

MFR_PWM_MODE[7]=0

Low Current Range (mV)

CODE

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

15.45

16.59

17.73

18.86

20.42

21.14

22.27

23.41

24.55

25.68

26.82

27.95

29.50

30.23

31.36

32.50

8.59

9.22

38.64

41.48

44.32

47.16

51.04

52.84

55.68

58.52

61.36

64.20

67.05

69.89

74.50

75.57

78.41

81.25

21.46

23.04

24.62

26.20

28.36

29.36

30.93

32.51

34.09

35.67

37.25

38.83

41.38

41.98

43.56

45.14

9.85

10.48

11.34

11.74

12.37

13.01

13.64

14.27

14.90

15.53

16.50

16.79

17.42

18.06

Note: Only V

codes 2–8 are supported for DCR sensing.

ILIMIT

Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output

current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:

Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).

The LTC3884 automatically convert currents to the appropriate internal bit value.

The I

range is set with bit 7 of the MFR_PWM_MODE command.

OUT

The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.

If the IOUT_OC_FAULT_LIMIT is exceeded, the device:

• Sets the IOUT bit in the STATUS word

• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT

• Notifies the host by asserting ALERT, unless masked

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

86

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

IOUT_OC_WARN_LIMIT

This command sets the value of the output current measured by the ADC that causes an output overcurrent warning

in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.

In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.

This command has two data bytes and is formatted in Linear_5s_11s format

Input Current and Limits

CMD

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

UNITS

NVM

MFR_IIN_CAL_GAIN

0xE8 The resistance value of the input current sense

element in mΩ.

R/W Word

L11

mΩ

Y

5.000

0xCA80

MFR_IIN_CAL_GAIN

The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.

(see also READ_IIN).

This command has two data bytes and is formatted in Linear_5s_11s format.

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0x5D Input overcurrent warning

limit.

TYPE

PAGED

FORMAT

UNITS

NVM

IIN_OC_WARN_LIMIT

R/W Word

N

L11

A

Y

10.0

0xD280

IIN_OC_WARN_LIMIT

The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes

a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been

exceeded.

In response to the IIN_OC_WARN_LIMIT being exceeded, the device:

• Sets the OTHER bit in the STATUS_BYTE

• Sets the INPUT bit in the upper byte of the STATUS_WORD

• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and

• Notifies the host by asserting ALERT pin

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

87

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

TEMPERATURE

External Temperature Calibration

DATA

DEFAULT

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM VALUE

MFR_TEMP_1_GAIN

0xF8

Sets the slope of the external temperature

sensor.

R/W Word

Y

CF

Y

1.0

0x4000

MFR_TEMP_1_OFFSET

0xF9

Sets the offset of the external temperature R/W Word

sensor.

L11

C

0.0

0x8000

MFR_TEMP_1_GAIN

TheMFR_TEMP_1_GAINcommandwillmodifytheslopeoftheexternaltemperaturesensortoaccountfornon-idealities

in the element and errors associated with the remote sensing of the temperature in the inductor.

This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is

–14

N • 2 . The nominal value is 1.

MFR_TEMP_1_OFFSET

The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non-

idealities in the element and errors associated with the remote sensing of the temperature in the inductor.

This command has two data bytes and is formatted in Linear_5s_11s format.

External Temperature Limits

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

UNITS

NVM

OT_FAULT_LIMIT

0x4F

0x51

0x53

External overtemperature fault limit.

R/W Word

Y

L11

C

Y

100.0

0xEB20

OT_WARN_LIMIT

UT_FAULT_LIMIT

External overtemperature warning

limit.

R/W Word

Y

C

Y

85.0

0xEAA8

External undertemperature fault limit. R/W Word

–40.0

0xE580

OT_FAULT_LIMIT

The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees

Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this

limit has been exceeded.

This command has two data bytes and is formatted in Linear_5s_11s format.

OT_WARN_LIMIT

The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees

Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if

this limit has been exceeded.

3884fe

88

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

In response to the OT_WARN_LIMIT being exceeded, the device:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has two data bytes and is formatted in Linear_5s_11s format.

UT_FAULT_LIMIT

TheUT_FAULT_LIMITcommandsetsthevalueoftheexternalsensetemperaturemeasuredbytheADC,indegreesCelsius,

whichcausesanundertemperaturefault.TheREAD_TEMPERATURE_1valuewillbeusedtodetermineifthislimithasbeen

exceeded.

Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response

set to ignore to avoid ALERT being asserted.

This command has two data bytes and is formatted in Linear_5s_11s format.

TIMING

Timing—On Sequence/Ramp

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

TON_DELAY

0x60

Time from RUN and/or Operation on to

R/W Word

Y

L11

ms

Y

0.0

output rail turn-on.

0x8000

TON_RISE

0x61

Time from when the output starts to

rise until the output voltage reaches the

VOUT commanded value.

Maximum time from the start of TON_

RISE for VOUT to cross the VOUT_UV_

FAULT_LIMIT.

R/W Word

Y

ms

Y

8.0

0xD200

TON_MAX_FAULT_LIMIT

VOUT_TRANSITION_RATE

TON_DELAY

0x62

0x27

Y

L11

ms

10.0

0xD280

Rate the output changes when VOUT

commanded to a new value.

V/ms

0.25

0xAA00

The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output

voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of

270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.

This command has two data bytes and is formatted in Linear_5s_11s format.

TON_RISE

The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output

enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during

TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3884 digital slope will be bypassed and the output voltage

transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE

is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

89

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

TON_MAX_FAULT_LIMIT

The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power

up the output without reaching the output undervoltage fault limit.

A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.

The maximum limit is 83 seconds.

This command has two data bytes and is formatted in Linear_5s_11s format.

VOUT_TRANSITION_RATE

When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the

output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded

rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.

This command has two data bytes and is formatted in Linear_5s_11s format.

Timing—Off Sequence/Ramp

DATA

FORMAT UNITS

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

NVM

TOFF_DELAY

0x64

0x65

0x66

Time from RUN and/or Operation off to

the start of TOFF_FALL ramp.

Time from when the output starts to fall R/W Word

until the output reaches zero volts.

Maximum allowed time, after TOFF_FALL R/W Word

completed, for the unit to decay below

12.5%.

R/W Word

Y

L11

ms

Y

0.0

0x8000

TOFF_FALL

Y

8.0

0xD200

150

0xF258

TOFF_MAX_WARN_LIMIT

TOFF_DELAY

The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output

voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of

270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied

when a fault event occurs

This command has two data bytes and is formatted in Linear_5s_11s format.

TOFF_FALL

The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-

age is commanded to zero. It is the ramp time of the V

set to high impedance state.

DAC. When the V

DAC is zero, the PWM output will be

OUT

The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part

to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.

The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum

fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty

of 0.1ms.

In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by

the output capacitance and load current.

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

90

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

TOFF_MAX_WARN_LIMIT

The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds

12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V

voltage

OUT

is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.

A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage

indefinitely. Other than 0, values from 120ms to 524 seconds are valid.

This command has two data bytes and is formatted in Linear_5s_11s format.

Precondition for Restart

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0xDC Minimum time the RUN pin is held

low by the LTC3884.

TYPE

PAGED

FORMAT

UNITS

NVM

MFR_RESTART_ DELAY

R/W Word

Y

L11

ms

Y

500

0xFBE8

MFR_RESTART_DELAY

This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length

of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.

Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after

which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_

FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,

set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_

RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the

output takes a long time to decay below 12.5% of the programmed value.

This command has two data bytes and is formatted in Linear_5s_11s format.

FAULT RESPONSE

Fault Responses All Faults

DATA

FORMAT

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

UNITS

NVM

MFR_RETRY_ DELAY

0xDB

Retry interval during FAULT retry R/W Word

mode.

Y

L11

ms

Y

350

0xFABC

MFR_RETRY_DELAY

This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified

intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has

been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.

Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required

for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is

too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of

MFR_CHAN_CONFIG.

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

91

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Fault Responses Input Voltage

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

VIN_OV_FAULT_RESPONSE

0x56

Action to be taken by the device when an R/W Byte

input supply overvoltage fault is detected.

Y

Reg

Y

0x80

VIN_OV_FAULT_RESPONSE

The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-

voltage fault. The data byte is in the format given in Table 11.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Set the INPUT bit in the upper byte of the STATUS_WORD

• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

Fault Responses Output Voltage

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

VOUT_OV_FAULT_RESPONSE

0x41

0x45

0x63

Action to be taken by the device when an R/W Byte

output overvoltage fault is detected.

Y

Reg

Y

0xB8

VOUT_UV_FAULT_RESPONSE

Action to be taken by the device when an R/W Byte

output undervoltage fault is detected.

Y

TON_MAX_FAULT_

RESPONSE

Action to be taken by the device when a

TON_MAX_FAULT event is detected.

R/W Byte

VOUT_OV_FAULT_RESPONSE

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output

overvoltage fault. The data byte is in the format given in Table 7.

The device also:

• Sets the VOUT_OV bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

The only values recognized for this command are:

0x00–Part performs OV pull down only, or OV_PULLDOWN.

0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).

3884fe

92

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until

it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault

condition causes the unit to shut down.

0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-

manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.

The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.

0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared

or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or

removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.

Any other value will result in a CML fault and the write will be ignored.

This command has one data byte.

Table 7. VOUT_OV_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

Part performs OV pull down only or OV_PULLDOWN

(i.e., turns off the top MOSFET and turns on lower MOSFET

while V is > VOUT_OV_FAULT).

For all values of bits [7:6], the LTC3884:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

OUT

01

The PMBus device continues operation for the delay time

specified by bits [2:0] and the delay time unit specified for that

particular fault. If the fault condition is still present at the end of

the delay time, the unit responds as programmed in the Retry

Setting (bits [5:3]).

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

10

11

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

Not supported. Writing this value will generate a CML fault.

• Bias power is removed and reapplied to the LTC3884.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

000-111 The delay time in 10µs increments. This delay time determines

how long the controller continues operating after a fault is

detected. Only valid for deglitched off state.

VOUT_UV_FAULT_RESPONSE

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output

undervoltage fault. The data byte is in the format given in Table 8.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

3884fe

93

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command

• Notifies the host by asserting ALERT pin, unless masked

The UV fault and warn are masked until the following criteria are achieved:

1) The TON_MAX_FAULT_LIMIT has been reached

2) The TON_DELAY sequence has completed

3) The TON_RISE sequence has completed

4) The VOUT_UV_FAULT_LIMIT threshold has been reached

5) The IOUT_OC_FAULT_LIMIT is not present

The UV fault and warn are masked whenever the channel is not active.

The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.

This command has one data byte.

Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

The PMBus device continues operation without interruption.

(Ignores the fault functionally)

For all values of bits [7:6], the LTC3884:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

01

The PMBus device continues operation for the delay time

specified by bits [2:0] and the delay time unit specified for

that particular fault. If the fault condition is still present at the

end of the delay time, the unit responds as programmed in the

Retry Setting (bits [5:3]).

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

10

11

The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3].

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

Not supported. Writing this value will generate a CML fault.

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

000-111 The delay time in 10µs increments. This delay time determines

how long the controller continues operating after a fault is

detected. Only valid for deglitched off state.

3884fe

94

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

TON_MAX_FAULT_RESPONSE

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX

fault. The data byte is in the format given in Table 11.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the VOUT bit in the STATUS_WORD

• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.

Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.

This command has one data byte.

Fault Responses Output Current

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

IOUT_OC_FAULT_RESPONSE

0x47

Action to be taken by the device when an R/W Byte

output overcurrent fault is detected.

Y

Reg

Y

0x00

IOUT_OC_FAULT_RESPONSE

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output

overcurrent fault. The data byte is in the format given in Table 9.

The device also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the IOUT_OC bit in the STATUS_BYTE

• Sets the IOUT bit in the STATUS_WORD

• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

3884fe

95

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Table 9. IOUT_OC_FAULT_RESPONSE Data Byte Contents

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

The LTC3884 continues to operate indefinitely while maintaining

the output current at the value set by IOUT_OC_FAULT_LIMIT

without regard to the output voltage (known as constant-

current or brick-wall limiting).

For all values of bits [7:6], the LTC3884:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

01

10

Not supported.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

The LTC3884 continues to operate, maintaining the output

current at the value set by IOUT_OC_FAULT_LIMIT without

regard to the output voltage, for the delay time set by bits [2:0].

If the device is still operating in current limit at the end of the

delay time, the device responds as programmed by the Retry

Setting in bits [5:3].

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

11

The LTC3884 shuts down immediately and responds as

programmed by the Retry Setting in bits [5:3].

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared by cycling the RUN pin or

removing bias power.

The device attempts to restart continuously, without limitation,

until it is commanded OFF (by the RUN pin or OPERATION

command or both), bias power is removed, or another fault

condition causes the unit to shut down. Note: The retry interval

is set by the MFR_RETRY_DELAY command.

Delay Time

000-111 The number of delay time units in 16ms increments. This

delay time is used to determine the amount of time a unit is

to continue operating after a fault is detected before shutting

down. Only valid for deglitched off response.

Fault Responses IC Temperature

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

MFR_OT_FAULT_

RESPONSE

0xD6

Action to be taken by the device when an

internal overtemperature fault is detected.

R Byte

N

Reg

0xC0

MFR_OT_FAULT_RESPONSE

The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal

overtemperature fault. The data byte is in the format given in Table 10.

The LTC3884 also:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Sets the MFR bit in the STATUS_WORD, and

• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

3884fe

96

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Table 10 . Data Byte Contents MFR_OT_FAULT_RESPONSE

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

01

10

Not supported. Writing this value will generate a CML fault.

Not supported. Writing this value will generate a CML fault

For all values of bits [7:6], the LTC3884:

• Sets the corresponding fault bit in the status commands and

• Notifies the host by asserting ALERT pin, unless masked.

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

11

The device’s output is disabled while the fault is present.

Operation resumes and the output is enabled when the fault

condition no longer exists.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

• Bias power is removed and reapplied to the LTC3884.

Retry Setting

5:3

2:0

000

The unit does not attempt to restart. The output remains

disabled until the fault is cleared.

001-111 Not supported. Writing this value will generate CML fault.

Delay Time

XXX

Not supported. Value ignored

Fault Responses External Temperature

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

OT_FAULT_ RESPONSE

0x50

Action to be taken by the device when an

external overtemperature fault is detected,

R/W Byte

Y

Reg

Y

0xB8

UT_FAULT_ RESPONSE

0x54

Action to be taken by the device when an

external undertemperature fault is detected.

R/W Byte

Y

0xB8

OT_FAULT_RESPONSE

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-

perature fault on the external temp sensors. The data byte is in the format given in Table 11.

The device also:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

This command has one data byte.

UT_FAULT_RESPONSE

The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-

temperature fault on the external temp sensors. The data byte is in the format given in Table 11.

The device also:

• Sets the TEMPERATURE bit in the STATUS_BYTE

• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and

• Notifies the host by asserting ALERT pin, unless masked

3884fe

97

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

This condition is detected by the ADC so the response time may be up to t

.

CONVERT

This command has one data byte.

Table 11. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,

OT_FAULT_RESPONSE, UT_FAULT_RESPONSE

BITS DESCRIPTION

VALUE MEANING

7:6

Response

00

01

10

The PMBus device continues operation without interruption.

Not supported. Writing this value will generate a CML fault.

For all values of bits [7:6], the LTC3884:

• Sets the corresponding fault bit in the status commands, and

• Notifies the host by asserting ALERT pin, unless masked.

The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3].

11

Not supported. Writing this value will generate a CML fault.

The fault bit, once set, is cleared only when one or more of the

following events occurs:

• The device receives a CLEAR_FAULTS command.

• The output is commanded through the RUN pin, the OPERATION

command, or the combined action of the RUN pin and

OPERATION command, to turn off and then to turn back on, or

• The device receives a RESTORE_USER_ALL command.

• The device receives a MFR_RESET command.

• The device supply power is cycled.

Retry Setting

5:3

2:0

000

111

The unit does not attempt to restart. The output remains

disabled until the fault is cleared until the device is commanded

OFF bias power is removed.

The PMBus device attempts to restart continuously, without

limitation, until it is commanded OFF (by the RUN pin or

OPERATION command or both), bias power is removed, or

another fault condition causes the unit to shut down without

retry. Note: The retry interval is set by the MFR_RETRY_DELAY

command.

Delay Time

XXX

Not supported. Values ignored

FAULT SHARING

Fault Sharing Propagation

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

0xD2 Configuration that determines which faults

are propagated to the FAULT pins.

TYPE

PAGED FORMAT UNITS

NVM

MFR_FAULT_

PROPAGATE

R/W Word

Y

Reg

Y

0x6993

MFR_FAULT_PROPAGATE

The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The com-

mand is formatted as shown in Table 12. Faults can only be propagated to the FAULTn pin if they are programmed to

respond to faults.

This command has two data bytes.

3884fe

98

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Table 12: FAULTn Propagate Fault Configuration

The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output

channels. Others are specific to an output channel. They can also be used to share faults between channels.

BIT(S)

SYMBOL

OPERATION

B[15]

VOUT disabled while not decayed.

This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC3884 is a

zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then

the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT

will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition

if bit 15 is asserted.

B[14]

b[13]

Mfr_fault_propagate_short_CMD_cycle 0: No action

1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high

after sequence off.

t

OFF(MIN)

Mfr_fault_propagate_ton_max_fault

0: No action if a TON_MAX_FAULT fault is asserted

1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted

FAULT0 is associated with page 0 TON_MAX_FAULT faults

FAULT1 is associated with page 1 TON_MAX_FAULT faults

b[12]

b[11]

Reserved

Mfr_fault0_propagate_int_ot,

Mfr_fault1_propagate_int_ot

Reserved

0: No action if the MFR_OT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted

b[10]

b[9]

Reserved

b[8]

Mfr_fault0_propagate_ut,

Mfr_fault1_propagate_ut

0: No action if the UT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 UT faults

FAULT1 is associated with page 1 UT faults

b[7]

Mfr_fault0_propagate_ot,

Mfr_fault1_propagate_ot

0: No action if the OT_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OT faults

FAULT1 is associated with page 1 OT faults

b[6]

b[5]

b[4]

Reserved

Mfr_fault0_propagate_input_ov,

Mfr_fault1_propagate_input_ov

Reserved

0: No action if the VIN_OV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted

b[3]

b[2]

Mfr_fault0_propagate_iout_oc,

Mfr_fault1_propagate_iout_oc

0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OC faults

FAULT1 is associated with page 1 OC faults

b[1]

b[0]

Mfr_fault0_propagate_vout_uv,

Mfr_fault1_propagate_vout_uv

0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 UV faults

FAULT1 is associated with page 1 UV faults

Mfr_fault0_propagate_vout_ov,

Mfr_fault1_propagate_vout_ov

0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted

1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted

FAULT0 is associated with page 0 OV faults

FAULT1 is associated with page 1 OV faults

3884fe

99

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Fault Sharing Response

DATA

DEFAULT

VALUE

0xC0

COMMAND NAME

CMD CODE DESCRIPTION

0xD5 Action to be taken by the device when the

FAULT pin is asserted low.

TYPE

R/W Byte

PAGED FORMAT UNITS

Y

NVM

Y

MFR_FAULT_RESPONSE

Reg

MFR_FAULT_RESPONSE

The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin

being pulled low by an external source.

Supported Values:

VALUE

0xC0

MEANING

FAULT_INHIBIT The LTC3884 will three-state the output in response to the FAULT pin pulled low.

FAULT_IGNORE The LTC3884 continues operation without interruption.

0x00

The device also:

• Sets the MFR Bit in the STATUS_WORD.

• Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low

• Notifies the Host by Asserting ALERT, Unless Masked

This command has one data byte.

SCRATCHPAD

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

USER_DATA_00

0xB0

OEM reserved. Typically used for part

serialization.

R/W Word

N

Reg

Y

NA

USER_DATA_01

USER_DATA_02

0xB1

0xB2

Manufacturer reserved for LTpowerPlay.

R/W Word

Y

N

Reg

Y

NA

OEM reserved. Typically used for part

serialization.

USER_DATA_03

USER_DATA_04

0xB3

0xB4

A NVM word available for the user.

R/W Word

Y

N

Reg

Y

0x0000

3884fe

100

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

USER_DATA_00 through USER_DATA_04

These commands are non-volatile memory locations for customer storage. The customer has the option to write any

value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of

these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable

inventory control and incompatibility with these products.

These commands have 2 data bytes and are in register format.

IDENTIFICATION

DATA

FORMAT UNITS

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED

NVM

PMBus_REVISION

0x98

PMBus revision supported by this device.

R Byte

N

Reg

FS

0x22

Current revision is 1.2.

CAPABILITY

0x19

Summary of PMBus optional communication

protocols supported by this device.

R Byte

N

0xB0

MFR_ID

0x99

0x9A

0xE7

The manufacturer ID of the LTC3884 in ASCII.

Manufacturer part number in ASCII.

R String

R Word

N

ASC

Reg

LTC

MFR_MODEL

MFR_SPECIAL_ID

LTC3884

0x4C0X

Manufacturer code representing the LTC3884.

PMBus_REVISION

The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3884

is PMBus Version 1.2 compliant in both Part I and Part II.

This read-only command has one data byte.

CAPABILITY

This command provides a way for a host system to determine some key capabilities of a PMBus device.

The LTC3884 supports packet error checking, 400kHz bus speeds, and ALERT pin.

This read-only command has one data byte.

MFR_ID

The MFR_ID command indicates the manufacturer ID of the LTC3884 using ASCII characters.

This read-only command is in block format.

MFR_MODEL

The MFR_MODEL command indicates the manufacturer’s part number of the LTC3884 using ASCII characters.

This read-only command is in block format.

MFR_SPECIAL_ID

The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTC3884, XX is adjustable by

the manufacturer.

This read-only command has two data bytes.

3884fe

101

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

FAULT WARNING AND STATUS

DEFAULT

VALUE

NA

See CMD

Details

COMMAND NAME

CLEAR_FAULTS

SMBALERT_MASK

CMD CODE DESCRIPTION

TYPE

PAGED

N

Y

FORMAT UNITS

NVM

0x03

0x1B

Clear any fault bits that have been set. Send Byte

Mask activity.

Block R/W

Reg

Y

MFR_CLEAR_PEAKS

STATUS_BYTE

0xE3

0x78

Clears all peak values.

One byte summary of the unit’s fault

condition.

Two byte summary of the unit’s fault

condition.

Output voltage fault and warning

status.

Output current fault and warning

status.

Input supply fault and warning status.

External temperature fault and warning R/W Byte

status for READ_TEMERATURE_1.

Send Byte

R/W Byte

Y

NA

Reg

STATUS_WORD

STATUS_VOUT

STATUS_IOUT

0x79

0x7A

0x7B

R/W Word

R/W Byte

Y

NA

STATUS_INPUT

STATUS_ TEMPERATURE

0x7C

0x7D

N

Y

Reg

NA

STATUS_CML

0x7E

0x80

Communication and memory fault and R/W Byte

warning status.

N

Y

Reg

NA

STATUS_MFR_ SPECIFIC

Manufacturer specific fault and state

information.

R/W Byte

MFR_INFO

MFR_PADS

MFR_COMMON

0xB6

0xE5

0xEF

Manufacturing specific information.

Digital status of the I/O pads.

Manufacturer status bits that are

common across multiple ADI chips.

R Word

R Byte

N

Reg

NA

CLEAR_FAULTS

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all

status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output

if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain

set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault

occurs within that time frame it may be cleared before the status register is set.

This write-only command has no data bytes.

The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut

down for a fault condition are restarted when:

• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin

and OPERATION command, to turn off and then to turn back on, or

• MFR_RESET command is issued.

• Bias power is removed and reapplied to the integrated circuit

3884fe

102

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

SMBALERT_MASK

The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they

are asserted.

Figure 45 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in

themaskbytealignwithbitsinthespecifiedstatusregister. Forexample, iftheSTATUS_TEMPERATUREcommandcode

is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning

would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE

bits would continue to assert ALERT if set.

Figure 46 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state

of any supported status register, again without PEC.

SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3884.

Factory default masking for applicable status registers is shown below. Providing an unsupported command code to

SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.

SMBALERT_MASK Default Setting: (Refer Also to Figure 2)

STATUS RESISTER

STATUS_VOUT

STATUS_IOUT

ALERT Mask Value MASKED BITS

0x00

None

ꢁ

ꢔ

ꢁ

8

ꢁ

8

ꢁ

8

ꢁ

ꢂꢃꢄꢅꢆ

ꢄꢇꢇꢈꢆꢂꢂ

ꢂꢉꢊꢄꢃꢆꢈꢋꢌꢉꢄꢂꢍ

ꢎꢏꢉꢉꢄꢐꢇ ꢎꢏꢇꢆ

ꢂꢋꢄꢋꢑꢂꢌꢒ

ꢎꢏꢉꢉꢄꢐꢇ ꢎꢏꢇꢆ

ꢂ

ꢓ

ꢄ

ꢉꢄꢂꢍ ꢊꢕꢋꢆ

ꢄ

ꢀ

3884 ꢖ4ꢔ

Figure 48. Example of Writing SMBALERT_MASK

ꢒ

ꢕ

ꢒ

8

ꢒ

8

ꢒ

8

ꢒ

ꢀꢁꢂꢃꢄ

ꢂꢅꢅꢆꢄꢀꢀ

ꢀꢇꢈꢂꢁꢄꢆꢉꢊꢇꢂꢀꢋ

ꢌꢍꢇꢇꢂꢎꢅ ꢌꢍꢅꢄ

ꢈꢁꢍꢌꢋ ꢌꢍꢏꢎꢉ

ꢐꢑ ꢒꢓ

ꢀꢉꢂꢉꢏꢀꢊꢖ

ꢌꢍꢇꢇꢂꢎꢅ ꢌꢍꢅꢄ

ꢀ

ꢔ

ꢂ

ꢗ

ꢒ

ꢕ

ꢒ

8

ꢒ

8

ꢒ

ꢀꢁꢂꢃꢄ

ꢂꢅꢅꢆꢄꢀꢀ

ꢈꢁꢍꢌꢋ ꢌꢍꢏꢎꢉ

ꢐꢑ ꢒꢓ

ꢀꢘ

ꢆ

ꢂ

ꢇꢂꢀꢋ ꢈꢛꢉꢄ

ꢎꢂ

ꢙ

3884 ꢚ48

Figure 49. Example of Reading SMBALERT_MASK

STATUS_TEMPERATURE

STATUS_CML

0x00

0x11

None

STATUS_INPUT

STATUS_MFR_SPECIFIC

Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)

MFR_CLEAR_PEAKS

The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the

MFR_*_PEAK data values.

This write-only command has no data bytes.

3884fe

103

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

STATUS_BYTE

The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the

lower byte of the status word.

STATUS_BYTE Message Contents:

BIT

7*

6

STATUS BIT NAME

MEANING

BUSY

OFF

A fault was declared because the LTC3884 was unable to respond.

This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not

being enabled.

5

4

3

2

1

0

VOUT_OV

IOUT_OC

VIN_UV

An output overvoltage fault has occurred.

An output overcurrent fault has occurred.

Not supported (LTC3884 returns 0).

TEMPERATURE

CML

A temperature fault or warning has occurred.

A communications, memory or logic fault has occurred.

NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.

This command has one data byte.

STATUS_WORD

The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the

STATUS_WORD is the same as the STATUS_BYTE command.

STATUS_WORD High Byte Message Contents:

BIT

15

14

13

12

11

10

9

STATUS BIT NAME

MEANING

V

An output voltage fault or warning has occurred.

An output current fault or warning has occurred.

An input voltage fault or warning has occurred.

A fault or warning specific to the LTC3884 has occurred.

The POWER_GOOD state is false if this bit is set.

Not supported (LTC3884 returns 0).

OUT

I

INPUT

MFR_SPECIFIC

POWER_GOOD#

FANS

OTHER

Not supported (LTC3884 returns 0).

8*

UNKNOWN

Not supported (LTC3884 returns 0).

*ALERT can be asserted if either of these bits is set. It may be cleared by writing a 1 to its bit position in the STATUS_BYTE, in lieu of a CLEAR_FAULTS

command.

If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.

This command has two data bytes.

3884fe

104

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

STATUS_VOUT

The STATUS_VOUT command returns one byte of V

status information.

OUT

STATUS_VOUT Message Contents:

BIT

7

MEANING

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

overvoltage fault.

overvoltage warning.

undervoltage warning.

undervoltage fault.

max warning.

6

5

4

3

2

TON max fault.

1

TOFF max fault.

0

Not supported (LTC3884 returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

STATUS_IOUT

The STATUS_IOUT command returns one byte of I

status information.

OUT

STATUS_IOUT Message Contents:

BIT

7

MEANING

overcurrent fault.

I

OUT

6

Not supported (LTC3884 returns 0).

I overcurrent warning.

OUT

5

4:0

Not supported (LTC3884 returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

3884fe

105

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

STATUS_INPUT

The STATUS_INPUT command returns one byte of V (VINSNS) status information.

IN

STATUS_INPUT Message Contents:

BIT

7

MEANING

overvoltage fault.

V

IN

6

Not supported (LTC3884 returns 0).

V undervoltage warning.

IN

5

4

Not supported (LTC3884 returns 0).

3

Unit off for insufficient V .

IN

2

Not supported (LTC3884 returns 0).

1

I overcurrent warning.

IN

0

Not supported (LTC3884 returns 0).

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not

generate an ALERT even if it is set. This command has one data byte.

STATUS_TEMPERATURE

The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged

command and is related to the respective READ_TEMPERATURE_1 value.

STATUS_TEMPERATURE Message Contents:

BIT

7

MEANING

External overtemperature fault.

External overtemperature warning.

Not supported (LTC3884 returns 0).

External undertemperature fault.

Not supported (LTC3884 returns 0).

6

5

4

3:0

.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

This command has one data byte.

3884fe

106

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

STATUS_CML

The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.

STATUS_CML Message Contents:

BIT

7

MEANING

Invalid or unsupported command received.

Invalid or unsupported data received.

Packet error check failed.

6

5

4

Memory fault detected.

3

Processor fault detected.

2

Reserved (LTC3884 returns 0).

Other communication fault.

Other memory or logic fault.

1

0

If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued

operation of the part is not recommended if these bits are continuously set.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

STATUS_MFR_SPECIFIC

The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.

The format for this byte is:

BIT MEANING

7

6

5

4

3

2

1

0

Internal Temperature Fault Limit Exceeded.

Internal Temperature Warn Limit Exceeded.

Factory Trim Area NVM CRC Fault.

PLL is Unlocked

Fault Log Present

V

DD33

UV or OV Fault

ShortCycle Event Detected

FAULT Pin Asserted Low by External Device

If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.

The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear

status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared

by issuing the MFR_FAULT_LOG_CLEAR command.

Any supported fault bit in this command will initiate an ALERT event.

This command has one data byte.

3884fe

107

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_PADS

This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit

assignments of this command are as follows:

BIT ASSIGNED DIGITAL PIN

15

14

V

OV Fault

UV Fault

DD33

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation

10 SYNC clocked by external device (when LTC3884 configured to drive SYNC pin)

9

8

7

6

5

4

3

2

1

0

Channel 1 Power Good

Channel 0 Power Good

LTC3884 Driving RUN1 Low

LTC3884 Driving RUN0 Low

RUN1 Pin State

RUN0 Pin State

LTC3884 Driving FAULT1 Low

LTC3884 Driving FAULT0 Low

FAULT1 Pin State

FAULT0 Pin State

A 1 indicates the condition is true.

This read-only command has two data bytes.

MFR_COMMON

The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.

BIT

7

MEANING

Chip Not Driving ALERT Low

LTC3884 Not Busy

Calculations Not Pending

LTC3884 Outputs Not in Transition

NVM Initialized

6

5

4

3

2

Reserved

1

SHARE_CLK Timeout

WP Pin Status

0

This read-only command has one data byte.

3884fe

108

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_INFO

The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple

ADI PSM products.

MFR_INFO Data Contents:

BIT

15:5

4

MEANING

Reserved.

EEPROM ECC status.

0: Corrections made in the EEPROM user space.

1: No corrections made in the EEPROM user space.

Reserved

3:0

EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM

bulk read operation. This read-only command has two data bytes.

TELEMETRY

CMD

DEFAULT

VALUE

COMMAND NAME

READ_VIN

READ_IIN

READ_VOUT

READ_IOUT

CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS

NVM

0x88 Measured input supply voltage.

0x89 Measured input supply current.

0x8B Measured output voltage.

0x8C Measured output current.

0x8D External diode junction temperature. This

is the value used for all temperature related

processing, including IOUT_CAL_GAIN.

R Word

N

Y

L11

L16

L11

V

A

V

A

C

NA

READ_TEMPERATURE_1

READ_TEMPERATURE_2

0x8E Internal junction temperature. Does not affect

any other commands.

R Word

N

L11

C

NA

READ_FREQUENCY

READ_POUT

READ_PIN

MFR_PIN_ACCURACY

MFR_IOUT_PEAK

0x95 Measured PWM switching frequency.

0x96 Calculated output power.

0x97 Calculated input power.

0xAC Returns the accuracy of the READ_PIN command R Byte

0xD7 Report the maximum measured value of

READ_IOUT since last MFR_CLEAR_PEAKS.

0xDD Maximum measured value of READ_VOUT

since last MFR_CLEAR_PEAKS.

0xDE Maximum measured value of READ_VIN since

last MFR_CLEAR_PEAKS.

R Word

Y

N

Y

L11

Hz

W

%

A

NA

5.0%

NA

R Word

L11

L16

L11

MFR_VOUT_PEAK

MFR_VIN_PEAK

Y

N

Y

V

C

NA

MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external

Temperature (READ_TEMPERATURE_1) since

last MFR_CLEAR_PEAKS.

MFR_READ_IIN_PEAK

0xE1 Maximum measured value of READ_IIN

command since last MFR_CLEAR_PEAKS.

R Word

N

L11

A

NA

MFR_READ_ICHIP

0xE4 Measured current used by the LTC3884.

R Word

N

L11

A

C

NA

MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last

MFR_CLEAR_PEAKS.

MFR_ADC_CONTROL

0xD8 ADC telemetry parameter selected for repeated R/W Byte

fast ADC read back.

N

Reg

NA

3884fe

109

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

READ_VIN

The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This

IN

compensates for the IR voltage drop across the V filter element due to the supply current of the LTC3884.

IN

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_VOUT

The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.

This read-only command has two data bytes and is formatted in Linear_16u format.

READ_IIN

The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor

(see also MFR_IIN_CAL_GAIN).

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_IOUT

The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:

a) the differential voltage measured across the I

b) the IOUT_CAL_GAIN value

pins

SENSE

c) the MFR_IOUT_CAL_GAIN_TC value, and

d) READ_TEMPERATURE_1 value

e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_TEMPERATURE_1

The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_TEMPERATURE_2

The READ_TEMPERATURE_2 command returns the LTC3884’s die temperature, in degrees Celsius, of the internal

sense element.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

READ_FREQUENCY

The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

READ_POUT

The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on

the most recent correlated output voltage and current reading.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

3884fe

110

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

READ_PIN

The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the

most recent input voltage and current reading.

This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

MFR_PIN_ACCURACY

TheMFR_PIN_ACCURACYcommandreturnstheaccuracy,inpercent,ofthevaluereturnedbytheREAD_PINcommand.

There is one data byte. The value is 0.1% per bit which gives a range of 0.0% to 25.5%.

This read-only command has one data byte and is formatted as an unsigned integer.

MFR_IOUT_PEAK

The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_VOUT_PEAK

The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_16u format.

MFR_VIN_PEAK

The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_TEMPERATURE_1_PEAK

The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the

READ_TEMPERATURE_1 measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_READ_IIN_PEAK

TheMFR_READ_IIN_PEAKcommandreportsthehighestcurrent, inAmperes, reportedbytheREAD_IINmeasurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This command has two data bytes and is formatted in Linear_5s_11s format.

MFR_READ_ICHIP

The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC3884.

This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe

111

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_TEMPERATURE_2_PEAK

The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the

READ_TEMPERATURE_2 measurement.

This command is cleared using the MFR_CLEAR_PEAKS command.

This read-only command has two data bytes and is formatted in Linear_5s_11s format.

MFR_ADC_CONTROL

The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs

the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t

.

CONVERT

The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.

This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions

may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard

telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be

commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command

back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all

warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage

servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.

COMMANDED VALUE

TELEMETRY COMMAND NAME

DESCRIPTION

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Reserved

Channel 1 external temperature

Reserved

Channel 1 measured output current

Channel 1 measured output voltage

Channel 0 external temperature

Reserved

Channel 0 measured output current

Channel 0 measured output voltage

Internal junction temperature

Measured input supply current

Measured supply current of the LTC3884

Measured input supply voltage

Standard ADC Round Robin Telemetry

READ_TEMPERATURE_1

READ_IOUT

READ_VOUT

READ_TEMPERATURE_1

READ_IOUT

READ_VOUT

READ_TEMPERATURE_2

READ_IIN

MFR_READ_ICHIP

READ_VIN

If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML

faults will continue to be issued by the LTC3884 until a valid command value is entered. The accuracy of the measured

input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry.

This write-only command has 1 data byte and is formatted in register format.

3884fe

112

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

NVM MEMORY COMMANDS

Store/Restore

CMD

DEFAULT

VALUE

COMMAND NAME

CODE DESCRIPTION

TYPE

PAGED

FORMAT

UNITS

NVM

STORE_USER_ALL

0x15

0x16

0xF0

Store user operating memory to

EEPROM.

Send Byte

N

NA

RESTORE_USER_ALL

Restore user operating memory from Send Byte

EEPROM.

N

NA

MFR_COMPARE_USER_ALL

Compares current command contents Send Byte

with NVM.

STORE_USER_ALL

The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating

Memory to the matching locations in the non-volatile User NVM memory.

Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten-

tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is

disabled. The command is re-enabled when the IC temperature drops below 125°C.

Communication with the LTC3884 and programming of the NVM can be initiated when EXTV or VDD33 is available

CC

and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B

followed by 0xC4. The LTC3884 will now communicate normally, and the project file can be updated. To write the

updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be

issued to allow the PWM to be enabled and valid ADCs to be read.

This write-only command has no data bytes.

RESTORE_USER_ALL

The RESTORE_USER_ALL command instructs the LTC3884 to copy the contents of the non-volatile User memory to

the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value

retrieved from the User commands. The LTC3884 ensures both channels are off, loads the operating memory from

the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both

PWM channels if applicable.

STORE_USER_ALL, MFR_COMPARE_USER_ALLandRESTORE_USER_ALLcommandsaredisabledifthedieexceeds

130°C and are not re-enabled until the die temperature drops below 125°C.

This write-only command has no data bytes.

MFR_COMPARE_USER_ALL

The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with

what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.

This write-only command has no data bytes.

3884fe

113

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Fault Log Operation

A conceptual diagram of the fault log is shown in Figure 50. The fault log provides telemetry recording capability to

the LTC3884. During normal operation, the contents of the status registers, the output voltage readings, temperature

readings as well as peak values of these quantities are stored in a continuously updated buffer in RAM. You can think

of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM

for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log available

for reading at a later time. As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced.

When reading the fault log from RAM, all 6 events of cyclical data remain. However, when the fault log is read from

EEPROM (after a reset), the last 2 events are lost. The read length of 147 bytes remains the same, but the fifth and

sixth events are a repeat of the fourth event.

RAM

EEPROM

8

ꢇꢎꢏ ꢊꢅꢇꢎꢃꢋꢒꢌ

ꢏꢆꢋꢂꢃꢋꢈꢆꢈꢌꢉꢓ

ꢀꢃꢉꢉ ꢑꢈꢀꢀꢅꢊ

ꢂꢃꢄꢅ ꢆꢀ ꢀꢇꢈꢉꢂ

ꢂꢊꢇꢋꢌꢀꢅꢊ ꢂꢆ

ꢅꢅꢍꢊꢆꢄ ꢇꢋꢎ

ꢉꢆꢏꢐ

•

ꢇꢀꢂꢅꢊ ꢀꢇꢈꢉꢂ

ꢊꢅꢇꢎ ꢀꢊꢆꢄ

ꢅꢅꢍꢊꢆꢄ ꢇꢋꢎ

ꢉꢆꢏꢐ ꢑꢈꢀꢀꢅꢊ

3884 ꢀ4ꢁ

Figure 50 . Fault Log Conceptual Diagram

Fault Logging

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

R Block

PAGED FORMAT UNITS NVM

MFR_FAULT_LOG

0xEE

0xEA

Fault log data bytes.

N

CF

Y

NA

MFR_FAULT_LOG_ STORE

Command a transfer of the fault log from RAM Send Byte

to EEPROM.

MFR_FAULT_LOG_CLEAR

0xEC

Initialize the EEPROM block reserved for fault

logging.

Send Byte

N

NA

3884fe

114

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_FAULT_LOG

The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-

rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in

non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this

command are listed in Table 13. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the

command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147

bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may

not contain valid data.

NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.

This read-only command is in block format.

MFR_FAULT_LOG_STORE

The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event

occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in

the MFR_CONFIG_ALL command.

If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature

drops below 125°C.

This write-only command has no data bytes.

Table 13. Fault Logging

This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.

Data Format Definitions

LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1

LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only

BYTE = 8 bits interpreted per definition of this command

DATA

FORMAT BYTE NUM BLOCK READ COMMAND

DATA

BITS

Block Length

BYTE

147

The MFR_FAULT_LOG command is a fixed length of 147 bytes

The block length will be zero if a data log event has not been captured

HEADER INFORMATION

Fault Log Preface

[7:0]

[15:8]

[7:0]

ASC

Reg

0

1

2

Returns LTxx beginning at byte 0 if a partial or complete fault log exists.

Word xx is a factory identifier that may vary part to part.

3

Fault Source

MFR_REAL_TIME

[7:0]

Reg

4

5

Refer to Table 13a.

48 bit share-clock counter value when fault occurred (200µs resolution).

[15:8]

[23:16]

[31:24]

[39:32]

[47:40]

6

7

8

9

10

3884fe

115

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

MFR_VOUT_PEAK (PAGE 0)

MFR_VOUT_PEAK (PAGE 1)

MFR_IOUT_PEAK (PAGE 0)

MFR_IOUT_PEAK (PAGE 1)

[15:8]

L16

L11

11

Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

12

13

Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

14

15

Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

16

17

Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS

command.

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

18

19

20

21

22

23

24

25

26

MFR_VIN_PEAK

L11

Peak READ_VIN since last power-on or CLEAR_PEAKS command.

External temperature sensor 0 during last event.

READ_TEMPERATURE1 (PAGE 0)

READ_TEMPERATURE1 (PAGE 1)

READ_TEMPERATURE2

External temperature sensor 1 during last event.

LTC3884 die temperature sensor during last event.

CYCLICAL DATA

EVENT n

Event “n” represents one complete cycle of ADC reads through the MUX

at time of fault. Example: If the fault occurs when the ADC is processing

step 15, it will continue to take readings through step 25 and then store

the header and all 6 event pages to EEPROM

(Data at Which Fault Occurred; Most Recent Data)

READ_VOUT (PAGE 0)

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

BYTE

3884fe

116

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

EVENT n-1

(data measured before fault was detected)

READ_VOUT (PAGE 0)

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

EVENT n-5

BYTE

(Oldest Recorded Data)

READ_VOUT (PAGE 0)

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

[15:8]

[7:0]

LIN 16

LIN 11

BYTE

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

READ_VOUT (PAGE 1)

READ_IOUT (PAGE 0)

READ_IOUT (PAGE 1)

READ_VIN

READ_IIN

STATUS_VOUT (PAGE 0)

STATUS_VOUT (PAGE 1)

STATUS_WORD (PAGE 0)

BYTE

[15:8]

[7:0]

[15:8]

[7:0]

WORD

BYTE

STATUS_WORD (PAGE 1)

STATUS_MFR_SPECIFIC (PAGE 0)

STATUS_MFR_SPECIFIC (PAGE 1)

BYTE

3884fe

117

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PMBus COMMAND DETAILS

Table 13a: Explanation of Position_Fault Values

POSITION_FAULT VALUE

SOURCE OF FAULT LOG

0xFF

0x00

0x01

0x02

0x03

0x05

0x06

0x07

0x0A

0x10

0x11

MFR_FAULT_LOG_STORE

TON_MAX_FAULT Channel 0

VOUT_OV_FAULT Channel 0

VOUT_UV_FAULT Channel 0

IOUT_OC_FAULT Channel 0

TEMP_OT_FAULT Channel 0

TEMP_UT_FAULT Channel 0

VIN_OV_FAULT

MFR_TEMPERATURE_2_OT_FAULT

TON_MAX_FAULT Channel 1

VOUT_OV_FAULT Channel 1

MFR_FAULT_LOG_CLEAR

The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the

STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.

This write-only command is send bytes.

Block Memory Write/Read

DATA

DEFAULT

VALUE

COMMAND NAME

CMD CODE DESCRIPTION

TYPE

PAGED FORMAT UNITS NVM

MFR_EE_UNLOCK

0xBD

0xBE

0xBF

Unlock user EEPROM for access by MFR_EE_ERASE

R/W Byte

N

Reg

NA

and MFR_EE_DATA commands.

MFR_EE_ERASE

MFR_EE_DATA

Initialize user EEPROM for bulk programming by

MFR_EE_DATA.

R/W Byte

Data transferred to and from EEPROM using

sequential PMBus word reads or writes. Supports bulk

programming.

R/W

Word

All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the

die temperature drops below 125°C.

MFR_EE_xxxx

The MFR_EE_xxxx commands facilitate bulk programming of the LTC3884 internal EEPROM. Contact the factory for

details.

3884fe

118

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

3884fe

119

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

3884fe

120

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

ꢀꢁꢂ

1Ω

1%

2mΩ

ꢀ

ꢁꢂ

ꢃꢀ ꢄꢅ ꢆ4ꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃꢄ

2mΩ

ꢀꢁ

4ꢀꢁꢂꢃ

ꢀꢁ

ꢅꢆꢇ

ꢈꢀ

ꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢄꢄ

ꢁꢂ

ꢀꢁ

ꢂꢃꢄꢅꢆ

ꢀꢁ

ꢀꢁꢂ8ꢃꢄ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ3ꢄꢅꢆꢄꢇꢁ

ꢀꢁꢂꢃꢄ4ꢅꢆꢄꢇꢁ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

SER2009-681ML

DCR=0.63 mΩ

SER2010-901ML

DCR=0.9 mΩ

ꢀ3

ꢀ4

ꢀꢁꢂ

4ꢀꢁꢁꢂ

ꢀꢁꢂ3884

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀꢁꢂꢂꢃꢄ

ꢀ

ꢁꢁꢂꢃ

ꢀꢁꢂꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ4ꢁꢂꢃ

4ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂꢃꢄ

976Ω

1%

ꢀꢁꢂ

ꢀ

ꢁꢁ33

ALERT

FAULT0

FAULT1

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ8ꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄꢅꢀꢆ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂꢃ

ꢄꢄ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢀꢀꢁꢂꢃ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢀ

ꢅ

ꢁꢂꢃꢄ

ꢅ

ꢁꢂꢃꢁꢂꢄ

3ꢅ3ꢀꢆꢇꢈꢉ

ꢅꢆꢇꢀꢈꢅꢇꢉ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢁꢂꢃꢁꢂꢄ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

ꢇꢈ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢆꢇ

ꢀꢁꢂꢁꢃ

ꢀꢁꢂꢃꢄ

ꢆꢇ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄ

ꢀ

ꢇꢈ

ꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄ

ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢀ

ꢁꢁ33 ꢀꢀꢁꢂ

ꢀꢁꢂꢂꢃꢄ

ꢀꢀꢁꢂ3ꢃꢄꢅꢆꢇꢈ3ꢆꢉ

ꢀ

3884

ꢀ

ꢁꢁꢂꢃ

ꢁꢁ33

ꢀꢁꢂ

ꢀꢁꢀꢂꢃ

ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢀꢇꢈ3ꢉꢊꢋ

High Efficiency, 425kHz, Dual-Output, 2.5V/25A and 3.3V/25A Buck Converter

3884fe

121

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

ꢀ3

ꢀꢁꢂ

1Ω

1%

2mΩ

ꢀ

ꢁꢂ

ꢃꢄꢀ ꢅꢆ ꢃ4ꢀ

ꢀꢁꢂꢃꢄ

ꢅꢆꢇ

ꢈꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

4ꢀꢁꢂꢃ

2mΩ

ꢀꢁ

ꢂ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢄꢄ

ꢁꢂ

ꢀꢁ

ꢁꢂꢃ

ꢀꢁ

ꢂꢃꢄ

ꢀꢁ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ4ꢅꢆꢄꢇꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢄ4ꢅꢆꢄꢇꢁ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢅꢆꢅꢄꢃꢇꢈ

DCR=1.2 mΩ

ꢀ4

ꢀ3

ꢀꢁꢂ

ꢀꢁꢂ3884

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ

4ꢀꢁꢁꢂ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ

ꢀꢁꢂꢃ

ꢀꢁꢂꢂꢃꢄ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢂꢃꢄ

ꢀꢀꢁꢂ

ꢀ

ꢅꢆꢇꢈ

ꢀꢁꢂ

ꢁꢂꢃꢄ

ꢀꢁꢂ

3ꢀꢁꢂꢃ

ꢀ4ꢁꢂꢃ

ꢀꢁꢂ

3ꢀꢁ4ꢂ

ꢃꢄ

ꢀꢁꢂ

ꢀ

ꢅꢆꢇꢈ

ꢁꢂꢃꢄ

ꢀ

ꢁꢁ33

ALERT

FAULT0

FAULT1

ꢀꢁꢂꢃꢄꢅꢀꢆ

3ꢀꢁ4ꢂ

ꢃꢄ

ꢀꢁꢂꢃꢄ

ꢀ3ꢁꢀꢂ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃ

ꢀꢁ

ꢅ

ꢀꢁꢂꢃ

ꢄꢄ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢀꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢄꢅꢆꢀꢇꢈꢆꢉ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢀ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢆꢇ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

ꢇꢈ

ꢁꢂꢃꢁꢂꢄ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

ꢇꢈ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢆꢇ

ꢀꢁꢂꢁꢃ

ꢀꢁꢂꢃꢄ

ꢀ

ꢀꢁꢂꢃ

ꢁꢂꢃ

ꢀꢁꢂꢃ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢁꢂꢃꢄ

ꢀ

ꢀꢀꢁꢂ

ꢀꢀꢁꢂ3ꢃꢄꢅꢆꢇꢈ3ꢆꢉ

3ꢀ3ꢁꢂ

ꢀꢀꢁꢂ3ꢃꢄꢅꢆꢇꢈ3ꢆꢉ

ꢀ

ꢀꢁꢂꢃ ꢀꢁꢂꢃ

ꢁꢁ33

ꢀ

ꢁꢁ33

ꢀꢀꢁꢂ

ꢀꢁꢀꢂꢃ

ꢀꢁꢂ

3884 ꢀꢁꢂ8

ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢀꢇꢈ3ꢉꢊꢋ

Low DCR Sensing, 250 kHz, Single-Output, 5V/60 A Buck Converter

3884fe

122

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

3884fe

123

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATIONS

1mΩ

0.47µF

0Ω

V

IN1

665Ω

BOOT

1Ω

V

IN

7V TO 14V

V

IN1

V

IN

PHASE

4.7µF

0.215µH, L1

V

OUT

22µF

TDA21470

1.05V

120A

SW

2.2µF

×4

C

OUT2

OUT1

+

–

+

V

I

INTV

IN IN

IN CC

100µF

×3

470µF

×2

EN

PWM

+

V

PWM0

OS

OUT

SENSE0

SENSE1

SENSE0

SENSE1

6.3V

2.5V

+

I

T

/FLT

OUT

SENSE0

V

DRV

220nF

V

DR

5V

–

PGND

V

CC

I

SENSE0

LGND

–

4.7µF

330pF

SENSE1

10nF

4.7µF

WP

+

I

SENSE1

TSNS0

TSNS1

LTC3884-1

5k

SDA

SCL

PWM1

0.47µF

0Ω

I

TH

TH0

665Ω

5k

I

6.8nF

TH1

330pF

SHARE_CLK

BOOT

I

THR0

THR1

DD25

ALERT

V

PHASE

IN1

IN

0.215µH, L2

22µF

TDA21470

V

DD33

SW

×4

V

C

OUT4

OUT3

+

V

CC0

100µF

×3

470µF

×2

EN

PWM

24.9k 24.9k 24.9k

1µF

V

0_CFG

1_CFG

ASEL1

OUT

CC1

4.7µF

V

OS

5k

6.3V

2.5V

FAULT0

OUT

T

/FLT

V

OUT

DRV

FAULT1

RUN0

V

DR

5V

PGND

V

CC

FREQ_CFG

ASEL0

LGND

4.7µF

330pF

RUN1

7.32k 5.76k 5.76k

4.7µF

SYNC

PGOOD0

EXTV

CC

5k

PGOOD1

PHASE_CFG

GND

0.47µF

0Ω

2Ω

V

IN

7V TO 14V

BOOT

V

INTV

PHASM0

LTC3874-1

IN

CC

V

IN1

V

PHASE

4.7µF

IN

0.1µF

0.215µH, L3

RUN0

22µF

×4

TDA21470

SW

RUN1

ILIM

C

OUT6

OUT5

+

100µF

470µF

×2

SYNC

LOWDCR

EN

×3

6.3V

V

PWM

MODE0

MODE1

PWM0

+

OS

2.5V

I

T

/FLT

V

SENSE0

OUT

DRV

220nF

V

DR

5V

–

PGND

V

CC

I

SENSE0

LGND

FAULT0

FAULT1

330pF

4.7µF

PWM1

+

4.7µF

V

I

CC0

CC1

SENSE1

665Ω

220nF

V

DD33_1

1µF

–

I

SENSE1

I

TH

TH0

TH1

100k

47pF

I

FREQ

GND

0.47µF

0Ω

EXTV

CC

BOOT

V

IN1

V

PHASE

IN

0.215µH, L4

22µF

×4

TDA21470

SW

C

OUT8

OUT7

+

100µF

×3

470µF

×2

EN

V

OS

PWM

6.3V

2.5V

PINS NOT USED IN CIRCUITS TDA21470: REFIN , GATEL, I , OCSET

OUT

T

/FLT

V

OUT

DRV

COUT1, 3, 5, 7: MURATA GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)

COUT2, 4, 6, 8: PANASONIC ETPF470M5H (470µF, 2.5V)

V

DR

5V

PGND

V

CC

3884 TA10

LGND

L1, L2, L3, L4: EATON FP1007R3-R22-R (0.215µH, DCR = 0.29mΩ)

330pF

4.7µF

V

DR

FROM EXTERNAL 5V POWER SUPPLY

4.7µF

665Ω

Low DCR Sensing, 50 0 kHz 4-Phase 1.0 5 Step-Down Converter

3884fe

124

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3884#packaging for the most recent package drawings.

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ704 Rev C)

0.70 0.05

5.ꢀ5 0.05

5.50 REF

6.ꢀ0 0.05 7.50 0.05

(4 SIDES)

5.ꢀ5 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.ꢀꢀ5

TYP

7.00 0.ꢀ0

(4 SIDES)

R = 0.ꢀ0

TYP

47 48

0.40 0.ꢀ0

PIN ꢀ TOP MARK

(SEE NOTE 6)

ꢀ

2

PIN ꢀ

CHAMFER

C = 0.35

5.ꢀ5 0.ꢀ0

5.50 REF

(4-SIDES)

5.ꢀ5 0.ꢀ0

(UK48) QFN 0406 REV C

0.200 REF

0.25 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE

3884fe

125

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC3884#packaging for the most recent package drawings.

RHE Package

48-Lead Plastic GQFN (5mm × 6mm)

ꢘꢊefeꢫeꢬꢭe ꢕꢆꢑ ꢉꢌꢎ ꢮ ꢂꢀꢯꢂ8ꢯꢃꢀꢖꢩ ꢊeꢰ ꢟꢚ

ꢂꢁꢙꢂ

ꢂꢁꢀꢀ

ꢖꢁꢙꢂ

±ꢂꢁꢃꢂ

ꢂꢁꢖꢂ ꢂꢁꢂꢀ

ꢂꢁ4ꢂ ꢟꢏꢑ

3ꢁꢙꢂ ±ꢂꢁꢂꢀ

ꢂꢁ8ꢂ

ꢃꢁꢥꢂ

±ꢂꢁꢃꢂ

ꢂꢁ8ꢀ ꢪ ꢃꢁꢃꢂ

ꢘꢪ4ꢚ

ꢂꢁꢖꢀ

ꢒꢋꢑꢓꢋꢎꢇ

ꢅꢔꢆꢕꢍꢄꢇ

ꢀꢁꢖꢂ ±ꢂꢁꢂꢀ

ꢊꢇꢑꢅꢗꢗꢇꢄꢉꢇꢉ ꢏꢅꢕꢉꢇꢊ ꢒꢋꢉ ꢕꢋꢛꢅꢔꢆ

ꢋꢒꢒꢕꢛ ꢏꢅꢕꢉꢇꢊ ꢗꢋꢏꢓ ꢆꢅ ꢋꢊꢇꢋꢏ ꢆꢜꢋꢆ ꢋꢊꢇ ꢄꢅꢆ ꢏꢅꢕꢉꢇꢊꢇꢉ

ꢒꢍꢄ ꢃ ꢄꢅꢆꢑꢜ

ꢂꢁ3ꢀ × 4ꢀ°

ꢑꢜꢋꢗꢝꢇꢊ

ꢃꢁꢂꢂ ꢊꢇꢝ

ꢂꢁ8ꢂ ꢊꢇꢝ

ꢀꢁꢂꢂ ±ꢂꢁꢃꢂ

3ꢥ

48

38

ꢃ

ꢒꢍꢄ ꢃ

ꢂꢁꢀꢀ

ꢊꢇꢝ

ꢆꢅꢒ ꢗꢋꢊꢓ

ꢘꢏꢇꢇ ꢄꢅꢆꢇ ꢙꢚ

ꢃꢁꢃꢂ ꢪ ꢂꢁ8ꢀ

ꢘꢪ4ꢚ

ꢂꢁꢖꢀ ꢊꢇꢝ

ꢃꢁꢥꢂ

±ꢂꢁꢃꢂ

ꢙꢁꢂꢂ ±ꢂꢁꢃꢂ

ꢂꢁꢖꢀ

ꢊꢇꢝ

ꢖꢁꢙꢂ

±ꢂꢁꢃꢂ

ꢂꢁ4ꢂ

ꢟꢏꢑ

ꢂꢁ8ꢀ

ꢂꢁꢃꢂ

ꢂꢁꢖꢂ

ꢂꢁꢂꢀ

ꢂꢁ8ꢂ ꢊꢇꢝ

ꢖ4

ꢃ4

ꢘꢊꢜꢇ48ꢚ ꢎꢨꢝꢄ ꢂꢙꢃꢩ ꢊꢇꢦ ꢟ

ꢖ4

ꢃꢀ

ꢃꢁꢃꢂ ꢂꢁꢃꢂ

ꢟꢅꢆꢆꢅꢗ ꢦꢍꢇꢌꢧꢇꢞꢒꢅꢏꢇꢉ ꢒꢋꢉ

ꢃꢁꢂꢂ ꢊꢇꢝ

ꢂꢁ4ꢂ ꢂꢁꢃꢂ

ꢂꢁꢙꢀ ±ꢂꢁꢂꢀ

ꢄꢅꢆꢇꢈ

ꢃꢁ ꢉꢊꢋꢌꢍꢄꢎ ꢍꢏ ꢄꢅꢆ ꢋ ꢐꢇꢉꢇꢑ ꢒꢋꢑꢓꢋꢎꢇ ꢅꢔꢆꢕꢍꢄꢇ

ꢖꢁ ꢉꢊꢋꢌꢍꢄꢎ ꢄꢅꢆ ꢆꢅ ꢏꢑꢋꢕꢇ

4ꢁ ꢉꢍꢗꢇꢄꢏꢍꢅꢄꢏ ꢅꢝ ꢇꢞꢒꢅꢏꢇꢉ ꢒꢋꢉ ꢅꢄ ꢟꢅꢆꢆꢅꢗ ꢅꢝ ꢒꢋꢑꢓꢋꢎꢇ ꢉꢅ ꢄꢅꢆ ꢍꢄꢑꢕꢔꢉꢇ

ꢗꢅꢕꢉ ꢝꢕꢋꢏꢜꢁ ꢗꢅꢕꢉ ꢝꢕꢋꢏꢜꢠ ꢍꢝ ꢒꢊꢇꢏꢇꢄꢆꢠ ꢏꢜꢋꢕꢕ ꢄꢅꢆ ꢇꢞꢑꢇꢇꢉ ꢂꢁꢖꢀꢡꢡ ꢅꢄ ꢋꢄꢛ ꢏꢍꢉꢇ

ꢀꢁ ꢇꢞꢒꢅꢏꢇꢉ ꢒꢋꢉ ꢏꢜꢋꢕꢕ ꢟꢇ ꢒꢢ ꢄꢣ ꢋꢤ ꢒꢕꢋꢆꢇꢉ

3ꢁ ꢋꢕꢕ ꢉꢍꢗꢇꢄꢏꢍꢅꢄꢏ ꢋꢊꢇ ꢍꢄ ꢗꢍꢕꢕꢍꢗꢇꢆꢇꢊꢏ

ꢙꢁ ꢏꢜꢋꢉꢇꢉ ꢋꢊꢇꢋ ꢍꢏ ꢅꢄꢕꢛ ꢋ ꢊꢇꢝꢇꢊꢇꢄꢑꢇ ꢝꢅꢊ ꢒꢍꢄ ꢃ ꢕꢅꢑꢋꢆꢍꢅꢄ

3884fe

126

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

REVISION HISTORY

REV

DATE

11/15 Added Note 19.

Changed operation default value.

Corrected top mark.

DESCRIPTION

PAGE NUMBER

A

10

38, 73

4

B

2/16

Modified I – switch circuitry.

17

IN

C

D

5/17

9/17

Added ECC.

All

Added LTC3884-1 part numbers and RHE package option.

1, 4, 5, 7, 11,

17, 18, 20, 22,

51, 56, 61,

124, 126

Added conditions and change limits for PWM.

7

Temp dotted t

10

SU(DAT).

E

11/17 Changed package type description from QFN to GQFN.

1, 5

3884fe

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

127

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.linear.com/LTC3884

LTC3884/LTC3884-1

TYPICAL APPLICATION

ꢀ3

ꢀꢁꢂ

1Ω

1%

2mΩ

ꢀ

ꢁꢂ

ꢃꢀ ꢄꢅ ꢆ4ꢀ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃ

ꢄꢅ

ꢀꢁꢂꢃꢄ

ꢅꢆꢇ

ꢈꢀ

4ꢀꢁꢂꢃ

ꢀꢁ

ꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀ

ꢀꢁ

ꢀ

ꢀꢁ

ꢁꢂ

ꢀꢁ

ꢂꢃꢄꢅꢆꢇ

ꢀꢁꢂ

ꢀꢁ

ꢂꢃꢁꢄꢅꢆ

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁ

ꢀꢁꢂꢃꢄ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀꢁꢁꢂꢃꢄ

ꢀꢁꢂ

ꢀ443ꢁꢂꢁꢃꢄ

DCR=0.32mΩ

ꢀ443ꢁꢂꢁꢃꢄ

DCR=0.32mΩ

ꢀ3

ꢀ4

ꢀꢁꢂ

ꢀꢁꢂ3884

ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢁꢉ

4ꢀꢁꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ

ꢀꢁꢂꢂꢃꢄ

ꢀꢁꢂ

ꢀꢀꢁꢂ

ꢀ

ꢀꢁꢂꢃ

ꢀꢁꢂ

ꢀ4ꢁꢂꢃ ꢀ4ꢁꢂꢃ

ꢀꢁꢂ

715Ω

1%

ꢀ

ꢀꢁꢂꢃ

715Ω

1%

ꢀꢁꢂꢃꢄꢅꢀꢆ

ꢀ

ꢁꢁ33

ALERT

ꢀꢀꢁ

4ꢀ3ꢁꢂ ꢀꢁꢂꢃꢄ

FAULT0

FAULT1

ꢀꢁꢂꢃꢄꢅꢆꢇꢈ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢄꢄ

ꢀꢁꢂ

ꢀꢁꢂꢃ

ꢀꢁ

ꢀꢁꢂꢃꢄ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢀꢀꢁꢂꢃ

ꢅ

ꢁꢂꢃꢁꢂꢄ

ꢅ

ꢀ

ꢁꢂꢃꢁꢂꢄ

ꢅ

ꢀ

ꢁꢂꢃ

ꢄꢅꢆꢀꢇꢈꢉꢊ

ꢁꢂꢃꢁꢂꢄ

ꢆ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢆꢇ

33ꢀꢁꢂ

ꢃꢄ3ꢅ

ꢆꢇ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

ꢇꢈ

ꢀꢁꢁꢂꢃ

ꢄꢅ3ꢆ

ꢇꢈ

ꢁꢂꢃꢁꢂꢄ

ꢇꢁꢃꢁꢄ

ꢈ

ꢇꢉꢄ

ꢈ

ꢇꢉꢄ

ꢈ

ꢇꢉꢊꢄ

ꢀ

ꢇꢉꢊꢄ

ꢀꢁꢂꢃ

ꢀ

ꢀꢁꢂꢃ ꢀꢁꢂꢃ

ꢁꢁ33

ꢁꢁꢂꢃ

ꢀꢀꢁꢂ3ꢃꢄꢅꢆꢇꢈ3ꢆꢉ

ꢀꢁꢂꢃꢄ

ꢀꢀꢁꢂ3ꢃꢄꢅꢆꢇꢈ3ꢆꢉ

ꢀ

ꢁꢁ33

ꢀꢀꢁꢂ

3ꢀ3ꢁꢂ

ꢀꢁꢂ

ꢀꢁꢀꢂꢃ

3884 ꢀꢁꢂꢂ

ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢀꢇꢈ3ꢉꢊꢋ

Low DCR Sensing, 425kHz, Single-Output, 1.2V/60 A Buck Converter

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

4.5V ≤ V ≤17V; 0.5V ≤ V

2

LTM4676A

LTM4675

LTM4677

Dual 13A or Single 26A Step-Down DC/DC µModule

( 0.5%) ≤ 5.5V, I C/PMBus Interface,

OUT

IN

Regulator with Digital Power System Management

16mm × 16mm × 5mm, BGA Package

2

Dual 9A or Single 18A μModule Regulator with Digital

Power System Management

4.5V ≤ V ≤17V; 0.5V ≤ V ( 0.5%) ≤ 5.5V, I C/PMBus Interface,

IN

OUT

11.9mm × 16mm × 5mm, BGA Package

2

Dual 18A or Single 36A µModule Regulator with Digital

Power System Management

4.5V ≤ V ≤ 16V; 0.5V ≤ V ( 0.5%) ≤ 1.8V, I C/PMBus Interface,

IN

OUT

16mm × 16mm × 5.01mm, BGA Package

Multiphase Step-Down Synchronous Slave Controller with 4.5V ≤ V ≤ 38V, V up to 5.5V, Very High Output Current, Accurate

IN OUT

LTC3874/

LTC3874-1

Sub MilliOhm DCR Sensing Current Sharing, Current Mode Applications

Dual Output Multiphase Step-Down DC/DC Controller with 4.5V ≤ V ≤ 24V, 0.5V ≤ V ( 0.5%) ≤ 5.5V, I C/PMBus Interface,

IN OUT0,1

2

LTC3887/

LTC3887-1

Digital Power System Management, 30mS Start-Up

–1 Version uses DrMOS or Power Blocks

2

LTC3882/

Dual Output Multiphase Step-Down DC/DC Voltage Mode

Controller with Digital Power System Management

3V ≤ V ≤ 38V, 0.5V ≤ V ≤ 5.25V, ( 0.5%) V

Accuracy I C/

IN

OUT1,2

OUT

2

LTC3882-1

PMBus Interface, uses DrMOS or Power Blocks

LTC3886

LTC3815

60V Dual Output Step-Down Controller with Digital Power

System Management

4.5V ≤ V ≤ 60V, 0.5V ≤ V

( 0.5%) ≤ 13.8V, I C/PMBus Interface,

IN

OUT0,1

Input Current Sense

6A Monolithic Synchronous DC/DC Step-Down Converter

with Digital Power System Management

2.25V ≤ V ≤ 5.5V, 0.4V ≤ V

≤ 0.72V , Programmable V

Range

IN

OUT

IN

OUT

25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC

Licensed under U.S. Patent 7000125 and other related patents worldwide.

3884fe

LT 1117 REV E • PRINTED IN USA

www.linear.com/LTC3884

128

 ANALOG DEVICES, INC. 2017

For more information www.linear.com/LTC3884


型号：	LTC3884
厂家：	Linear
描述：	Dual Output PolyPhase Step-Down Controller with Sub-Milliohm DCR Sensing and Digital Power System Management
文件：	总128页 (文件大小：4052K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3884 [Linear]

相关型号：

LTC3884-1

LTC3886

LTC3886-1

LTC3886EUKG#PBF

LTC3886IUKG

LTC3887

LTC3887-1

LTC3887EUJ#PBF

LTC3887IUJ#PBF

LTC3888

LTC3888-1

LTC3888-2