LTC4211IMS#TRPBF_技术文档

LTC4222

Dual Hot Swap Controller

2

with I C Compatible

Monitoring

FEATURES

DESCRIPTION

The LTC^®4222 Hot Swap™ controller allows two power

paths to be safely inserted and removed from a live back-

plane. Using external N-channel pass transistors, board

supply voltages and inrush currents are ramped up at an

adjustable rate. An I C interface and onboard ADC allows

for monitoring of current, voltage and fault status for

each channel.

n

Allows Safe Insertion Into a Live Backplane

n

10-Bit ADC Monitors Currents and Voltages

2

n

I C/SMBus Interface

n

Wide Operating Voltage Range: 2.9V to 29V

2

n

dI/dt Controlled Soft-Start

n

High Side Drive for External N-Channel MOSFETs

n

No External Gate Capacitors Required

n

Input Overvoltage/Undervoltage Protection

The device features adjustable, analog, foldback current

limit circuits and a soft-start circuit that sets the dI/dt of

the inrush currents. An I C interface may conﬁgure the

part to latch off or automatically restart after the LTC4222

detects a fault on either channel.

n

Optional Latchoff or Auto-Retry After Faults

n

Alert Host After Faults

2

n

Inrush Current Limit with Foldback

n

Available in 32-Pin (5mm × 5mm) QFN

and 36-Pin SSOP Packages

The controller has additional features to interrupt the host

when a fault has occurred, notify when output power is

good, detect insertion of a load card and power-up either

APPLICATIONS

n

Live Board Insertion

2

automatically upon insertion or wait for an I C command

n

Electronic Circuit Breakers

to turn on.

n

Computers, Servers

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot

Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners. Protected by U.S. Patents including 7330065.

n

Platform Management

TYPICAL APPLICATION

Advanced Mezzanine Card Application

6mΩ

Si7336ADP

12V

7.4A

12V

34k

10.2k

3.57k

10Ω

–

0.1µF

Start-Up Waveform with Sequencing

10k

1.02k

UV1

OV1

ON

SDA

SCL

V

SENSE1 GATE1 SOURCE1

DD1

3.4k

FB1

GPIO1

EN1

V

IN1/2

10V/DIV

12PGOOD

ON

SDA

SCL

ADIN1

CONTACT

BOUNCE

ALERT

TIMER

V

OUT2

10V/DIV

CONFIG

ADR0

ADR1

ADR2

1µF

LTC4222

NC

SS

V

OUT1

68nF

10V/DIV

ADIN2

INTV

CC

0.1µF

EN2

GPIO

PGOOD

10V/DIV

GND

OV2

UV2

GPIO2

FB2

AUXPGOOD

3.4k

–

V

DD2

SENSE2 GATE2 SOURCE2

4222 TA01b

1.02k

50ms/DIV

3.57k

4.99k

10Ω

10nF

10k

0.1µF

3.3V

6.55k

3.3V

150mA

Si1046R

300mΩ

BACKPLANE PLUG-IN

CARD

4222 TA01a

4222fb

1

LTC4222

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1, 2)}

Supply Voltages (V ).............................. –0.3V to 35V

ADINn, CONFIG...................................... –0.3V to 12V

ALERT, SCL, SDA, SDAI, SDAO............ –0.3V to 6.5V

Output Voltages

GATEn, GPIOn........................................ –0.3V to 35V

Operating Temperature Range

DDn

Supply Voltage (INTV )........................... –0.3V to 6.5V

CC

Input Voltages

GATEn – SOURCEn (Note 3).................... –0.3V to 5V

+

–

SENSE n..........................V

– 6.5V to V

+ 0.3V

DDn

+

SENSE n.............................–0.3V to SENSE n + 0.3V

SOURCEn.................................................. –5V to 35V

LTC4222C ................................................ 0°C to 70°C

LTC4222I..............................................–40°C to 85°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

+

UVn.....................................–0.3V to SENSE n + 0.3V

ENn, FBn, ON, OVn ................................ –0.3V to 12V

ADR0-2, TIMER, SS...............–0.3V to INTV + 0.3V

SSOP ................................................................ 300°C

CC

PIN CONFIGURATION

TOP VIEW

–

1

2

GATE1

SOURCE1

FB1

36

25

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

SENSE1

TOP VIEW

+

3

V

DD1

4

GPIO1

EN1

UV1

OV1

32 31 30 29 28 27 26 25

5

SS

1

2

3

4

5

6

7

8

24 EN1

6

ADIN1

ON1

SS

CONFIG

23 ADIN1

7

CONFIG

INTV

CC

ON

22

21

8

ON2

INTV

CC

GND

ADR0

ADR1

ADR2

TIMER

ALERT

9

ALERT

SCL

GND

ADR0

ADR1

ADR2

TIMER

OV2

33

20 SCL

SDA

10

11

12

13

14

15

16

17

18

19

SDAI

18 ADIN2

SDAO

ADIN2

EN2

17 EN2

9

10 11 12 13 14 15 16

GPIO2

FB2

UV2

V

DD2

+

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

SOURCE2

GATE2

SENSE2

–

T

= 125°C, θ = 34°C/W

JA

JMAX

EXPOSED PAD (PIN 33), PCB GND CONNECTION OPTIONAL

G PACKAGE

36-LEAD PLASTIC SSOP

= 125°C, θ = 95°C/W

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC4222CG#PBF

LTC4222IG#PBF

LTC4222CUH#PBF

LTC4222IUH#PBF

TAPE AND REEL

PART MARKING*

LTC4222CG

LTC4222IG

LTC4222

PACKAGE DESCRIPTION

36-Lead Plastic SSOP

32-Lead (5mm × 5mm) Plastic QFN

TEMPERATURE RANGE

0°C to 70°C

–40°C to 85°C

0°C to 70°C

LTC4222CG#TRPBF

LTC4222IG#TRPBF

LTC4222CUH#TRPBF

LTC4222IUH#TRPBF

LTC4222

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

4222fb

2

LTC4222

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Input Supply Range

2.9

29

V

mA

V

DDn

DD1

DD2

I

V

Input Supply Current

V

= 12V

0.85

3

1.25

4.5

DD1

DD2

DD1

= 12V, I

= 0mA

DD2

INTVCC

V

Input Supply Undervoltage Lockout

Rising

DD

2.34

60

2.43

80

2.53

100

DDn(UVL)

V

Input Supply Undervoltage Lockout

Hysteresis

mV

DDn(HYST)

l

INTV

Internal Regulator Voltage

I

= 0mA

3.15

2.55

35

3.3

2.64

50

3.45

2.73

65

V

CC

INTVCC

INTV Undervoltage Lockout

INTV Rising

CC

CC(UVL)

CC(HYST)

CC

INTV Undervoltage Lockout Hysteresis

mV

CC

Current Limit and Circuit Breaker (Both Channels)

l

Circuit Breaker Threshold (V – V

)

47.5

48.75

50

52.5

51.25

mV

∆V

SENSE(TH)

DD

SENSE

l

Current Limit Voltage (V – V

)

V

= 1.3V

= 0V

46

14

130

50

16.6

150

54

19

165

mV

∆V

SENSE

DD

SENSE

FB

Start-Up Timer Expired

l

t

OC Fault Filter

10

0

20

30

45

µs

∆V

= 100mV

D(OC)

SENSE

+

–

I

SENSE /SENSE Pin Input Current

V

= 12V

SENSE

µA

SENSE(IN)

Gate Drive

l

∆V

External N-Channel Gate Drive

= 2.9V to 29V

DD

4.7

5.9

6.5

V

GATE

(V

GATE

– V

) (Note 3)

SOURCE

l

I

External N-Channel Gate Pull-Up Current

External N-Channel Gate Pull-Down Current

Gate On, V

Gate Off, V

= 0V

–8

–12

1

–18

2.0

µA

mA

GATE(UP)

GATE(DN)

GATE(LIM)

GATE

= 15V

0.8

GATE

Pull-Down Current from GATE to SOURCE

During OC/UVLO

V

GATE

= 15V, (V – V )n = 200mV

SENSE

450

DD

l

t

(V – SENSE) High to GATE Low

V

– SENSE = 200mV, C = 10nF

GATE

0.5

4.3

1

µs

V

PHL(SENSE)

DD

V

(GATE-SOURCE) Voltage for Power Bad Fault

= 2.9V to 29V

3.8

4.7

GS(POWERBAD)

SOURCE

Comparator Inputs

l

V

CONFIG, EN, FB, ON, OV and UV Input

Threshold

V

Rising

1.215

1.235

1.255

V

INPUT(TH)

IN

l

CONFIG, EN, ON Hysteresis

FB Power Good Hysteresis

OV Hysteresis

80

2

128

7

180

20

mV

µA

V

∆V

CONFIG,EN,ON(HYST)

FB(HYST)

16

60

24

90

0

32

OV(HYST)

UV Hysteresis

110

1

UV(HYST)

I

CONFIG, FB, ON, OV and UV Input Current

EN Pull-Up Current

V

= 3V

= 0V

(IN)

EN(UP)

IN

5

10

0.4

125

1

20

EN

UV

V

UV Reset Threshold Voltage

UV Reset Threshold Hysteresis

GPIO Input Threshold

Falling

0.36

60

0.46

180

1.2

UV(RTH)

mV

V

∆V

UV(RHYST)

GPIO(TH)

V

GPIO

Rising

0.8

4222fb

3

LTC4222

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Other Pin Functions

l

V

GPIO Output Low Voltage

GPIO Input Leakage Current

SOURCE Input Current

I

= 5mA

= 15V

0.25

0

0.4

1

V

µA

µs

GPIO(OL)

GPIO(OH)

SOURCE

P(GATE)

GPIO

I

t

V

GPIO

SOURCE = 15V

70

115

3

170

5

Input (ON, OV, UV, EN) to GATE Off

Propagation Delay

l

t

GATE Turn-On Delay

ON

4

100

5

8

125

6.7

µs

ms

s

D(GATE)

UV, OV, EN

75

4.2

Overcurrent Auto-Retry

l

V

TIMER Low Threshold

TIMER High Threshold

TIMER Pull-Up Current

0.18

1.215

90

0.2

1.235

100

0.22

1.260

110

V

TIMERL(TH)

TIMERH(TH)

TIMER(UP)

I

µA

TIMER Pull-Down Current for OC

Auto-Retry

1.6

2.15

2.6

TIMER(DOWN)

l

I

TIMER Pin OC Auto-Retry Duty Cycle

Soft-Start Ramp Pull-Up Current

38

50

58

N/A

TIMER(UP/DOWN)

l

Ramping

Waiting for GATE to Slew

7.5

0.5

10

0.75

12.5

0.95

µA

SS

ADC

l

RES

Resolution (No Missing Codes)

10

Bits

V

Full-Scale Voltage (1023 • V

)

LSB

(V – SENSE)

64

32

1.28

mV

V

FS

DD

SOURCE

ADIN

LSB

LSB Step Size

(V – SENSE)

62.5

31.25

1.25

µV

mV

DD

SOURCE

ADIN

l

V

Offset Error

(V – SENSE)

3

2

LSB

OS

DD

SOURCE

ADIN

l

INL

Integral Nonlinearity

(Note 5)

0.5

LSB

l

TUE

Total Unadjusted Error/Full-Scale Error

(V – SENSE)

1.5

1

%

DD

SOURCE

ADIN

l

R

ADIN Sampling Resistance

ADIN Input Current

Conversion Rate

V

= 1.28V

1

2

0

MΩ

µA

ADIN

I

V

0.1

ADIN

15

Hz

4222fb

4

LTC4222

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_DD= 12V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C Interface

l

V

ADR0, ADR1, ADR2 Input High Voltage

ADR0, ADR1, ADR2 Hi-Z Input Current

INTV

CC

V

ADR(H)

CC

– 0.8

– 0.4

– 0.2

I

ADR0, ADR1, ADR2 = 0.8V,

5

0

–5

µA

ADR(IN,Z)

INTV – 0.8V

CC

l

V

ADR0, ADR1, ADR2 Input Low Voltage

ADR0, ADR1, ADR2 Input Current

ALERT Output Low Voltage

ALERT Input Current

0.2

0.4

0.2

1.7

0.2

0.8

80

0.4

1

V

µA

V

ADR(L)

I

ADR0, ADR1, ADR2 = 0V, INTV

–80

ADR(IN)

CC

V

I

= 3mA

ALERT(OL)

ALERT(OH)

ALERT

I

ALERT = INTV

µA

V

CC

V

SDA, SCL Input Threshold

SDA, SCL Input Current

1.5

1.9

1

SDA,SCL(TH)

SDA,SCL(OH)

I

SCL, SDA = INTV

µA

V

CC

V

SDA Output Low Voltage

I

= 3mA

0.4

SDA(OL)

SDA

2

I C Interface Timing

f

t

SCL Clock Frequency

Operates with f

≤ f

SCL(MAX)

400

1000

0.12

100

30

kHz

µs

ns

ms

pF

SCL(MAX)

BUF(MIN)

HD,STA(MIN)

SU,STA(MIN)

SU,STO(MIN)

HD,DAT(MIN)

HD,DATO

SCL

Bus Free Time Between Stop/Start Condition

Hold Time After (Repeated) Start Condition

Repeated Start Condition Set-Up Time

Stop Condition Set-Up Time

Data Hold Time (Input)

1.3

600

100

900

600

250

40

140

30

Data Hold Time (Output)

300

600

30

Data Set-Up Time

SU,DAT(MIN)

SP

Suppressed Spike Pulse Width

Stuck-Bus Reset Time

50

25

110

32

SCL or SDA Held Low

SDAI Tied to SDAO (Note 5)

RST

C

SCL, SDA Input Capacitance

10

X

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Integral Nonlinearity is deﬁned as the deviation of a code from a

precise analog input voltage. Maximum speciﬁcations are limited by the

LSB step size and the single shot measurement. Typical speciﬁcations are

measured from 1/4, 1/2, 3/4 areas of the quantization band.

Note 2: All currents into pins are positive, all voltages are referenced to

Note 5: Guaranteed by design and not subject to test.

GND unless otherwise speciﬁed.

Note 3: An internal clamp limits the GATE pin to a minimum of 5V above

SOURCE. Driving this pin to voltages beyond the clamp may damage the

device.

4222fb

5

LTC4222

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C. V}_DDn= 12V unless otherwise noted.

I_DD1vs V_DD1

I_DD2vs V_DD2

INTV_CCvs V_DD2

1.0

0.9

0.8

0.7

0.6

0.5

0.4

4.0

3.5

3.0

2.5

2.0

3.4

3.3

3.2

3.1

3.0

2.9

2.8

0

5

10

15

20

25

30

0

5

10

15

(V)

DD2

20

25

30

2.5

3.0

3.5

V

4.0

(V)

4.5

5.0

V

(V)

V

DD1

DD2

4222 G01

4222 G02

4222 G03

INTV_CCvs I_LOAD

V_TH(UV)vs Temperature

V_HYST(UV)vs Temperature

3.50

3.25

3.00

2.75

2.50

1.250

1.245

1.240

1.235

1.230

1.225

1.220

100

95

90

85

80

V

= 2.9V

= 3.3V

= 5V

DD2

= 12V

0

2.5

5.0

7.5

10.0 12.5 15.0

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

I

(mA)

TEMPERATURE (°C)

LOAD

4222 G04

4222 G05

4222 G06

V_THCircuit Breaker vs

Temperature

Current Limit vs V_FB

I_TIMERvs Temperature

60

50

40

30

20

10

0

53

52

51

50

49

48

47

110

105

100

95

90

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4

(V)

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

V

TEMPERATURE (°C)

FB

4222 G08

4222 G09

4222 G07

4222fb

6

LTC4222

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C. V}_DDn= 12V unless otherwise noted.

∆V_GATEvs Temperature

∆V_GATEvs I_GATE

I_GATEvs Temperature

6.1

6.0

5.9

5.8

5.7

5.6

5.5

5.4

6.5

6.0

5.5

5.0

4.5

4.0

12.0

11.9

11.8

11.7

11.6

11.5

V

= 2.9V

= 3.3V

= 5V

DD2

= 12V

V

= 2.9V

= 3.3V

= 5V

DD2

= 12V

–50

–25

0

25

50

75

100

0

2

4

6

8

10

12

14

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

I

(A)

TEMPERATURE (°C)

GATE

4222 G10

4222 G11

4222 G12

ADC Total Unadjusted Error vs

CODE (ADIN1)

V_OL(GPIO)vs I_GPIO

ADC INL vs CODE (ADIN1)

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

V

= 12V

V

= 2.9V

DD2

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

2

4

6

8

10

0

256

512

768

1024

0

256

512

768

1024

I

(mA)

CODE

GPIO

4222 G13

4222 G14

4222 G15

ADC Full-Scale Error vs

Temperature

ADC DNL vs CODE (ADIN1)

T_PHLV_GATEvs V_SENSEOverdrive

0.5

0.4

4

3

100

10

1

0.3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–1

–2

–3

–4

0.1

0

256

512

768

1024

–50

–25

0

25

50

75

100

0

50 100 150 200 250 300 350 400

CODE

TEMPERATURE (°C)

V

(mV)

SENSE

4222 G16

4222 G17

4222 G18

4222fb

7

LTC4222

PIN FUNCTIONS

ADIN: ADC Input. A voltage between 0 and 1.28V applied

tothispinismeasuredbytheon-boardADC. Tietoground

if unused.

bits 6 and 7. Also a power bad fault is logged when the

FB pin is low, the LTC4222 has ﬁnished the startup cycle

and the GATE pin is high. See Applications Information.

The start-up current limit folds back from 50mV sense

voltage to 16.6mV as the FB voltage drops from 0.8V to

0.2V. Foldback is not active once the part leaves startup

and the current limit is increased to 150mV.

ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying

these pins to ground, open, or INTV conﬁgures one

CC

of 27 possible addresses. See Table 1 in Applications

Information.

GATE1,GATE2:GateDriveforExternalN-ChannelMOSFET.

An internal 12µA current source charges the gate of the

MOSFET. No compensation capacitor is required on the

GATE pin, but a resistor and capacitor network from this

pin to ground may be used to set the turn-on output volt-

age slew rate. During turn-off there is a 1mA pull-down

ALERT: Fault Alert Output. Open-drain logic output that

is pulled to ground when a fault occurs to alert the host

controller. A fault alert is enabled by setting the corre-

sponding bit in the ALERT register as shown in Table 4.

See Applications Information. Tie to ground if unused.

CONFIG:ConﬁgurationInput.Conﬁgurestheparttocontrol

thetwochannelstogetherorindependently.WhenCONFIG

is tied to GND both channels start up at the same time. A

fault, EN or ON turn-off command on either channel will

current.Duringashortcircuitorundervoltagelockout(V

DD

or INTV ), a 450mA pull-down current source between

CC

GATE and SOURCE is activated.

GND: Device Ground.

shut down both channels. When CONFIG is tied to INTV ,

CC

either channel can start up independently. A fault, EN or

ON turn-off command will result in the associated chan-

nel turning off, while the other channel remains on. If one

channeliscommandedtoturnonwhileanotherchannelis

in the turn-on sequence, the LTC4222 waits until the ﬁrst

channel has ﬁnished its turn-on sequence before turning

on the second channel.

GPIO1,GPIO2:GeneralPurposeInput/Output.Open-drain

logic output or logic input. Defaults to an output set to pull

low to indicate power is not good. Conﬁgure according

to Table 3.

INTV : Low Voltage Supply Decoupling Output. Connect

CC

a 0.1µF capacitor from this pin to ground.

ON:(QFNPackage)OnControlInput. Formedbyinternally

tying the ON1 and ON2 lines together.

EN1, EN2: Enable Input. Ground this pin to indicate a

board is present and enable the N-channel MOSFET to

turn-on. When this pin is high, the MOSFET is not allowed

to turn on. An internal 10µA current source pulls up this

pin. Transitions on this pin are recorded in the FAULT

register. Ahigh-to-lowtransitionactivatesthelogictoread

the state of the ON pin and clear faults. See Applications

Information.

ON1, ON2: (SSOP Package) On Control Inputs. A rising

edgeturnsontheexternalN-channelFETandafallingedge

turns it off. This pin also conﬁgures the state of the FET

ON register bit (and hence the external FET) at power up.

For example, if the ON pin is tied high, then the FET ON bit

(Control bit 3 in Table 3) goes high 100ms after power-up.

Likewise if the ON pin is tied low then the channel remains

off after power-up until the FET ON bit is set high using

EXPOSED PAD: (Pin 33, QFN Package) Exposed Pad. May

be left open or connected to device ground.

2

the I C bus. A high-to-low transition on this pin clears the

fault register for the related channel. The two ON pins are

tied together internally on the QFN package.

FB1, FB2: Foldback Current Limit and Power-Good Input.

A resistive divider from the output is tied to this pin. When

the voltage at this pin drops below 1.235V, power is not

considered good. The power bad condition may result

in the GPIO pin pulling low or going high impedance

depending on the conﬁguration of CONTROL register

OV1,OV2:OvervoltageComparatorInput.Connectthispin

to an external resistive divider from V . If the voltage at

DD

thispinrisesabove1.235V,anovervoltagefaultisdetected

and the GATE turns off. Tie to GND if unused.

4222fb

8

LTC4222

PIN FUNCTIONS

SOURCE1, SOURCE2: N-Channel MOSFET Source and

ADC Input. Connect this pin to the source of the external

N-channel MOSFET switch for gate drive return. This pin

also serves as the ADC input to monitor output voltage.

The pin provides a return for the gate pull-down circuit.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-collector output

from a master controller. An external pull-up resistor or

current source is required.

SS: Soft-Start Input. Sets the inrush current slew rate at

start-up. Connect a 68nF capacitor to provide 5mV/ms as

the slew rate for the sense voltage in start-up. This cor-

responds to 1A/ms with a 5mΩ sense resistor. Note that

a large soft-start capacitor and a small TIMER capacitor

may result in a condition where the timer expires before

the inrush current has started. Allow an additional 2nF of

timer capacitance per 1nF of soft-start capacitor to ensure

proper start-up.

SDAO: (SSOP Package) Serial Bus Data Output. Open-

drain output for sending data back to the master control-

ler or acknowledging a write operation. Normally tied to

SDAI to form the SDA line. An external pull-up resistor

or current source is required. Internally tied to SDAI in

QFN package.

SDAI: (SSOP Package) Serial Bus Data Input. A high im-

pedance input for shifting in address, command or data

bits. NormallytiedtoSDAOtoformtheSDAline. Internally

tied to SDAO in QFN package.

TIMER: Start-Up Timer Input. Connect a capacitor be-

tween this pin and ground to set a 12.3ms/µF duration

for start-up, after which an overcurrent fault is logged if

the inrush is still current limited. The duration of the off

time is 600ms/µF when overcurrent auto-retry is enabled,

resulting in a 1:50 duty cycle. An internal timer provides

a 100ms start-up time and 5 second auto-retry time if

SDA: (QFN Package) Serial Bus Data Input/Output Line.

Formed by internally tying the SDAO and SDAI lines

together. An external pull-up resistor or current source

is required.

–

SENSE1 , SENSE2 : Negative Current Sense Input. Con-

nectthispintotheoutputofthecurrentsenseresistor. The

current limit circuit controls the corresponding GATE pin

this pin is tied to INTV . Allow an additional 2nF of timer

CC

capacitance per 1nF of soft-start (SS) capacitor to ensure

+

voltage to limit the sense voltage between the SENSE and

proper start-up.

–

SENSE pins to the level set by the soft-start and foldback

UV1, UV2: Undervoltage Comparator Input. Connect this

characteristic, with a maximum of 50mV during start-up

and to 150mV independent of soft-start and foldback after

the start-up timer has expired. A circuit breaker, enabled

after start-up, trips when the sense voltage exceeds 50mV

for 20µs.

pin to an external resistive divider from V . If the volt-

DD

age at this pin falls below 1.145V, an undervoltage fault

is detected and the GATE turns off. Pulling this pin below

0.4V resets the fault register for that channel except for

the UV fault bit. Tie to INTV if unused.

CC

+

SENSE1 , SENSE2 : (SSOP Package) Positive Current

Sense Input. Connect this pin to the input of the current

sense resistor. It must be connected to the same trace as

V , V : Supply Voltage Input and Positive Current

DD1 DD2

SenseInput.Thispinhasanundervoltagelockoutthreshold

of 2.43V. In the QFN package this pin is also the positive

current sense input.

V

. Internally tied to V

in the QFN package.

DDn

4222fb

9

LTC4222

FUNCTIONAL DIAGRAM

–

+

SENSE

SENSE (SSOP)

FB

0.2V

0.6V

FOLDBACK

and DIDT

+

GATE

CHARGE

PUMP

AND

1.235V

–

+

0mV TO

UVS

CB

CS

UV

50mV

150mV

SOURCE

–

GATE

–

+

UV

+

–

DRIVER

0.4V

+

FET ON

RESET

RST

FAULT

GPIO

–

+

–

+

–

OV

GP

PWRGD

+

PG

OVS

1V

OV1

1.235V

INTV

CC

1.235V

EN

–

1.235V

+

–

10µA

EN

ON

+

–

2.43V

ONS

+

–

ON

UVLO1

LOGIC

1.235V

V

DD

V

DD

UVLO

2x

1x

0.2V

+

–

SS

SOFT-START

COUPLE

INTV

CC

TM1

100µA

CONFIG

+

–

TIMER

2µA

1.235V

+

–

V

DD2

TM2

INTV

CC

3.3V

GEN

1.235V

SDAI (SSOP)

SDAO (SSOP)

2

5

I C ADDR

+

–

SDA (QFN)

SCL

2

I C

UVLO2

V

CC

UVLO

2.64V

ALERT

10 BIT

ADIN1

ADIN2

A/D CONVERTER

SOURCE1

– SENSE1

ADR0

ADR1

ADR2

V

DDA

1 OF 27

SOURCE2

– SENSE2

V

DDB

4222 BD

4222fb

10

LTC4222

TIMING DIAGRAM

SDAI/SDAO

t

SP

t

SU, STA

t

SU, DAT

t

BUF

HD, DATO,

HD, DATI

t

HD, STA

t

SU, STO

t

SP

4222 TD01

SCL

t

HD, STA

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

OPERATION

The LTC4222 is designed to turn two supply voltages

on and off in a controlled manner, allowing boards to be

safely inserted or removed from a live backplane. During

normal operation, the charge pump and gate drivers turn

on external N-channel MOSFET gates to pass power to

the loads. The gate driver circuits use a charge pump that

overheating. At this point the TIMER capacitor starts to

discharge with the 2µA current source until the voltage

drops below 0.2V (comparator TM1) which tells the logic

that the pass transistor has cooled and it is safe to turn

on again if overcurrent auto-retry is enabled. If the TIMER

pin is tied to INTV , the cool-down time defaults to

CC

derives its power from the V

or V

pin, whichever is

5 seconds using an internal system timer.

DD1

DD2

higher. Also included in the gate driver circuits are internal

6.5V GATE-to-SOURCE clamps to protect the oxide of

logic-level MOSFETs. During start-up the inrush currents

are tightly controlled by using current limit foldback, soft-

start dI/dt limiting and output dI/dt limiting. The LTC4222

is capable of controlling both channels independently, or

coupling control signals so that both channels start up

and turn off together.

The output voltages are monitored using the FB resistive

dividerandthepowergood(PG)comparatorstodetermine

when output voltages are acceptable for the loads. The

power good conditions are signaled by the GPIO1 and

GPIO2 pins using open-drain pull-down transistors. The

GPIO pins may also be independently conﬁgured to signal

powerbad,orasgeneralpurposeinputs(GPcomparators),

or general purpose open-drain outputs.

The current sense (CS) ampliﬁers monitor the load cur-

The Functional Diagram shows the monitoring blocks of

the LTC4222. The group of comparators on the left side

includes the undervoltage (UV), overvoltage (OV), reset

(RST), enable (EN) and on (ON) comparators for chan-

nel 1 or 2. These comparators determine if the external

conditions are valid prior to turning on their correspond-

ing GATE. The two undervoltage lockout circuits, UVLO1

and UVLO2, validate the input supplies and the internally

+

rents using the difference between the SENSE (V for

DD

–

QFN) and SENSE pin voltages. A CS ampliﬁer limits the

currentintheloadbypullingbackontheGATE-to-SOURCE

voltage in an active control loop when the sense voltage

exceeds the commanded value. The CS ampliﬁers require

+

20µA input bias current from both the SENSE and the

–

SENSE pins.

A short circuit on an output to ground results in excessive

powerdissipationduringactivecurrentlimiting.Tolimitthis

power,thecorrespondingCSampliﬁerregulatesthevoltage

generated 3.3V supply, INTV . UVLO2 also generates

CC

the power-up initialization to the logic circuits as INTV

crosses this rising threshold.

CC

+

–

between the SENSE and SENSE pins at 150mV.

The CONFIG pin is used to select the desired start-up

behavior of the LTC4222. When the CONFIG pin is low,

both channels will start up and turn off simultaneously

and a fault on either channel will result in both channels

turning off, or prevent both channels from starting up.

4222fb

If an overcurrent condition persists, the internal circuit

breaker (CB) registers a fault when the sense voltage

exceeds 50mV for more than 20µs. This indicates to

the logic that it is time to turn off the GATE to prevent

11

LTC4222

OPERATION

When the CONFIG pin is high the two channels work

completely independently and ignore the behavior of the

other channel. This allows for the channels to start up in

sequence by connecting the GPIO (power good) output of

one channel to the UV pin of the other channel.

Included in the LTC4222 is a 10-bit A/D signal. The 6-input

multiplexer ahead of the A/D converter allows to select

between the two ADIN pins, the two SOURCE pins and

the two current sense devices.

2

An I C interface is provided to read the A/D registers. It

The two channels share the TIMER and SS (soft-start)

pins that control start-up behavior. If the CONFIG pin is

high and one channel is enabled while the other channel

is starting up, the LTC4222 will wait for the start-up cycle

to end before starting up the second channel to ensure

that it gets a full timer cycle. The exception to this is the

ON pins, which turn on the corresponding channel imme-

diately. When both channels start up simultaneously, the

inrush current for both channels is limited by whichever

FB pin is lowest.

also allows the host to poll the device and determine if

faults have occurred. If the ALERT line is conﬁgured as

an interrupt, the host is enabled to respond to faults in

real time. The SDA line is divided into an SDAI (input)

and SDAO (output). This simpliﬁes applications using an

optoisolator driven directly from the SDAO output. The

2

I C device address is forwarded to the address decoder

from the ADR0, ADR1 and ADR2 pins. These inputs have

three states each that decode into a total of 27 device

addresses.

APPLICATIONS INFORMATION

AtypicalLTC4222applicationisinahighavailabilitysystem

in which two positive voltage supplies are distributed to

one or more cards. The device measures card voltages

andcurrentsandrecordspastandpresentfaultconditions

for both channels. The system queries each LTC4222 over

supplies, V , must exceed their 2.44V undervoltage

DDn

lockoutlevels.Nexttheinternallygeneratedsupply,INTV ,

CC

must cross its 2.64V undervoltage threshold. This gener-

ates a 60µs to 120µs power-on-reset pulse. During reset

the fault registers are cleared and the control registers are

set or cleared as described in the register section.

2

the I C periodically and reads status and measurement

information.

Afterapower-on-resetpulse,theLTC4222goesthroughthe

followingturn-onsequenceforoneorbothchannels. First

the UV and OV comparators indicate that input power is

withintheacceptablerange, whichisindicatedbySTATUS

bits0to1inTable5. Second, theENpinisexternallypulled

low. Finally, all of these conditions must be satisﬁed for

the duration of 100ms to ensure that any contact bounce

during insertion has ended. Additionally, if the CONFIG pin

is low all initial conditions for both channels must be met

before the pair are allowed to turn on together.

A basic LTC4222 application circuit is shown in Figure 1.

The following sections cover turn-on, turn-off and acts

upon various faults that the LTC4222 detects. External

component selection is discussed in detail in the Design

Example section.

Turn-On Sequence

The power supplies on a board are controlled by using

external N-channel pass transistors (Q1 and Q2) placed

in the power path. Note that resistor R provides current

When these initial conditions are satisﬁed, the ON pin

is checked and its state written to bit 3 in the CONTROL

register (Table 3). If it is high, the external MOSFET is

turned on. If the ON pin is low, the external MOSFET is

turned on when theON pinisbrought high orif aserialbus

turn-on command is sent by setting CONTROL bit 3. If the

CONFIG pin is low, either both ON pins must be high or

both CONTROL registers third bits must be set in order for

Sn

detection.ResistorsR1n,R2nandR3ndeﬁneundervoltage

and overvoltage levels for the two channels. R5n prevents

high frequency oscillations in Qn and R6n. C1n forms an

optional network that may be used to provide an output

dV/dt limited start-up.

Several conditions must be present before the external

MOSFET for a given channel turns on. First the external

the external MOSFETs to be turned on simultaneously.

4222fb

12

LTC4222

APPLICATIONS INFORMATION

R

Q1

FDD3706

S1

0.01Ω

V

IN1

12V

Z1

SA14A

R71

R11

10.2k

R5-1

10Ω

140k

R

G1

15k

R81

3.57k

C

F1

R41

100k

C

G1

R21

4.53k

0.1µF

3.9nF

–

UV1

OV1

ON

SDA

SCL

V

DD1

SENSE1 GATE1

SOURCE1

FB1

R31

13.7k

GPIO1

EN1

ADIN1

TIMER

ON

SDA

SCL

ALERT

C

TIMER

CONFIG

ADR0

ADR1

ADR2

0.68µF

SS

LTC4222

NC

C

SS

68nF

ADIN2

EN2

INTV

CC

C3

0.1µF

GND

OV2

UV2

GPIO2

FB2

SOURCE2

R32

13.7k

–

V

SENSE2 GATE2

DD2

R22

3.32k

R

G2

15k

R42

100k

R82

3.57k

C

F2

C

R5-2

10Ω

G2

0.1µF

R12

23.7k

3.9nF

R72

4.99k

V

IN2

3.3V

Q2

FDD3706

Z2

SA14A

R

S2

0.01Ω

BACKPLANE PLUG-IN

CARD

4222 TA01a

Figure 1. Typical Application

A MOSFET is turned on by charging up the GATE with a

12µA current source. When the GATE voltage reaches the

MOSFET threshold voltage, the MOSFET begins to turn on

and the SOURCE voltage then follows the GATE voltage

as it increases.

pin reaches threshold of 1.235V, the part checks to see if

it is in current limit. If this is the case, the overcurrent fault

bit, FAULT bit 2 in Table 6, is set and the part turns off. If

the part is not in current limit, the 50mV circuit breaker is

armed and the current limit is switched to 150mV. Alter-

nately an internal 100ms start-up timer may be selected

While the MOSFET is turning on, the inrush current in-

by tying the TIMER pin to INTV .

CC

creases linearly at a dI/dt rate selected by capacitor C .

SS

This is accomplished using the current limit ampliﬁer

controlling the GATE pin voltage. Once the inrush current

reachesthelimitsetbytheFBpin,thedI/dtrampstopsand

the inrush current follows the foldback proﬁle as shown

in Figure 2. When both channels turn on simultaneously,

the foldback current limit is set by the lower of the two

FB pins.

AstheSOURCEvoltagerises, theFBpinvoltagefollowsas

set by R7 and R8. Once FB crosses its 1.235V threshold,

andthestart-uptimerhasexpired,thecorrespondingGPIO

pin, in the default power good conﬁguration, ceases to

pull low and indicates that power is now good. Alternately

STATUS bit 3 can be read to check power-good status,

where a zero indicates that power is good.

A start-up timer is used to prevent damaging the MOSFET

when starting up into a short-circuit. The TIMER capacitor

integrates at 100µA during start-up and once the TIMER

If a series resistor and capacitor from GATE to GROUND

(R6 and C1) are employed to provide a constant inrush

currentduringstart-up,whichprovidesaconstantdV/dtat

4222fb

13

LTC4222

APPLICATIONS INFORMATION

drive voltage is 4.7V. The GATE-to-SOURCE voltage is

clamped below 6.5V to protect the gates of logic-level

N-channel MOSFETs.

V

+ 6V

V

DD

GATE

V

DD

OUT

Turn-Off Sequence

GPIO

(POWER GOOD)

One or both GATE pins are turned off by a variety of con-

ditions. A normal turn-off is initiated by an ON pin going

low or a serial bus turn-off command. Additionally, several

fault conditions cause a GATE to turn off. These include an

input overvoltage (OV pin), input undervoltage (UV pin),

V

SENSE

t

STARTUP

50mV

–

overcurrentcircuitbreaker(SENSE pin),orENtransitioning

17mV

high. Writing a logic one into the UV, OV or OC fault bits

(FAULT register bits 0 to 2 in Table 6) also latches off the

associated GATE if their auto-retry bits are set to false.

I

• R

SENSE

LOAD

4222 F02

SS

FB

LIMITED

TIMER

EXPIRES

LIMITED

A MOSFET is turned off with a 1mA current pulling down

the GATE pin to ground. With the MOSFET turned off, the

Figure 2. Power-Up Waveform

SOURCE and FB voltages drop as C discharges. When

L

the output, a 12µA pull-up current (I

) from the GATE

GATE

the FB voltage crosses below its threshold, GPIO may be

conﬁgured to pull low to indicate that the output power

is no longer good.

pin slews the gate upwards and resulting current is less

than the current limit. Because the inrush current is less

thanthecurrentlimit, thestart-uptimercanexpirewithout

producing an overcurrent fault and a small timer capacitor

may be used. After the timer has expired power good will

not be signaled until the FB pin crosses its threshold and

the GATE-to-SOURCE voltage crosses the 4.3V threshold

that indicates the MOSFET is fully enhanced. When both

those conditions are met the output voltage is suitable

for the load to be turned on and the impedance back to

the supply through the MOSFET is low. Power good is

then asserted with the GPIO pin or read via the interface,

signaling that it is safe to turn on downstream loads. A

power-bad fault is not generated when starting up in this

manner because the FB pin will cross its threshold before

If the INTV pin drops below 2.60V for greater than 1µs,

CC

ortheassociatedV pinfallsbelow2.35Vforgreaterthan

DD

2µs, a fast shut down of the MOSFET is initiated. In this

case the GATE pin is pulled down with a 450mA current

to the SOURCE pin.

Overcurrent Fault

TheLTC4222hasdifferentcurrentlimitingbehaviorduring

start-up, when the output supply ramps up under TIMER,

SS and FB control, and normal operation. As such it can

generate an overcurrent fault during both phases of op-

eration. Both set the faulting supply’s overcurrent fault bit

(FAULT register bit 2) and shut off the faulting GATE, or

both GATEs if the CONFIG pin is low.

the GATE-to-SOURCE threshold is crossed. R should be

G

chosen such that I

• R is less than the threshold of

GATE

G

the MOSFET to avoid a current spike at the beginning of

During start-up when both TIMER and SS are ramping,

the current limit is a function of SS pin voltage and the

voltage on the FB pins. A supply could power up entirely

in current limit depending on the bypass capacitor at the

outputs of the ramping supplies. The TIMER pin sets

the time duration for current limit during start-up, either

12.3ms/µF when using a timer capacitor, or 100ms when

startup. Reducing R degrades the stability of the current

G

limit circuit, see applications information on current limit

stability.

GATE Pin Voltage

A curve of GATE-to-SOURCE voltage vs V is shown in

DD

theTypicalPerformanceCharacteristics.Atminimuminput

the TIMER pin is tied to INTV . If the supply is still in

CC

supply voltage of 2.9V, the minimum GATE-to-SOURCE

current limit at the end of the timing cycle, an overcurrent

4222fb

14

LTC4222

APPLICATIONS INFORMATION

fault is declared for that supply and the MOSFET is turned

off. If the CONFIG pin is low, then both channels will turn

off together. After the switch has turned off due to an

OC fault the part will wait for a cool-down period before

allowing the switch to turn on again. If the TIMER pin is

Overvoltage Fault

An overvoltage fault occurs when an OV pin rises above

its 1.235V threshold for more than 2µs. This shuts off

the corresponding GATE with a 1mA current to ground

and sets the overvoltage present STATUS bit 0 and the

overvoltage FAULT bit 0. If the pin subsequently falls back

belowthethresholdfor100ms,theGATEisallowedtoturn

on again unless overvoltage auto-retry has been disabled

by clearing CONTROL bit 0. If the CONFIG pin is tied low,

an OV fault on either channel will shut off both channels

simultaneously.

tied to V the cool-down period will be 5 seconds on the

CC

internal timer. Otherwise if using a TIMER capacitor, the

capacitorwilldischargeat2µAandtheinternal100mstimer

is started, when the 100ms timer expires and the TIMER

pin reaches its 0.2V lower threshold the part is allowed to

restart if the overcurrent fault bit (FAULT register bit 2) has

been cleared or the overcurrent auto-retry bit (CONTROL

register bit 2) has been set.

Undervoltage Fault

Afterstart-up,asupplyhasdual-levelglitch-tolerantprotec-

tion against overcurrent faults. The sense resistor voltage

dropismonitoredbya50mVelectroniccircuitbreakerand

a 150mV active current limit. In the event that a supply’s

current exceeds the circuit breaker threshold, an internal

20µs timer is started. If the supply is still overcurrent after

20µs the circuit breaker trips and the switch is turned off.

An analog current limit loop prevents the supply current

from exceeding the 150mV current limit in the event of a

short circuit. The 20µs ﬁlter delay and the higher current

limit threshold prevent unnecessary resets of the board

due to minor current surges. The LTC4222 will stay in

the latched off state unless the overcurrent auto-retry bit

(CONTROL register bit 2) is set, in which case the switch

turnsonagainafter100mswhenusingtheexternalTIMER

capacitortosetthestart-uptime,or5secondswhenusing

the internal timer. Note that current limit foldback is not

active after start-up.

An undervoltage fault occurs when a UV pin falls below

its 1.235V threshold for more than 2µs. This turns off the

corresponding GATE with a 1mA current to ground and

sets undervoltage present STATUS bit 1 and undervoltage

FAULT bit 1. If the UV pin subsequently rises above the

threshold for 100ms, the GATE is turned on again unless

undervoltage auto-retry has been disabled by clearing

CONTROL bit 1. When power is applied to the device, if

UV is below its 1.235V threshold after INTV crosses its

CC

2.64V undervoltage lockout threshold, an undervoltage

fault is logged in the FAULT register. If the CONFIG pin is

tied low, an UV fault on either channel will shut off both

channels simultaneously.

ON Signals and the CONFIG Pin

2

Turn-on commands are issued from the ON pins or the I C

interface. Internally, risingandfallingedgesoftheONpins

set and reset the FET_ON register bits. Unlike the other

control signals such as UV, OV and EN, the rising edge of

theONsignalisnotﬁlteredbythe100msinternaltimerand

instead turns on the corresponding channel immediately.

Cycling an ON signal cancels the corresponding channel’s

overcurrent auto-retry cool-down period, allowing the

channel to restart after a 100ms delay.

LOAD CURRENT

5A/DIV

V

GATE

10V/DIV

V

SOURCE

10V/DIV

V

GPIO

5V/DIV

To start up and shut down both channels at the same time

set the CONFIG pin low. Both channels then start up when

all the UV, OV, EN and ON signals are in the correct state

to turn on both channels, and when any of these signals

turns one channel off, both channels turn off.

4222 F03

10µs/DIV

C

= 0F

SHORT

= 20mΩ

= 1k

= 1µF

L

R

= 5mΩ

S

G

C

Figure 3. Short-Circuit Waveform

4222fb

15

LTC4222

APPLICATIONS INFORMATION

Setting the CONFIG pin high allows the two channels to

start up and turn off independently. When both ON signals

are brought high sequentially, the channel turned on ﬁrst

immediately begins to start up and the second channel

has a 200ns window to assert it’s ON signal in order to

start up in the same timer period. If the second ON signal

is asserted after the 200ns window but before the end of

the ﬁrst channel’s start-up time, the second channel start-

up is delayed. The second channel will then start 100ms

after the ﬁrst channel’s start-up timer has expired and the

TIMER pin, if used, reaches its 200mV low threshold.

is reinserted the fault register is cleared except for FAULT

bit 4. After 100ms the state of the ON pin is latched into

bit 3 of the CONTROL register. At this point the channel

starts up again.

If a connection sense on the plug-in card is driving an EN

pin, insertion or removal of the card may cause the pin

voltagetobounce. Thisresultsinclearingthefaultregister

when the card is removed. The pin may be debounced

, on the EN pin as shown in

using a ﬁlter capacitor, C

EN

Figure 4. The ﬁlter time is given by:

t

= C • 123 (ms/µF)

FILTER

EN

When an external TIMER capacitor is used, the TIMER

capacitorvoltagerampsupwitha100µAcurrent.Oncethe

TIMERpinreachesits1.235VthresholdtheTIMERbegins

todischarge.WhiletheTIMERcapacitorisdischarging,the

ON signal for the second channel should not be asserted

for 2ms/µF of TIMER capacitance. This allows the TIMER

capacitortoreturntoitslowstateandensuresthatthenext

channel to start receives a full timer cycle. This wait time

is unnecessary when using the internal 100ms timer.

OUT

LTC4222

SOURCE

10µA

EN

+

LOAD

C

EN

1.235V

–

GND

4222 F04

Board Present Change of State

CONNECTOR

PLUG-IN

CARD

MOTHERBOARD

The EN pins may be used to detect the presence of one or

twodownstreamcards.WheneveranENpintoggles,FAULT

bit 4 is set to indicate a change of state. When the EN pin

goes high, indicating board removal, the corresponding

GATEturnsoffimmediately(witha1mAcurrenttoground)

and the board present STATUS bit 4, is cleared. If the EN

pin is pulled low, indicating a board insertion, all fault bits

for that channel except FAULT bit 4 are cleared and enable

STATUS bit 4, is set. If the EN pin remains low for 100ms

the state of the ON pin is captured in ‘FET On’ CONTROL

bit 3. This turns the switch on if the ON pin is tied high.

There is an internal 10µA pull-up current source on the

EN pin. If the CONFIG pin is tied low, both EN pins must

be low for 100ms for the two channels to be enabled and

if either EN pin goes high both channels will turn off.

Figure 4. Plug-In Card Insertion/Removal

FET Short Fault

AFETshortfaultisreportedifthedataconvertermeasures

a current sense voltage greater than or equal to 2mV while

the corresponding GATE is turned off. This condition sets

FET short bit, Fault bit 5.

Power-Bad Fault

A power-bad fault is reported if a FB pin voltage drops

below its 1.235V threshold for more than 2µs when the

corresponding GATE is above the 4.3V gate to source

threshold. This pulls the GPIO pin low immediately in the

default power good conﬁguration, and sets power-bad

present bit, STATUS bit 3, and power-bad bit, FAULT bit 3.

Acircuitpreventspower-badfaultsiftheGATE-to-SOURCE

voltage is low, eliminating false power-bad faults during

power-uporpower-down.IftheFBpinvoltagesubsequently

rises back above the threshold, a power good conﬁgured

GPIO pin returns to a high impedance state and STATUS

If a channel shuts down due to a fault, it may be desirable

to restart that channel simply by removing and reinserting

the related load card. In cases where the LTC4222 and the

switch reside on a backplane or midplane and the load

resides on a plug-in card, the EN pin detects when the

plug-incardisremoved.Figure4showsanexamplewhere

theENpinisusedtodetectinsertion.Oncetheplug-incard

bit 3 is reset.

4222fb

16

LTC4222

APPLICATIONS INFORMATION

Fault Alerts

bits 0 or 1 holds the switch off and the fault register is

ignored. Subsequently, when STATUS register bits 0 and

1 are cleared by removal of the fault condition, the switch

is allowed to turn on again. The LTC4222 will set FAULT

bit 2 and turn off in the event of an overcurrent fault,

preventing it from remaining in an overcurrent condition.

If conﬁgured to auto-retry, the LTC4222 will continually

attempt to restart after cool-down cycles until it succeeds

instartingupwithoutgeneratinganovercurrentfault.Note

that if a switch is on after an auto-retry and the FAULT bit

has not been reset, clearing the corresponding auto-retry

bit will turn the channel off.

When any of the fault bits in a FAULT register (see Table 4)

are set, an optional bus alert is generated if the appropri-

ate bit in the ALERT register has been set. This allows

only selected faults to generate alerts. At power-up the

default state is to not alert on faults and the ALERT pin

is high. If an alert is enabled, the corresponding fault

causes the ALERT pin to pull low. After the bus master

controller broadcasts the Alert Response Address, the

LTC4222 responds with its address on the SDA line and

releases ALERT as shown in Table 7. If there is a collision

between two LTC4222s responding with their addresses

simultaneously, then the device with the lower address

wins arbitration and responds ﬁrst. The ALERT line is also

released if the device is addressed by the bus master if

ALERT is pulled low due to an alert.

Data Converter

The LTC4222 incorporates a 10-bit A/D converter that

continuously scans six different voltages. The SOURCE

pins have a 1/24 resistive divider to monitor a full-scale

voltageof32Vwith31.25mVresolution.TheADINpinsare

monitored with a 1.28V full scale and 1.25mV resolution,

Once the ALERT signal has been released for one fault, it

is not pulled low again until the FAULT register indicates a

different fault has occurred or the original fault is cleared

and it occurs again. Note that this means repeated or

continuing faults do not generate alerts until the associ-

ated FAULT register bit has been cleared.

and the voltage between the V and SENSE pins is moni-

DD

tored with a 64mV full scale and 62.5µV resolution.

Results from each conversion are stored, left justiﬁed, in

registers as seen in Tables 7 and 8, and are updated 15

times per second. Setting ADC_CONTROL register bit 0

invokes a test mode that halts the data converter so that

the data converter result registers may be written to and

read from for software testing.

Resetting Faults

Faults are reset with any of the following conditions on a

given channel. First, a serial bus command writing zeros

to the FAULT register bits 0 to 5 clears the associated

faults. Second, FAULT register bits 0 to 5 are cleared when

the corresponding switch is turned off by the ON pin or

STATUS bit 3 going from high to low, if the corresponding

UV pin is brought below its 0.4V reset threshold for 2µs,

The data converter also has a direct address mode that

allows the user to take a speciﬁc measurement at a spe-

ciﬁc time and hold that value for later readback. Direct

address mode is entered by setting the Halt bit, bit 0, in

the ADC_CONTROL register (see Table 9). Then when

the channel address bits, ADC_CONTROL bits 1 to 3, are

written to, the ADC will make a single measurement on

the channel indicated by those bits, then stop. Setting the

ADCAlertbit,ADC_CONTROLbit4,willenableaninterrupt

when the data converter ﬁnishes the conversion, result-

ing in the ALERT pin pulling low when the data is ready.

Alternately, the ADC Busy bit, ADC_CONTROL bit 5, can

be polled to check for the end of the conversion, after a

direct address conversion the ADC Busy bit will go low. In

normal mode ADC Busy is always high. Resetting the Halt

bit returns the data converter to the scan mode.

or if INTV falls below its 2.64V undervoltage lockout

CC

threshold. Finally, when EN is brought from high to low,

only corresponding FAULT bits 0-3 and 5 are cleared, and

bit 4, which indicates a EN change of state, is set. Note

that faults that are still present, as indicated in the STATUS

registers, cannot be cleared.

The FAULT registers are not cleared when auto-retrying.

Whenauto-retryisdisabledtheexistenceofanovervoltage,

undervoltage, or overcurrent fault keeps the switch off.

As soon as the fault is cleared, the switch turns on. If

auto-retry is enabled, then a high value in STATUS register

4222fb

17

LTC4222

APPLICATIONS INFORMATION

Conﬁguring the GPIO Pins

capacitance being between 0.2µF and 9µF, the presence

of R5 resistance, the absence of a drain bypass capacitor,

a combination of bus wiring inductance and bus supply

outputimpedance.Topreventthissecondtypeofoscillation

avoid load capacitance below 10µF, alternately connect an

external capacitor from the MOSFET gate to ground with

a value greater than 1.5nF.

Table3describesthepossiblestatesoftheGPIOpinsusing

theCONTROLregistersbits6and7.Atpower-up,thedefault

state is for a GPIO pin to go high impedance when power is

good (FB pin greater than 1.235V). Other applications for a

GPIO pin are to pull down when power is good, a general

purpose output and a general purpose input.

A simple application of the GPIO pin in the power good

conﬁguration is to connect it to the UV pin of the other

channel with the CONFIG pin high. This will result in the

second channel being turned on after the ﬁrst channel has

started up and signaled power good.

Supply Transients

TheLTC4222isdesignedtoridethroughsupplytransients

caused by load steps. If there is a shorted load and the

parasitic inductance back to the supply is greater than

0.5µH, there is a chance that the supply collapses before

the active current limit circuit brings down the GATE pin.

If this occurs, the undervoltage monitors pull the corre-

sponding GATE pin low. The undervoltage lockout circuit

Current Limit Stability

For many applications the LTC4222 current limit will be

stable without additional components. However there are

certain conditions where additional components may be

needed to improve stability. The dominant pole of the cur-

rent limit circuit is set by the capacitance and resistance at

the gate of the external MOSFET, and larger gate capaci-

tance makes the current limit loop more stable. Usually

a total of 8nF gate to source capacitance is sufﬁcient for

has a 2µs ﬁlter time after V drops below 2.35V. The UV

DD

pin reacts in 2µs to shut the GATE off, but it is recom-

mended to add a ﬁlter capacitor, C , to prevent unwanted

F

shutdown caused by a transient. Eventually either the UV

pin or undervoltage lockout responds to bring the current

under control before the supply completely collapses.

stabilityandistypicallyprovidedbyinherentMOSFETC ,

Supply Transient Protection

GS

however the stability of the loop is degraded by increasing

The LTC4222 is safe from damage with supply voltages up

to 35V. However, spikes above 35V may damage the part.

During a short-circuit condition, large changes in current

ﬂowing through power supply traces may cause induc-

tive voltage spikes which exceed 35V. To minimize such

spikes, the power trace inductance should be minimized

by using wider traces or heavier trace plating. Also, a

snubber circuit dampens inductive voltage spikes. Build

a snubber by using a 100Ω resistor in series with a 0.1µF

R

or by reducing the size of the resistor on a gate RC

SENSE

network if one is used, which may require additional gate

to source capacitance. Board level short-circuit testing

is highly recommended as board layout can also affect

transient performance, for stability testing the worst-case

conditionforcurrentlimitstabilityoccurswhentheoutput

is shorted to ground after a normal start-up.

There are two possible parasitic oscillations when the

MOSFET operates as a source follower when ramping

at power-up or during current limiting. The ﬁrst type of

oscillation occurs at high frequencies, typically above

1MHz. This high frequency oscillation is easily damped

with R5 as shown in Figure 1. In some applications, one

may ﬁnd that R5 helps in short-circuit transient recovery

as well. However, too large of an R5 value will slow down

the turn-off time. The recommended R5 range is between

5Ω and 500Ω.

capacitor between V and GND. A surge suppressor, Z1

DD

in Figure 1, at the input can also prevent damage from

voltage surges.

Design Example

As a design example, take the following speciﬁcations for

channel 1: V = 12V, I

= 5A, I

= 1A, dI/dt

IN

MAX

INRUSH

= 10.75V, V

OV(FALLING)

= 10A/ms, C = 330µF, V

L

UV(RISING)

2

= 14.0V,V

=11.6V,andI CADDRESS=1000111.

PWRGD(UP)

This completed design is shown in Figure 1.

The second type of source follower oscillation occurs at

frequencies between 200kHz and 800kHz due to the load

4222fb

18

LTC4222

APPLICATIONS INFORMATION

Selectionofthesenseresistor,R ,issetbytheovercurrent

The inrush dI/dt is set to 10A/ms using C :

SS

S

threshold of 50mV:

I_SS

 

1

C_SS=

•0.0429•

50mV

I_MAX

A

R_SENSE

R_S=

= 0.01Ω

dl/dt

 

s

 

10µA •0.0429•1

10000•0.01Ω

The MOSFET is sized to handle the power dissipation dur-

ing inrush when output capacitor C is being charged.

=

= 4.3nF choose 4.7nF

OUT

A method to determine power dissipation during inrush

For a start-up time of 4ms with a 2x safety margin we

choose:

is based on the principle that:

Energy in C = Energy in Q1

L

2•t_STARTUP

C_TIMER

=

+ C_SS•2

This uses:

Energy in C_L= CV²= (0.33mF)(12)²

12.3ms/µF

8ms

1

+ 4.7nF •2= 0.68µF

2

12.3ms/µF

or 0.024 joules. Calculate the time it takes to charge up

OUT

Note the minimum value of C

is 10nF.

TIMER

C

:

The UV and OV resistor string values can be solved in the

following method. First pick R3 based on I being

1.235V/R3 at the edge of the OV rising threshold. Then

solve the following equations:

C_L•V_DDI

0.33mF •12V

STRING

INRUSH

t_STARTUP

=

= 4ms

I

1A

INRUSH

The power dissipated in the MOSFET:

V

UV_TH(RISING)

R2= ^OV(OFF)•R3•

–R3

Energy in C_L

V_UV(ON)

OV_TH(FALLING)

P_DISS

=

= 6W

t_STARTUP

V_UV(ON)•(R3+ R2)

R1=

–R3–R2

TheSOA(safeoperatingarea)curvesofcandidateMOSFETs

must be evaluated to ensure that the heat capacity of the

package tolerates 6W for 4ms. The SOA curves of the

Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,

satisfying this requirement. Since the FDC653N has less

than 8nF of gate capacitance and we are using a GATE

RC network, the short-circuit stability of the current limit

should be checked and improved by adding a capacitor

from GATE to SOURCE if needed.

UV_TH(RISING)

In our case we choose R3 to be 3.4k to give a resistor

string current below 100µA.

Then solving the equations results in R2 = 1.16k and

R1 = 34.6k.

The FB divider is solved by picking R8 and solving for R7,

choosing 3.57k for R8 we get:

The inrush current is set to 1A using C1:

V_PWRGD(UP)•R8

R7=

–R8

C_L•I_GATE

C1=

FB_TH(RISING)

I

INRUSH

Resulting in R7 = 30k

0.33mF •12µA

C1=

or C1= 3.9nF

A 0.1µF capacitor, C , is placed on the UV pins to prevent

F

1A

supply glitches from turning off the GATE via UV or OV.

4222fb

19

LTC4222

APPLICATIONS INFORMATION

Digital Interface

The address is set with the help of Table 1, which indi-

cates binary address 1000111 corresponds to address

4. Address 4 is set by setting ADR2 low, ADR1 open and

ADR0 high.

The LTC4222 communicates with a bus master using a

2

2-wire interface compatible with I C Bus and SMBus, an

2

I C extension for low power devices. The LTC4222 is a

read-write slave device and supports SMBus bus Read

Byte, Write Byte, Read Word and Write Word commands.

A complete list of the resistors of the LTC4222 is shown

in Table 2. The second word in a Read Word command is

the contents of the subsequent 8-bit register. The second

word in a Write Word command is ignored. Data formats

for these commands are shown in Figures 6 to 11.

Next the value of R5 and R6 are chosen to be the default

values 10Ω and 15kΩ as discussed previously.

In addition a 0.1µF ceramic bypass capacitor is placed on

the INTV pin.

CC

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is required. The minimum trace width for 1oz copper

foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

resistance of about 530µΩ. Small resistances add up

quickly in high current applications. To improve noise

immunity, put the resistive dividers to the UV, OV and FB

TheLTC4222interfacealsofeaturesa25mstimeoutfeature

to prevent the bus being stuck low if a communication

error occurs. If either the SCL or SDA lines remain low

for more than 25ms the LTC4222 will reset it’s interface

and release the SDAO pin, freeing the bus to resume

communication.

The LTC4222 also features PMBus compatibility, the in-

terfacewillnotacknowledgeunsupportedcommandsand

the internal addresses are in the manufacturer speciﬁed

address space under the PMBus speciﬁcation.

pins close to the device and keep traces to V and GND

DD

short. It is also important to put the bypass capacitor for

the INTV pin, C3, as close as possible between INTV

CC

and GND. 0.1µF capacitors from the UV pins (and OV pins

throughresistorR2)toGNDalsohelpsrejectsupplynoise.

Figure 5 shows a layout that addresses these issues. Note

that surge suppressor, Z1 is placed between supply and

ground using wide traces.

START and STOP Conditions

When the bus is idle, both SCL and SDA are high. A bus

mastersignalsthebeginningofatransmissionwithastart

condition by transitioning SDA from high to low while SCL

ishigh,asshowninFigure6.Whenthemasterhasﬁnished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

I

LOAD

SENSE RESISTOR R

S

R1

R3

Z1

2

I C Device Addressing

C

F

R2

VIAS TO

GROUND

PLANE

Twenty seven distinct bus addresses are available using

three3-stateaddresspins,ADR0,ADR1andADR2.Table 1

shows the correspondence between pin states and ad-

dresses. In addition, the LTC4222 responds to two special

addresses. Address (1100 0110) is a mass write address

that writes to all LTC4222s, regardless of their individual

address settings. Mass write can be disabled by setting

registerbit4intheCONTROLregisterofchannel2tozero.

Address(0001100)istheSMBusAlertResponseAddress.

If the LTC4222 is pulling low on the ALERT pin due to an

C

SS

CONFIG

SS

LTC4222UHD

C3

INTV

GND

CC

VIA TO

GROUND

PLANE

4222 F05

Figure 5. Recommended Layout

4222fb

20

LTC4222

APPLICATIONS INFORMATION

SDA

a6 - a0

b7 - b0

SCL

1 - 7

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

4222 F06

Figure 6. Data Transfer Over I²C or SMBus

alert, it acknowledges this address by broadcasting its

LTC4222 acknowledges this and then the master sends

a command byte which indicates which internal register

the master wishes to write. The LTC4222 acknowledges

this and then latches the lower three bits of the command

byte into its internal Register Address pointer. The master

thendeliversthedatabyteandtheLTC4222acknowledges

once more and latches the data into its control register.

The transmission is ended when the master sends a STOP

condition. If the master continues sending a second data

byte, as in a Write Word command, the second data byte

is acknowledged by the LTC4222 but ignored, as shown

in Figure 8.

address and releasing the ALERT pin.

Acknowledge

The acknowledge signal is used in handshaking between

transmitter and receiver to indicate that the last byte of

data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it pulls down the SDA line so that it

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generatingaSTOPcondition.Whenthemasterisreceiving

data from the slave, the master pulls down the SDA line

during the clock pulse to indicate receipt of the data. After

the last byte has been received the master leaves the SDA

line HIGH (not acknowledge) and issues a stop condition

to terminate the transmission.

Read Protocol

The master begins a read operation with a START con-

dition followed by the seven bit slave address and the

R/W bit set to zero, as shown in Figure 9. The addressed

LTC4222 acknowledges this and then the master sends

a command byte which indicates which internal register

the master wishes to read. The LTC4222 acknowledges

this and then latches the lower three bits of the command

byte into its internal Register Address pointer. The master

then sends a repeated START condition followed by the

Write Protocol

The master begins communication with a START con-

dition followed by the seven bit slave address and the

R/W bit set to zero, as shown in Figure 7. The addressed

S

ADDRESS W A

a7:a0

COMMAND

b7:b0

A

0

DATA

b7:b0

A

0

DATA

A

0

P

0

X X X X X X X X

S

ADDRESS W A

a7:a0

COMMAND

b7:b0

A

0

DATA

b7:b0

A

0

P

4222 F08

0

Figure 8. LTC4222 Serial Bus SDA Write Word Protocol

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

S: START CONDITION

S

ADDRESS W A

a7:a0

COMMAND

b7:b0

A

0

S

ADDRESS

a7:a0

R

1

A

0

DATA

b7:b0

A

P

P: STOP CONDITION

0

1

4222 F07

4222 F09

Figure 9. LTC4222 Serial Bus SDA Read Byte Protocol

Figure 7. LTC4222 Serial Bus SDA Write Byte Protocol

4222fb

21

LTC4222

APPLICATIONS INFORMATION

same seven bit address with the R/W bit now set to one.

The LTC4222 acknowledges and send the contents of the

requested register. The transmission is ended when the

mastersendsaSTOPcondition.Ifthemasteracknowledges

the transmitted data byte, as in a Read Word command,

Figure 10, the LTC4222 repeats the requested register as

the second data byte.

correspondingfaultcausestheALERTpintopulllow.After

the bus master controller broadcasts the Alert Response

Address, the LTC4222 responds with its address on the

SDA line and then release ALERT as shown in Figure 11.

The ALERT line is also released if the device is addressed

by the bus master. The ALERT signal is not pulled low

again until the FAULT register indicates a different fault

has occurred or the original fault is cleared and it occurs

again. Note that this means repeated or continuing faults

do not generate alerts until the associated FAULT register

bit has been cleared.

Alert Response Protocol

When any of the fault bits in the FAULT register are set,

an optional bus alert is generated if the appropriate bit in

the ALERT register is also set. If an alert is enabled, the

S

ADDRESS W A

a7:a0

COMMAND

b7:b0

A

0

S

ADDRESS

a7:a0

R

1

A

0

DATA

b7:b0

A

0

DATA

b7:b0

A

P

0

1

4222 F10

Figure 10. LTC4222 Serial Bus SDA Read Word Protocol

ALERT

RESPONSE

ADDRESS

DEVICE

S

R

1

P

A

0

A

ADDRESS

0 0 0 1 1 0 0

a7:a0

1

4222 F11

Figure 11. LTC4222 Serial Bus SDA Alert Response Protocol

4222fb

22

LTC4222

APPLICATIONS INFORMATION

Table 1. LTC4222 I²C Device Addressing

DEVICE

LTC4222

ADDRESS PINS

DESCRIPTION

ADDRESS

DEVICE ADDRESS

h

7

1

0

1

6

1

0

1

5

0

1

0

1

4

0

1

0

1

0

1

0

1

0

3

0

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ADR2

X

ADR1

X

ADR0

X

Mass Write

C6

19

Alert Response

1

X

0

1

88

X

L

NC

H

L

8A

8C

8E

L

NC

H

2

L

NC

L

3

L

4

98

L

5

9A

9C

9E

L

H

6

L

NC

H

7

L

8

A8

AA

AC

AE

B8

BA

BC

BE

C8

CA

CC

CE

D8

DA

DC

DE

E8

NC

H

NC

H

L

9

NC

H

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

NC

L

H

L

NC

H

L

NC

H

L

H

NC

H

NC

L

H

L

H

L

NC

H

L

H

L

EA

EC

NC

H

L

H

L

4222fb

23

LTC4222

APPLICATIONS INFORMATION

Table 2. LTC4222 Register Addresses and Contents

REGISTER ADDRESS

Decimal

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

Hex

D0h

D1h

D2h

D3h

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

E0h

E1h

E2h

E3h

E4h

REGISTER NAME

Control1 (A1)

Alert1 (B1)

DESCRIPTION

Sets Behavior for Channel 1

Selects Which Channel 1 Faults Generate Alerts

Displays the Status of Channel 1

Fault Log for Channel 1

Sets Behavior for Channel 2

Selects which Channel 2 Faults Generate Alerts

Displays the Status of Channel 2

Fault Log for Channel 2

ADC SOURCE1 MSB data

ADC SOURCE1 LSB data

ADC SOURCE2 MSB data

ADC SOURCE2 LSB data

ADC ADIN1 MSB

Status1 (C1)

Fault1 (D1)

Control2 (A2)

Alert2 (B2)

Status2 (C2)

Fault2 (D2)

SOURCE1 MSB

SOURCE1 LSB

SOURCE2 MSB

SOURCE2 LSB

ADIN1 MSB

ADIN1 LSB

ADC ADIN1 LSB

ADIN2 MSB

ADC ADIN2 MSB

ADIN2 LSB

ADC ADIN2 LSB

SENSE1 MSB

SENSE1 LSB

SENSE2 MSB

SENSE2 LSB

ADC CONTROL

ADC SENSE1 MSB

ADC SENSE1 LSB

ADC SENSE2 MSB

ADC SENSE2 LSB

Conﬁgures Behavior of the ADC

+ Set bit ADC_CONTROL(0) before writing

4222fb

24

LTC4222

APPLICATIONS INFORMATION

Table 3. CONTROL Registers A – Read/Write

BIT CONTROL 1 (D0h)

CONTROL 2 (D4h)

OPERATION

7:6 GPIO1 Conﬁgure

GPIO2 Conﬁgure

FUNCTION

A6

0

A7

0

GPIO PIN

GPIO = C3

GPIO = A5

C6 = GPIO

Power Good (Default)

Power

Good

0

1

General Purpose Output

General Purpose Input

1

0

1

5

4

3

GPIO1 Output

GPIO2 Output

Output Data for GPIO Pins When Conﬁgured as General Purpose Output

1 = High Impedance, 0 = Pulled Low

Reserved

Mass Write Enable

Channel 2 FET On Control

Allows Mass Write Addressing

1 = Mass Write Enabled (Default), 0 = Mass Write Disabled

Channel 1 FET On Control

On Control Bit, Latches the State of the On Pin at the End of the

Debounce Delay

1 = FET On, 0 = FET Off

2

1

0

Channel 1 Overcurrent Auto-Retry Channel 2 Overcurrent Auto-Retry Overcurrent Auto-Retry Bit

1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent

(Default)

Channel 1 Undervoltage Auto-Retry Channel 2 Undervoltage Auto-Retry Undervoltage Auto-retry

1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After

Undervoltage

Channel 1 Overvoltage Auto-Retry Channel 2 Overvoltage Auto-Retry Overvoltage Auto-retry

1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After

Overvoltage

Table 4. ALERT Registers B – Read/Write

BIT ALERT 1 (D1h)

ALERT 2 (D5h)

OPERATION

Not Used

7

6

5

Reserved

Channel 1 FET Short Alert

Channel 2 FET Short Alert

Enables Alert for FET Short Condition