LTC4267IGN-3#PBF [Linear]
LTC4267-3 - Power over Ethernet IEEE 802.3af PD Interface with Integrated 300kHz Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LTC4267IGN-3#PBF |
厂家: | Linear |
描述: | LTC4267-3 - Power over Ethernet IEEE 802.3af PD Interface with Integrated 300kHz Switching Regulator; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总34页 (文件大小:363K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4267-3
Power over Ethernet
IEEE 802.3af PD Interface with
Integrated Switching Regulator
FEATURES
n
DESCRIPTION
Complete Power Interface Port for IEEE 802®.3af
Powered Device (PD)
The LTC®4267-3 combines an IEEE 802.3af compliant
PoweredDevice(PD)interfacewitha300kHzcurrentmode
switching regulator, providing a complete power solution
for PD applications. The LTC4267-3 integrates the 25k
signature resistor, classification current source, thermal
overload protection, signature disable and power good
signal along with an undervoltage lockout optimized for
use with the IEEE-required diode bridge. The LTC4267-3
providesanincreasedoperationalcurrentlimit,maximizing
power available for class 3 applications.
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Onboard 100V, UVLO Switch
Constant-Frequency 300kHz Operation
Precision Dual Level Inrush Current Limit
Integrated Current Mode Switching Regulator
Onboard 25k Signature Resistor with Disable
Programmable Classification Current (Class 0-4)
Thermal Overload Protection
Power Good Signal
Integrated Error Amplifier and Voltage Reference
Low Profile 16-Pin SSOP or DFN Packages
The 300kHz current mode switching regulator provides
higher output power or smaller external size compared
to its lower frequency counterparts. The LTC4267-3 is
designed for driving a 6V rated N-channel MOSFET and
features programmable slope compensation, soft-start,
and constant-frequency operation, minimizing noise even
with light loads. The LTC4267-3 includes an onboard er-
ror amplifier and voltage reference allowing use in both
isolated and nonisolated configurations.
APPLICATIONS
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IP Phone Power Management
n
Wireless Access Points
n
Security Cameras
Power over Ethernet
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L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
++
LTPoE is a trademark of Linear Technology Corporation. All other trademarks are the property
The LTC4267-3 is available in a space saving, low profile
16-pin SSOP or DFN packages.
of their respective owners.
TYPICAL APPLICATION
Class 2 PD with 3.3V Isolated Power Supply
PA1133 SBM1040
3.3V
1.5A
10k
+
–48V
•
HD01
FROM
V
P
PORTP
VCC
+
320µF
MIN
P
CHASSIS
DATA PAIR
5µF
MIN
VCC
+
–
•
4.7µF
PWRGD
LTC4267-3
SMAJ58A
NGATE
SENSE
/RUN
Si3440
10k
0.1µF
0.1Ω
P
VCC
R
I
TH
CLASS
470Ω
+
HD01
R
–48V
FROM
SPARE PAIR
CLASS
68.1Ω
6.8k
V
FB
1%
100k
–
22nF
SIGDISA
PGND
BAS516
V
P
OUT
PORTN
PS2911
60.4k
TLV431
42671 TA01
42673fa
1
LTC4267-3
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
P
with Respect to V
Voltage...0.3V to –100V
V , I /RUN to PGND Voltages................–0.3V to 3.5V
SENSE to PGND Voltage ..............................–0.3V to 1V
PORTN
PORTP
FB TH
, SIGDISA, PWRGD
OUT
Voltage..................... V
+ 100V to V
–0.3V
NGATE Peak Output Current (<10μs) ..........................1A
Operating Ambient Temperature Range
PORTN
PORTN
P
VCC
to PGND Voltage (Note 2)
Low Impedance Source ...........................–0.3V to 8V
LTC4267C-3............................................. 0°C to 70°C
LTC4267I-3 ..........................................–40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
Current Fed..........................................5mA into P
VCC
R
Voltage.................V
+ 7V to V
– 0.3V
CLASS
PORTN
PORTN
PWRGD Current.....................................................10mA
R
Current.....................................................100mA
CLASS
NGATE to PGND Voltage ...........................–0.3V to P
VCC
PIN CONFIGURATION
TOP VIEW
TOP VIEW
I
/RUN
1
2
3
4
5
6
7
8
16 V
FB
TH
PGND
/RUN
1
2
3
4
5
6
7
8
16 PGND
PGND
15 PGND
14 SENSE
I
15
14
13
12
11
10
9
V
TH
FB
NGATE
NGATE
SENSE
P
13 V
PORTP
VCC
17
P
V
VCC
PORTP
R
12 SIGDISA
11 PWRGD
CLASS
NC
R
SIGDISA
PWRGD
CLASS
NC
VPORTN
NC
10
9
P
OUT
V
NC
P
PORTN
OUT
PGND
PGND
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
= 150°C, θ = 90°C/W
T
= 150°C, θ = 43.5°C/W
JA
JMAX
EXPOSED PAD (PIN 17) MUST BE SOLDERED
TO ELECTRICALLY ISOLATED PCB HEAT SINK
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
LTC4267CDHC-3#PBF
LTC4267IDHC-3#PBF
LTC4267CGN-3#PBF
LTC4267IGN-3#PBF
LEAD BASED FINISH
LTC4267CDHC-3
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4267CDHC-3#TRPBF 4267-3
0°C to 70°C
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
PACKAGE DESCRIPTION
LTC4267IDHC-3#TRPBF
LTC4267CGN-3#TRPBF
LTC4267IGN-3#TRPBF
TAPE AND REEL
4267-3
–40°C to 85°C
0°C to 70°C
4267-3
4267I-3
PART MARKING*
4267-3
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
LTC4267CDHC-3#TR
LTC4267IDHC-3#TR
LTC4267CGN-3#TR
LTC4267IGN-3#TR
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
LTC4267IDHC-3
4267-3
–40°C to 85°C
0°C to 70°C
LTC4267CGN-3
4267-3
LTC4267IGN-3
4267-3
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42673fa
2
LTC4267-3
The ● denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Voltage with Respect to V
Pin
PORTP
PORTN
Maximum Operating Voltage
Signature Range
(Notes 4, 5, 6)
●
●
●
●
●
–57
–9.5
–21
–37.2
–31.5
V
V
V
V
V
–1.5
–12.5
–34.8
–29.3
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
–36
–30.5
●
●
●
●
V
V
V
V
P
P
P
P
Turn-On Voltage
Turn-Off Voltage
Hysteresis
Voltage with Respect to PGND
Voltage with Respect to PGND
7.6
4.6
1
8.7
5.7
3
9.2
7
V
V
V
V
TURNON
TURNOFF
HYST
VCC
VCC
VCC
VCC
V
– V
TURNOFF
TURNON
Shunt Regulator Voltage
I
= 1mA, V /RUN = 0V, Voltage with Respect
8.3
9.4
10.3
CLAMP1mA
PVCC
ITH
to PGND
●
●
V
V
V
P
– V Margin
TURNON
0.05
0.6
V
MARGIN
CLAMP1mA
I
I
Supply Current when ON
V
= –48V, P , PWRGD, SIGDISA Floating
3
mA
VPORTN_ON
PVCC_ON
PORTN
PORTN
OUT
Supply Current
Normal Operation
Start-Up
(Note 7)
V
P
VCC
/RUN – PGND = 1.3V
– PGND = VT
●
●
350
90
µA
µA
240
40
ITH
VCC
– 100mV
URNON
●
●
●
●
I
V
Supply Current During
V
= –17.5V, P
Tied to V , R ,
PORTP CLASS
0.35
0.5
0.65
mA
VPORTN_
PORTN
PORTN
OUT
Classification
SIGDISA Floating (Note 8)
CLASS
Current Accuracy During
Classification
10mA < I
(Note 9)
< 40mA, –12.5V ≤ V
≤ –21V
3.5
%
ΔI
CLASS
PORTN
CLASS
R
Signature Resistance
–1.5V ≤ V
≤ –9.5V, P
Tied to V , IEEE
PORTP
23.25
26.00
11.8
kW
kW
SIGNATURE
INVALID
PORTN
OUT
802.3af 2-Point Measurement (Notes 4, 5)
R
Invalid Signature Resistance
–1.5V ≤ V ≤ – 9.5V, SIGDISA and P
Tied to
OUT
9
PORTN
V
, IEEE 802.3af 2-Point Measurement (Notes
PORTP
4, 5)
●
●
V
V
Signature Disable
With Respect to V
3
57
V
V
IH
PORTN
High Level Input Voltage
High Level Invalidates Signature (Note 10)
Signature Disable
Low Level Input Voltage
With Respect to V
0.45
IL
PORTN
Low Level Enables Signature
●
●
R
Signature Disable, Input Resistance With Respect to V
100
kW
INPUT
PORTN
V
Power Good Output Low Voltage
I = 1mA V
= –48V,
0.5
V
PG_OUT
PORTN
PWRGD Referenced to V
PORTN
Power Good Trip Point
V
= –48V, Voltage between V
and P
PORTN OUT
PORTN
V
V
(Note 11)
●
●
1.3
2.7
1.5
3
1.7
3.3
V
V
PG _FALL
PG_RISE
P
P
Falling
Rising
OUT
OUT
●
I
Power Good Leakage Current
On-Resistance
V
= 0V, PWRGD FET Off, V = 57V
PWRGD
1
µA
PG_LEAK
PORTN
R
I = 300mA, V
to P
= –48V, Measured from V
1
1.6
2
W
W
ON
PORTN
(Note 11)
PORTN
●
●
OUT
V
I
Shutdown Threshold (at I /RUN)
P
V
– PGND = V + 100mV
TURNON
0.15
0.2
0.28
0.3
0.45
0.4
V
µA
ITHSHDN
TH
VCC
Start-Up Current Source at I /RUN
/RUN – PGND = 0V, P
VCC
ITH
– P
= 8V
GND
THSTART
TH
●
V
Regulated Feedback Voltage
Referenced to PGND, P
VCC
– P
GND
= 8V (Note 12)
0.780
0.800
10
0.812
50
V
FB
I
FB
V
Input Current
FB
P
VCC
– P
= 8V (Note 12)
GND
nA
g
Error Amplifier Transconductance
Output Voltage Line Regulation
Output Voltage Load Regulation
I
/RUN Pin Load = 5µA (Note 12)
200
333
0.05
500
µA/V
mV/V
m
TH
V
< P
< V
(Note 12)
CLAMP
ΔV
ΔV
TURNOFF
VCC
O(LINE)
I
TH
/RUN Sinking 5µA, P
– P
= 8V (Note 12)
= 8V (Note 12)
3
3
mV/µA
mV/µA
VCC
GND
– P
TH
O(LOAD)
I
/RUN Sourcing 5µA, P
VCC
GND
= 0V, Power MOSFET Off, P = 57V (Note 13)
OUT
●
I
P
Leakage
V
150
µA
POUT_LEAK
OUT
PORTN
42673fa
3
LTC4267-3
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
350
90
TYP
MAX
450
205
330
9.6
UNITS
mA
●
●
I
I
f
Input Current Limit, High Level
Input Current Limit, Low Level
Oscillator Frequency
V
V
V
V
= –48V, P
= –43V (Note 14, 15)
= –43V (Note 14, 15)
LIM_HI
LIM_LO
OSC
PORTN
PORTN
OUT
= –48V, P
mA
OUT
/RUN – PGND = 1.3V, P
– P
= 8V
270
300
8
kHz
%
VCC
GND
ITH
ITH
DC
DC
t
Minimum Switch On Duty Cycle
/RUN – PGND = 1.3V, V – PGND = 0.8V, P
VCC
VCC
ON(MIN)
FB
– P
= 8V
GND
Maximum Switch On Duty Cycle
V
/RUN – PGND = 1.3V, V – PGND = 0.8V, P
GND
70
90
80
90
%
ON(MAX)
ITH
FB
– P
= 8V
NGATE Drive Rise Time
NGATE Drive Fall Time
Peak Current Sense Voltage
C
= 3000pF, P
= 3000pF, P
– P
– P
= 8V
= 8V
40
40
100
5
ns
ns
VCC
VCC
GND
GND
RISE
FALL
LOAD
t
C
LOAD
GND
●
V
I
R
= 0, P
– P
= 8V (Note 16)
115
mV
A
VCC
GND
IMAX
SL
Peak Slope Compensation Output
Current
P
VCC
– P
– P
= 8V (Note 17)
SLMAX
t
Soft-Start Time
P
VCC
= 8V
1.4
ms
°C
GND
SFST
T
Thermal Shutdown Trip Temperature (Notes 14, 18)
140
SHUTDOWN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
R
. The current accuracy does not include variations in R
CLASS
CLASS
resistance. The total classification current for a PD also includes the IC
quiescent current (I ). See the Applications Information section.
Note 10: To disable the 25k signature, tie SIGDISA to V
SIGDISA high with respect to V
section.
VPORTN_CLASS
or hold
PORTP
Note 2: P
internal clamp circuit self regulates to 9.4V with respect to
. See the Applications Information
VCC
PORTN
PGND.
Note 3: The LTC4267-3 operates with a negative supply voltage in the
range of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface
are always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and
a “rising negative voltage” refers to a voltage that is becoming more
negative.
Note 4: The LTC4267-3 is designed to work with two polarity protection
diode drops between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics section are with respect to this product pins and
are designed to meet IEEE 802.3af specifications when these diode drops
are included. See the Application Information section.
Note 5: Signature resistance is measured via the two-point ΔV/ΔI method
as defined by IEEE 802.3af. The PD signature resistance is offset from
the 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4267-3
pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and
–9.5V.
Note 6: The PD interface includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD
will power up from a voltage source with 20Ω series resistance on the first
trial.
Note 11: For the DHC package, this parameter is assured by design and
wafer level testing.
Note 12: The switching regulator is tested in a feedback loop that servos
V
to the output of the error amplifier while maintaining I /RUN at the
FB
TH
midpoint of the current limit range.
Note 13: I includes current drawn through P
by the power
OUT
POUT_LEAK
good status circuit. This current is compensated for in the 25k signature
resistance and does not affect PD operation.
Note 14: The LTC4267-3 PD Interface includes thermal protection. In
the event of an overtemperature condition, the PD interface will turn off
the switching regulator until the part cools below the overtemperature
limit. The LTC4267-3 is also protected against thermal damage from
incorrect classification probing by the PSE. If the LTC4267-3 exceeds the
overtemperature threshold, the classification load current is disabled.
Note 15: The PD interface includes dual level input current limit. At turn-
on, before the P
to a low level. After the load capacitor is charged and the P
load capacitor is charged, the PD current level is set
OUT
– V
OUT
PORTN
voltage difference is below the power good threshold, the PD switches to
high level current limit. The PD stays in high level current limit until the
input voltage drops below the UVLO turn-off threshold.
Note 16: Peak current sense voltage is reduced dependent on duty cycle
and an optional external resistor in series with the SENSE pin (R ). For
SL
Note 7: Dynamic Supply current is higher due to the gate charge being
delivered at the switching frequency.
details, refer to the programmable slope compensation feature in the
Applications Information section.
Note 17: Guaranteed by design.
Note 18: The LTC4267-3 features thermal overload protection. Thermal
overload protection is intended to protect the device during momentary
fault conditions and continuous operation in thermal overload should be
avoided as it may impair device reliability.
Note 8: I
programmed at the R
does not include classification current
VPORTN_CLASS
pin. Total current in classification mode will be
CLASS
I
+ I
CLASS
(See note 9).
VPORTN_CLASS
Note 9: I
is the measured current flowing through R
. ΔI
CLASS
CLASS CLASS
accuracy is with respect to the ideal current defined as I
= 1.237/
CLASS
42673fa
4
LTC4267-3
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Classification Range
Input Current vs Input Voltage
0.5
0.4
0.3
0.2
50
40
30
20
12.0
11.5
T
= 25°C
T = 25°C
A
CLASS 1 OPERATION
A
CLASS 4
CLASS 3
11.0
85°C
–40°C
10.5
10.0
CLASS 2
CLASS 1
0.1
0
10
0
9.5
9.0
CLASS 0
0
–4
–6
–8
–10
0
–20
–30
–40
–50
–60
–2
–10
–12
–14
–16
–18
VOLTAGE (V)
–20
–22
V
VOLTAGE (V)
V
PORTN
VOLTAGE (V)
V
PORTN
PORTN
42673 G01
42673 G02
42673 G03
Signature Resistance
vs Input Voltage
Normalized UVLO Threshold
vs Temperature
Input Current vs Input Voltage
3
2
1
0
2
1
28
27
EXCLUDES ANY LOAD CURRENT
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
∆V V2 – V1
RESISTANCE =
DIODES: S1B
=
T
= 25°C
∆I
I – I
A
2 1
T
= 25°C
A
IEEE UPPER LIMIT
26
LTC4267-3 + 2 DIODES
0
25
24
–1
LTC4267-3 ONLY
IEEE LOWER LIMIT
23
22
–2
–40
–45
–50
–55
–60
–40 –20
0
20
40
60
80
V1: –1
V2: –2
–3
–4
–5
–6
PORTN
–7
–8
–9
–10
TEMPERATURE (°C)
V
VOLTAGE (V)
PORTN
V
VOLTAGE (V)
42673 G04
42673 G06
42673 G05
Power Good Output Low Voltage
vs Current
P
OUT Leakage Current
Current Limit vs Input Voltage
120
4
3
2
1
0
400
300
200
100
T
= 25°C
V
T
= 0V
A
IN
A
85°C
= 25°C
– 40°C
HIGH CURRENT MODE
90
60
30
0
LOW CURRENT MODE
85°C
– 40°C
0
2
4
6
8
10
0
20
40
60
–45
–50
–55
–40
–60
P
PIN VOLTAGE (V)
CURRENT (mA)
OUT
V
VOLTAGE (V)
PORTN
42673 G07
42673 G08
42673 G09
42673fa
5
LTC4267-3
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Reference Voltage
vs Temperature
Reference Voltage
vs Supply Voltage
801.0
800.8
800.6
800.4
800.2
800.0
799.8
799.6
799.4
799.2
799.0
812
808
804
800
796
792
788
330
320
310
300
290
280
270
P
= 8V
V
= 8V
CC
VCC
T
= 25°C
A
P
≤ V
VCC
CLAMP1mA
–30 –10 10 30 50
TEMPERATURE (°C)
110
50 70
–50 –30 –10 10 30
TEMPERATURE (°C)
–50
70 90
8
9.5
6
7
7.5
8.5
9
90 110 130
6.5
P
SUPPLY VOLTAGE (V)
VCC
42673 G10
42673 G11
42673 G12
Oscillator Frequency
vs VCC Shunt Regulator Current
PVCC Undervoltage Lockout
Thresholds vs Temperature
Oscillator Frequency
vs Supply Voltage
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
330
320
310
300
290
280
270
330
320
310
300
290
280
270
V
TURNON
V
TURNOFF
30
–50
80 90
–30 –10 10
50
110
6
7
7.5
8
8.5
9
0
10
15
20
25
30
35
6.5
5
TEMPERATURE (°C)
V
SUPPLY VOLTAGE (V)
I
(mA)
CC
CC
42673 G14
42673 G13b
42673 G13
PVCC Shunt Regulator Voltage
vs Temperature
I
PVCC Supply Current
vs Temperature
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
265
260
255
250
245
240
235
230
225
220
215
P
V
= 8V
VCC
ITH/RUN
= 1.3V
I
= 1mA
PVCC
–50 –30 –10 10 30 50 70
TEMPERATURE (°C)
90
–50
30
TEMPERATURE (°C)
70 90
110
–30 –10 10
50
110
42673 G15
42673 G16
42673fa
6
LTC4267-3
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up IPVCC Supply Current
vs Temperature
ITH/RUN Shutdown Threshold
vs Temperature
ITH/RUN Start-Up Current Source
vs Temperature
450
400
600
500
400
300
200
100
0
60
50
40
30
20
10
0
P
V
= V
ITH/RUN
+ 0.1V
P
= V
– 0.1V
TURNON
VCC
TURNON
= 0V
VCC
350
300
250
200
150
100
–30 –10 10 30 50
TEMPERATURE (°C)
110
50 70
–50 –30 –10 10 30
TEMPERATURE (°C)
–50
70 90
90 110
50 70
–50 –30 –10 10 30
TEMPERATURE (°C)
90 110
42673 G18
42673 G19
42673 G17
Peak Current Sense Voltage
vs Temperature
Soft-Start Time vs Temperature
120
115
110
105
100
95
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
P
= 8V
VCC
90
85
80
30 50
–50 –30 –10 10
TEMPERATURE (°C)
30 50
TEMPERATURE (°C)
70 90 110
–50 –30 –10 10
70 90 110
42673 G20
42673 21
42673fa
7
LTC4267-3
PIN FUNCTIONS(DFN/SSOP)
PGND (Pins 2, 15/Pins 1, 8, 9, 16): Switching Regulator
PWRGD (Pin 11): Power Good Output, Open-Drain.
Indicates that the PD MOSFET is on and the switching
regulator can start operation. Low impedance indicates
power is good. PWRGD is high impedance during detec-
tion, classification and in the event of a thermal overload.
Negative Supply. This pin is the negative supply rail for the
switching regulator controller and must be tied to P
.
OUT
I /RUN (Pin 1/Pin 2): Current Threshold/Run Input. This
TH
pin performs two functions. It serves as the switching
regulator error amplifier compensation point as well as
the run/shutdown control input. Nominal voltage range is
0.7V to 1.9V. Forcing the pin below 0.28V with respect to
PGND causes the controller to shut down.
PWRGD is referenced to V
.
PORTN
SIGDISA (Pin 12): Signature Disable Input. SIGDISA al-
lows the PD to present an invalid signature resistance and
remain inactive. Connecting SIGDISA to V
lowers
PORTP
the signature resistance to an invalid value and disables
all functions of the LTC4267-3. If unused, tie SIGDISA to
PORTN
NGATE (Pin 3): Gate Driver Output. This pin drives the
regulator’s external N-Channel MOSFET and swings from
V
.
PGND to P
.
VCC
V
(Pin 13): Positive Power Input. Tie to the input
PORTP
P
(Pin 4): Switching Regulator Positive Supply. This
VCC
port power return through the input diodes.
pin is the positive supply rail for the switching regulator
and must be closely decoupled to PGND.
SENSE (Pin 14): Current Sense. This pin performs two
functions.Itmonitorstheregulatorswitchcurrentbyread-
ing the voltage across an external sense resistor. It also
injectsacurrentrampthatdevelopsaslopecompensation
voltage across an optional external programming resistor.
See the Applications Information section.
R
(Pin 5): Class Select Input. Used to set the current
CLASS
value the PD maintains during classification. Connect a
resistor between R and V (see Table 2).
CLASS
PORTN
NC (Pins 6, 8, 9/Pin 6): No Internal Connection.
(Pin 7): Negative Power Input. Tie to the –48V
V
V (Pin16/Pin15):FeedbackInput.Receivesthefeedback
PORTN
FB
input port through the input diodes.
voltagefromtheexternalresistordivideracrosstheoutput.
P
(Pin10):PowerOutput.Supplies–48Vtotheswitch-
ExposedPad(Pin17,DFNOnly):Ground.TheExposedPad
must be soldered to an electrically isolated PCB heat sink.
OUT
ingregulatorPGNDpinandanyadditionalPDloadsthrough
an internal power MOSFET that limits input current. P
OUT
is high impedance until the voltage reaches the turn-on
UVLO threshold. The output is then current limited. See
the Application Information section.
42673fa
8
LTC4267-3
BLOCK DIAGRAM
V
SIGDISA
P
VCC
PORTP
CLASSIFICATION
CURRENT LOAD
SHUTDOWN
COMPARATOR
1.237V
+
–
P
<
0.3µA 0.28V
+
–
VCC
V
TURNON
UNDERVOLTAGE
LOCKOUT
V
CC
SHUNT
9k
25k
SIGNATURE
RESISTOR
800mV
REFERENCE
REGULATOR
EN
R
CLASS
16k
PWRGD
SHUTDOWN
SOFT-
START
CLAMP
POWER GOOD
CONTROL
CIRCUITS
CURRENT
P
VCC
–
ERROR
AMPLIFIER
COMPARATOR
+
–
SWITCHING
NGATE
R
LOGIC AND
BLANKING
CIRCUIT
+
Q
V
FB
INPUT
CURRENT
LIMIT
GATE
DRIVER
S
375mA
I
/RUN
TH
EN
+
SLOPE
140mA
COMP
CURRENT
RAMP
20mV
300kHz
OSCILLATOR
–
1.2V
V
PORTN
SENSE
42673 BD
P
OUT
PGND
BOLD LINE INDICATES HIGH CURRENT PATH
W U U
U
APPLICATIO S I FOR ATIO
OVERVIEW
LTC4267-3hasbeenspecificallydesignedtointerfacewith
both IEEE compliant Power Sourcing Equipment (PSE)
and legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. By setting
the initial inrush current limit to a low level, a PD using
the LTC4267-3 minimizes the current drawn from the PSE
duringstart-up.Afterpoweringup,theLTC4267-3switches
to the high level current limit, thereby allowing the PD to
consume up to 13.0W if an IEEE 802.3af PSE is present.
This low level current limit also allows the LTC4267-3 to
charge arbitrarily large load capacitors without exceeding
the inrush limits of the IEEE 802.3af specification. This
dual level current limit provides the system designer with
flexibility to design PDs which are compatible with legacy
PSEs while also being able to take advantage of the higher
power available in an IEEE 802.3af system.
The LTC4267-3 is partitioned into two major blocks: a
Powered Device (PD) interface controller and a current
mode flyback switching regulator. The Powered Device
(PD) interface is intended for use as the front end of a
PD adhering to the IEEE 802.3af standard, and includes
a trimmed 25k signature resistor, classification current
source, and an input current limit circuit. With these
functions integrated into the LTC4267-3, the signature
and power interface for a PD can be built that meets all
the requirements of the IEEE 802.3af specification with a
minimum of external components.
The switching regulator portion of the LTC4267-3 is a
constant-frequency current mode controller that is opti-
mized for Power over Ethernet applications. The regulator
is designed to drive a 6V N-channel MOSFET and features
soft-start and programmable slope compensation. The
integrated error amplifier and precision reference give the
PD designer the option of using a nonisolated topology
withouttheneedforanexternalamplifierorreference. The
Using an LTC4267-3 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4267-3 current limit circuit includes an onboard 100V
power MOSFET. This low leakage MOSFET is specified to
42673fa
9
LTC4267-3
APPLICATIONS INFORMATION
DETECTION V1
DETECTION V2
TIME
avoid corrupting the 25k signature resistor while also sav-
ing board space and cost. In addition, the inrush current
limit requirement of the IEEE 802.3af standard can cause
largetransientpowerdissipationinthePD.TheLTC4267-3
is designed to allow multiple turn-on sequences without
overheating the miniature 16-lead package. In the event of
excessive power cycling, the LTC4267-3 provides thermal
overload protection to keep the onboard power MOSFET
within its safe operating area.
–10
–20
–30
–40
–50
CLASSIFICATION
UVLO
TURN-OFF
UVLO
TURN-ON
TIME
C1
τ = R
LOAD
–10
–20
–30
–40
–50
UVLO
OFF
UVLO
ON
UVLO
OFF
OPERATION
I
dV
dt
LIM_LO
C1
=
The LTC4267-3 PD interface has several modes of opera-
tion depending on the applied input voltage as shown in
Figure 1 and summarized in Table 1. These modes satisfy
therequirementsdefinedintheIEEE802.3afspecification.
TIME
–10
–20
–30
–40
–50
The input voltage is applied to the V
pin and must
POWER
BAD
POWER
GOOD
POWER
BAD
PORTN
be negative relative to the V
pin. Voltages in the data
PORTP
sheet for the PD interface portion of the LTC4267-3 are
with respect to V while the voltages for the switch-
PWRGD TRACKS
PORTP
V
PORTN
ing regulator are referenced to PGND. It is assumed that
PGND is tied to P . Note the use of different ground
OUT
CURRENT
LIMIT, I
I
LIM_LO
symbols throughout the data sheet.
LIM_LO
LOAD, I
(UP TO I
)
LOAD
LIM_HI
Table 1. LTC4267-3 Operational Mode
as a Function of Input Voltage
I
CLASS
CLASSIFICATION
CLASS
I
INPUT VOLTAGE
(V
PORTN
with RESPECT to V
) LTC4267-3 MODE OF OPERATION
Inactive
PORTP
TIME
DETECTION I
2
0V to –1.4V
DETECTION I
1
–1.5V to –9.5V**
–9.8V to –12.4V
25k Signature Resistor Detection
VOLTAGES WITH RESPECT TO V
V1 – 2 DIODE DROPS
PORTP
Classification Load Current Ramps up
from 0% to 100%
I
1
=
25kΩ
V2 – 2 DIODE DROPS
25kΩ
I
2
=
–12.5V to UVLO*
UVLO* to –57V
Classification Load Current Active
I
I
DEPENDENT ON R
SELECTION
Power Applied to Switching Regulator
CLASS
CLASS
= 140mA (NOMINAL), I
= 375mA (NOMINAL)
LIM_LO
LIM_HI
*V
UVLO includes hysteresis.
PORTN
V
OUT
Rising input threshold ≅ –36.0V
I
=
(UP TO I
)
LOAD
LIM_HI
R
LOAD
Falling input threshold ≅ –30.5V
**Measured at LTC4267-3 pin. The LTC4267-3 meets the IEEE 802.3af 10V
minimum when operating with the required diode bridges.
R
LOAD
R9
I
IN
R
V
CLASS PORTP
PSE
V
IN
V
OUT
LTC4267-3
R
CLASS
C1
PWRGD
V
P
OUT
PORTN
42673 F01
PGND
Figure 1. Output Voltage, PWRGD and PD
Current as a Function of Input Voltage
42673fa
10
LTC4267-3
APPLICATIONS INFORMATION
Series Diodes
commodate the voltage drop of the two diodes. The IEEE
specificationrequiresthePSEtouseaΔV/ΔImeasurement
technique to keep the DC offset of these diodes from af-
fecting the signature resistance measurement. However,
the diode resistance appears in series with the signature
resistor and must be included in the overall signature
resistance of the PD. The LTC4267-3 compensates for
the two series diodes in the signature path by offsetting
the resistance so that a PD built using the LTC4267-3 will
meet the IEEE specification.
The IEEE 802.3af-defined operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to accept power of either polarity
at each of its inputs, so it is common to install diode
bridges (Figure 2). The LTC4267-3 takes this into account
by compensating for these diode drops in the threshold
points for each range of operation. A similar adjustment
is made for the UVLO voltages.
Detection
In some applications it is necessary to control whether
or not the PD is detected. In this case, the 25k signature
resistor can be enabled and disabled with the use of the
SIGDISA pin (Figure 3). Disabling the signature via the
SIGDISA pin will change the signature resistor to 9k
(typical) which is an invalid signature per the IEEE 802.3af
specification. ThisinvalidsignatureispresentforPDinput
voltagesfrom–2.8Vto–10V.Iftheinputrisesabove–10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4267-3. To disable the signature,
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable as
aPD.Withtheterminalvoltageinthisrange,theLTC4267-3
connects an internal 25k resistor between the V
and
PORTP
V
pins. This precision, temperature compensated
PORTN
resistor presents the proper signature to alert the PSE
that a PD is present and desires power to be applied. The
internal low-leakage UVLO switch prevents the switching
regulator circuitry from affecting the detection signature.
tie SIGDISA to V . Alternately, the SIGDISA pin can
PORTP
be driven high with respect to V
high, all functions of the PD interface are disabled.
. When SIGDISA is
The LTC4267-3 is designed to compensate for the voltage
and resistance effects of the IEEE required diode bridge.
The signature range extends below the IEEE range to ac-
PORTN
RJ45
+
1
T1
TX
–
TX
BR1
2
3
+
TO PHY
RX
–
RX
6
POWERED DEVICE (PD)
INTERFACE
V
PORTP
AS DEFINED
+
–
SPARE
BY IEEE 802.3af
4
5
LTC4267-3
BR2
D3
V
PORTN
7
8
42673 F02
SPARE
Figure 2. LTC4267-3 PD Front End Using
Diode Bridges on Main and Spare Inputs
42673fa
11
LTC4267-3
APPLICATIONS INFORMATION
CURRENT PATH
LTC4267-3
V
PORTP
PSE
PROBING
LTC4267-3
SIGNATURE DISABLE
SIGDISA
9k
VOLTAGE
TO
PSE
25k SIGNATURE
RESISTOR
V
PORTP
R
CLASS
SOURCE
–15.5V TO –20.5V
16k
CONSTANT
LOAD
R
CLASS
CURRENT
INTERNAL
TO LTC4267-3
V
PORTN
V
PORTN
42673 F04
42673 F03
V
PSE CURRENT MONITOR
Figure 3. 25k Signature Resistor with Disable
PSE
PD
Figure 4. IEEE 802.3af Classification Probing
Classification
The IEEE 802.3af specification limits the classification
time to 75ms because a significant amount of power is
dissipated in the PD. The LTC4267-3 is designed to handle
the power dissipation for this time period. If the PSE prob-
ing exceeds 75ms, the LTC4267-3 may overheat. In this
situation, the thermal protection circuit will engage and
disabletheclassificationcurrentsourceinordertoprotect
the part. The LTC4267-3 stays in classification mode until
the input voltage rises above the UVLO turn-on voltage.
Once the PSE has detected a PD, the PSE may option-
ally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
to identify lower power PDs and allocate less power for
these devices. The IEEE 802.3af specification defines five
classes (Table 2) with varying power levels. The designer
selects the appropriate classification based on the power
consumption of the PD. For each class, there is an as-
sociated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current to determine the proper classification and
PD power requirements.
V
Undervoltage Lockout
PORTN
TheIEEEspecificationdictatesamaximumturn-onvoltage
of 42V and a minimum turn-off voltage of 30V for the PD.
Inaddition,thePDmustmaintainlargeon-offhysteresisto
prevent resistive losses in the wiring between the PSE and
the PD from causing start-up oscillation. The LTC4267-3
incorporates an undervoltage lockout (UVLO) circuit that
During classification (Figure 4), the PSE presents a fixed
voltage between –15.5V and –20.5V to the PD. With the
input voltage in this range, the LTC4267-3 asserts a load
current from the V
pin through the R
resistor.
PORTP
CLASS
The magnitude of the load current is set by the R
CLASS
monitors the line voltage at V
to determine when
resistor. Theresistorvaluesassociatedwitheachclassare
shown in Table 2. Note that the switching regulator will
not interfere with the classification measurement since
the LTC4267-3 has not passed power to the regulator.
PORTN
to apply power to the integrated switching regulator
(Figure 5). Before the power is applied to the switching
regulator, the P
pin is high impedance and sitting at
OUT
the ground potential since there is no charge on capacitor
C1. When the input voltage rises above the UVLO turn-on
threshold, the LTC4267-3 removes the detection and clas-
sification loads and turns on the internal power MOSFET.
C1 charges up under the LTC4267-3 current limit control
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4267-3 RCLASS Resistor Selection
Maximum
Power Levels
at Input of PD
(W)
Nominal
Classification
Load Current
(mA)
LTC4267-3
R
CLASS
Resistor
Class
Usage
Default
(Ω, 1%)
and the P
pin transitions from 0V to V
. This
OUT
PORTN
0
1
2
3
4
0.44 to 13.0
0.44 to 3.84
3.84 to 6.49
6.49 to 13.0
Reserved*
<5
10.5
18.5
28
Open
124
sequence is shown in Figure 1. The LTC4267-3 includes
a hysteretic UVLO circuit on V that keeps power
Optional
Optional
Optional
Reserved
PORTN
68.1
45.3
30.9
applied to the load until the input voltage falls below the
UVLO turn-off threshold. Once the input voltage drops
below –30V, the internal power MOSFET is turned off and
40
*Class 4 is currently reserved and should not be used.
42673fa
12
LTC4267-3
APPLICATIONS INFORMATION
the classification current is reenabled. C1 will discharge
limit because the load capacitor is charged with a current
below the IEEE inrush current limit specification.
through the PD circuitry and the P
impedance state.
pin will go to a high
OUT
As the LTC4267-3 switches from the low to high level
current limit, the current will increase momentarily. This
current spike is a result of the LTC4267-3 charging the
last 1.5V at the high level current limit. When charging a
10µF capacitor, the current spike is typically 100µs wide
and 125% of the nominal low level current limit.
+
C1
LTC4267-3
V
PORTP
5µF
MIN
TO
PSE
UNDERVOLTAGE
LOCKOUT
CIRCUIT
PGND
The LTC4267-3 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys-
tem designer with the flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
V
P
OUT
PORTN
42673 F05
CURRENT-LIMITED
TURN ON
INPUT
VOLTAGE
0V TO UVLO*
>UVLO*
LTC4267-3
POWER MOSFET
OFF
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD ≅ –36V
FALLING INPUT THRESHOLD ≅ –30.5V
During the current limited turn on, a large amount of
power is dissipated in the power MOSFET. The LTC4267-3
PD interface is designed to accept this thermal load and
is thermally protected to avoid damage to the onboard
power MOSFET. Note that in order to adhere to the IEEE
802.3af standard, it is necessary for the PD designer to
ensurethePDsteadystatepowerconsumptionfallswithin
the limits shown in Table 2. In addition, the steady state
Figure 5. LTC4267-3 VPORTN Undervoltage Lockout
Input Current Limit
IEEE 802.3af specifies a maximum inrush current and
also specifies a minimum load capacitor between the
V
and P
pins. To control turn-on surge current
PORTP
OUT
in the system, the LTC4267-3 integrates a dual level cur-
rent limit circuit with an onboard power MOSFET and
sense resistor to provide a complete inrush control circuit
without additional external components. At turn-on, the
LTC4267-3 will limit the input current to the low level,
allowing the load capacitor to ramp up to the line voltage
in a controlled manner.
current must be less than I
.
LIM_HI
Power Good
TheLTC4267-3PDInterfaceincludesapowergoodcircuit
(Figure 6) that is used to indicate that load capacitor C1
is fully charged and that the switching regulator can start
operation. The power good circuit monitors the voltage
across the internal UVLO power MOSFET and PWRGD is
asserted when the voltage falls below 1.5V. The power
good circuit includes hysteresis to allow the LTC4267-3 to
operate near the current limit point without inadvertently
disabling PWRGD. The MOSFET voltage must increase to
3V before PWRGD is disabled.
TheLTC4267-3hasbeenspecificallydesignedtointerface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. At turn-on
the LTC4267-3 current limit is set to the lower level. After
C1 is charged up and the P
– V
voltage difference
OUT
PORTN
isbelowthepowergoodthreshold,theLTC4267-3switches
to the high level current limit. The dual level current limit
allowslegacyPSEswithlimitedcurrentsourcingcapability
to power up the PD while also allowing the PD to draw full
power from an IEEE 802.3af PSE. The dual level current
limit also allows use of arbitrarily large load capacitors.
The IEEE 802.3af specification mandates that at turn-on
the PD not exceed the inrush current limit for more than
50ms. The LTC4267-3 is not restricted to the 50ms time
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
theLTC4267-3willdependonthemagnitudeofthevoltage
step, the rise time of the step, the value of capacitor C1
and the switching regulator load. For fast rising inputs,
42673fa
13
LTC4267-3
APPLICATIONS INFORMATION
R9
100k
LTC4267-3
PWRGD
Q1
R9
100k
I
TH
/RUN
FMMT2222
I
/RUN
TH
V
THERMAL SHUTDOWN
PORTP
PWRGD
LTC4267-3
TO
PSE
LTC3803
I
/RUN
TH
C17
UVLO
+
R18
5µF
100V
C1
C15
GND
–
+
C1
5µF
MIN
10k
+
TO
PSE
0.047µF
OPTIONAL
AUXILIARY
SWITCHING
REGULATOR
D6
MMBD4148
PGND
PGND
300k
V
P
OUT
–48V
PORTN
+
1.125V
PGND
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP
–
300k
V
P
OUT
PORTN
PGND
R
42673 F06
START
Q1
R9
100k
FMMT2222
Figure 6. LTC4267-3 Power Good
P
V
VCC
PORTP
PWRGD
LTC4267-3
TO
PSE
C
PVCC
+
R18
5µF
100V
C1
C15
10k
the LTC4267-3 will attempt to quickly charge capacitor C1
using an internal secondary current limit circuit. In this
scenario, the PSE current limit should provide the overall
limit for the circuit. For slower rising inputs, the 375mA
current limit in the LTC4267-3 will set the charge rate of
the capacitor C1. In either case, the PWRGD signal may
go inactive briefly while the capacitor is charged up to the
new line voltage. In the design of a PD, it is necessary
to determine if a step in the input voltage will cause the
PWRGD signal to go inactive and how to respond to this
event. In some designs, it may be desirable to filter the
PWRGD signal so that intermittent power bad conditions
are ignored. Figure 7 demonstrates a method to insert a
lowpass filter on the power good interface.
0.047µF
D6
MMBD4148
PGND
V
P
–48V
PORTN
OUT
PGND
PIN
ALTERNATE ACTIVE-HIGH ENABLE FOR P
C15 AND C17 OPTIONAL
SEE APPLICATIONS INFORMATION SECTION
VCC
42673 F07
Figure 7. Power Good Interface Examples
PD Interface Thermal Protection
The LTC4267-3 PD Interface includes thermal overload
protection in order to provide full device functionality
in a miniature package while maintaining safe operating
temperatures. Several factors create the possibility of
significant power dissipation within the LTC4267-3. At
turn-on, before the load capacitor has charged up, the
instantaneous power dissipated by the LTC4267-3 can be
as much as 10W. As the load capacitor charges up, the
power dissipation in the LTC4267-3 will decrease until it
reaches a steady-state value dependent on the DC load
current. Thesizeoftheloadcapacitordetermineshowfast
the power dissipation in the LTC4267-3 will subside. At
roomtemperature,theLTC4267-3cantypicallyhandleload
capacitors as large as 800µF without going into thermal
shutdown. With large load capacitors, the LTC4267-3 die
temperature will increase by as much as 50°C during a
single turn-on sequence. If for some reason power were
removed from the part and then quickly reapplied so that
the LTC4267-3 had to charge up the load capacitor again,
the temperature rise would be excessive if safety precau-
tions were not implemented.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the switching regulator with the PWRGD signal. If the
regulatorisnotdisabledduringthecurrent-limitedturn-on
sequence, the PD circuitry will rob current intended for
charging up the load capacitor and create a slow rising
input, possibly causing the LTC4267-3 to go into thermal
shutdown.
The PWRGD pin connects to an internal open drain, 100V
transistor capable of sinking 1mA. Low impedance to
V
indicates power is good. PWRGD is high imped-
PORTN
ance during signature and classification probing and in
the event of a thermal overload. During turn-off, PWRGD
is deactivated when the input voltage drops below 30V.
In addition, PWRGD may go active briefly at turn-on for
fast rising input waveforms. PWRGD is referenced to the
V
pin and when active, will be near the V
po-
The LTC4267-3 PD interface protects itself from thermal
damage by monitoring the die temperature. If the die
PORTN
PORTN
tential. Connect the PWRGD pin to the switching regulator
circuitry as shown in Figure 7.
42673fa
14
LTC4267-3
APPLICATIONS INFORMATION
temperature exceeds the overtemperature trip point, the
current is reduced to zero and very little power is dissi-
pated in the part until it cools below the overtemperature
set point. Once the LTC4267-3 has charged up the load
capacitor and the PD is powered and running, there will
be minor residual heating due to the DC load current of
the PD flowing through the internal MOSFET.
In the typical application circuit (Figure 11), the isolated
topology employs an external resistive voltage divider to
present a fraction of the output voltage to an external er-
ror amplifier. The error amplifier responds by pulling an
analog current through the input LED on an optoisolator.
The collector of the optoisolator output presents a corre-
sponding current into the I /RUN pin via a series diode.
TH
This method generates a feedback voltage on the I /RUN
TH
During classification, excessive heating of the LTC4267-3
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4267-3, thermal overload circuitry will
disableclassificationcurrentifthedietemperatureexceeds
the overtemperature trip point. When the die cools down
below the trip point, classification current is reenabled.
pin while maintaining isolation.
The voltage on the I /RUN pin controls the pulse-width
TH
modulator formed by the oscillator, current comparator,
and RS latch. Specifically, the voltage at the I /RUN pin
TH
sets the current comparator’s trip threshold. The current
comparator monitors the voltage across a sense resistor
inserieswiththesourceterminaloftheexternalN-Channel
MOSFET. The LTC4267-3 turns on the external power
MOSFET when the internal free-running 300kHz oscillator
sets the RS latch. It turns off the MOSFET when the cur-
rent comparator resets the latch or when 80% duty cycle
is reached, whichever happens first. In this way, the peak
current levels through the flyback transformer’s primary
The PD is designed to operate at a high ambient tem-
perature and with the maximum allowable supply (57V).
However, there is a limit to the size of the load capacitor
that can be charged up before the LTC4267-3 reaches the
overtemperaturetrippoint.Hittingtheovertemperaturetrip
point intermittently does not harm the LTC4267-3, but it
willdelaythecompletionofcapacitorcharging.Capacitors
up to 200µF can be charged without a problem over the
full operating temperature range.
and secondary are controlled by the I /RUN voltage.
TH
In applications where a nonisolated topology is desir-
able (Figure 11), an external resistive voltage divider can
present a fraction of the output voltage directly to the
Switching Regulator Main Control Loop
Due to space limitations, the basics of current mode
DC/DC conversion will not be discussed here. The reader
is referred to the detail treatment in Application Note 19
or in texts such as Abraham Pressman’s Switching Power
Supply Design.
V
pin of the LTC4267-3. The divider must be designed
FB
so when the output is at its desired voltage, the V pin
FB
voltage will equal the 800mV onboard internal reference.
The internal error amplifier responds by driving the I /
TH
RUN pin. The LTC4267-3 switching regulator performs in
In a Power over Ethernet System, the majority of applica-
tionsinvolveanisolatedpower supplydesign. Thismeans
that the output power supply does not have any DC elec-
trical path to the PD interface or the switching regulator
primary. The DC isolation is achieved typically through
a transformer in the forward path and an optoisolator in
the feedback path or a third winding in the transformer.
The typical application circuit shown on the front page
of the data sheet represents an isolated design using an
optoisolator. In applications where a nonisolated topology
is desired, the LTC4267-3 features a feedback port and
an internal error amplifier that can be enabled for this
specific application.
a similar manner as described previously.
Regulator Start-Up/Shutdown
The LTC4267-3 switching regulator has two shutdown
mechanisms to enable and disable operation: an un-
dervoltage lockout on the P
supply pin and a forced
VCC
shutdown whenever external circuitry drives the I /RUN
TH
pin low. The LTC4267-3 switcher transitions into and out
of shutdown according to the state diagram (Figure 8).
It is important not to confuse the undervoltage lockout
of the PD interface at V
with that of the switching
PORTN
regulator at P . They are independent functions.
VCC
42673fa
15
LTC4267-3
APPLICATIONS INFORMATION
Adjustable Slope Compensation
LTC4267-3
PWM
SHUTDOWN
The LTC4267-3 switching regulator injects a 5µA peak
current ramp out through its SENSE pin which can be
used for slope compensation in designs that require it.
This current ramp is approximately linear and begins at
zero current at 6% duty cycle, reaching peak current at
80% duty cycle. Programming the slope compensation
via a series resistor is discussed in the External Interface
and Component Selection section.
V
/RUN
ITHSHDN
ITH
V
> V
ITHSHDN
ITH/RUN
AND P
< V
P
VCC
< V
> V
TURNON
TURNOFF
VCC
(NOMINALLY 8.7V)
(NOMINALLY
0.28V)
LTC4267-3
PWM
ENABLED
ALL VOLTAGES WITH
RESPECT TO PGND
42673 F08
Figure 8. LTC4267-3 Switching Regulator
Start-Up/Shutdown State Diagram
EXTERNAL INTERFACE AND COMPONENT SELECTION
Input Interface Transformer
The undervoltage lockout mechanism on P
prevents
VCC
the LTC4267-3 switching regulator from trying to drive
the external N-Channel MOSFET with insufficient gate-to-
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 9). For
PoE devices, the isolation transformer must include a
center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Bel Fuse, Coil-
craft, PulseandTyco(Table3)canprovideassistancewith
selectionofanappropriateisolationtransformerandproper
termination methods. These vendors have transformers
specifically designed for use in PD applications.
source voltage. The voltage at the P
pin must exceed
VCC
V
(nominally 8.7V with respect to PGND) at least
TURNON
momentarily to enable operation. The P
voltage must
VCC
fall to V
(nominally 5.7V with respect to PGND)
TURNOFF
before the undervoltage lockout disables the switching
regulator. This wide UVLO hysteresis range supports
applications where a bias winding on the flyback trans-
former is used to increase the efficiency of the LTC4267-3
switching regulator.
TheI /RUNcanbedrivenbelowV
(nominally0.28V
TH
ITHSHDN
Table 3. Power over Ethernet Transformer Vendors
with respect to PGND) to force the LTC4267-3 switching
VENDOR
CONTACT INFORMATION
regulator into shutdown. An internal 0.3µA current source
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com
always tries to pull the I /RUN pin towards P . When
TH
VCC
the I /RUN pin voltage is allowed to exceed V
and
TH
ITHSHDN
P
exceedsV
,theLTC4267-3switchingregulator
TURNON
VCC
begins to operate and an internal clamp immediately pulls
the I /RUN pin to about 0.7V. In operation, the I /RUN
Coilcraft, Inc.
1102 Silver Lake Road
Cary, IL 60013
TH
TH
Tel: 847-639-6400
FAX: 847-639-1469
http://www.coilcraft.com
pinvoltagewillvaryfromroughly0.7Vto1.9Vtorepresent
current comparator thresholds from zero to maximum.
Pulse Engineering
Tyco Electronics
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
Internal Soft-Start
An internal soft-start feature is enabled whenever the
LTC4267-3 switching regulator comes out of shutdown.
Specifically, the I /RUN voltage is clamped and is
prevented from reaching maximum until 1.4ms have
passed. This allows the input current of the PD to rise in a
smooth and controlled manner on start-up and stay within
the current limit requirement of the LTC4267-3 interface.
FAX: 858-674-8262
http://www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com
TH
42673fa
16
LTC4267-3
APPLICATIONS INFORMATION
Diode Bridge
points to meet IEEE 802.3af compliance. D13 is added
to compensate for the change in UVLO turn-on voltage
caused by the Schottky diodes and consumes little power.
IEEE 802.3af allows power wiring in either of two configu-
rations: on the TX/RX wires or via the spare wire pairs in
the RJ45 connector. The PD is required to accept power in
eitherpolarityoneitherthemainorspareinputs;therefore
it is common to install diode bridges on both inputs in
ordertoaccommodatethedifferentwiringconfigurations.
Figure 9 demonstrates an implementation of these diode
bridges. The IEEE 802.3af specification also mandates
that the leakage back through the unused bridge be less
than 28µA when the PD is powered with 57V.
Input Capacitor
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1µF capacitor (C14 in Figure 9) is used to
meet the AC impedance requirement.
Input Series Resistance
LinearTechnologyhasseenthecustomercommunitycable
discharge requirements increase by nearly 500,000 times
the original test levels. The PD must survive and operate
reliably not only when an initially charged cable connects
and dissipates the energy through the PD front end, but
alsowhentheelectricalpowersystemgroundsaresubject
to very high energy events (e.g. lightning strikes).
The LTC4267-3 has several different modes of operation
based on the voltage present between V
and V
PORTN
PORTP
pins. The forward voltage drop of the input diodes in a
PD design subtracts from the input voltage and will af-
fect the transition point between modes. When using the
LTC4267-3, it is necessary to pay close attention to this
forwardvoltagedrop.Selectionofoversizeddiodeswillhelp
keepthePDthresholdsfromexceedingIEEEspecifications.
In these high energy events, adding 10Ω series resistance
into the V
pin greatly improves the robustness of the
PORTP
The input diode bridge of a PD can consume over 4% of
the available power in some applications. It may be de-
sirable to use Schottky diodes in order to reduce power
loss. However, if the standard diode bridge is replaced
with a Schottky bridge, the transition points between the
modes will be affected. Figure 10 shows a technique for
usingSchottkydiodeswhilemaintainingproperthreshold
LTC4267-3 based PD. (see Figure 9.) The TVS limits the
voltage across the port while the 10Ω and 0.1µF capaci-
tance reduces the edge rate the LTC4267-3 encounters
across its pin. The added 10Ω series resistance does not
operationally affect the LTC4267-3 PD Interface nor does
it affect its compliance with the IEEE 802.3 standard.
RJ45
+
1
TX
16 T1
15
1
2
BR1
HD01
–
TX
14
11
3
6
2
3
+
TO PHY
RX
10
9
7
8
–
RX
6
PULSE H2019
+
–
10Ω
SPARE
4
5
7
8
V
BR2
HD01
PORTP
D3
C14
0.1µF
100V
SMAJ58A
TVS
LTC4267-3
PORTN
SPARE
V
42673 F09
Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
42673fa
17
LTC4267-3
APPLICATIONS INFORMATION
D11
B1100
D9
B1100
R2
75Ω
R1
75Ω
C3
C7
10Ω
0.01µF
0.01µF
D10
B1100
D12
B1100
200V
200V
C11
0.1µF
100V
D6
SMAJ58A
C2
1000pF
2kV
OUT
J2
TO PHY
T1
+
–
16
1
2
3
TX
TX
+
TXOUT
1
15
14
D13
MMSD4148
–
TXOUT
2
3
6
C25
0.01µF
200V
C24
0.01µF
200V
+
–
RX
RX
11
10
9
6
7
8
+
RXOUT
IN
FROM
PSE
R31
75Ω
R30
75Ω
–
RXOUT
D14
B1100
4
+
SPARE
SPARE
5
7
8
D15
B1100
–
RJ45
R
V
VPORTP
CLASS
D17
B1100
D16
B1100
LTC4267-3
R
CLASS
NOTES: UNLESS OTHERWISE SPECIFIED
1. ALL RESISTORS ARE 5%
1%
2. SELECT R
FOR CLASS 1-4 OPERATION. REFER
PORTN
CLASS
TO DATA SHEET APPLICATIONS INFORMATION SECTION
C2: AVX 1808GC102MAT
42673 F10
D9 TO D12, D14 TO D17: DIODES INC., B1100
T1: PULSE H2019
Figure 10. PD Front End with Isolation Transformer, Two Schottky Diode Bridges
Transient Voltage Suppressor
Classification Resistor Selection (R
)
CLASS
TheLTC4267-3specifiesandabsolutemaximumvoltageof
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4267-3, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4267-3 as
showninFigure9.ASMAJ58Aisrecommendedfortypical
PDapplications. However, aSMBJ58Amaybepreferredin
applications where the PD front-end must absorb higher
energy discharge events.
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from R
to
CLASS
V
(Figure 4) sets the value of the load current. The
designer should determine which power category the PD
PORTN
falls into and then select the appropriate value of R
CLASS
from Table 2. If a unique load current is required, the value
of R
can be calculated as:
CLASS
R
CLASS
= 1.237V/(I
– I
)
IN_CLASS
DESIRED
42673fa
18
LTC4267-3
APPLICATIONS INFORMATION
where I
is the LTC4267-3 IC supply current dur-
disable interface is shown in Figure 16, option 2. Note that
the SIGDISA input resistance is relatively large and the
threshold voltage is fairly low. Because of high voltages
presentontheprintedcircuitboard, leakagecurrentsfrom
IN_CLASS
ing classification and is given in the electrical specifica-
tions. The R resistor must be 1% or better to avoid
CLASS
degrading theoverall accuracyoftheclassification circuit.
Resistor power dissipation will be 50mW maximum and
is transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
the V
pin could inadvertently pull SIGDISA high. To
PORTP
ensure trouble-free operation, use high voltage layout
techniques in the vicinity of SIGDISA. If unused, connect
capacitance at the R
node. The classification circuit
SIGDISA to V
.
CLASS
PORTN
can be disabled by floating the R
pin. The R
CLASS
CLASS
Load Capacitor
pin should not be shorted to V
as this would force
PORTN
the LTC4267-3 classification circuit to attempt to source
very large currents and quickly go into thermal shutdown.
The IEEE 802.3af specification requires that the PD main-
tain a minimum load capacitance of 5µF (provided by C1
in Figure 11). It is permissible to have a much larger load
capacitor and the LTC4267-3 can charge very large load
capacitors before thermal issues become a problem. The
load capacitor must be large enough to provide sufficient
energy for proper operation of the switching regulator.
However, the capacitor must not be too large or the PD
design may violate IEEE 802.3af requirements.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. The designer has the option of using this
signal to enable the onboard switching regulator through
the I /RUN or the P
pins. Examples of active-high
TH
VCC
interface circuits for controlling the switching regulator
are shown in Figure 7.
If the load capacitor is too large, there can be a problem
with inadvertent power shutdown by the PSE. Consider
the following scenario. If the PSE is running at –57V
(maximumallowed)andthePDhasdetectedandpowered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
–44V(minimumallowed),theinputbridgewillreversebias
and the PD power will be supplied by the load capacitor.
Depending on the size of the load capacitor and the DC
load of the PD, the PD will not draw any power for a period
of time. If this period of time exceeds the IEEE 802.3af
300ms disconnect delay, the PSE will remove power from
the PD. For this reason, it is necessary to ensure that
inadvertent shutdown cannot occur.
In some applications, it is desirable to ignore intermittent
power bad conditions. This can be accomplished by in-
cluding capacitor C15 in Figure 7 to form a lowpass filter.
With the components shown, power bad conditions less
than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the switching regulator using C
or C17
PVCC
as shown in Figure 7.
It is recommended that the designer use the power
good signal to enable the switching regulator. Using
PWRGD ensures the capacitor C1 has reached within
1.5V of the final value and is ready to accept a load. The
LTC4267-3 is designed with wide power good hysteresis
to handle sudden fluctuations in the load voltage and
current without prematurely shutting off the switching
regulator. Please refer to the Power-Up Sequencing of the
Application Information section.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily, caus-
ing the capacitor to charge at a somewhat reduced rate.
Conversely, charging a very large capacitor may cause the
current limit to increase slightly. In either case, once the
output voltage reaches its final value, the input current
limit will be restored to its nominal value.
Signature Disable Interface
Todisablethe25ksignatureresistor, connectSIGDISApin
to the V
pin. Alternately, SIGDISA pin can be driven
PORTP
high with respect to V
. An example of a signature
PORTN
42673fa
19
LTC4267-3
APPLICATIONS INFORMATION
The load capacitor can store significant energy when fully
charged. The design of a PD must ensure that this energy
is not inadvertently dissipated in the LTC4267-3. The
polarity-protection diode(s) prevent an accidental short
Choose resistance values for R1 and R2 to be as large as
possible to minimize any efficiency loss due to the static
current drawn from V , but just small enough so that
OUT
whenV
isinregulation,theerrorcausedbythenonzero
input current from the output of the resistor divider to the
OUT
on the cable from causing damage. However, if the V
PORTN
pin is shorted to V
inside the PD while the capacitor
error amplifier pin is less than 1%.
PORTP
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4267-3.
Error Amplifier and Optoisolator Considerations
In an isolated topology, the selection of the external error
amplifier depends on the output voltage of the switching
regulator. Typical error amplifiers include a voltage refer-
ence of either 1.25V or 2.5V. The output of the amplifier
and the amplifier upper supply rail are often tied together
internally. The supply rail is usually specified with a wide
upper voltage range, but it is not allowed to fall below the
reference voltage. This can be a problem in an isolated
switcher design if the amplifier supply voltage is not prop-
erly managed. When the switcher load current decreases
and the output voltage rises, the error amplifier responds
by pulling more current through the LED. The LED voltage
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the Maintain
Power Signature (MPS) to determine if a PD continues
to require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05µF. If either the DC current
is less than 10mA or the AC impedance is above 26.25k,
the PSE may disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2M
to guarantee power will be removed.
can be as large as 1.5V, and along with R , reduces the
LIM
Selecting Feedback Resistor Values
supply voltage to the error amplifier. If the error amp does
not have enough headroom, the voltage drop across the
The regulated output voltage of the switching regulator is
LED and R
may shut the amplifier off momentarily,
LIM
determined by the resistor divider across V
(R1 and
OUT
causing a lock-up condition in the main loop. The switcher
will undershoot and not recover until the error amplifier
releases its sink current. Care must be taken to select the
R2 in Figure 11) and the error amplifier reference voltage
. The ratio of R2 to R1 needed to produce the desired
V
REF
voltage can be calculated as:
referencevoltageandR valuesothattheerroramplifier
LIM
ꢀ R2ꢀ=ꢀR1ꢀ•ꢀ(V – V )/V
OUT
REF REF
always has enough headroom. An alternate solution that
avoids these problems is to utilize the LT1431 or LT4430
wheretheoutputoftheerroramplifierandamplifiersupply
rail are brought out to separate pins.
Inanisolatedpowersupplyapplication,V isdetermined
REF
by the designer’s choice of an external error amplifier.
Commercially available error amplifiers or programmable
shuntregulatorsmayincludeaninternalreferenceof1.25V
or 2.5V. Since the LTC4267-3 internal reference and error
The PD designer must also select an optoisolator such
that its bandwidth is sufficiently wider than the bandwidth
of the main control loop. If this step is overlooked, the
main control loop may be difficult to stabilize. The output
collector resistor of the optoisolator can be selected for
an increase in bandwidth at the cost of a reduction in gain
of this stage.
amplifier are not used in an isolated design, tie the V
pin to PGND.
FB
In a nonisolated power supply application, the LTC4267-3
onboardinternalreferenceanderroramplifiercanbeused.
TheresistordivideroutputcanbetieddirectlytotheV pin.
FB
The internal reference of the LTC4267-3 is 0.8V nominal.
42673fa
20
LTC4267-3
APPLICATIONS INFORMATION
Output Transformer Design Considerations
1.9V range. Layout is critical around the R
resistor.
SENSE
For example, a 0.020Ω sense resistor, with one milliohm
(0.001Ω) of parasitic resistance will cause a 5% reduction
in peak switch current. The resistance of printed circuit
copper traces cannot necessarily be ignored and good
layout techniques are mandatory.
Since the external feedback resistor divider sets the
output voltage, the PD designer has relative freedom in
selecting the transformer turns ratio. The PD designer
can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)
which yields more freedom in setting the total turns and
mutual inductance and may allow the use of an off the
shelf transformer.
Programmable Slope Compensation
The LTC4267-3 switching regulator injects a ramping
current through its SENSE pin into an external slope
Transformer leakage inductance on either the primary or
secondary causes a voltage spike to occur after the output
switch (Q1 in Figure 11) turns off. The input supply volt-
age plus the secondary-to-primary referred voltage of the
flyback pulse (including leakage spike) must not exceed
theallowedexternalMOSFETbreakdownrating.Thisspike
is increasingly prominent at higher load currents, where
more stored energy must be dissipated. In some cases,
a “snubber” circuit will be required to avoid overvolt-
age breakdown at the MOSFET’s drain node. Application
Note 19 is a good reference for snubber design.
compensation resistor (R in Figure 11). This current
SL
ramp starts at zero after the NGATE pin has been high for
the LTC4267-3’s minimum duty cycle of 6%. The current
rises linearly towards a peak of 5µA at the maximum duty
cycle of 80%, shutting off once the NGATE pin goes low.
A series resistor (R ) connecting the SENSE pin to the
SL
current sense resistor (R
) develops a ramping volt-
SENSE
age drop. From the perspective of the LTC4267-3 SENSE
pin, this ramping voltage adds to the voltage across the
senseresistor,effectivelyreducingthecurrentcomparator
threshold in proportion to duty cycle. This stabilizes the
control loop against subharmonic oscillation. The amount
ofreductioninthecurrentcomparatorthreshold(∆V
can be calculated using the following equation:
Current Sense Resistor Consideration
The external current sense resistor (R
in Figure 11)
SENSE
)
allows the designer to optimize the current limit behavior
for a particular application. As the current sense resistor
is varied from several ohms down to tens of milliohms,
peak swing current goes from a fraction of an ampere to
several amperes. Care must be taken to ensure proper
circuit operation, especially for small current sense resis-
tor values.
SENSE
ΔV ꢀ=ꢀ5µAꢀ•ꢀR ꢀ•ꢀ[(DutyꢀCycleꢀ–ꢀ6%)/74%]
SENSE SL
Note: The LTC4267-3 enforces 6% < Duty Cycle < 80%.
DesignsnotneedingslopecompensationmayreplaceR
with a short-circuit.
SL
Choose R
such that the switching current exercises
SENSE
Applications Employing a Third Transformer Winding
theentirerangeoftheI /RUNvoltage.Thenominalvoltage
TH
range is 0.7V to 1.9V and R
can be determined by
A standard operating topology may employ a third wind-
ing on the transformer’s primary side that provides power
SENSE
experiment. The main loop can be temporarily stabilized
byconnectingalargecapacitoronthepowersupply.Apply
the maximum load current allowable at the power sup-
to the LTC4267-3 switching regulator via its P
pin
VCC
(Figure 11). However, this arrangement is not inherently
self-starting.Start-upisusuallyimplementedbytheuseof
ply output based on the class of the PD. Choose R
SENSE
such that I /RUN approaches 1.9V. Finally, exercise the
an external “trickle-charge” resistor (R
) in conjunc-
TH
START
output load current over the entire operating range and
tionwiththeinternalwidehysteresisundervoltagelockout
circuit that monitors the P pin voltage.
ensure that I /RUN voltage remains within the 0.7V to
TH
VCC
42673fa
21
LTC4267-3
APPLICATIONS INFORMATION
ISOLATED DESIGN EXAMPLE
D1
T1
V
PORTP
V
OUT
+
–
–48V
FROM
DATA PAIR
•
C1
R
START
C
L
L
SEC
OUT
PRI
PGND
P
•
VCC
C
PVCC
P
VCC
PGND
NGATE
V
Q1
PORTP
0.1µF
100V
R
R
R
SL
LIM
CLASS
SENSE
LTC4267-3
R
CLASS
+
–
–48V
FROM
SPARE PAIR
R
SENSE
SIGDISA
PGND
PORTP
V
PORTN
V
V
V
FB
PORTN
I
/RUN
OUT
TH
OPTOISOLATOR
P
PGND
P
ERROR
AMPLIFIER
VCC
PGND
R
C
R2
R1
C
C
PGND
C
ISO
NONISOLATED DESIGN EXAMPLE
T1
L
BIAS
D2
•
•
D1
PGND
C1
V
+
–
OUT
–48V
FROM
R
V
R3
START
L
L
SEC
C
PRI
OUT
DATA PAIR
PGND
•
C
PVCC
PGND
P
PGND
VCC
0.1µF
100V
NGATE
Q1
PORTP
R
R
CLASS
SL
SENSE
LTC4267-3
R
CLASS
+
–
–48V
FROM
SPARE PAIR
R
SENSE
SIGDISA
R2
PGND
V
PORTN
V
FB
I
/RUN
TH
P
PGND
R1
OUT
C
C
42673 F11
PGND
Figure 11. Typical LTC4267-3 Application Circuits
42673fa
22
LTC4267-3
APPLICATIONS INFORMATION
R
is connected to V
and supplies a current,
. After some time, the
threshold.Also,thethirdwinding’snominaloutputvoltage
START
PORTP
typically 100µA, to charge C
should be at least 0.5V below the minimum rated P
PVCC
VCC
voltage on C
reaches the P
turn-on threshold. The
clamp voltage to avoid running up against the LTC4267-3
shunt regulator, needlessly wasting power.
PVCC
VCC
LTC4267-3 switching regulator then turns on abruptly and
draws its normal supply current. The NGATE pin begins
switching and the external MOSFET (Q1) begins to deliver
P
VCC
Shunt Regulator
power. The voltage on C
begins to decline as the
PVCC
In applications including a third transformer winding,
the internal P shunt regulator serves to protect the
switchingregulatordrawsitsnormalsupplycurrent,which
exceedsthedeliveryfromR .Aftersometime,typically
VCC
START
LTC4267-3switchingregulatorfromovervoltagetransients
as the third winding is powering up.
tens of milliseconds, the output voltage approaches the
desired value. By this time, the third transformer winding
is providing virtually all the supply current required by the
LTC4267-3 switching regulator.
If a third transformer winding is undesirable or unavail-
able, the shunt regulator allows the LTC4267-3 switching
regulatortobepoweredthroughasingledroppingresistor
One potential design pitfall is under-sizing the value of
from V
as shown in Figure 12. This simplicity comes
PORTP
capacitor C
. In this case, the normal supply current
PVCC
at the expense of reduced efficiency due to static power
dissipation in the R dropping resistor.
drawnthroughP willdischargeC
rapidlybeforethe
VCC
PVCC
START
third winding drive becomes effective. Depending on the
particular situation, this may result in either several off-on
cycles before proper operation is reached or permanent
The shunt regulator can sink up to 5mA through the P
VCC
must be
pin to PGND. The values of R
and C
START
PVCC
relaxation oscillation at the P
node.
selected for the application to withstand the worst-case
load conditions and drop on P , ensuring that the P
VCC
VCC
VCC
Resistor R
should be selected to yield a worst-case
START
turn-off threshold is not reached. C
should be sized
PVCC
minimumchargingcurrentgreaterthatthemaximumrated
LTC4267-3 start-up current to ensure there is enough cur-
sufficientlytohandletheswitchingcurrentneededtodrive
NGATE while maintaining minimum switching voltage.
renttochargeC
totheP turn-onthreshold. R
PVCC
VCC START
should also be selected large enough to yield a worst-case
maximum charging current less than the minimum-rated
+
P
P
supply current, so that in operation, most of the
current is delivered through the third winding. This
VCC
VCC
V
PORTP
R
START
–48
FROM
PSE
results in the highest possible efficiency.
P
VCC
CapacitorC shouldthenbemadelargeenoughtoavoid
LTC4267-3
PGND
C
PVCC
PVCC
the relaxation oscillation behavior described previously.
This is difficult to determine theoretically as it depends on
the particulars of the secondary circuit and load behavior.
Empirical testing is recommended.
P
OUT
–
V
PORTN
PGND
42673 F14
The third transformer winding should be designed so
that its output voltage, after accounting for the forward
Figure 12. Powering the LTC4267-3 Switching
Regulator via the Shunt Regulator
diode voltage drop, exceeds the maximum P
turn-off
VCC
42673fa
23
LTC4267-3
APPLICATIONS INFORMATION
External Preregulator
Compensating the Main Loop
The circuit in Figure 13 shows a third way to power the
LTC4267-3 switching regulator circuit. An external series
preregulator consists of a series pass transistor Q1, zener
Inanisolatedtopology,thecompensationpointistypically
chosenbythecomponentsconfiguredaroundtheexternal
error amplifier. Shown in Figure 14, a series RC network
is connected from the compare voltage of the error am-
plifier to the error amplifier output. In PD designs where
diode D1, and a bias resistor R . The preregulator holds
B
P
at7.6Vnominal, wellabovethemaximumratedP
VCC
VCC
momentarily
turn-on threshold,
turn-off threshold of 6.8V. Resistor R
transient load response is not critical, replace R with a
START
Z
charges the P
node up to the P
short.TheproductofR2andC shouldbesufficientlylarge
VCC
VCC
C
enabling the switching regulator. The voltage on C
to ensure stability. When fast settling transient response
PVCC
begins to decline as the switching regulator draws its
is critical, introduce a zero set by R C . The PD designer
Z C
normal supply current, which exceeds the delivery of
must ensure that the faster settling response of the output
R
. After some time, the output voltage approaches
voltage does not compromise loop stability.
START
the desired value. By this time, the pass transistor Q1
C
C
catchesthedecliningvoltageontheP pin,andprovides
R
VCC
Z
V
OUT
TO OPTO-
ISOLATOR
virtually all the supply current required by the LTC4267-3
R2
switching regulator. C
should be sized sufficiently to
PVCC
handle the switching current needed to drive NGATE while
maintaining minimum switching voltage.
R1
42673 F14
+
Figure 14. Main Loop Compensation for an Isolated Design
R
B
R
START
V
PORTP
Q1
D1
–48
FROM
PSE
8.2V
In a nonisolated design, the LTC4267-3 incorporates an
P
VCC
PGND
internal error amplifier where the I /RUN pin serves as
LTC4267-3
PGND
TH
C
a compensation point. In a similar manner, a series RC
PVCC
PGND
network can be connected from I /RUN to PGND as
TH
P
OUT
–
V
PORTN
shown in Figure 15. C and R are chosen for optimum
C
Z
42673 F15
load and line transient response.
PGND
Figure 13. Powering the LTC4267-3 Switching
Regulator with an External Preregulator
LTC4267-3
The external preregulator has improved efficiency over
the simple resistor-shunt regulator method mentioned
I
/RUN
PGND
Z
TH
previously. R can be selected so that it provides a small
B
C
C
R
current necessary to maintain the zener diode voltage and
themaximumpossiblebasecurrentQ1willencounter.The
actual current needed to power the LTC4267-3 switching
42673 F15
regulator goes through Q1 and P
sources current on
VCC
Figure 15. Main Loop Compensation for a Nonisolated Design
an “as-needed” basis. The static current is then limited
only to the current through R and D1.
B
42673fa
24
LTC4267-3
APPLICATIONS INFORMATION
Selecting the Switching Transistor
Figure 16 demonstrates three methods of diode ORing
external power into a PD. Option 1 inserts power before
the LTC4267-3 interface controller while options 2 and
3 bypass the LTC4267-3 interface controller section and
power the switching regulator directly.
With the N-channel power MOSFET driving the primary of
the transformer, the inductance will cause the drain of the
MOSFET to traverse twice the voltage across V
PGND. The LTC4267-3 operates with a maximum supply
of – 57V; thus the MOSFET must be rated to handle 114V
or more with sufficient design margin. Typical transis-
tors have 150V ratings while some manufacturers have
developed 120V rated MOSFETs specifically for Power-
over-Ethernet applications.
and
PORTP
If power is inserted before the LTC4267-3 interface con-
troller, it is necessary for the wall transformer to exceed
the LTC4267-3 UVLO turn-on requirement and include a
transient voltage suppressor (TVS) to limit the maximum
voltage to 57V. This option provides input current limit
for the transformer, provides a valid power good signal,
and simplifies power priority issues. As long as the wall
transformer applies power to the PD before the PSE, it
will take priority and the PSE will not power up the PD
because the wall power will corrupt the 25k signature. If
the PSE is already powering the PD, the wall transformer
power will be in parallel with the PSE. In this case, prior-
ity will be given to the higher supply voltage. If the wall
transformer voltage is higher, the PSE should remove the
line voltage since no current will be drawn from the PSE.
On the other hand, if the wall transformer voltage is lower,
the PSE will continue to supply power to the PD and the
walltransformerwillnotbeused. Properoperationshould
occur in either scenario.
The NGATE pin of the LTC4267-3 drives the gate of the
N-channel MOSFET. NGATE will traverse a rail-to-rail volt-
age from PGND to P . The designer must ensure the
VCC
MOSFET provides a low “ON” resistance when switched
to P
as well as ensure the gate of the MOSFET can
VCC
handle the P
supply voltage.
VCC
For high efficiency applications, select an N-channel
MOSFET with low total gate charge. The lower total gate
charge improves the efficiency of the NGATE drive circuit
and minimizes the switching current needed to charge
and discharge the gate.
Auxiliary Power Source
In some applications, it may be desirable to power the
PD from an auxiliary power source such as a wall trans-
former. The auxiliary power can be injected into the PD at
several locations and various trade-offs exist. Power can
be injected at the 3.3V or 5V output of the isolated power
supply with the use of a diode ORing circuit. This method
accesses the internal circuits of the PD after the isolation
barrier and therefore meets the 802.3af isolation safety
requirements for the wall transformer jack on the PD.
Power can also be injected into the PD interface portion of
the LTC4267-3. In this case, it is necessary to ensure the
user cannot access the terminals of the wall transformer
jack on the PD since this would compromise the 802.3af
isolation safety requirements.
If auxiliary power is applied directly to the LTC4267-3
switching regulator (bypassing the LTC4267-3 PD inter-
face), a different set of tradeoffs arise. In the configuration
shown in option 2, the wall transformer does not need
to exceed the LTC4267-3 turn-on UVLO requirement;
however, it is necessary to include diode D9 to prevent
the transformer from applying power to the LTC4267-3
interface controller. The transformer voltage requirement
will be governed by the needs of the onboard switching
regulator. However, power priority issues require more
intervention. If the wall transformer voltage is below
the PSE voltage, then priority will be given to the PSE
power.TheLTC4267-3interfacecontrollerwilldrawpower
42673fa
25
LTC4267-3
APPLICATIONS INFORMATION
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267-3 PD
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1µF
100V
TX
R
START
2
3
+
–
BR1
HD01
TO PHY
RX
C1
RX
6
V
PORTP
+
–
P
SPARE
VCC
4
5
7
8
~
~
+
–
LTC4267-3
PGND
BR2
HD01
C
PVCC
SPARE
V
P
PORTN OUT
PGND
+
D8
S1B
ISOLATED
WALL
TRANSFORMER
38V TO 57V
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267-3 PD WITH SIGNATURE DISABLED
RJ45
1
+
T1
TX
TX
D3
SMAJ58A
~
~
+
–
–
TVS
100k
C14
0.1µF
100V
R
START
2
3
+
BR1
HD01
TO PHY
RX
–
C1
BSS63
RX
6
V
PORTP
100k
+
–
SIGDISA
SPARE
4
5
7
8
~
~
+
–
P
VCC
LTC4267-3
PGND
BR2
HD01
C
PVCC
SPARE
V
P
PORTN OUT
PGND
D9
+
–
S1B
ISOLATED
WALL
TRANSFORMER
D10
S1B
OPTION 3: AUXILIARY POWER APPLIED TO LTC4267-3 PD AND SWITCHING REGULATOR
RJ45
1
+
T1
TX
TX
D3
SMAJ58A
~
~
+
–
–
TVS
C14
0.1µF
100V
R
START
2
3
+
BR1
HD01
TO PHY
RX
–
C1
RX
6
V
PORTP
P
+
–
VCC
SPARE
4
5
7
8
~
~
+
–
LTC4267-3
BR2
HD01
C
PVCC
PGND
SPARE
V
P
PORTN OUT
PGND
+
D10
S1B
ISOLATED
WALL
TRANSFORMER
38V TO 57V
42673 F16
–
Figure 16. Auxiliary Power Source for PD
42673fa
26
LTC4267-3
APPLICATIONS INFORMATION
from the PSE while the transformer will sit unused. This
configuration is not a problem in a PoE system. On the
other hand, if the wall transformer voltage is higher than
the PSE voltage, the LTC4267-3 switching regulator will
draw power from the transformer. In this situation, it is
necessary to address the issue of power cycling that may
occur if a PSE is present. The PSE will detect the PD and
apply power. If the switcher is being powered by the wall
transformer, then the PD will not meet the minimum load
requirementandthePSEwillsubsequentlyremovepower.
The PSE will again detect the PD and power cycling will
start. With a transformer voltage above the PSE voltage,
it is necessary to either disable the signature, as shown
in option 2, or install a minimum load on the output of the
LTC4267-3 interface to prevent power cycling.
The LTC4267-3 includes a power good signal in the PD
interfacethatcanbeusedtoindicatetotheswitchingregu-
lator that the load capacitor is fully charged and ready to
handle the switcher load. Figure 7 shows two examples of
waysthePWRGDsignalcanbeusedtocontroltheswitch-
ing regulator. The first example employs an N-channel
MOSFET to drive the I /RUN port below the shutdown
TH
threshold (typically 0.28V). The second example drives
P
VCC
below the P
turn-off threshold. Employing the
VCC
second example has the added advantage of adding delay
to the switching regulator start-up beyond the time the
power good signal becomes active. The second example
ensures additional timing margin at start-up without the
needforaddeddelaycomponents. Inapplicationswhereit
is not desirable to utilize the power good signal, sufficient
timing margin can be achieved with R
and C
.
The third option also applies power directly to the
LTC4267-3 switching regulator, bypassing the LTC4267-3
interface controller and omitting diode D9. With the
diode omitted, the transformer voltage is applied to the
LTC4267-3interfacecontrollerinadditiontotheswitching
regulator. For this reason, it is necessary to ensure that the
transformer maintain the voltage between 38V and 57V
to keep the LTC4267-3 interface controller in its normal
operating range. The third option has the advantage of
automatically disabling the 25k signature resistor when
the external voltage exceeds the PSE voltage.
START
PVCC
R
START
and C
should be set to a delay of two to three
times longer than the duration needed to charge up C1.
PVCC
Layout Considerations for the LTC4267-3
The most critical layout considerations for the LTC4267-3
are the placement of the supporting external components
associatedwiththeswitching regulator.Efficiency,stability,
and load transient response can deteriorate without good
layout practices around critical components.
For the LTC4267-3 switching regulator, the current loop
through C1, T1 primary, Q1, and R
must be given
Power-Up Sequencing the LTC4267-3
SENSE
careful layout attention. (Refer to Figure 11.) Because of
the high switching current circulating in this loop, these
components should be placed in close proximity to each
other. In addition, wide copper traces or copper planes
should be used between these components. If vias are
necessarytocompletetheconnectivityofthisloop,placing
multiple vias lined perpendicular to the flow of current is
essential for minimizing parasitic resistance and reducing
current density. Since the switching frequency and the
power levels are substantial, shielding and high frequency
layout techniques should be employed. A low current,
The LTC4267-3 consists of two functional cells, the PD
interface and the switching regulator, and the power up
sequencingofthesetwocellsmustbecarefullyconsidered.
ThePDdesignershouldensurethattheswitchingregulator
doesnotbeginoperationuntiltheinterfacehas completed
charging up the load capacitor. This will ensure that the
switcher load current does not compete with the load
capacitor charging current provided by the PD interface
current limit circuit. Overlooking this consideration may
resultinslowpowersupplyrampup,power-uposcillation,
and possibly thermal shutdown.
42673fa
27
LTC4267-3
APPLICATIONS INFORMATION
low impedance alternate connection should be employed
between the PGND pins of the LTC4267-3 and the PGND
In essence, a tight overall layout of the high current loop
and careful attention to current density will ensure suc-
cessful operation of the LTC4267-3 in a PD.
side of R
, away from the high current loop. This
SENSE
Kelvin sensing will ensure an accurate representation of
Place C14 (Figure 9) as close as physically possible to the
LTC4267-3. Place the series 10Ω resistor close to C14.
the sense voltage is measured by the LTC4267-3.
The placement of the feedback resistors R1 and R2 as
Excessive parasitic capacitance on the R
pin should
CLASS
well as the compensation capacitor C is very important
be avoided. The SIGDISA pin is adjacent to the V
C
PORTP
in the accuracy of the output voltage, the stability of the
pin and any coupling, whether resistive or capacitive may
inadvertently disable the signature resistance. To ensure
consistentbehavior,theSIGDISApinshouldbeelectrically
connected and not left floating. Voltages in a PD can be as
large as –57V, so high voltage layout techniques should
be employed.
main control loop, and the load transient response. In
an isolated design application, R1, R2, and C should be
C
placed as close as possible to the error amplifier’s input
withminimumtracelengthsandminimumcapacitance. In
a nonisolated application, R1, and R2 should be placed as
close as possible to the V pin of the LTC4267-3 and C
FB
C
shouldbeplacedclosetotheI /RUNpinoftheLTC4267-3.
TH
42673fa
28
LTC4267-3
TYPICAL APPLICATIONS
Class 3 PD with 5V Nonisolated Power Supply
COILTRONICS
CTX-02-15242
4.7µH
5V
1.8A
12µF
100V
2.2µF
100V
220k
UPS840
300µF*
100k
MMBTA42
BAS516
•
10Ω
9.1V
+
V
•
P
PORTP
VCC
–48V
FROM
HD01
1µF
LTC4267-3
DATA PAIR
–
0.1µF
NGATE
PWRGD
SENSE
150pF
200V
FDC2512
10k
SMAJ58A
220Ω
R
CLASS
+
–48V
FROM
SPARE PAIR
45.3Ω
1%
0.04Ω
1%
42.2k
1%
HD01
V
FB
–
SIGDISA
I
TH
/RUN
22nF
27k
42673 TA02
V
PORTN
P
PGND
OUT
8.06k
1%
* THREE 100µF CERAMICS
42673fa
29
LTC4267-3
TYPICAL APPLICATIONS
42673fa
30
LTC4267-3
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706 Rev Ø)
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
2.20 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 ±0.10
5.00 ±0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 ±0.10
(2 SIDES)
1.65 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 ±0.05
0.75 ±0.05
0.200 REF
0.50 BSC
4.40 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
42673fa
31
LTC4267-3
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
.045 .005
(4.801 – 4.978)
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
42673fa
32
LTC4267-3
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
10/12 Changed 12.95W IEEE 802.3af reference to 13.0W
Updated maximum power levels for class 0 and class 3 to 13.0W
9
12
Added 10Ω resistor to V
pin in Figure 9 and Figure 10. Added Input Capacitor section, Input Series Resistance
PORTP
section and Transient Voltage Suppressor section
17, 18
28
Added C14 and 10Ω resistor layout recommendation
Added 10Ω resistor to V
pin
29, 30, 34
PORTP
42673fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC4267-3
TYPICAL APPLICATIONS
High-Efficiency Class 3 PD with 3.3V Isolated Power Supply
470pF
10Ω
PULSE
SBM1040
570µF*
4.7µH
PA1136
3.3V
2.6A
•
12µF
100V
2.2µF
100V
220k
9.1V
220k
330Ω
CHASSIS
•
510Ω
MMTBA42
BAS516
150pF
BAS516
P
VCC
MMSD4148
0.1µF
–48V
FROM
10Ω
•
V
R
P
PORTP
VCC
DATA PAIR
4.7µF
LTC4267-3
B1100
(8 PLACES)
Si3440
NGATE
SENSE
/RUN
10k
SMAJ58A
P
VCC
0.068Ω
1%
500Ω
I
TH
–48V
FROM
SPARE PAIR
CLASS
6.8k
P
VCC
100k
1%
45.3Ω
1%
33nF
100k
10k
BAS516
2N7002
SIGDISA
PWRGD
PS2911
V
V
FB
PORTN
MMSD4148
*100µF CERAMIC + 470µF TANTALUM
60.4k
1%
P
PGND
OUT
TLV431
2200pF
42673 TA04
“Y” CAP
250VAC
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Programming Resistor, Full Compliance to 802.3at
LTC4267-1
LTC4269-1
LTC4269-2
LTC4278
IEEE 802.3af PD Interface with Integrated
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Controller, 50kHz to 250kHz, 12V Auxiliary Support
++
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LTC4275C
LTPoE ™ PD Controller
Provides Up to 90W, External MOSFET for Lowest Power Dissipation and Highest
System Efficiency, 2-Event Classification, Programmable Classification
IEEE 802.3at PD Controller
IEEE 802.3at PD Controller
External MOSFET for Lowest Power Dissipation and Highest System Efficiency,
2-Event Classification, Programmable Classification
External MOSFET for Lowest Power Dissipation and Highest System Efficiency,
Programmable Classification
LTC4274
LTC4266
Single PoE PSE Controller
Quad PoE PSE Controller
Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring
Provides Up to 90W, 2-Event Classification, and Port Current and Voltage Monitoring
42673fa
LT 1012 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
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LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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