LTC4281CUFD#TRPBF_技术文档

LTC4281

Hot Swap Controller with I²C

Compatible Monitoring

FeaTures

DescripTion

The LTC^®4281 Hot Swap controller allows a board to be

safely inserted and removed from a live backplane. Using

anexternalN-channelpasstransistor,boardsupplyvoltage

and inrush current are ramped up at an adjustable rate.

n

Allows Safe Board Insertion Into Live Backplane

n

12-/16-Bit ADC with ±±0.7 ꢀotal Unadjusted Error

n

Monitors Current, Voltage, Power and Energy

n

Internal EEPROM for Nonvolatile Conﬁguration

2

n

Wide Operating Voltage Range: 209V to 33V

An I C interface and onboard ADC allows for monitoring

2

n

I C/SMBus Digital Interface (Coexists with PMBus

of board current, voltage, power, energy and fault status.

Devices)

The device features analog foldback current limiting to

limit the MOSFET power to a constant value. A wide input

voltage operating range comfortably allows applications

from 2.9V to 33V.

n

12V Gate Drive for Lower MOSFET R

DS(ON)

n

Programmable Current Limit with 2% Accuracy

MOSFET Power Limiting with Current Foldback

Continuously Monitors MOSFET Health

The LTC4281 is well suited to high power applications

because the precise monitoring capability and accurate

current limiting reduce the extremes in which both loads

and power supplies must safely operate. Non-volatile

configuration allows for flexibility in the autonomous

generation of alerts and response to faults.

Stores Minimum and Maximum Measurements

Alerts When Alarm Thresholds Exceeded

2

Reboots on I C Command

Input Overvoltage/Undervoltage Protection

Three General Purpose Input/Outputs

Internal ±±% or External Timebases

28-Pin 4mm × ±mm QFN Package

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

applicaTions

n

Enterprise Servers and Data Storage Systems

n

Network Routers and Switches

n

Base Stations

Platform Management

n

Typical applicaTion

12V, 65A Plug-In Board Resident Application

Start-Up Waveforms

V

12V

65A

0.5mΩ

OUT

12V

+

CONTACT BOUNCE

V

DD

10V/DIV

10Ω

SENSE ADC GATE SOURCE

SMCJ15CA

+

–

V

ADC SENSE

DD

∆V

GATE

10V/DIV

NC

UV

OV

FB

50ms DE-BOUNCE

SDAI

SDAO

SCL

POWER

GOOD

GPIO1

SDA

SCL

V

SOURCE

LTC4281

10V/DIV

ALERT

ADR0

ADR1

ADR2

ON

GPIO2

GPIO3

GP

GPIO1(PG)

10V/DIV

NC

4281 TA01b

20ms/DIV

12V

INTV

TIMER

WP CLKIN CLKOUT GND

CC

4.7µF

4281 TA01a

100k

NC

10nF

GND

BACKPLANE PLUG-IN

BOARD

4281f

1

For more information www.linear.com/LTC4281

LTC4281

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

Supply Voltage V .................................... –0.3V to 4±V

DD

Input Voltages

GATE – SOURCE (Note 3) ...................... –0.3V to 10V

28 27 26 25 24 23

+

–

SENSE , ADC , SENSE ...... V – 4.±V to V + 0.3V

ON

OV

1

2

3

4

5

6

7

8

22

21

20

19

18

17

16

15

GATE

SOURCE

FB

DD

–

ADC ........................................... –0.3V to V + 0.3V

DD

GND

WP

SOURCE................................................. –0.3V to 4±V

GND

ADR0-2, TIMER .....................–0.3V to INTV + 0.3V

29

CC

INTV

GPIO1

GPIO2

GPIO3

ALERT

CC

CLKIN. .................................................. –0.3V to ±.±V

TIMER

UV, OV, FB, WP, ON, GPIO1-3,

CLKOUT

CLKIN

SCL, SDAI............................................. .–0.3V to 4±V

Output Voltages

9

10 11 12 13 14

UFD PACKAGE

GATE, GPIO1-3, ALERT, SDAO................ –0.3V to 4±V

CLKOUT ...................................–0.3 to INTV + 0.3V

CC

28-LEAD (4mm × 5mm) PLASTIC QFN

Output Current INTV (V > 4V) ........................2±mA

CC DD

T

= 12±°C, θ = 43°C/W

JMAX

JA

Operating Ambient Temperature Range

EXPOSED PAD (PIN 29) PCB CONNECTION OPTIONAL

LTC4281C ................................................ 0°C to 70°C

LTC4281I..............................................–40°C to 8±°C

Storage Temperature Range .................. –6±°C to 12±°C

orDer inForMaTion

LEAD FREE FINISH

LTC4281CUFD#PBF

LTC4281IUFD#PBF

ꢀAPE AND REEL

PARꢀ MARKING*

4281

PACKAGE DESCRIPꢀION

ꢀEMPERAꢀURE RANGE

LTC4281CUFD#TRPBF

LTC4281IUFD#TRPBF

28-Lead (4mm × ±mm) Plastic QFN

0°C to 70°C

4281

–40°C to 8±°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in ±00 unit reels through

designated sales channels with #TRMPBF suffix.

4281f

2

For more information www.linear.com/LTC4281

LTC4281

elecTrical characTerisTics ^ꢀhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢀ_A= 25°C0 V_DD= 12V unless otherwise noted0

SYMBOL

Supplies

PARAMEꢀER

CONDIꢀIONS

MIN

ꢀYP

MAX

UNIꢀS

l

V

Input Supply Range

2.9

33

8

V

mA

V

DD

I

Input Supply Current

3.±

2.7

40

DD

V

Input Supply Undervoltage Lockout

Input Supply Undervoltage Lockout Hysteresis

Internal Regulator Voltage

V

Rising

2.6±

1±

2.7±

7±

DD(UVL)

DD

mV

V

DD(HYST)

INTV

3.1

2.4±

±0

3.3

2.6

110

3.±

2.7

17±

CC

INTV Undervoltage Lockout

INTV Rising

V

CC(UVL)

CC(HYST)

CC

INTV Undervoltage Lockout Hysteresis

mV

CC

Current Limit

∆V

l

Current Limit Voltage DAC Zero-Scale

Current Limit Voltage DAC Full-Scale

V

= 1.3V, I = 000

12.2±

3.4

12.±

3.7±

12.7±

4.1

mV

SENSE

FB

LIM

= 0V, I = 000

LIM

l

V

= 1.3V, I = 111

32.88

8.81

34.37

10.31

3±.87

11.81

mV

FB

LIM

= 0V, I = 111

LIM

l

Current Limit Voltage DAC INL

–0.0±

0

0.0±

±1±

±1

LSB

mV

µA

Fast Current Limit Comparator Offset

–

I

–

+

SENSE Pin Input Current

V

SENSE

V

SENSE

= 12V

0

SENSE

+

SENSE Pin Input Current

0

90

130

µA

SENSE

Gate Drive

∆V

l

Gate Drive (V

– V

) (Note 3)

SOURCE

V

= 2.9V to 33V, I = –1µA

GATE

10

–1±

0.±

0.3

12.±

–20

1.3

0.9

0.±

8

13.±

–30

3

V

µA

mA

A

GATE

DD

I

Gate Pull-Up Current

Gate On, V

Gate Off, V

= 0V

GATE

Gate Pull-Down Current

Gate Fast Pull-Down Current

Overcurrent to GATE Low

= 10V

∆V

=100mV, ∆V

= 10V

3

SENSE

GATE

t

=0mV Step to 100mV, C = 10nF

1

µs

V

PHL(FAST)

V

∆V

GATE

FET Off Threshold

±

10

GATE

Comparator Inputs

l

I

UV, OV, FB, ON WP Input Current

, SOURCE Rising Threshold Voltages for

V = 1.2V

0

±1

µA

IN

l

V

±%

10%

1±%

–±

–7.±

–12.±

–17.±

–10

–1±

–20

%

TH-R

TH-F

TH-R

TH-F

DD

UV, Power Good (Note 6)

–10

–1±

l

V

, SOURCE Falling Threshold Voltages for

±%

10%

1±%

–10

–1±

–20

–12.±

–17.±

–22.±

–1±

–20

–2±

%

DD

UV, Power Good (Note 6)

l

V

Rising Threshold Voltages of OV (Note 6) ±%

10

1±

20

12.±

17.±

22.±

1±

20

2±

%

DD

10%

1±%

l

Falling Threshold Voltages of OV (Note 6) ±%

±

10

1±

7.±

12.±

17.±

10

1±

20

%

10%

1±%

l

V

UV, OV, FB, ON Rising Threshold

UV, OV, FB, ON Hysteresis

1.26

23

1.28

43

1.3

63

V

mV

V

TH

HYST

TH

FET-Bad FAULT V Threshold

1±0

1.26

2

200

1.28

20

270

1.3

3±

DS

WP Pin Threshold Voltage

WP Pin Hysteresis

Falling

TH

mV

µs

HYST

PHL

t

Turn-Off Propagation Delay

ON, UV, OV Turn-Off

10

2±

4±

4281f

3

For more information www.linear.com/LTC4281

LTC4281

elecTrical characTerisTics ^ꢀhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢀ_A= 25°C0 V_DD= 12V unless otherwise noted0

SYMBOL

PARAMEꢀER

CONDIꢀIONS

MIN

10

ꢀYP

2±

MAX

4±

UNIꢀS

µs

l

t

Fast Turn On Propagation Delay

Debounced Turn On Propagation Delay

ON Pin Turn On

UV, OV Turn On

PHL

D

4±

±0

±±

ms

Crystal Oscillator

l

V

CLKIN Pin Rising Threshold

Maximum CLKIN Pin Input Frequency

CLKIN Pin Input Current

0.4

1

2

V

MHz

µA

TH

f

I

2±

MAX

V = 0V to 3.3V

–10

10

CLKIN

CLKOUT

CLKOUT Pin Output Current

–1±0

1±0

µA

GPIO Pin Functions

l

V

GPIO, ALERT Threshold

Falling

1.26

2

1.28

20

1.31

3±

V

mV

V

TH

GPIO, ALERT Hysteresis

HYST

OL

GPIO, ALERT Output Low Voltage

GPIO, ALERT Leakage Current

I = 3mA

V = 33V

0.3

0

0.4

±1

I

t

µA

µs

OH

PHL

Stress Condition to GPIO2 Low Propagation

Delay

GATE Low or V = 1V

±

13

3±

DS

ꢀIMER Pin Functions

l

V

TIMER Low Threshold

Falling

Rising

0.11

1.2±

–18

3

0.1±

1.28

–20

±

0.19

1.31

–22

7

V

TH

TIMER High Threshold

I

TIMER Pull-Up Current

V = 0V

V = 1.3V

µA

%

TIMER

TIMER Pull-Down Current

Overcurrent Auto-Retry Duty Cycle

Doc

0.04±

0.08

0.11

SOURCE, ADC Pin Currents

l

I

SOURCE Input Current

V = 12V

70

180

0

3±0

±1

µA

SOURCE

–

ADC

+

ADC

ADC Input Current

V

– = 33V

+ = 33V

ADC

+

ADC Input Current

2±

110

ADC

l

RESOLUTION

ADC Resolution (No Missing Codes)

ADC Offset Error, Percent of Full-Scale

ADC Total Unadjusted Error (Note ±)

12/16

Bits

%

V

±0.2±

OS

l

TUE

∆V , SOURCE, V , GPIO

±0.7

±1.0

±±.1

±1.0

%

ADC

DD

POWER

ENERGY (Internal Timebase)

ENERGY (Crystal/External Timebase)

l

FSE

ADC Full-Scale Error

ADC Full-Scale Range

∆V , SOURCE, V , GPIO

±0.7

±1.0

±±.1

±1.0

%

ADC

POWER

DD

ENERGY (Internal Timebase)

ENERGY (Crystal/External Timebase)

+

–

V

∆V

= ADC – ADC

40

mV

V

FS

ADC

SOURCE/V = 24V Range

33.28

16.64

8.32

DD

SOURCE/V = 12V Range

V

DD

SOURCE/V = ±V Range

V

DD

SOURCE/V = 3.3V Range

±.±47

1.28

V

DD

GPIO

V

l

INL

ADC Integral Nonlinearity, 12-Bit Mode

0.2

±±

LSB

4281f

4

For more information www.linear.com/LTC4281

LTC4281

elecTrical characTerisTics ^ꢀhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢀ_A= 25°C0 V_DD= 12V unless otherwise noted0

SYMBOL

PARAMEꢀER

CONDIꢀIONS

∆V

MIN

ꢀYP

MAX

UNIꢀS

V

FS

Alarm Threshold Full-Scale Range

40

mV

V

ADC

(256 • V

)

SOURCE/V = 24V

33.28

16.64

8.32

LSB

DD

SOURCE/V = 12V

V

DD

SOURCE/V = ±V

V

DD

SOURCE/V = 3.3V

±.±47

1.28

V

DD

GPIO

V

l

R

GPIO ADC Sampling Resistance

Conversion Rate

V = 1.28V

1

2

MΩ

GPIO

l

f

12-Bit Mode, Internal Clock

16-Bit Mode, Internal Clock

14.±

0.906

1±.26

0.9±4

16

1

Hz

CONV

2

I C Interface

l

V

ADRn Input High Threshold

INTV

CC

– 0.2

V

ADR(H)

CC

– 0.8

– 0.±

l

I

ADRn Allowable Leakage in Open State

ADRn Input Low Threshold

ADRn Input Current

±3

µA

V

ADR(IN,Z)

V

0.2

0.±

0.8

±80

2.0

±1

ADR(L)

I

ADR = 0V, ADR = INTV

µA

V

ADR(IN)

CC

V

SDAI, SCL Input Threshold

SDAI, SCL Input Current

1.±

1.7

SDA,SCL(TH)

I

SCL, SDA = ±.0V

I = 3mA

µA

V

SDA,SCL(OH)

V

SDAO, Output Low Voltage

SDAO, Pin Input Leakage Current

0.3

0

0.4

±1

SDAO(OL)

I

V

SDAO

= 33V

µA

SDAO(OH)

2

I C Interface ꢀiming

l

f

t

Maximum SCL Clock Frequency

Bus Free Time Between STOP/START Condition

Hold Time After (Repeated) START Condition

Repeated START Condition Set-Up Time

STOP Condition Set-Up Time

400

1000

0.12

30

kHz

µs

us

ns

pF

ms

SCL(MAX)

1.3

600

100

900

600

2±0

10

BUF(MIN)

HD,STA(MIN)

SU,STA(MIN)

SU,STO(MIN)

HD,DATI(MIN)

HD,DATO

30

140

30

Data Hold Time (Input)

Data Hold Time (Output)

300

±0

±00

30

Data Set-Up Time

SU,DAT(MIN)

SP(MAX)

Maximum Suppressed Spike Pulse Width

110

C

SCL, SDA Input Capacitance

(Note 4)

X

2

t

I C Stuck Bus Timeout

2±

30

3±

D(STUCK)

EEPROM Characteristics

Endurance

l

(Notes 7, 8)

10,000

Cycles

Years

ms

Retention

20

1

t

Write Operation Time

2.2

4

WRITE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive. All voltages are referenced to

GND unless otherwise specified.

Note 3: An internal clamp limits the GATE pin to a minimum of 11V above

SOURCE. Driving this pin to voltages beyond the clamp may damage the

device.

Note 4: Guaranteed by design and not subject to test.

Note 5: TUE is the maximum ADC error for any code, given as a

percentage of full scale.

Note 6: UV, OV and FB internal thresholds are given as a percent

difference from the configured operating voltage.

Note .: EEPROM endurance and retention are guaranteed by design,

characterization and correlation with statistical process controls.

Note 8: EEPROM endurance and retention will be degraded when T > 8±°C.

J

4281f

5

For more information www.linear.com/LTC4281

LTC4281

Typical perForMance characTerisTics ^T_A^{= 25°C, V}_DD= 12V unless otherwise noted.

3.3V Output Supply vs Load

Current for V_DD= 12V

Supply Current vs Voltage

3.3V Output Supply vs Voltage

4.50

4.25

4.00

3.75

3.50

3.25

3.00

3.5

3.4

3.3

3.2

3.1

3.0

3.50

3.25

3.00

2.75

2.50

0

5

10

15

20

(V)

25

30

35

0

4

8

12

16

20

2.50

3

3.50

V

4

4.50

5

V

I

(mA)

LOAD

(V)

DD

4281 G01

4281 G03

4281 G02

Current Limit Threshold

vs Temperature

Current Limit Foldback Profile

MOSFET Power Limit

30

25

20

15

10

5

30

25

20

15

10

5

27

26

25

24

23

22

V

= 12V

DD

R

SENSE

= 1mΩ

0

2

4

6

8

10

12

0

2

4

6

8

10

12

–50

–25

0

25

50

75

100

V

(V)

V

(V)

TEMPERATURE (°C)

OUT

4281 G05

4281 G04

4281 G06

External MOSFET Gate Drive

vs Temperature

Current Limit Propagation Delay

vs Overdrive

External MOSFET Gate Drive

vs Leakage Current

1k

100

10

13.2

13.0

12.8

12.6

12.4

12.2

12.0

14

12

10

8

FAST PULL–DOWN

6

4

1

V

= 12V

= 5V

= 3.3V

V

= 12V

= 5V

= 3.3V

DD

2

V

= 25mV

ILIM

0.1

0

20

40

60

(mV)

80

100

–50

–25

0

25

50

75

100

0

4

8

12

16

20

24

V

- V

ILIM

TEMPERATURE (°C)

I

GATE

(LEAKAGE) (µA)

SENSE

4281 G07

4281 G08

4281 G09

4281f

6

For more information www.linear.com/LTC4281

LTC4281

Typical perForMance characTerisTics

External MOSFET Gate Drive

Current vs Temperature

GPIO Pin Output Low Voltage

vs Load (V_OL(GPIO)vs I_GPIO

ADC Total Unadjusted Error

vs Code (TUE vs Code)

(I_GATECurrent vs Temperature)

)

–26

–24

–22

–20

–18

1.0

0.8

0.6

0.4

0.2

0

0.000

–0.005

–0.010

–0.015

–0.020

–0.025

85°C

25°C

–40°C

–50

–25

0

25

50

75

100

0

2

4

6

8

10

0

1024

2048

3071

4095

TEMPERATURE (°C)

I

(mA)

CODE

GPIO

4281 G10

4281 G11

4281 G12

ADC Integral Non-Linearity

vs Code (INL vs Code)

ADC Differential Non-Linearity

vs Code (DNL vs Code)

ADC Full-Scale Error

vs Temperature (V_FSEvs Temp.)

1.0

0.8

1.0

0.8

0.10

0.05

0.6

0.4

0.00

0.2

Right Click In Graph Area for Menu

Double Click In Graph Area for Data Setup

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.05

–0.10

–0.15

–0.20

0

1024

2048

3072

4096

1

1024

2048

3072

4095

–50

–25

0

25

50

75

100

CODE

TEMPERATURE (°C)

4281 G13

4281 G14

4281 G15

16-Bit GPIO ADC Noise Histogram

16-Bit Current ADC Noise Histogram

12-Bit GPIO ADC Noise Histogram

7000

6000

5000

4000

3000

2000

1000

0

5000

4000

3000

2000

1000

0

5000

4000

3000

2000

1000

0

V

= 1.000V

V

= 1.000V

∆V

= 20mV

ADC

GPIO

IN

RESOLUTION = 12b

= 312.5µV

RESOLUTION = 16b

= 19.5µV

RESOLUTION = 16b

= 610nV

V

LSB

–3

–2

–1

0

1

2

3

–4 –3 –2 –1

0

1

2

3

4

–4 –3 –2 –1

0

1

2

3

4

CODE VARIATION (LSB)

4281 G18

4281 G16

4281 G17

4281f

7

For more information www.linear.com/LTC4281

LTC4281

pin FuncTions

+

ADC : Positive Kelvin ADC Current Sense Input. Connect

GND: Device Ground.

this pin to the input side of the current sense resistor.

GPIO1: General Purpose Input/Open-Drain Output. Con-

figurabletogeneralpurposeoutput,logicinput,andpower

good or power bad signal. Tie to ground if unused.

Must be connected to the same trace as V or a resistive

DD

averaging network which adds up to 1Ω to V .

DD

–

ADC : Negative Kelvin ADC Current Sense Input. Connect

GPIO2: General Purpose Input/Open-Drain Output. Con-

figurable to general purpose output, logic input, MOSFET

stress output, or data converter input. Tie to ground if

unused.

this pin to the output of the current sense resistor or a

resistive averaging network.

ADR0 -ADR2: Serial Bus Address Inputs. Tying these pins

to ground (L), open (NC), or INTV (H) configures one

CC

GPIO3: General Purpose Input/ Open-Drain Output. Con-

figurable to general purpose output, logic input, or data

converter input. Tie to ground if unused.

of 27 possible addresses. See Table 1 in the Applications

Information section.

2

ALERT: I C Bus ALERT Output or General Purpose Input/

INTV : 3.3V Supply Decoupling Output. Connect a 1µF

CC

Output. Configurable to ALERT output, general purpose

capacitor from this pin to ground. To ensure fault logging

afterpowerislosta4.7μFcapacitorshouldbeused. 25mA

may be drawn from this pin to power 3.3V application

circuitry. Increase capacitance by 1µF/mA external load

if fault logging is used. This pin should not be driven and

is not current limited.

output or logic input. Tie to ground if unused.

CLKIN:ClockInput.Connecttoanoptionalexternalcrystal

oscillator circuit or drive with an external clock. Tie to

ground if unused.

CLKOUT: Clock Output. Connect to an optional external

crystal oscillator circuit. Can be configured in non-volatile

memory to output the internal clock or a low pulse when

the ADC finishes a conversion. Float if unused.

ON: On Control Input. Used to monitor a connection sense

pin on the backplane connector. The default polarity is

high = on, but may be reconfigured to low = on by setting

CONTROL1 register 0x00 bit 5 low. A on-to-off transition

on this pin clears the fault register if CONTROL1 register

0x00 bit 7 is set high. The ON pin has a precise 1.28V

threshold, allowing it to double as a supply monitor.

FB: Foldback Current Limit and Power Good Input. A

resistive divider from the output is tied to this pin. When

the voltage at this pin drops below 1.28V, power is not

consideredgood.Thepowerbadconditionmayresultinthe

GPIO1pinpullingloworgoinghighimpedancedepending

on the configuration of GPIO_CONFIG register 0x07 bits

4 and 5, also a power bad fault is logged in this condition

if the GATE pin is high. The start-up current limit folds

back to 30% as the FB pin voltage drops from 1.3V to 0V.

OV: Overvoltage Input Pin. An overvoltage condition is

present when this pin is above the configured threshold.

Connect a resistive divider when the internal divider is

disabled, otherwise leave open.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted

in or out on rising edges of SCL. This is a high impedance

pin that is generally driven by an open-drain output from

a master controller. An external pull-up resistor or current

source is required.

GATE: Gate Drive for External N-Channel MOSFET. An

internal 20µA current source charges the gate of the

MOSFET. No compensation capacitor is required on the

GATE pin, but a resistor and capacitor network from this

pin to ground may be used to set the output voltage slew

rate. During turn-off there is a 1mA pull-down current.

SDAI: Serial Bus Data Input. A high impedance in-

put for shifting in address, command or data bits.

Normally tied to SDAO to form the SDA line.

During a short-circuit or undervoltage lockout (V or

DD

INTV ), a 900mA pull-down between GATE and SOURCE

CC

is activated.

4281f

8

For more information www.linear.com/LTC4281

LTC4281

pin FuncTions

SDAO:SerialBusDataOutput.Open-drainoutputforsend-

ing data back to the master controller or acknowledging a

writeoperation.NormallytiedtoSDAItoformtheSDAline.

An external pull-up resistor or current source is required.

TIMER: Current Limit and Retry Timer Input. Connect a

capacitor between this pin and ground to set a 64ms/µF

duration for current limit, after which an overcurrent fault

is logged and GATE is pulled low. The duration of the off

time is 73s/µF when overcurrent auto-retry is enabled,

resulting in a 0.08% duty cycle.

+

SENSE : Positive Kelvin Current Sense Input. Connect

this pin to the input of the current sense resistor or an

averaging network in the case of multiple sense resistors.

Theparallelresistanceofanaveragingnetworkshouldnot

UV:UndervoltageInput.Anundervoltageconditionispres-

ent whenever this pin is below the configured threshold.

Connect a resistive divider when the internal divider is

disabled. A capacitor may be placed on this pin to filter

brief UV glitches on the input supply.

exceed 1Ω. Must operate at the same potential as V .

DD

–

SENSE : Negative Kelvin Current Sense Input. Connect

this pin to the output of the current sense resistor. The

currentlimitcircuitcontrolstheGATEpintolimitthesense

V : Supply Voltage Input and UV/OV Input. This pin has

DD

+

–

voltage between the SENSE and SENSE pins to the value

selected in the ILIM register or less.

an undervoltage lockout threshold of 2.7V. The UV and

OV thresholds are also measured at this pin, and the ADC

may be configured to read the voltage at this pin.

SOURCE:N-ChannelMOSFETSourceandADCInput.Con-

nect to the source of the external N-channel MOSFET. This

pin provides a return for the gate pull-down circuit and

alsoservesastheADCinputtomonitortheoutputvoltage.

WP: EEPROM Write Protect. All writes to the EEPROM

except fault logging are blocked when WP is high.

4281f

9

For more information www.linear.com/LTC4281

LTC4281

FuncTional DiagraM

24

–

25

+

SENSE

SLOW CL

–

+

SOURCE

+

– –

FAST CL

GATE

22

21

+

25mV

+

–

1V

FB 0.3V

CHARGE

PUMP AND

GATE DRIVER

164k

13.5V

3.3V

75mV

SOURCE

25k

5V

FET ON

ILIM

ADJUST

28k

12V

10k

24V

+

–

GATE UP

ADJ

+

–

10k

8V

GPIO1

GPIO2

GPIO3

GP

+

–

19

18

17

+

–

PG

1.280V

FB

–5, 10, OR 15%

21

1

ON

GP

+

–

ON

+

–

1.280V

LOGIC

1.280V

WP

+

–

4

GP

1.280V

+

V

1.280V

2.64V

–

DD

+

–

31

FET BAD

SOURCE

+

200mV

–

UVLO2

+

–

164k

25k

28k

10k

UV

INTV

CC

3.3V

5V

5

INTV

CC

3.3V

LDO

TM1

TM2

V

DD

+

–

0.2V

20µA

UVLO1

TIMER

GND

12V

24V

2.8V

V

+

–

DD(UVLO)

6

3

+

–

5µA

1.280V

5, 10,

OR 15%

SDAI

12

MIN

MAX

LOG

UV

OV

12

13

14

15

9

+

–

UV

OV

SDAO

A/D

CONVERTER 1

16

GPIO2

32

2

12

SCL

ALERT

ADR0

GPIO3

2

OV

I C

SOURCE

+

–

16

MULT

1.280V

5, 10, OR 15%

V

DD

POWER

48

A/D

CONVERTER 2

ACC1

ACC2

ADR1

10

11

ENERGY

32

∆V

SENSE

+

–

ADR2

OSC

CLK

1

TIME

+

–

CLKIN

8

CLKOUT

ADC ADC

30 26

7

4281 BD

4281f

10

For more information www.linear.com/LTC4281

LTC4281

operaTion

The LTC4281 is designed to turn a board’s supply voltage

on and off in a controlled manner, allowing the board to

be safely inserted or removed from a live backplane. Dur-

ing normal operation, the gate driver turns on an external

N-channel MOSFET to pass power to the load. The gate

driver uses a charge pump that derives its power from the

full-scale. GPIO2 may be configured to pull low to indicate

that the external MOSFET is in a state of stress when the

MOSFET is commanded to be on and either the gate volt-

age is lower than it should be or the DRAIN-to-SOURCE

voltage exceeds 200mV.

The Functional Diagram shows the monitoring blocks of

the LTC4281. The group of comparators on the left side

includes the undervoltage (UV), overvoltage (OV), and

(ON) comparators. These comparators determine if the

external conditions are valid prior to turning on the GATE.

But first the two undervoltage lockout circuits, UVLO1

and UVLO2, validate the input supply and the internally

V

pin. Also included in the gate driver is 12.5V GATE-

DD

to-SOURCE clamp to protect the oxide of the external

MOSFET. During start-up the inrush current is tightly

controlled by using current limit foldback.

The current limit (CL) amplifier monitors the load cur-

rent with a current sense resistor connected between the

+

–

SENSE and SENSE pins. The CL amplifier limits the cur-

rent in the load by pulling back on the GATE-to-SOURCE

voltage in an active control loop when the sense voltage

exceeds the commanded value.

generated 3.3V supply, INTV . UVLO2 also generates

CC

the power-up initialization to the logic circuits and copies

the contents of the EEPROM to operating memory after

INTV crosses this rising threshold.

CC

An overcurrent fault at the output may result in excessive

MOSFET power dissipation during active current limiting.

To limit this power, the CL amplifier regulates the voltage

between the SENSE and SENSE pins at the value set in

the ILIM register. When the output (SOURCE pin) is low,

power dissipation is further reduced by folding back the

current limit to 30% of nominal.

Included in the LTC4281 is a pair of 12 to 16-bit A/D

converters. One data converter continuously monitors the

+

–

ADC toADC voltage,samplingevery16µsandproducing

a 12-bit result of the average current sense voltage every

65ms. Theotherdataconverterissynchronizedtothefirst

one and measures the GPIO voltage and SOURCE voltage

during the same time period. Every time the ADCs finish

taking a measurement, the current sense voltage is mul-

tiplied by the measurement of the SOURCE pin to provide

a power measurement. Every time power is measured, it

is added to an energy accumulator which keeps track of

how much energy has been transmitted to the load. The

energy accumulator can generate an optional alert upon

overflow, and can be preset to allow it to overflow after

a given amount of energy has been transmitted. A time

accumulator also keeps track of how many times the

power meter has been incremented; dividing the results

of the energy accumulator by the time accumulator gives

the average system power. The minimum and maximum

+

–

The TIMER pin ramps up with 20μA when the current

limit circuit is active. The LTC4281 turns off the GATE and

registers a fault when the TIMER pin reaches its 1.28V

threshold. At this point the TIMER pin ramps down using

a 5μA current source until the voltage drops below 0.2V

(comparator TM1). The TIMER pin will then ramp up and

down 256 times with 20µA/5µA before indicating that the

externalMOSFEThascooledanditissafetoturnonagain,

provided overcurrent auto-retry is enabled.

The output voltage is monitored using the SOURCE pin

and the power good (PG) comparator to determine if the

power is available for the load. The power good condition

can be signaled by the GPIO1 pin. The GPIO1 pin may also

be configured to signal power bad, as a general purpose

input (GP comparator), or a general purpose open-drain

output.

+

–

measurements of GPIO, SOURCE, ADC to ADC and

POWER are stored, and optional alerts may be generated

if a measurement is above or below user configurable

8-bit thresholds.

An internal EEPROM provides nonvolatile configuration

of the LTC4281’s behavior, records fault information and

provides four bytes of uncommitted memory for general

purpose storage.

GPIO2 and GPIO3 may also be configured as general

purpose inputs or general purpose open-drain outputs.

Additionally, the ADC measures these pins with a 1.28V

4281f

11

For more information www.linear.com/LTC4281

LTC4281

operaTion

An I C interface is provided to read the A/D data registers.

2

faults in real time. The I C device address is decoded us-

It also allows the host to poll the device and determine

if faults have occurred. If the ALERT pin is configured

as an ALERT interrupt, the host is enabled to respond to

ing the ADR0-ADR2 pins. These inputs have three states

each that decode into a total of 27 device addresses, as

shown in Table 1.

applicaTions inForMaTion

A typical LTC4281 application is a high availability system

in which a positive voltage supply is distributed to power

individual hot-swapped cards. The device measures card

voltages and currents and records past and present

fault conditions. The LTC4281 stores min and max ADC

measurements, calculates power and energy, and can

be configured to generate alerts based on measurement

results, avoiding the need for the system to poll the de-

vice on a regular basis. The LTC4281 is configured with

nonvolatileEEPROMmemory, allowingittobeconfigured

during board level testing and avoid having to configure

the Hot Swap controller at every insertion.

Turn-On Sequence

The power supply on a board is controlled by using an

N-channel pass transistor, Q1, placed in the power path.

Resistor R senses current through Q1. Resistors R1, R2

S

and R3 define undervoltage and overvoltage levels. R4

preventshighfrequencyself-oscillationsinQ1,capacitors

C4 and C5 form a resonator network with crystal Y1 to

provide an accurate time base.

Several conditions must be present before the external

MOSFET turns on. First the external supply, V , must

DD

exceed its 2.7V undervoltage lockout level. Next the

internally generated supply, INTV , must cross its 2.6V

CC

A basic LTC4281 application circuit is shown in Figure 1.

The following sections cover turn-on, turn-off and various

faults that the LTC4281 detects and acts upon. External

component selection is discussed in detail in the Design

Example section.

undervoltage threshold. This generates a 1ms power-on-

resetpulse. Duringresetthefaultregistersareclearedand

the control registers are loaded with the data held in the

corresponding EEPROM registers.

R

S

Q1

0.5mΩ

V

PSMN2R0-30YLE × 2

OUT

12V

+

R7

30.1k

1%

65A ADJUSTABLE

C

R3

34.8k

1%

L

R4

10Ω

R8

3.57k

1%

R2

1.18k

1%

C

0.1µF

25V

F

+

–

V

ADC SENSE

SENSE

ADC

GATE SOURCE

DD

R1

3.4k

1%

UV

OV

SDAI

SDAO

SCL

FB

Z1

SMCJI5C

×2

GPIO1

GPIO2

GPIO3

POWER GOOD

SDA

SCL

ALERT

LTC4281

GP

ALERT

ADR0

ADR1

ADR2

NC

12V

ON

INTV

TIMER

WP CLKIN

CLKOUT GND

Y1

4MHz

CC

100k

C3

4.7µF

C4

C5

36pF

C

TIMER

15nF

36pF

GND

ABLS-4.000MHZ-B4-T

4281 F01

BACKPLANE PLUG-IN

CARD

Figure 1. Typical Application

4281f

12

For more information www.linear.com/LTC4281

LTC4281

applicaTions inForMaTion

After a power-on-reset pulse, the UV and OV pins verify

that input power is within the acceptable range. The state

of the UV and OV comparators is indicated by STATUS

register 0x1E bits 1 and 2 and must be stable for at least

50ms to qualify for turn-on. The ON pin is checked to see

that a connection sense (“short”) pin has asserted to the

correct state. By default the ON pin has no delay, but a

50ms debounce delay may be added by setting CONTROL

register 0x00 bit 6 high. When these conditions are satis-

fied, turn-on is initiated. Figure 4 shows connection sense

configurations for both high- and low-going short pins.

The ON pin has a precise 1.28V threshold, allowing it to

also monitor a voltage through the short pin, such as a

housekeeping or auxiliary supply delivered by the back-

plane. Use of the UV/OV divider for short pin detection in

high current applications is not recommended, as voltage

drops in the connector and fuse will impair the accuracy

of the intended function.

While the MOSFET is turning on, the power dissipation in

the MOSFET is limited to a fixed value by the current limit

foldbackprofileasshowninFigure2. AstheSOURCEvolt-

age rises, the FB pin follows as set by R7 and R8. Once

the GATE pin crosses its 8V ∆V

threshold and the FB

GATE

pin has exceeded its 1.28V threshold, the GPIO1 pin (in

its power good configuration) releases high to indicate

power is good and the load may be activated.

Attheminimuminputsupplyvoltageof2.9V,theminimum

GATE-to-SOURCE drive voltage is 10V. The GATE-to-

SOURCE voltage is clamped below 13.5V to protect the

gates of 20V N-channel MOSFETs. A curve of GATE-to-

SOURCEdrive(∆V

)versusV isshownintheTypical

GATE

DD

Performance Characteristics.

Turn-Off Sequence

A normal turn-off sequence is initiated by card withdrawal

whenthebackplaneconnectorshortpinopens,causingthe

ON pin to change state. Turn-off may be also initiated by

writing a 0 to CONTROL register 0x00 bit 3. Additionally,

severalfaultconditionsturnofftheGATEpin.Theseinclude

an input overvoltage, input undervoltage, overcurrent or

The MOSFET is then turned on by charging up the GATE

pin with a 20μA current source. When the GATE pin volt-

age reaches the MOSFET threshold voltage, the MOSFET

begins to turn on and the SOURCE voltage then follows

the GATE voltage as it increases.

V

DD

+ 12V

V

GATE

V

DD

+ 8V

V

DD

OUT

POWER GOOD

(GPIO1)

V

= 8V

GS

V

SENSE

100%

30%

I

• R

S

LOAD

CURRENT

LIMITED

NORMALIZED

MOSFET POWER

100%

4281 F02

FB

LIMITED POWER

Figure 2. Power-Up Waveforms

4281f

13

For more information www.linear.com/LTC4281

LTC4281

applicaTions inForMaTion

FET-BAD fault. Setting high any of the UV, OV , OC or

FET-BAD fault bits (bits 0-2 and 6 of the FAULT_LOG

register 0x04, also latches off the GATE pin if the associ-

ated auto-retry bits are set low.

loop is degraded by reducing the size of the resistor on

a gate RC network if one is used, which may necessitate

additional GATE-to-SOURCE capacitance. Board level

short-circuit testing is highly recommended as board

layout can also affect transient performance, the worst-

case condition for current limit stability occurs when the

output is shorted to ground after a normal start-up.

TheMOSFETisturnedoffwitha1mAcurrentpullingdown

the GATE pin to ground. With the MOSFET turned off, the

SOURCEandFBvoltagesdropastheloadcapacitancedis-

charges. WhentheFBvoltagecrossesbelowitsthreshold,

GPIO1 pulls low to indicate that the output power is no

longer good if configured to indicate power good. If the

Parasitic MOSFET Oscillations

Not all circuit oscillations can be ascribed to the current

limit loop. Some higher frequency oscillations can arise

from the MOSFET itself. There are two possible parasitic

oscillation mechanisms. The first type of oscillation oc-

curs at high frequencies, typically above 1MHz. This high

frequency oscillation is easily damped with gate resistor

R4 as shown in Figure 1. In some applications, one may

find that this resistor helps in short-circuit transient re-

covery as well. However, too large of a resistor will slow

down the turn-off time. The recommended R4 range is

between 5Ω and 500Ω. 10Ω provides stability without

affecting turn-off time. This resistor must be located at the

MOSFET package with no other components connected

to the MOSFET gate pin.

V

pin falls below 2.66V for greater than 2µs or INTV

DD

CC

drops below 2.49V for greater than 2µs, a fast shut down

of the MOSFET is initiated. The GATE pin is then pulled

down with a 900mA current to the SOURCE pin.

Current Limit Adjustment

ThecurrentlimitsensevoltageoftheLTC4281isadjustable

between 12.5mV and 34.4mV in 3.1mV steps via the I C

2

interface with bits 7-5 of the ILIM_ADJUST register 0x11.

DefaultvaluesarestoredintheonboardEEPROM.Thiscan

beusedtoadjustthesensevoltagetoachieveagivencurrent

limit using the limited selection of standard sense resistor

values available around 1mΩ. It also allows the LTC4281

to reduce available current for light loads or increase it in

anticipation of a surge. This feature also enables the use

of board trace as a sense resistors by trimming the sense

voltage to match measured copper resistance during final

test. The measured copper resistance may be written to

the undedicated scratch pad area of the EEPROM so that

it is available to scale ADC current measurements.

Asecondtypeofparasiticoscillationoccursatfrequencies

between 200kHz and 800kHz when the MOSFET source is

loaded with less than 10µF, and the drain is fed with an

inductive impedance such as contributed by wiring induc-

tance. To prevent this second type of oscillation load the

source with more than 10µF and bypass the input supply

with a 10Ω, 100nF snubber to ground.

Current Limit Stability

Overcurrent Fault

For most applications the LTC4281 current limit loop is

stable without additional components. However there

are certain conditions where additional components may

be needed to improve stability. The dominant pole of the

current limit circuit is set by the capacitance at the gate of

the external MOSFET, and larger gate capacitance makes

the current limit loop more stable. Usually a total of 8nF

GATE-to-SOURCEcapacitanceissufficientforstabilityand

The LTC4281 features an adjustable current limit with

foldback that protects the MOSFET from excessive load

current. To protect the MOSFET during active current

limit, the available current is reduced as a function of the

output voltage sensed by the FB pin such that the power

dissipated by the MOSFET is constant. A graph in the

Typical Performance Characteristics shows the current

limit and power versus FB voltage.

is provided by inherent MOSFET C . The stability of the

GS

4281f

14

For more information www.linear.com/LTC4281

LTC4281

applicaTions inForMaTion

Anovercurrentfaultoccurswhenthecurrentlimitcircuitry

has been engaged for the MOSFET for longer than the

time-out delay set by the TIMER capacitor. Current limit-

ing begins when the current sense voltage between the

threshold the switches are allowed to turn on again if the

overcurrent auto-retry bit is set or the overcurrent fault

2

bit has been reset by the I C interface.

The waveform in Figure 3 shows how the output turns off

following a short circuit.

+

–

SENSE and SENSE pins reaches the current limit level

(which depends on foldback and the current limit configu-

ration). The GATE pin is then pulled down and regulated in

order to limit the current sense voltage to the current limit

value. When the GATE pin regulator is in current limit, the

circuit breaker time delay starts by charging the external

timer capacitor from the TIMER pin with a 20µA pull-up

current. If the TIMER pin reaches its 1.28V threshold, the

external switch turns off with a 1mA current from GATE to

ground. If the GATE pin stops current limiting before the

TIMER pin reaches the 1.28V threshold, the TIMER pin

will discharge with 5μA. For a given circuit breaker time

Overvoltage Fault

An overvoltage fault occurs when the OV pin rises above

the OV threshold for longer than 15µs. This shuts off

the GATE pin with a 1mA current to ground and sets the

overvoltage present and overvoltage fault bits (Bit 0) in

STATUS and FAULT_LOG registers 0x1E and 0x04. If the

voltage subsequently falls back below the threshold for

50ms, the GATE pin is allowed to turn on again unless

overvoltage auto-retry has been disabled by clearing the

OV auto-retry bit (Bit 0) in CONTROL register 0x00. If an

externalresistivedividerisused,theOVthresholdis1.28V

on the OV pin. When using the internal dividers the OV

delay, t , the equation for setting the timing capacitor’s

CB

value is as follows:

C = t • 0.016[μF/ms]

T

CB

threshold is referenced to the V pin.

DD

IfanovercurrentfaultisdetectedtheMOSFETisturnedoff

andtheTIMERpinbeginsdischargingwitha5µApull-down

current. When the TIMER pin reaches its 0.15V threshold,

it will cycle up and down with 20µA and 5µA 256 times to

allow the MOSFET time to cool down. When automatically

retrying, the resulting overcurrent duty cycle is 0.08%.

The final time the TIMER pin falls below its 0.15V lower

Undervoltage Fault

An undervoltage fault occurs when the UV pin falls below

its 1.28V threshold for longer than 15µs. This shuts off

the GATE pin with a 1mA current to ground and sets the

undervoltage present and undervoltage fault bits (Bit 0)

in STATUS and FAULT_LOG registers 0x1E and 0x04. If

GATE

10V/DIV

SOURCE

10V/DIV

TIMER EXPIRES

TIMER

2V/DIV

Current

50A/DIV

4281 F03

200µs/DIV

Figure 3. Short-Circuit Waveform

4281f

15

For more information www.linear.com/LTC4281

LTC4281

applicaTions inForMaTion

the voltage subsequently rises back above the threshold

for 50ms, the GATE pin is allowed to turn on again unless

undervoltage auto-retry has been disabled by clearing

the UV auto-retry bit in CONTROL register 0x00. For the

internal thresholds, the UV and OV signals may be filtered

by placing a capacitor on the UV pin.

12V

LTC4281

ON

10k

C

ON

ON/OFF Control

TheONpincanbeconfiguredactivehighoractivelowwith

CONTROLregister0x00bit5(1foractivehigh).Intheactive

high configuration it is a true ON input, in the active low

configuration it can be used as an ENABLE input to detect

card insertion with a grounded short pin. The delay from

the ON pin commanding the part to turn on until the GATE

pin begins to rise is set by CONTROL registers 0x00 bit 6.

IfthisbitislowtheGATEpinturnsonimmediately, andifit

is high it turns on after a 50ms debounce delay. Whenever

theONpintoggles,bit4inFAULT_LOGregister0x04isset

to indicate a change of state and the other bits in FAULT

register 0x04 are reset unless the ON_FAULT_MASK bit 7

in CONTROL register 0x00 is set.

4281 F04a

(a) ON Configured Active High (Default)

CONTROL Register 0 x0 0 Bit 5=1

12V

10k

C

ON

LTC4281

ON

The FET_ON bit, bit 3 of CONTROL register 0x00, is set

or reset by the rising and falling edges of the ON pin and

4281 F04b

2

by I C write commands. When the LTC4281 comes out of

(b) ON Configured Active Low CONTROL

Register 0 x0 0 Bit 5=0

UVLO the default state for bit 3 is read out of the EEPROM.

If it is a 0, the part is configured to stay off after power-up

and ignore the state of the ON pin. If it is a 1 the condition

of the ON pin will be latched to bit 3 after the debounce

period and the part will turn the GATE on if the ON pin is

in the ON state.

12V MAIN

LTC4281

ON

AUX 3.3V

If the system shuts down due to a fault, it may be desirable

to restart the system simply by removing and reinserting

a load card. In cases where the LTC4281 and the switch

reside on a backplane or midplane and the load resides on

a plug-in card, the ON pin detects when the plug-in card is

removed. Figure 4 shows an example where the ON pin is

usedtodetectinsertion.Oncetheplug-incardisreinserted

the FAULT_LOG register 0x04 is cleared (except for bit 5,

13k

10k

C

ON

4281 F04c

(c) ON Pin Sensing of AUX Supply ON

Pin Configured Active High (Default)

Figure 4. Connection Sense Configurations with the ON Pin

4281f

16

For more information www.linear.com/LTC4281

LTC4281

applicaTions inForMaTion

which indicates the ON pin changed state). After the ON

pin turn-on delay, the system is allowed to start up again.

When either FET-bad condition is present while the

MOSFET is commanded on, an internal FET-bad fault

timer starts. When the timer reaches the threshold set in

FET_BAD_FAULT_TIME register 0x06 (1ms per LSB for a

maximum of 255ms), a FET-bad fault condition is set, the

part turns off, and the GATE pin is pulled low with a 1mA

current. In the case of a GAIN-to-DRAIN short, it may be

impossible for the LTC4281 to turn off the MOSFET. In

this case the LTC4281 can be configured to signal power-

bad to the load so the load goes into a low current state

and send a FET-bad fault alert to the controller that may

be able to shut down upstream supplies and/or flag the

card for service.

If a connection sense on the plug-in card is driving the ON

pin, insertion or removal of the card may cause the pin

voltagetobounce. ThisresultsinclearingtheFAULT_LOG

register when the card is removed. The pin may be de-

bounced using a filter capacitor, C , on the ON pin as

ON

shown in Figure 4. Note that the polarity of the ON pin is

inverted with CONTROL Register 0x00 bit 5 set to 0.

FET-Bad Fault

In a Hot Swap application several things can prevent the

MOSFET from turning on and reaching a low impedance

state. A damaged MOSFET may have leakage from gate

TheLTC4281treatsaFET-badfaultsimilartoanovercurrent

fault, and will auto-retry after 256 timer cycles if the

overcurrent auto-retry bit is set. Note that during start-

up, the FET-bad condition is present because the voltage

from DRAIN to SOURCE is greater than 200mV and the

GATE pin is not fully enhanced, thus the FET-bad timeout

must be long enough to allow for the largest allowable

load to start up. FET-bad faults are disabled by setting

the FET_BAD_FAULT_TIMER value to 0x00.

to drain or have degraded R

. Debris on the board

DS(ON)

may also produce leakage or a short from the GATE pin

to the SOURCE pin, the MOSFET drain, or to ground. In

these conditions the LTC4281 may not be able to pull the

GATE pin high enough to fully enhance the MOSFET, or

the MOSFET may not reach the intended R

when

DS(ON)

the GATE pin is fully enhanced. This can put the MOSFET

in a condition where the power in the MOSFET is higher

than its continuous power capability, even though the

current is below the current limit. The LTC4281 monitors

the integrity of the MOSFET in two ways, and acts on both

of them in the same manner.

FET Short Fault

AFETshortfaultisreportedifthedataconvertermeasures

a current sense voltage greater than or equal to 0.25mV

while the GATE pin is turned off. This condition sets the

FET_SHORTbit5instatusregister0x1E,andFET_SHORT_

FAULT bit 5 in fault register 0x04.

First, the LTC4281 monitors the voltage between the

MOSFET V and SOURCE pins. The LTC4281 has a

DD

comparator that detects a bad DRAIN-to-SOURCE voltage

(V ) whenever the V is greater than 200mV.

DS

Power-Bad Fault

Second,theLTC4281monitorstheGATEvoltage.TheGATE

voltage may not fully enhance with a damaged MOSFET,

and a severely damaged MOSFET most often has GATE,

DRAIN and SOURCE all shorted together. If the LTC4281

is in the ON state, but the GATE pin does not come up to

its 8V threshold above SOURCE, a FET-bad condition is

detected.

The POWER_GOOD status bit, bit 3 in STATUS register

0x1E, is set when the FB pin voltage rises above its 1.28V

threshold. To indicate POWER_GOOD on the GPIO1 pin,

the GATE pin must first exceed the 8V V thresholds after

GS

start-up, this requirement prevents POWER_GOOD from

asserting during start-up when the FB pin first crosses its

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GATE_HIGH

POWER_BAD_FAULT PRESENT

POWER_GOOD(GPIO)

POWER_GOOD

STATUS

S

R

Q

FET_ON

4281 F05

Figure 5. POWER_GOOD Logic

threshold.Afterstart-uptheGPIO1pinwilloutputthevalue

of the FB comparator so that POWER_GOOD stays high

even in cases such as an input voltage step that causes

After the bus master controller broadcasts the Alert

ResponseAddress,theLTC4281respondswithitsaddress

ontheSDAlineandreleasesALERTasshowninFigure16.

If there is a collision between two LTC4281s responding

with their addresses simultaneously, then the device with

the lower address wins arbitration and releases its ALERT

pin. The devices that lost arbitration will still hold the

ALERT pin low and will respond with their addresses and

the GATE pins to briefly dip below 8V V . See Figure 5.

GS

A power bad fault is generated when the FB pin is low and

the GATE pin is high, preventing power-bad faults during

power-up or power-down.

2

release ALERT as the I C master broadcasts additional

Fault Alerts

Alert Response protocols until ALERT is release by all

devices. The ALERT pin can also be released by clearing

A fault condition sets the corresponding fault bit in

FAULT_LOG register 0x04, ADC_ALERT_LOG register

0x05, and TIMER_OVERFLOW_PRESENT (Bit 1) and

METER_OVERFLOW_PRESENT (Bit 2) in the STATUS

register 0x1F. Fault bits are reset by writing a 0 and the

overflow status bits are reset by resetting the energy

meter by setting and resetting ADC_CONTROL register

0x1D bit 6. A fault condition can also generate an alert

(ALERT asserts low) by setting the corresponding bit in

the alert mask registers: ALERT registers 0x02 and 0x03,

and GPIO_CONFIG register bit 0. A low on ALERT may

be generated upon completion of an ADC measurement

by setting bit 2 in the GPIO_CONFIG register 0x07. This

condition does not have a corresponding fault bit. Faults

with enabled alerts set bit 7 in the ALERT_CONTROL

register 0x1C, which controls the state of the ALERT pin.

Clearing this bit will cause the ALERT pin to go high and

setting this bit causes it to go low. Alert masking stored

in EEPROM is transferred into registers at power up.

2

ALERT_CONTROL bit 7 in register 0x1C with the I C

interface.

The ALERT pin can also be used as a GPIO pin, which

pulls low by setting ALERT_CONTROL bit 6 in register

0x1C. The ALERT pin input status is located in STATUS

register 0x1F bit 4.

Once the ALERT signal has been released from a fault, it

will pull low again if the corresponding fault reoccurs, but

not if the fault remains continuously present.

Resetting Faults in FAULT_LOG

The faults in FAULT_LOG register 0x04 may cause the

part to latch off if their corresponding auto-retry bits are

not set. In backplane resident applications it is desirable

to latch off if a card has produced a failure and start up

normally if the card is replaced. To allow this function the

ON pin must be used as a connection sense input. When

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CONTROL bit 7 in register 0x00 is not set, a turn-off signal

from the ON pin (card removed) will clear the FAULT_LOG

register except for bit 4 (ON changed state). The entire

at the V pin or V

at the SOURCE pin by setting bit 3,

OUT

DD

and can select between measuring GPIO2 or GPIO3 with

bit 2. The data converter full-scale is 40mV for the current

sensevoltage,achoiceof33.28V,16.64V,8.32Vor5.547V

FAULT_LOG register also cleared when the INTV pin

CC

falls below it’s 2.49V threshold (UVLO), and individual

for V and V

, and 1.28V for GPIO.

DD

SOURCE

–

2

bits may be cleared manually via the I C interface. Note

+

The ADC and ADC pins allow the ADC to measure the

voltage across the sense resistor. Some applications may

use two or more sense resistors in parallel to limit the

power in each resistor or achieve a specific parallel resis-

tance or tolerance unavailable in a single sense resistor.

In this case averaging resistors can be used to accurately

measure the current by choosing averaging resistors with

the same ratio as the sense resistors they connect to. See

Figure 6. In this case the effective ADC sense resistor

that faults that are still present, as indicated in STATUS

register 0x1E, cannot be cleared.

TheFAULT_LOGregisterisnotclearedwhenauto-retrying.

When auto-retry is disabled the existence of a logged fault

keeps the MOSFET off. As soon as the FAULT_LOG is

cleared,theMOSFETturnson.Ifauto-retryisenabled,then

ahighstatusbitkeepstheMOSFEToffandtheFAULT_LOG

bit is ignored. Subsequently, when the FAULT_LOG bit is

cleared by removal of the fault condition, the MOSFET is

allowed to turn on again even though the fault bit remains

set as a record of the previous fault condition.

is R in parallel with k•R for the current limit. Scaling

S

A

the averaging resistors, R , by the same scaling factor,

k, allows the ADC to measure the correct sense voltage

for this effective sense resistor. The smallest averaging

resistor should not exceed 1Ω.

Reboot

The LTC4281 features a reboot command bit, located in

bit 7 of ADC_CONTROL register 0x1D. Setting this bit will

cause the LTC4281 to reset and copy the contents of the

EEPROM to operating memory the same as after initial

power-up. The 50ms debounce before the part restarts

is lengthened to 3.2s for reboot in order to allow load

capacitance to discharge and reset before the LTC4281

turns back on. On systems where the Hot Swap controller

+

ADC

+

SENSE

R

k•R

A

R

SENSE2

SENSE1

R

k • R

S

k•R

A

–

ADC

–

2

SENSE

4281 F06

supplies power to the I C master, this allows the master

to issue a command that power cycles the entire board,

including itself.

Figure 6. Weighted Averaging Sense Voltages

Data Converters

The LTC4281 incorporates a pair of sigma-delta A/D con-

vertersthatareconfigurableto12or16bits.Oneconverter

continuously samples the current sense voltage, while the

other monitors the input/output voltage and the voltage

on a GPIO input. The sigma-delta architecture inherently

averages signal noise during the measurement period.

The two data converters are synchronized, and after each

currentmeasurementconversion,themeasuredcurrentis

multiplied by the measured V or V

to yield input

DD

SOURCE

or output power. After each conversion the measurement

results and power are compared to the recorded min and

max values. If the measurement is a new min or max, then

The data converters may be run in a 12-bit or 16-bit mode,

as selected by bit 1 in ILIM_ADJUST register 0x11. The

second data converter may be configured to measure V

IN

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those registers are updated. The measurements are also

compared to the min/max alarm thresholds in registers

0x08 to 0x0F and will set the corresponding ADC alert bit

in ADC_ALERT_LOG register 0x05 and generate an alert

if configured to do so in ALERT register 0x03.

To calculate input/output voltage:

CODE(word)•V

FS(OUT)

V =

2¹⁶−1

where V

is 33.28V, 16.64V, 8.32V or 5.547V de-

FS(OUT)

After each measurement, calculated power is added to

an accumulator that meters energy. Since the current is

continuously monitored by a dedicated ADC, the current

is sampled every 16µs, ensuring that the energy meter will

accuratelymeternoisyloadsupto62.5kHznoisefrequency.

The 6-byte energy meter is capable of accumulating 20

days of power at full scale, which is several months at a

nominal power level. An optional alert may be generated

when the meter overflows. To measure coulombs, the

energy meter may be configured to accumulate current

rather than power by setting CLK_DIVIDER register 0x10

bit 7.

pending on the part being in 24V, 12V, 5V or 3.3V mode,

respectively.

To calculate current in amperes:

CODE(word)•0.040V

I=

2¹⁶−1 •R_SENSE

(

)

To calculate power in watts:

CODE(word)•0.040V •V_FS(OUT)•2¹⁶

P=

2¹⁶−1 ²•R_SENSE

(

)

A time counter keeps track of how many times power has

been added into the energy meter. Dividing the energy by

the number in the counter will yield the average power

over the accumulated interval. When metering coulombs

dividing the metered charge by the counter produces the

averagecurrentovertheaccumulationinterval.The4-byte

time counter will keep count for 10 years in the 12-bit

mode before overflowing, and can generate an alert at

full scale to indicate that the counter is about to roll over.

To calculate energy in joules:

CODE(48 bits)•0.040V •V_FS(OUT)•t_CONV•2⁸

E=

2¹⁶−1 ²•R_SENSE

(

)

To calculate coulombs:

CODE(48 Bits)•0.040V •t_CONV

(2¹⁶−1)•R_SENSE

C=

Multiplying the value in the counter by t

yields the

CONV

time that the energy meter has been accumulating.

where t

= (1/f

) is 0.065535s for 12-bit mode and

CONV

CON

1.0486s for 16-bit mode.

Boththeenergyaccumulatorandtimecounterarewritable,

allowing them to be pre-loaded with a given energy and/

or time before overflow so that the LTC4281 will generate

an overflow alert after either a specified amount of energy

has been delivered or time has passed.

To calculate average power over the energy accumulation

period:

E

P(AVG)=

t_CONV•CODE(COUNTER)

The following formulas are used to convert the values in

the ADC result registers into physical units. The data in

the 12-bit mode is left justified, so the same equations

apply to the 12-bit mode and the 16-bit mode.

C

I(AVG)=

t_CONV•CODE(COUNTER)

To calculate GPIO voltage alarm thresholds:

To calculate GPIO voltage:

CODE(byte)•1.280

V =

CODE(word)•1.280

V =

2¹⁶−1

255

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To calculate input/output voltage alarm thresholds:

divider, the clock frequency is divided by twice the value in

CLK_DIVIDER register 0x10 bits 0-4. Code 00000 passes

theclockthroughwithoutdivisionwhilecode01000divides

a 4MHz clock down to 250kHz. The divided external clock

may differ from 250kHz by 5% without affecting other

specifications.

CODE(byte)•V

FS(OUT)

V_ALARM

=

255

where V

is 33.28V, 16.64V, 8.32V or 5.5467V de-

FS(OUT)

pending on the part being in 24V, 12V, 5V or 3.3V mode,

respectively.

Configuring the GPIO Pins

To calculate current alarm thresholds in amperes:

The LTC4281 has three GPIO pins and an ALERT pin, all

of which can be used as general purpose input/output

pins.TheGPIO1pinisconfiguredusingtheGPIO_CONFIG

register 0x07 bits 5-4. GPIO2 will pull low to indicate

MOSFET stress if GPIO_CONFIG bit 1 is set and pulls low

if bit 6 is low. GPIO3 pulls low if GPIO_CONFIG bit 7 is set

and is otherwise high impedance. The ALERT pin can be

used as a GPIO pin by setting all the alert enable bits to 0

to disable alerts, then setting bit 6 in ALERT_CONTROL

register 0x1C. Bit 7 in ALERT_CONTROL can also be set

to pull the ALERT pin low, but bit 7 will cause the part to

respond to the alert response protocol, while bit 6 will not.

CODE(byte)•0.040V

I=

255•R_SENSE

To calculate power alarm threshold in watts:

CODE(byte)•0.040V •V_FS(OUT)•2⁸

P=

R_SENSE•255•255

Note that falling alarm thresholds use CODE(byte)+1 in

the above equations since they trip at the top edge of the

code, which is 1LSB higher than the rising threshold.

GPIO1-GPIO3andALERTallhavecomparatorsmonitoring

the voltage on these pins with a threshold of 1.28V when

the pins are serving as outputs. The results may be read

fromthesecondbyteoftheSTATUSregister,0x1F,bits4-7.

CLKIN, CLKOUT: Crystal Oscillator/External Clock

Accurately measuring energy by integrating power re-

quires a precise integration period. The on-chip clock

of the LTC4281 is trimmed to 1.5% and specified over

temperature to 5% and is invoked by grounding CLKIN.

Forincreasedaccuracyacrystaloscillatororexternalpreci-

sion clock may be used on the CLKIN and CLKOUT pins.

A 4MHz crystal oscillator or resonator may be connected

to the two CLK pins as shown in Figure 1.

Supply Transients

Incard-residentapplications,outputshortcircuitsworking

against the inductive nature of the supply can easily cause

the input voltage to dip below the UV threshold.

In severe cases where the supply inductance is 500nH

Crystal oscillators are sensitive to noise and parasitic

capacitance. Care should be taken in layout to minimize

trace length between the LTC4281 and the crystal. Keep

noisy traces away from the crystal traces, or shield the

crystal traces with a ground trace.

or more, the input can dip below the V undervoltage

DD

lockout threshold of 2.66V. Because the current passing

through the sense resistor changes no faster than a rate

of V

/L

, such as 12V/500nH = 24A/µs, it is

SUPPLY SUPPLY

possible for the UV comparator and in particular, the V

DD

Alternatively, an external clock may be applied to CLKIN

withCLKOUTleftunconnected.TheLTC4281canacceptan

external clock between 250kHz and 15.5MHz, with clocks

fasterthan250kHzreducedto250kHzbyaprogrammable

UVLO circuit to respond before the current reaches the

current limit threshold. The V UVLO circuit responds

DD

after a 2µs filter delay, pulling the GATE pin to SOURCE

with 900mA. Once the MOSFET turns off, V will return

DD

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LTC4281

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to its nominal voltage and the part initiates a new startup

sequence. The UV comparator responds after a 15µs

filter delay, making it less likely that this path will engage

before current limiting commences; adding a 100nF filter

capacitor to the UV pin ensures this. The fast current limit

amplifierengagesat3xthecurrentlimitthreshold,andhas

a propagation delay of 500ns. If the supply inductance is

less than 500nH in a 12V application, it is unlikely that the

Supply Transient Protection

The worst-case Z1 current is that which triggers the fast

current limit circuit. Several 1500W surge suppressors

may be required to clamp this current for high power

applications. Many 20V to 30V MOSFETs enter avalanche

breakdownbefore45V.InthosecasestheMOSFETcanact

asasurgesuppressorandprotecttheHotSwapcontroller

frominductiveinputvoltagesurges. Inapplicationswhere

a high current ground is not available to connect the surge

suppressor, the surge suppressor may be connected

from input to output, allowing the output capacitance to

absorb spikes.

V

UVLO threshold will be breached and the fast di/dt

DD

rate allows the current to rise to the 3x level long before

the UV pin responds.

Once the fast current limit amplifier begins to arrest the

short-circuit current, the input voltage rapidly recovers

and even overshoots its DC value. The LTC4281 is safe

from damage up to 45V. To minimize spikes in backplane-

resident applications, bypass the LTC4281 input supply

Design Example

Asadesignexample,considerthefollowingspecifications:

V

= 12V, I

OV(OFF)

= 50A, C = 3300μF, V

= 10.75V,

)

UV ON

(

IN

MAX

= 14.0V, V

L

2

with an electrolytic capacitor between V and GND. In

DD

= 11.6V, and I C address

PWRGD(UP)

card-resident applications clamp the V pin with a surge

DD

= 1010011, with overcurrent threshold set to 25mV. This

completed design is shown in Figure 7.

suppressor Z1, as shown in Figure 7.

R

S

Q1

0.5mΩ

V

PSMN2R0-30YLE × 2

OUT

12V

50A

12V

+

R7

30.1k

1%

C

L

R3

34.8k

1%

3300µF

R4

10Ω

R8

3.57k

1%

R2

1.18k

1%

C

0.1µF

25V

F

+

–

V

ADC SENSE

SENSE

ADC

GATE SOURCE

DD

R1

3.4k

1%

UV

OV

SDAI

SDAO

SCL

FB

GPIO1

GPIO2

GPIO3

POWER GOOD

SDA

SCL

ALERT

LTC4281

GP

ALERT

ADR0

ADR1

ADR2

Z1

NC

SMCJ15CA

× 2

12V

ON

INTV

TIMER

WP CLKIN

CLKOUT GND

Y1

4MHz

CC

100k

C3

4.7µF

C4

C5

36pF

C

TIMER

36pF

47nF

GND

ABLS-4.000MHZ-B4-T

4281 F07

BACKPLANE PLUG-IN

BOARD

Figure 7. Design Example

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Selection of the sense resistor, R , is set by the current

For a start-up time of 1.33ms with a 2x safety margin we

choose:

S

limit threshold of 25mV:

25mV

I_MAX

t_STARTUP

64ms/µF

1.33ms

64ms/µF

R_S=

= 0.5mΩ

C_TIMER= 2•

= 2•

≅ 47nF

In the event that the circuit attempts to start up into a

short circuit the current will be 30% of 50A, 15A, and the

voltage across the MOSFET will be 12V which the MOS-

FET will carry for 1.33ms. This is within the SOA of the

PSMN2R0-30YLE, so the application will safely survive

this fault condition.

The MOSFET is sized to handle the power dissipation dur-

ing inrush when output capacitor C is being charged.

OUT

A method to determine power dissipation during inrush

is based on the principle that:

Energy in C = Energy in Q1

L

where:

The UV and OV resistor string values can be solved in the

following method. To keep the error due to 1µA of leak-

age to less than 1% choose a divider current of at least

200µA. R1 < 1.28V/200µA = 6.4kΩ. Then calculate the

following equations:

1

2

1

2

Energy in C_L= CV²= 3.3mF 12 = 0.24J

(

2

) ( )

During inrush, current limit foldback will limit the power

dissipation in the MOSFET to:

V

UV_TH(RISING)

R2= ^OV(OFF)•R1•

V_UV(ON)

–R1

7.5mV •12V

OV_TH(FALLING)

P_DISS

=

= 180W

R_S

V_UV(ON)• R1+R2

(

)

–R1–R2

R3=

Calculate the time it takes to charge up C

Energyin C_L0.24J

:

UV_TH(RISING)

OUT

t_STARTUP

=

= 1.33ms

In our case we choose R1 to be 3.4kΩ to give a resistor

string current greater than 200μA. Then solving the equa-

tions results in R2 = 1.18kΩ and R3 = 34.8kΩ.

P_DISS

180W

TheSOA(safeoperatingarea)curvesofcandidateMOSFETs

must be evaluated to ensure that the heat capacity of the

package tolerates 180W for 1.33ms. The SOA curve of the

NXP PSMN2R0-30YLE shows 200W for 80ms, satisfying

this requirement. Additional MOSFETs in parallel may

be required to keep the MOSFET temperature or power

dissipation within limits at maximum load current. This

depends on board layout, airflow and efficiency require-

ments. To get the maximum DC dissipation below 2W per

MOSFET, a pair of PSMN2RO-30YLE is required for Q1.

Since the PSMN2R0-30YLE has 10nF of gate capacitance

it is likely to be stable, but the short-circuit stability of the

current limit should be checked and improved by adding

capacitors from GATE to SOURCE if needed.

The FB divider is solved by picking R8 and solving for R7,

choosing 3.57kΩ for R8 we get:

V_PWRGD(UP)•R8

R7=

–R8

FB_TH(RISING)

Resulting in R7 = 30.1kΩ.

Since this application uses external resistive dividers

for UV, OV and FB, and the operating voltage is 12V, the

CONTROL register 0x01 is set to 0x02 to disable the in-

ternal thresholds and set the ADC to the 12V range. The

EEPROM CONTROL register 0x21 is also set to 0x02 so

the part will boot in the proper configuration.

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Since the start-up time is 1.33ms, the FET_BAD_FAULT_

TIME is set to 3ms for a ≥ 2x safety margin by writing

0x03 to the FET_BAD_FAULT_TIME register 0x06.

To improvenoiseimmunity,puttheresistivedividerstothe

UV, OV and FB pins close to the device and keep traces to

DD

V

and GND short. It is also important to put the bypass

capacitorC3ascloseaspossiblebetweenINTV andGND.

CC

A 0.1μF capacitor, C , is placed on the UV pin to prevent

F

A 0.1μF capacitor from the UV pin (and OV pin through

resistorR2)toGNDalsohelpsrejectsupplynoise.Figure8

shows a layout that addresses these issues. Note that

a surge suppressor, Z1, is placed between supply and

ground using wide traces.

supply glitches from turning off the GATE via UV or OV.

The address is set with the help of Table 1, which indicates

binary address 1010011 (0xA6). Address 0xA6 is set by

setting ADR2 high, ADR1 open and ADR0 high.

Next the value of R4 is chosen to be the default value of

10Ω as discussed in the Current Limit Stability section.

A 4MHz crystal is placed between the CLKIN and CLKOUT

pins. The specified part requires 18pF load capacitance

which is provided by C4 and C5. To generate an internal

clock of 250kHz, 1000b is written to the CLOCK_DIVIDER

register 0x10 to divide the 4MHz crystal frequency by 16.

R1

Z1

R3

R2

C

F

C3

Since the fast pull-down is engaged at 150A, the input TVS

needs to be capable of clamping a 150A surge at a voltage

above the OV threshold but below the 45V absolute maxi-

mumratingoftheLTC4281forabout1µs. TheSMCJ15CA

clamps 61.5A at 24V for 8.3ms, and can dissipate 30kW

for 1µs. One SMCJ15CA will meet these requirements.

C

T

4281 F08

Figure 8. Recommended Layout

In addition a 4.7μF ceramic bypass capacitor is placed

It is ill advised to place the ground plane under the power

MOSFETs. If they fail and overheat that could result in a

catastrophic failure as the input gets shorted to ground

when the insulation between them fails.

on the INTV pin. No bypass capacitor is required on

CC

the V pin.

DD

Layout Considerations

To achieve accurate current sensing, Kelvin connections

are required. The minimum trace width for 1oz copper

foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider

is recommended. Note that 1oz copper exhibits a sheet

resistance of about 530μΩ/£. Small resistances add up

quickly in high current applications.

Digital Interface

The LTC4281 communicates with a bus master using a

2

2-wire interface compatible with I C Bus and SMBus, an

2

I C extension for low power devices. The LTC4281 is a

read-write slave device and supports SMBus Read Byte,

Write Byte, Read Word and Write Word commands, as

2

well as I C continuous read and continuous write com-

mands. Data formats for these commands are shown in

Figures 9 through 16.

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a6 – a0

b7 – b0

SDA

SCL

1 – 7

8

9

1 – 7

8

9

1 – 7

8

9

S

P

START

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

4281 F09

Figure 9. Data Transfer Over I²C or SMBus

S

ADDRESS

W

A

COMMAND

A

DATA

A

P

1 0 a4:a0

0

b7:b0

0

b7:b0

0

4281 F10

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W: WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

Figure 10 . LTC4281 Serial Bus SDA Write Byte Protocol

S

ADDRESS

W

A

COMMAND

A

DATA

A

DATA

A

P

1 0 a4:a0

0

b7:b0

0

b7:b0

0

b7:b0

0

4281 F11

Figure 11. LTC4281 Serial Bus SDA Write Word Protocol

S

ADDRESS

W

A

COMMAND

A

DATA

A

DATA

A

DATA

A

P

• • •

1 0 a4:a0

0

b7:b0

0

b7:b0

0

b7:b0

0

b7:b0

0

4281 F12

Figure 12. LTC4281 Serial Bus SDA Continuous Write Protocol

S

ADDRESS

W

A

COMMAND

A

S

ADDRESS

R

A

DATA

A

P

1 0 a4:a0

0

b7:b0

0

1 0 a4:a0

1

0

b7:b0

1

4281 F13

Figure 13. LTC4281 Serial Bus SDA Read Byte Protocol

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S

ADDRESS

W

A

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

A

P

1 0 a4:a0

0

b7:b0

0

1 0 a4:a0

1

0

b7:b0

0

b7:b0

1

4281 F14

Figure 14. LTC4281 Serial Bus SDA Read Word Protocol

S

ADDRESS

W

A

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

A

DATA

b7:b0

A

P

• • •

1 0 a4:a0

0

b7:b0

0

1 0 a4:a0

1

0

b7:b0

0

b7:b0

0

1

4281 F15

Figure 15. LTC4281 Serial Bus SDA Continuous Read Protocol

ALERT

RESPONSE

ADDRESS

DEVICE

ADDRESS

S

R

A

P

0 0 0 1 1 0 0

1

0

1 0 a4:a0 0

1

4281 F16

Figure 16. LTC4281 Serial Bus SDA Alert Response Protocol

START and STOP Conditions

Response Address. If the LTC4281 is pulling low on the

ALERT pin, it acknowledges this address by broadcasting

its address and releasing the ALERT pin.

When the bus is idle, both SCL and SDA are high. A bus

mastersignalsthebeginningofatransmissionwithastart

condition by transitioning SDA from high to low while

SCL is high, as shown in Figure 10. When the master has

finished communicating with the slave, it issues a STOP

condition by transitioning SDA from low to high while SCL

is high. The bus is then free for another transmission.

Acknowledge

The acknowledge signal is used in handshaking between

transmitter and receiver to indicate that the last byte of

data was received. The transmitter always releases the

SDA line during the acknowledge clock pulse. When the

slave is the receiver, it pulls down the SDA line so that it

remains LOW during this pulse to acknowledge receipt

of the data. If the slave fails to acknowledge by leaving

SDA high, then the master may abort the transmission by

generatingaSTOPcondition.Whenthemasterisreceiving

data from the slave, the master pulls down the SDA line

during the clock pulse to indicate receipt of the data. After

the last byte has been received the master leaves the SDA

line HIGH (not acknowledge) and issues a stop condition

to terminate the transmission.

2

I C Device Addressing

Twenty-seven distinct bus addresses are available using

three3-stateaddresspins,ADR0-ADR2.Table1showsthe

correspondence between pin states and addresses. Note

that address bits 7 and 6 are internally configured to 10. In

addition, the LTC4281 responds to two special addresses.

Address 0xBE is a mass write address that writes to all

LTC4281s, regardless of their individual address settings.

Mass write can be disabled by setting bit 4 in CONTROL

register 0x00 to zero. Address (0x19) is the SMBus Alert

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Write Protocol

2

results while the I C interface is busy. As long as the ADC

data is read out in a single transaction, all the data will

be synchronized. A STOP condition frees the LTC4281 to

update the ADC result registers. Status and fault registers

are updated in real time.

ThemasterbeginscommunicationwithaSTARTcondition

followed by the seven bit slave address and the R/W bit set

to zero, as shown in Figure 12. The addressed LTC4281

acknowledges this and then the master sends a command

byte indicating which internal register the master wishes

towrite. TheLTC4281acknowledgesthisandthenlatches

the command byte into its internal Register Address

pointer. The master then delivers the data byte and the

LTC4281 acknowledges once more and writes the data to

the destination register specified by the Register Address

pointer, then the pointer is incremented. If the Master

sends additional bytes, they are written sequentially to the

registers in order of their binary addresses. The transmis-

sion is ended when the master sends a STOP condition.

Alert Response Protocol

When any of the fault bits in FAULT_LOG register 0x04

are set, an optional bus alert is generated if the appropri-

ate bit in the ALERT register 0x02 is also set. If an alert is

enabled, the corresponding fault causes the ALERT pin to

pull low. After the bus master controller broadcasts the

Alert Response Address, the LTC4281 responds with its

address on the SDA line and then releases ALERT when

it has successfully completed transmitting its address as

shown in Figure 16.

Read Protocol

The ALERT signal is not pulled low again until the FAULT

register 0x04 indicates a different fault as occurred or

the original fault is cleared and it occurs again. Note that

this means repeated or continuing faults do not generate

alerts until the associated FAULT_LOG register bit has

been cleared.

ThemasterbeginsareadoperationwithaSTARTcondition

followed by the seven bit slave address and the R/W bit set

to zero, as shown in Figure 15. The addressed LTC4281

acknowledges this and then the master sends a command

byte which indicates which internal register the master

wishes to read. The LTC4281 acknowledges this and then

latches the command byte into its internal Register Ad-

dress pointer. The master then sends a repeated START

condition followed by the same seven bit address with the

R/W bit now set to one. The LTC4281 acknowledges and

sends the contents of the requested register. As long as

the master acknowledges the transmitted data byte the

internal register address pointer is incremented and the

next register byte is sent. The transmission is ended when

the master sends a STOP condition.

EEPROM

TheLTC4281hasanonboardEEPROMtoallownonvolatile

configurationandfaultlogging.TheEEPROMregistersare

denoted by ‘EE’ in the first column of register Table 2. The

EEPROM registers may be read and written like any other

register except that the EEPROM takes about 2ms to write

data. While the EEPROM is writing, the EEPROM_BUSY

bit, bit 2 in STATUS register 0x1F is set to 1. While the

2

EEPROM is busy the I C interface will NACK commands

to read or write to EEPROM registers, but other registers

may be accessed during this time. When the EEPROM

finishes writing, the EEPROM_BUSY bit will reset and the

EEPROM_DONEbit, bit7inFAULT_LOGregister0x04will

beset.IfconfiguredtogenerateanalertonEEPROM_DONE,

Bit 7 in ALERT register 0x02), the ALERT pin will pull low

Data Synchronization

TheADCmeasurementsandsubsequentcomputedvalues

are 16-48 bits wide, but must be read over the I C in 8-bit

segments. To ensure that the words are not updated in

the middle of reading them, the LTC4281 latches these

2

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to alert the host that the EEPROM write has finished and

the LTC4281 EEPROM is ready to receive another byte.

and overwriting the EEPROM. A 4.7µF capacitor on the

INTV pin allows the LTC4281 to operate and log faults

CC

to the EEPROM if input power is lost. A 1uF capacitor may

be used in applications that do not require fault logging.

When the LTC4281 comes out of UVLO or receives a

REBOOT command the contents of the EEPROM are

copiedtothecorrespondingoperatingregisters,whichare

offset from the EEPROM register addresses by 0x20. The

SCRATCH_PAD registers, 0x4C-0x4F, are free for general

purpose use, such as storing fault history, serial numbers

or calibration data. The factory default EEPROM contents

make the LTC4281 behave similar to the LTC4215 to ease

designmigrationandprovideausefuldesignstartingpoint.

2

The WP pin prevents I C writes to the EEPROM when

high. Attempts to write to the EEPROM while WP is high

will result in a NACK and no action. Usually the WP pin

is tied high through a resistor with a probe pad to allow

it to be pulled low manually, it may also be tied low to

enable writes all the time or connected to a GPIO pin or

other logic-level signal to allow software control of WP.

The EEPROM may still be read when WP is high. The

FAULT_LOG registers of the EEPROM will still log faults

when the WP pin is high. Linear Technology can provide

programmed parts that have WP locked in a high state to

make it impossible to change the default configuration by

any means. Please contact the factory.

TheFAULT_LOGandADC_ALERT_LOGregisters,0x04and

0x05,arenotloadedfromtheEEPROMatboot.Insteadthe

register data is copied into the EEPROM when any of the

bits in the log registers transition high and fault logging is

enabled in ADC_CONTROL register 0x1D. Fault logging is

disabled by default after boot so that logged faults are not

inadvertentlyclearedbypoweringupwithafaultcondition

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Table 1. LTC4281 Addressing

DEVICE

DESCRIPTION ADDRESS*

0 = Write

1 = Read

BINARY DEVICE ADDRESS

LTC4281 ADDRESS PINS

h

7

1

0

1

6

0

5

1

0

1

4

1

0

1

0

1

3

1

0

1

0

1

0

1

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ADR2

X

ADR1

X

ADR0

X

Mass Write

0xBE

0x19

0x80

0x82

0x84

0x86

0x88

0x8A

0x8C

0x8E

0x90

0x92

0x94

0x96

0x98

0x9A

0x9C

0x9E

0xA0

0xA2

0xA4

0xA6

0xA8

0xAA

0xAC

0xAE

0xB0

0xB2

0xB4

0

1

X

Alert Response

X

L

NC

H

L

NC

H

L

NC

L

H

L

NC

H

L

NC

H

NC

H

L

NC

H

NC

L

H

L

NC

H

L

NC

H

L

H

NC

H

NC

L

H

L

H

L

NC

H

L

H

L

NC

H

L

H

L

* 8-bit hexadecimal address with LSB R/W bit = 0.

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Table 2

READ/

WRITE

DATA

REGISTER NAME

CONTROL

COMMAND BYTE DESCRIPTION

LENGTH

DEFAULT

0xBB02

0x0000

0x00

0xFF

0x00-0x01

0x02-0x03

0x04

Configures On/Off Behavior

RW

R

16 Bits

8 Bits

48 Bits

32 Bits

8 Bits

16 Bits

8 Bits

16 Bits

ALERT

Enables Alerts

FAULT_LOG

Logs Faults

ADC_ALERT_LOG

FET_BAD_FAULT_TIME

GPIO_CONFIG

0x05

Logs ADC Alerts

0x06

Selects FET-BAD Fault Timeout

Configures GPIO Outputs

Threshold For Min Alarm on VSOURCE

Threshold for Max Alarm on VSOURCE

Threshold for Min Alarm on VGPIO

Threshold for Max Alarm on VGPIO

Threshold for Min Alarm on VSENSE

Threshold for Max Alarm on VSENSE

Threshold for Min Alarm on POWER

Threshold for Max Alarm on POWER

Division Factor for External Clock

Adjusts Current Limit Value

Meters Energy Delivered to Load

Counts Power Delivery Time

Clear Alerts, Force ALERT Pin Low

Control ADC, Energy Meter

Fault and Pin Status

0x07

0x00

0xFF

VGPIO_ALARM_MIN

VGPIO_ALARM_MAX

VSOURCE_ALARM_MIN

VSOURCE_ALARM_MAX

VSENSE_ALARM_MIN

VSENSE_ALARM_MAX

POWER_ALARM_MIN

POWER_ALARM_MAX

CLOCK_DIVIDER

0x08

0x09

0x0A

0x00

0xFF

0x0B

0x0C

0x00

0xFF

0x0D

0x0E

0x00

0xFF

0x0F

0x10

0x08

0x96

0x000000

0x0000

0x00

N/A

ILIM_ADJUST

0x11

ENERGY

0x12-0x17

0x18-0x1B

0x1C

TIME_COUNTER

ALERT_CONTROL

ADC_CONTROL

0x1D

STATUS

0x1E-0x1F

0x20-0x21

0x22-0x23

0x24

EE_CONTROL

EEPROM Default

RW

0xBB02

0x0000

0x00

0xFF

EE_ALERT

EEPROM Default

EE_FAULT

EEPROM Default

EE_ADC_ALERT_LOG

EE_FET_BAD_FAULT_TIME

EE_GPIO_CONFIG

EE_VGPIO_ALARM_MIN

EE_VGPIO_ALARM_MAX

EE_VSOURCE_ALARM_MIN

EE_VSOURCE_ALARM_MAX

EE_VSENSE_ALARM_MIN

EE_VSENSE_ALARM_MAX

EE_POWER_ALARM_MIN

EE_POWER_ALARM_MAX

EE_CLOCK_DECIMATOR

EE_ILIM_ADJUST

VGPIO

0x25

EEPROM Default

0x26

EEPROM Default

0x27

EEPROM Default

0x00

0xFF

0x28

EEPROM Default

0x29

EEPROM Default

0x2A

EEPROM Default

0x00

0xFF

0x2B

EEPROM Default

0x2C

EEPROM Default

0x00

0xFF

0x2D

EEPROM Default

0x2E

EEPROM Default

0x00

0xFF

0x2F

EEPROM Default

0x30

EEPROM Default

0x08

0x96

N/A

0x31

EEPROM Default

0x34-0x35

0x36-0x37

0x38-0x39

Most Recent ADC Result for VGPIO

Min ADC Result for VGPIO

Max ADC Result for VGPIO

VGPIO_MIN

N/A

VGPIO_MAX

N/A

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Table 2

READ/

WRITE

DATA

REGISTER NAME

VSOURCE

COMMAND BYTE DESCRIPTION

LENGTH

DEFAULT

N/A

0x3A-0x3B

0x3C-0x3D

0x3E-0x3F

0x40-0x41

0x42-0x43

0x44-0x45

0x46-0x47

0x48-0x49

0x4A-0x4B

0x4C-0x4F

ALL OTHERS

Most Recent ADC Result for VSOURCE

RW

16 Bits

32 Bits

VSOURCE_MIN

VSOURCE_MAX

VSENSE

Min ADC Result for VSOURCE

Max ADC Result for VSOURCE

Most Recent ADC Result for VSENSE

Min ADC Result for VSENSE

N/A

VSENSE_MIN

VSENSE_MAX

POWER

N/A

Max ADC Result for VSENSE

N/A

Most Recent ADC Result for POWER

Min ADC Result for POWER

N/A

POWER_MIN

POWER_MAX

EE_SCRATCH

RESERVED

N/A

Max ADC Result for POWER

N/A

Spare EEPROM memory

0x00000000

N/A

Reserved for Future Expansion, Do Not Write

DeTaileD i²c coMManD regisTer DescripTions

CONTROL Registers (R/W)

Byte 1 (0 x0 0 )

BIT(S) NAME

DEFAULT OPERATION

B[7]

ON_FAULT_MASK

1

If 1, blocks the ON pin from clearing the FAULT register to prevent repeated logged faults and

alerts.

B[6]

ON_DELAY

0

If 1, a 50ms debounce is applied to the ON pin commanding the part to turn on, if 0 the part turns

on immediately.

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

ON/ENB

1

0

1

The ON pin is active high when this bit is a 1 and active low when this bit is a 0.

2

MASS_WRITE_ENABLE

FET_ON

Writing a 1 enables MASS_WRITE to all LTC4281s on the I C bus.

Writing a 1 to this register turns the part on, writing a 0 turns off, overriding the ON pin.

Writing a 1 enables the part to auto-retry 256 timer cycles after an OC fault.

Writing a 1 enables the part to auto-retry 50ms after an UV fault.

OC_AUTORETRY

UV_AUTORETRY

OV_AUTORETRY

Writing a 1 enables the part to auto-retry 50ms after an OV fault.

Byte 2 (0 x0 1)

B[7-6] FB_MODE

B[5-4] UV_MODE

B[3-2] OV_MODE

B[1-0] VIN_MODE

00

10

Selects threshold for POWER_GOOD, 00 = external, 01 = 5%, 10 = 10%, 11 = 15%.

Selects threshold for UV faults, 00 = external, 01 = 5%, 10 = 10%, 11 = 15%.

Selects threshold for OV faults, 00 = external, 01 = 5%, 10 = 10%, 11 = 15%.

Selects operating range for UV/OV/FB and ADC: 00 = 3.3V, 01 = 5V, 10 = 12V, 11 = 24V.

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DeTaileD i²c coMManD regisTer DescripTions

ALERT Registers (R/W)

Byte 1 (0 x0 2)

BIT(S) NAME

DEFAULT OPERATION

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

EEPROM_DONE_ALERT

0

Writing a 1 generates alerts when the EEPROM finishes writing.

FET_BAD_FAULT_ALERT

FET_SHORT_ALERT

ON_ALERT

Writing a 1 generates alerts when FET-BAD faults are produced.

Writing a 1 generates alerts when the ADC detects FET-short faults.

Writing a 1 generates alerts when the ON pin changes state.

Writing a 1 generates alerts when power-bad faults are produced.

Writing a 1 generates alerts when overcurrent faults are produced.

Writing a 1 generates alerts when undervoltage faults are produced.

Writing a 1 generates alerts when overvoltage faults are produced.

PB_ALERT

OC_ALERT

UV_ALERT

OV_ALERT

Byte 2 (0 x0 3)

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

POWER_ALARM_HIGH

0

Writing a 1 generates alerts when the ADC result is above the POWER_ALARM_MAX threshold.

Writing a 1 generates alerts when the ADC result is below the POWER_ALARM_MIN threshold.

Writing a 1 generates alerts when the ADC result is above the VSENSE_ALARM_MAX threshold.

Writing a 1 generates alerts when the ADC result is below the VSENSE_ALARM_MIN threshold.

Writing a 1 generates alerts when the ADC result is above the VSOURCE_ALARM_MAX threshold.

Writing a 1 generates alerts when the ADC result is below the VSOURCE_ALARM_MIN threshold.

Writing a 1 generates alerts when the ADC result is above the VGPIO_ALARM_MAX threshold.

Writing a 1 generates alerts when the ADC result is below the VGPIO_ALARM_MIN threshold.

POWER_ALARM_LOW

VSENSE_ALARM_HIGH

VSENSE_ALARM_LOW

VSOURCE_ALARM_HIGH

VSOURCE_ALARM_LOW

VGPIO_ALARM_HIGH

VGPIO_ALARM_LOW

FAULT_LOG Register (R/W)

Byte 1 (0 x0 4)

BIT(S) NAME

DEFAULT OPERATION

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

EEPROM_DONE

FET_BAD_FAULT

FET_SHORT_FAULT

ON_FAULT

0

Set to 1 when the EEPROM finishes a write.

Set to 1 when a FET-BAD fault occurs.

Set to 1 when the ADC detects a FET-short fault.

Set to 1 by the ON pin changing state.

Set to 1 by a power-bad fault occurring.

Set to 1 by an overcurrent fault occurring.

Set to 1 by an undervoltage fault occurring.

Set to 1 by an overvoltage fault occurring.

POWER_BAD_FAULT

OC_FAULT

UV_FAULT

OV_FAULT

ADC_ALERT_LOG Register (R/W)

Byte 1 (0 x0 5)

BIT(S) NAME

DEFAULT OPERATION

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

POWER_ALARM_HIGH

POWER_ALARM_LOW

VSENSE_ALARM_HIGH

VSENSE_ALARM_LOW

VSOURCE_ALARM_HIGH

VSOURCE_ALARM_LOW

GPIO_ALARM_HIGH

0

Set to 1when the ADC makes a measurement above the POWER_ALARM_MAX threshold.

Set to 1when the ADC makes a measurement below the POWER_ALARM_MIN threshold.

Set to 1when the ADC makes a measurement above the VSENSE_ALARM_MAX threshold.

Set to 1when the ADC makes a measurement below the VSENSE_ALARM_MIN threshold.

Set to 1when the ADC makes a measurement above the VSOURCE_ALARM_MAX threshold.

Set to 1when the ADC makes a measurement below the VSOURCE_ALARM_MIN threshold.

Set to 1when the ADC makes a measurement above the VGPIO_ALARM_MAX threshold.

Set to 1when the ADC makes a measurement below the VGPIO_ALARM_MIN threshold.

GPIO_ALARM_LOW

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DeTaileD i²c coMManD regisTer DescripTions

FET_BAD_FAULT_TIME Register (R/W)

Byte 1 (0 x0 6)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] FET_BAD_FAULT_TIMEOUT

255

Selects the wait time for a FET-bad fault as a binary integer in ms. 0x00 disables.

GPIO_CONFIG Register (R/W)

Byte 1 (0 x0 7)

BIT(S) NAME

DEFAULT OPERATION

B[7]

B[6]

GPIO3_PD

GPIO2_PD

0

A 1 in this value will make the GPIO3 pin pull low, a 0 will make the pin high impedance

A 1 in this value will make the GPIO2 pin pull low, a 0 will make the pin high impedance

B[5-4] GPIO1_CONFIG

00

FUNCTION

B[5]

B[4] GPIO1 PIN

Power Good

0

1

0

1

0

1

GPIO1 = Power Good

Power Bad

GPIO1 = Power Bad

GPIO1 = B[3]

General Purpose Output

General Purpose Input

GPIO1 = High-Z

B[3]

B[2]

B[1]

B[0]

GPIO1_OUTPUT

0

Output data bit to GPIO1 pin when configured as output (1 = high impedance, 0 = pull low)

Writing a 1 generates alert when the ADC finishes making a measurement

ADC_CONV_ALERT

STRESS_TO_GPIO2

METER_OVERFLOW_ALERT

Writing a 1 generates alert GPIO2 to pull low when the MOSFET is dissipating power (stress)

Writing a 1 generates alert when the energy meter accumulator or time counter overflows

VGPIO_ALARM_MIN (Register R/W)

Byte 1 (0 x0 8)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] VGPIO_ALARM_MIN

0x00

Selects the maximum ADC measurement value that generates a VGPIO_MIN_ALARM

VGPIO_ALARM_MAX (Register R/W)

Byte 1 (0 x0 9)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] VGPIO_ALARM_MAX

0xFF

Selects the minimum ADC measurement value that generates a VGPIO_MAX_ALARM

VSOURCE_ALARM_MIN (Register R/W)

Byte 1 (0 x0 A)

BIT(S)

NAME

DEFAULT OPERATION

B[7-0]

VSOURCE_ALARM_MIN

0x00

Selects the maximum ADC measurement value that generates a VSOURCE_MIN_ALARM

VSOURCE_ALARM_MAX (Register R/W)

Byte 1 (0 x0 B)

BIT(S)

NAME

DEFAULT OPERATION

0xFF Selects the minimum ADC measurement value that generates a VSOURCE_MAX_ALARM

B[7-0]

VSOURCE_ALARM_MAX

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DeTaileD i²c coMManD regisTer DescripTions

VSENSE_ALARM_MIN Register (R/W)

Byte 1 (0 x0 C)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] VSENSE_ALARM_MIN

0x00

Selects the maximum ADC measurement value that generates a VSENSE_MIN_ALARM

VSENSE_ALARM_MAX (Register R/W)

Byte 1 (0 x0 D)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] VSENSE_ALARM_MAX

0xFF

Selects the minimum ADC measurement value that generates a VSENSE_MAX_ALARM

POWER_ALARM_MIN (Register R/W)

Byte 1 (0 x0 E)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] POWER_ALARM_MIN

0x00

Selects the maximum ADC measurement value that generates a POWER_MIN_ALARM

POWER_ALARM_MAX (Register R/W)

Byte 1 (0 x0 F)

BIT(S) NAME

DEFAULT OPERATION

B[7-0] POWER_ALARM_MAX

0xFF

Selects the minimum ADC measurement value that generates a POWER_MAX_ALARM

CLOCK_DIVIDER (Register R/W)

Byte 1 (0 x10 )

BIT(S)

NAME

DEFAULT OPERATION

B[7]

COULOMB_METER

0

Setting this bit to a 1 configures the Energy meter to accumulate current instead of power,

making it a Coulomb meter

B[6]

TICK_OUT

0

Configures the CLKOUT pin to output the internal time count (conversion time) as an open-drain

output

B[5]

INT_CLK_OUT

0

Configures the CLKOUT pin to output the internal system clock as an open-drain output

B[4-0]

CLOCK_DIVIDER

01000

The clock frequency input on the CLKIN pin gets divided by twice this integer to produce the

system clock at the target frequency of 250kHz. Code 00000 passes the clock without division.

4281f

34

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

ILIM_ADJUST Register (R/W)

Byte 1 (0 x11)

BIT(s)

NAME

Default Operation

100 Selects the current limit values [mV]

B[7-5]

ILIM_ADJUST

B[7]

0

B[6]

0

B[5]

0

FB = LOW

3.75

FB = HIGH FAST COMPARATOR

12.5

15.625

18.75

21.875

25

38

47

56

66

75

84

94

103

0

1

4.6875

5.625

0

1

0

1

6.5625

7.5

1

0

1

0

1

8.4375

9.375

28.125

31.25

34.375

1

0

1

10.3125

B[4-3]

FOLDBACK_MODE

10

Selects the voltage range for the current limit foldback profile: 00 = 3.3V, 01 = 5V, 10 = 12V,

11 = 24V

B[2]

B[1]

B[0]

VSOURCE/VDD

GPIO_MODE

16_BIT

1

0

Setting this bit to a 1 makes the ADC monitor the SOURCE voltage, 0 for V

Setting this bit to a 1 makes the ADC monitor GPIO2, 0 for GPIO3

DD

Setting this bit to a 1 will make the ADC operate in 16-bit mode, 0 will make the ADC operate in

12-bit mode

ENERGY REGISTER (R/W)

Byte 1-6 (0 x12-0 x17)

BIT(S)

NAME

DEFAULT OPERATION

B[48-0] ENERGY_METER

0x000000 Metered energy value

TIME_COUNTER REGISTER (R/W)

Byte 1-4 (0 x18-0 x1B)

BIT(S)

NAME

DEFAULT OPERATION

B[32-0] TIME_COUNTER

0x0000 Counts the number of conversion cycles that power measurements have been accumulated in

the energy meter

ALERT_CONTROL REGISTER (R/W)

Byte 1 (0 x1C)

BIT(S)

NAME

DEFAULT OPERATION

B[7]

ALERT_GENERATED

0

This bit is set to 1 when an alert is generated. It must be manually cleared by writing a 0 to it via

2

I C. This bit can be set via I C to simulate an alert

B[6]

ALERT_PD

RESERVED

0

When this bit is set to 1 the ALERT pin pulls low as a general purpose output low

B[5-0]

000000 Always read as 0

4281f

35

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

ADC_CONTROL Register (R/W)

Byte 1 (0 x1D)

BIT(S)

NAME

DEFAULT OPERATION

B[7]

REBOOT

0

Writing a 1 to this bit will cause the LTC4281 to turn off and reboot to the EEPROM default

configuration and restart, if configured to do so, after 3.2s.

B[6]

METER_RESET

0

Writing a 1 to this bit resets the energy meter accumulator and time counter and holds them

reset until this bit is cleared.

B[5]

B[4-3]

B[2]

METER_HALT

0

00

0

Writing a 1 to this bit stops the energy meter and time counter.

Always read as 0.

RESERVED

FAULT_LOG_ENABLE

Setting this bit to 1 enables registers 0x04 and 0x05 to be written to the EEPROM when a fault

bit transitions high.

B[1]

B[0]

GATELOW

ADC_HALT

GATELOW Gives the status of the GATE pin 0 if the GATE pin is higher than 8V (Read Only)

0

Single shot mode, writing to this register again with HALT = 1 will allow the ADCs to make a

single conversion and then stop, clearing this bit allows the ADCs to run continuously

STATUS Register (R)

Byte 1 (0 x1E)

BIT(S)

B[7]

NAME

OPERATION

ON_STATUS

A 1 indicates if the MOSFETs are commanded to turn on

B[6]

FET_BAD_COOLDOWN_STATUS

A 1 indicates that an FET-BAD fault has occurred and the part is going through a

cool-down cycle

B[5]

B[4]

B[3]

B[2]

FET_SHORT_PRESENT

ON_PIN_STATUS

A 1 indicates that the ADCs have detected a shorted MOSFET

A 1 indicates the status of the ON pin, 1 = high

POWER_GOOD_STATUS

OC_COOLDOWN_STATUS

A 1 indicates if the output voltage is greater than the power good threshold

A 1 indicates that an overcurrent fault has occurred and the part is going through a

cool-down cycle.

B[1]

B[0]

UV_STATUS

OV_STATUS

A 1 indicates that the input voltage is below the undervoltage threshold

A 1 indicates that the input voltage is above the overvoltage threshold

Byte 2 (0 x1F)

B[7]

GPIO3_STATUS

GPIO2_STATUS

GPIO1_STATUS

ALERT_STATUS

EEPROM_BUSY

A 1 indicates that the GPIO3 pin is above its input threshold

A 1 indicates that the GPIO2 pin is above its input threshold

A 1 indicates that the GPIO1 pin is above its input threshold

A 1 indicates that the ALERT pin is above its input threshold

B[6]

B[5]

B[4]

B[3]

This bit is high whenever the EEPROM is writing, and indicates that the EEPROM is not available

until the write is complete

B[2]

ADC_IDLE

This bit indicates that the ADC is idle. It is always read as 0 when the ADCs are free running, and

will read a 1 when the ADC is idle in single shot mode

B[1]

B[0]

TICKER_OVERFLOW_PRESENT

METER_OVERFLOW_PRESENT

A 1 indicates that the tick counter has overflowed

A 1 indicates that the energy meter accumulator has overflowed

4281f

36

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

EE_CONTROL Non-Volatile Register (R/W)

Byte 1 (0 x20 )

BIT(S)

B[7-4]

NAME

DEFAULT OPERATION

Same as CONTROL 0x00

10111

1

Stores default state for CONTROL byte 1 (0x00) in nonvolatile memory

B[3]

Sets the default ON state. 0 = OFF, 1 = ON-pin state.

Sets the default auto-retry behavior

B[2-0]

011

Byte 2 (0 x21)

B[7-0]

Same as CONTROL 0x01

0x02

Stores default state for CONTROL byte 2 (0x01) in nonvolatile memory

EE_ALERT Non-Volatile Register (R/W)

Byte 1 (0 x22)

BIT(S)

B[7-0]

NAME

DEFAULT OPERATION

Same as ALERT 0x02

0x00

Stores default state for ALERT byte 1 (0x02) in nonvolatile memory

Byte 2 (0 x23)

B[7-0]

Same as ALERT 0x03

0x00

Stores default state for ALERT byte 2 (0x03) in nonvolatile memory

EE_FAULT_LOG Non-Volatile Register (R/W)

Byte 1 (0 x24)

BIT(S)

NAME

DEFAULT OPERATION

B[7-0]

Same as FAULT_LOG

0x00

When a new fault occurs, the contents of FAULT_LOG register (0x04) are copied to this

nonvolatile memory location

EE_ADC_ALERT_LOG Non-Volatile Register (R/W)

Byte 1 (0 x25)

BIT(S)

NAME

DEFAULT OPERATION

B[7-0]

Same as ADC_ALERT_LOG

0x00

When a new ADC Alert is generated, the contents of ADC_ALERT_LOG register (0x05) are

copied to this nonvolatile memory location

EE_FET_BAD_FAULT_TIME Non-Volatile Register (R/W)

Byte 1 (0 x26)

BIT(S)

NAME

DEFAULT OPERATION

0xFF Stores default state for the FET_BAD_FAULT_TIME register (0x06) in nonvolatile memory

B[7-0]

Same as FET_BAD_FAULT_TIME

EE_GPIO_CONFIG Non-Volatile Register (R/W)

Byte 1 (0 x27)

BIT(S)

NAME

DEFAULT OPERATION

0x00 Stores default state for GPIO_CONFIG register (0x07) in nonvolatile memory

B[7-0]

Same as GPIO_CONFIG

EE_VGPIO_ALARM_MIN Non-Volatile Register (R/W)

Byte 1 (0 x28)

BIT(S)

NAME

DEFAULT OPERATION

0x00 Stores default state for VGPIO_ALARM_MIN register (0x08) in nonvolatile memory

B[7-0]

VGPIO_ALARM_MIN

4281f

37

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

EE_VGPIO_ALARM_MAX Non-Volatile Register (R/W)

Byte 1 (0 x29)

BIT(s)

NAME

Default

Operation

B[7-0]

VGPIO_ALARM_MAX

0xFF

Stores default state for VGPIO_ALARM_MAX register (0x09) in nonvolatile memory

EE_VSOURCE_ALARM_MIN Non-Volatile Register (R/W)

Byte 1 (0 x2A)

BIT(s)

NAME

Default

Operation

B[7-0]

VSOURCE_ALARM_MIN

0x00

Stores default state for VSOURCE_ALARM_MIN register (0x0A) in nonvolatile memory

EE_VSOURCE_ALARM_MAX Non-Volatile Register (R/W)

Byte 1 (0 x2B)

BIT(s)

NAME

Default

Operation

B[7-0]

VSOURCE_ALARM_MAX

0xFF

Stores default state for VSOURCE_ALARM_MAX register (0x0B) in nonvolatile memory

EE_VSENSE_ALARM_MIN Non-Volatile Register (R/W)

Byte 1 (0 x2C)

BIT(S)

NAME

DEFAULT OPERATION

0x00 Stores default state for VSENSE_ALARM_MIN register (0x0C) in nonvolatile memory

B[7-0]

VSENSE_ALARM_MIN

EE_VSENSE_ALARM_MAX Non-Volatile Register (R/W)

Byte 1 (0 x2D)

BIT(S)

NAME

DEFAULT OPERATION

0xFF Stores default state for VSENSE_ALARM_MAX register (0x0D) in nonvolatile memory

B[7-0]

VSENSE_ALARM_MAX

EE_POWER_ALARM_MIN Non-Volatile Register (R/W)

Byte 1 (0 x2E)

BIT(S)

NAME

DEFAULT OPERATION

0x00 Stores default state for POWER_ALARM_MIN register (0x0E) in nonvolatile memory

B[7-0]

POWER_ALARM_MIN

EE_POWER_ALARM_MAX Non-Volatile Register (R/W)

Byte 1 (0 x2F)

BIT(S)

NAME

DEFAULT OPERATION

0xFF Stores default state for POWER_ALARM_MAX register (0x0F) in nonvolatile memory

B[7-0]

POWER_ALARM_MAX

EE_CLOCK_DIVIDER Non-Volatile Register (R/W)

Byte 1 (0 x30 )

BIT(S)

NAME

DEFAULT OPERATION

0x08 Stores default state for CLOCK_DIVIDER register (0x10) in nonvolatile memory

B[7-0]

Same as CLOCK_DIVIDER

4281f

38

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

EE_ILIM_ADJUST Non-Volatile Register (R/W)

Byte 1 (0 x31)

BIT(S)

NAME

DEFAULT OPERATION

0x96 Stores default state for ILIM_ADJUST register (0x11) in nonvolatile memory

B[7-0]

Same as ILIM_ADJUST

Reserved

Byte 1 (0 x32)

BIT(S)

NAME

OPERATION

B[7-0]

Reserved

Always read as 0x00

Byte 2 (0 x33)

B[7-0]

Reserved

Always read as 0x00

VGPIO

Byte 1 (0 x34)

BIT(S)

NAME

OPERATION

B[7-0]

VGPIO_MSB

Stores the MSBs for the most recent VGPIO measurement result

Byte 2 (0 x35)

B[7-0]

VGPIO_LSB

Stores the LSBs for the most recent VGPIO measurement result

VGPIO_MIN

Byte 1 (0 x36)

BIT(S)

NAME

OPERATION

B[7-0]

VGPIO_MIN_MSB

Stores the MSBs for the smallest VGPIO measurement result

Byte 2 (0 x37)

B[7-0]

VGPIO_MIN_LSB

Stores the LSBs for the smallest VGPIO measurement result

VGPIO_MAX

Byte 1 (0 x38)

BIT(S)

NAME

OPERATION

B[7-0]

VGPIO_MAX_MSB

Stores the MSBs for the largest VGPIO measurement result

Byte 2 (0 x39)

B[7-0]

VGPIO_MAX_LSB

Stores the LSBs for the largest VGPIO measurement result

VSOURCE

Byte 1 (0 x3A)

BIT(S)

NAME

OPERATION

B[7-0]

VSOURCE_MAX_MSB

Stores the MSBs for the most recent VSOURCE measurement result

Byte 2 (0 x3B)

B[7-0]

VSOURCE_MAX_LSB

Stores the LSBs for the most recent VSOURCE measurement result

4281f

39

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

VSOURCE_MIN Register (R/W)

Byte 1 (0 x3C)

BIT(S)

B[7-0]

NAME

OPERATION

VSOURCE_MIN_MSB

Stores the MSBs for the smallest VSOURCE measurement result

Byte 2 (0 x3D)

B[7-0]

VSOURCE_MIN_LSB

Stores the LSBs for the smallest VSOURCE measurement result

VSOURCE_MAX Register (R/W)

Byte 1 (0 x3E)

BIT(S)

B[7-0]

NAME

OPERATION

VSOURCE_MAX_MSB

Stores the MSBs for the largest VSOURCE measurement result

Byte 2 (0 x3F)

B[7-0]

VSOURCE_MAX_LSB

Stores the LSBs for the largest VSOURCE measurement result

VSENSE Register (R/W)

Byte 1 (0 x40 )

BIT(S)

B[7-0]

NAME

OPERATION

VSENSE_MSB

Stores the MSBs for the most recent VSENSE measurement result

Byte 2 (0 x41)

B[7-0]

VSENSE_LSB

Stores the LSBs for the most recent VSENSE measurement result

VSENSE_MIN Register (R/W)

Byte 1 (0 x42)

BIT(S)

B[7-0]

NAME

OPERATION

VSENSE_MIN_MSB

Stores the MSBs for the smallest VSENSE measurement result

Byte 2 (0 x43)

B[7-0]

VSENSE_MIN_LSB

Stores the LSBs for the smallest VSENSE measurement result

VSENSE_MAX Register (R/W)

Byte 1 (0 x44)

BIT(S)

B[7-0]

NAME

OPERATION

VSENSE_MAX_MSB

Stores the MSBs for the largest VSENSE measurement result

Byte 2 (0 x45)

B[7-0]

VSENSE_MAX_LSB

Stores the LSBs for the largest VSENSE measurement result

POWER Register (R/W)

Byte 1 (0 x46)

BIT(S)

B[7-0]

NAME

OPERATION

POWER_MSB

Stores the MSBs for the most recent POWER measurement result

Byte 2 (0 x47)

B[7-0]

POWER_LSB

Stores the LSBs for the most recent POWER measurement result

4281f

40

For more information www.linear.com/LTC4281

LTC4281

DeTaileD i²c coMManD regisTer DescripTions

POWER_MIN Register (R/W)

Byte 1 (0 x48)

BIT(S)

B[7-0]

NAME

OPERATION

POWER_MIN_MSB

Stores the MSBs for the smallest POWER measurement result

Byte 2 (0 x49)

B[7-0]

POWER_MIN_LSB

Stores the LSBs for the smallest POWER measurement result

POWER_MAX Register (R/W)

Byte 1 (0 x4A)

BIT(S)

B[7-0]

NAME

OPERATION

POWER_MAX_MSB

Stores the MSBs for the largest POWER measurement result

Byte 2 (0 x4B)

B[7-0]

POWER_MAX_LSB

Stores the LSBs for the largest POWER measurement result

SCRATCH_PAD Non-Volatile Register (R/W)

Byte 1 (0 x4C)

BIT(S)

B[7-0]

NAME

DEFAULT OPERATION

SCRATCH_PAD_1

0x00

Uncommitted nonvolatile memory

Byte 2 (0 x4D)

B[7-0]

SCRATCH_PAD_2

SCRATCH_PAD_3

SCRATCH_PAD_4

Byte 3 (0 x4E)

B[7-0]

Byte 4 (0 x4F)

B[7-0]

4281f

41

For more information www.linear.com/LTC4281

LTC4281

Typical applicaTions

12V, 50 A Backplane Resident Application

R

Q2

S

0.5mΩ

V

OUT

PSMN2R0-30YLE × 2

12V

+

50A ADJUSTABLE

R1

34.8k

1%

R7

30.1k

1%

C

L

R4

10Ω

C

0.1µF

25V

R2

1.18k

1%

R8

F

3.57k

1%

R9

10k

5%

+

–

V

ADC

SENSE1 SENSE1

ADC

GATE

SOURCE

FB

GPIO1

GPIO2

GPIO3

SDAI

SDAO

SCL

DD

UV

OV

R3

3.4k

1%

POWER GOOD

GP

+

C

S

150µF

LTC4281

WP

SDA

NC

ADR0

ADR1

ADR2

SCL

ALERT

ON

ALERT

INTV

CC

TIMER

CLKIN

CLKOUT GND

R10

10k

5%

Y1

4MHz

12V

C4

33pF

C5

33pF

C3

1µF

C

TIMER

15nF

GND

ABLS-4.000MHZ-B4-T

4281 TA02

BACKPLANE PLUG-IN

BOARD

4281f

42

For more information www.linear.com/LTC4281

LTC4281

package DescripTion

Please refer to http://www.linear.com/product/LTC4281#packaging for the most recent package drawings.

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

0.70 ±0.05

4.50 ±0.05

3.10 ±0.05

2.50 REF

2.65 ±0.05

3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

3.50 REF

4.10 ±0.05

5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

2.50 REF

R = 0.115

TYP

R = 0.05

TYP

0.75 ±0.05

4.00 ±0.10

(2 SIDES)

27

28

0.40 ±0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

5.00 ±0.10

(2 SIDES)

3.50 REF

3.65 ±0.10

2.65 ±0.10

(UFD28) QFN 0506 REV B

0.25 ±0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

4281f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

43

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC4281

LTC4281

Typical applicaTion

12V, 65A Application with Optical I²C Isolation and Thermal Shutdown

12V

INTV

CC

R10

3.3k

R9

10k

5V

8

5V

2

6

PRF18BE471QB5RB

3

HCPL-0300 5

INTV

R

Q1

S1

V

0.5mΩ

PSMN2R0-30YLE × 2

OUT

SDA

12V

CC

+

65A ADJUSTABLE

C

L

SMCJ15CA

10Ω

6

5

8

2

+

–

V

ADC SENSE

SENSE ADC GATE SOURCE

FB

DD

HCPL-0300 3

NC

UV

OV

ON

GPIO1

GPIO2

GPIO3

CLKIN

SDAI

SDAO

SCL

ALERT

ADR0

ADR1

ADR2

INTV

LTC4281

CC

NC

R13

3.3k

4.7kΩ

R12

10k

5V

8

2

6

INTV

TIMER

WP

GND

SCL

CC

C3

4.7µF

C

3

HCPL-0300 5

TIMER

15nF

GND

4281 TA02

BACKPLANE PLUG-IN

BOARD

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC4151

High Voltage Current and Voltage Monitor with ADC 7V to 80V Single Voltage/Current Monitor with 12-Bit ADC

2

and I C

LTC4210

LTC4211

Hot Swap Controller

Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6

Operates from 2.5V to 16.5V, Multifunction Current Control, SO-8,

MSOP-8 or MSOP-10

LTC4212

LTC4215

LTC4216

LTC4222

LTC4245

Hot Swap Controller

Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10

Internal 8-Bit ADC, dl/dt Controlled Soft-Start

2

Hot Swap Controller with I C

Hot Swap Controller

Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm × 3mm) DFN

2.9V to 29V Dual Controller with 10-Bit ADC, dl/dt Controlled Soft-Start

Internal 8-Bit ADC, dl/dt Controlled Soft-Start

2

Dual Hot Swap Controller with ADC and I C

Multiple Supply CompactPCI or PCI Express Hot

Swap Controller with I C

2

LTC4260

LTC4261

Positive High Voltage Hot Swap Controller with ADC 8-Bit ADC Monitoring Current and Voltages, Supplies from 8.5V to 80V

2

and I C

Negative High Voltage Hot Swap Controller with

10-Bit ADC Monitoring Current and Voltages, Supplies from

–12V to –100V

2

ADC and I C

2

LTC4280

LTC4282

Hot Swap Controller with I C

Internal 8-Bit ADC, Adjustable Short-Circuit Filter Time

2

Hot Swap Controller with I C

Internal 12-Bit ADC, Power Monitoring, Dual Paths for SOA Sharing

4281f

LT 1215 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

44

For more information www.linear.com/LTC4281

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4281

●

 LINEAR TECHNOLOGY CORPORATION 2015


型号：	LTC4281CUFD#TRPBF
厂家：	Linear
描述：	LTC4281 - Hot Swap Controller with I<sup>2</sup>C Compatible Monitoring; Package: QFN; Pins: 28; Temperature Range: 0°C to 70°C 监控
文件：	总44页 (文件大小：849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4281CUFD#TRPBF [Linear]

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