LTC4307IDD-1-TRPBF [Linear]
High Defi nition Multimedia Interface (HDMI) Level- Shifting 2-Wire Bus Buffer; 高的Defi nition多媒体接口( HDMI )级别 - 转移2线总线缓冲器型号: | LTC4307IDD-1-TRPBF |
厂家: | Linear |
描述: | High Defi nition Multimedia Interface (HDMI) Level- Shifting 2-Wire Bus Buffer |
文件: | 总12页 (文件大小:161K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4307-1
High Definition Multimedia
Interface (HDMI) Level-
Shifting 2-Wire Bus Buffer
U
DESCRIPTIO
FEATURES
■
Bidirectional Buffer for Display Data Channel (DDC)
The LTC4307-1 is a 2-wire bus buffer that provides ca-
pacitance buffering between input and output. The HDMI
specification requires that devices have less than 50pF of
inputcapacitanceontheirDDCbuslines.TheLTC4307-1’s
capacitance buffering feature, in conjunction with its
sub-10pF data and clock input capacitance, allows HDMI
components to easily meet the 50pF requirement and
tolerate high capacitance on the internal bus.
■
Compliant with HDMI Specification Version 1.3
DDC Capacitance Requirement
■
Level Translation Between 3.3V and 5V
■
5ꢀV Human Body Model ꢁSD ꢂrotection
■
60mV Buffer Offset Independent of Load
2
■
Compatible with Non-Compliant V I C Devices
OL
■
■
■
■
■
Isolates Input SDA and SCL Line from Output
TM
2
2
Compatible with I C , I C Fast Mode and SMBus
READY Open-Drain Output
The LTC4307-1 also provides level-shifting between 3.3V
and5VsystemstoallowlowervoltageHDMItransmitters,
receivers and EEPROM to interface to the 5V DDC bus.
READY is an open-drain digital output flag that indicates
whether or not the input and output busses are connected
andcaninterfacetotheHDMIhotplugdetect(HPD)signal.
When driven high, the ENABLE digital input allows the
LTC4307-1 to connect after a stop bit or bus idle. Driving
ENABLE low breaks the connection between the input and
output busses.
High Impedance SDA, SCL Pins for V = 0V
CC
Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP
Packages
U
APPLICATIO S
■
HDMI
■
3.3V/5V Level Translation
■
Capacitance Buffer/Bus Extender
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7032051, 6356140, 6650174
U
TYPICAL APPLICATIO
Rising ꢁdge from Asserted Low
DVD PLAYER (SOURCE)
TV (SINK)
1000
3.3V
5V
0.1μF
800
EEPROM
1.8k 1.8k
10k
μC
10k
LTC4307-1
600
HDMI
CABLE
LOW
OFFSET
HDMI TX
IC
V
CC
<50pF
SDAOUT
SDAIN
SCLIN
HDMI RX
IC
SDAOUT
SDAIN
400
SCLOUT
ENABLE
GND
DDC GROUND
200
0
0
100
200
300
100ns/DIV
400
500
43071 TA01b
600
43071 TA01a
43071fa
1
LTC4307-1
W W U W
ABSOLUTE AXI U RATI GS
(Notes 1, 6)
V
to GND ................................................. –0.3V to 6V
Storage Temperature Range
CC
SDAIN, SCLIN, SDAOUT, SCLOUT,
DFN....................................................–65°C to 125°C
MSOP ................................................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
READY, ENABLE.......................................... –0.3V to 6V
Maximum Sink Current (SDAIN, SCLIN, SDAOUT,
SCLOUT, READY).............................................. 50mA
Operating Temperature Range
MSOP ............................................................... 300°C
LTC4307C ................................................ 0°C to 70°C
LTC4307I .............................................–40°C to 85°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8
7
6
5
V
CC
ENABLE
SCLOUT
SCLIN
GND
1
2
3
4
8 V
CC
7 SDAOUT
6 SDAIN
SDAOUT
SDAIN
9
READY
5 READY
MS8 PACKAGE
8-LEAD PLASTIC MSOP
= 125°C, θ = 200°C/W
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
JA
T
JMAX
= 125°C, θ = 43°C/W
JA
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LꢁAD FRꢁꢁ FINISH
LTC4307CDD-1#PBF
LTC4307IDD-1#PBF
LTC4307CMS8-1#PBF
LTC4307IMS8-1#PBF
TAꢂꢁ AND RꢁꢁL
ꢂART MARKING*
LDBP
ꢂACKAGꢁ DꢁSCRIꢂTION
TꢁMꢂꢁRATURꢁ RANGꢁ
0°C to 70°C
LTC4307CDD-1#TRPBF
LTC4307IDD-1#TRPBF
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LDBP
–40°C to 85°C
0°C to 70°C
LTC4307CMS8-1#TRPBF LTDBN
LTC4307IMS8-1#TRPBF LTDBN
8-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
ꢂARAMꢁTꢁR
CONDITIONS
MIN
TYꢂ
MAX
UNITS
ꢂower Supply
●
●
●
●
V
Positive Supply Voltage
Supply Current
2.3
5.5
11
V
mA
μA
μs
CC
I
I
t
V
V
= 5.5V, V
= V = 0V (Note 5)
SDAOUT
8
CC
CC
SCLOUT
Shutdown Supply Current
Bus Idle Time
= 5.5V, ENABLE = GND, SDA, SCL = 5.5V
900
95
1200
175
SD
CC
55
IDLE
43071fa
2
LTC4307-1
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
ꢂARAMꢁTꢁR
CONDITIONS
MIN
TYꢂ
1.4
0.1
95
MAX
UNITS
V
V
ENABLE Threshold
0.8
2
5
THR_ENABLE
ENABLE
●
I
t
t
t
t
ENABLE Input Current
ENABLE Delay Off-On
ENABLE Delay On-Off
READY Delay Off-On
READY Delay On-Off
READY Output Low Voltage
READY Off Leakage Current
ENABLE from 0V to V
μA
μs
CC
V
V
V
V
= 3.3V (Figure 1)
PLH_EN
CC
= 3.3V (Note 3) (Figure 1)
= 3.3V (Note 3) (Figure 1)
= 3.3V (Note 3) (Figure 1)
10
ns
PHL_EN
CC
10
ns
PLH_READY
PHL_READY
CC
10
ns
CC
●
●
V
I
= 3mA, V = 2.3V
0.4
5
V
OL_READY
OFF_READY
PULLUP
CC
I
V
CC
= READY = 5.5V
0.1
μA
ꢂropagation Delay
t
t
t
SDA/SCL Propagation Delay High to Low
SDA/SCL Propagation Delay Low to High
SDA/SCL Transition Time High to Low
C
V
= 50pF, 2.7k to V on SDA, SCL,
70
10
30
ns
ns
ns
PHL
PLH
FALL
LOAD
CC
CC
= 3.3V (Notes 2, 3) (Figure 1)
C
V
= 50pF, 2.7k to V on SDA, SCL,
CC
= 3.3V (Notes 2, 3) (Figure 1)
LOAD
CC
C
V
= 100pF, 10k to V on SDA, SCL,
300
100
LOAD
CC
CC
= 3.3V (Notes 3, 4) (Figure 1)
Input-Output Connection
●
V
Input-Output Offset Voltage
2.7k to V on SDA, SCL, V = 3.3V,
Driven SDA, SCL = 0.2V
20
60
mV
OS
CC
CC
V
V
SDA, SCL Logic Input Threshold Voltage
Rising Edge
(Note 3)
0.45V
0.55V
50
0.65V
V
THR
CC
CC
CC
SDA, SCL Logic Input Threshold Voltage
Hysteresis
mV
HYS
C
IN
Digital Input Capacitance SDAIN, SDAOUT, (Note 3)
SCLIN, SCLOUT
10
pF
●
●
I
Input Leakage Current
Output Low Voltage
SDA, SCL, Pins
SDA, SCL Pins, I
5
μA
V
LEAK
V
= 4mA,
SINK
0
0.4
OL
SDAIN/SCLIN = 0.2V, V = 2.7V
CC
●
●
2.7k to V on SDA, SCL, V = 3.3V,
120
160
600
205
1.2
mV
V
CC
CC
Driven SDA, SCL = 0.1V
V
Buffer Input Logic Low Voltage
V
CC
= 3.3V
ILMAX
Timing Characteristics
2
f
t
I C Maximum Operating Frequency
(Note 3)
(Note 3)
400
kHz
μs
I2C,MAX
BUF
Bus Free Time Between Stop and Start
Condition
1.3
t
t
t
t
t
Hold Time After (Repeated) Start Condition (Note 3)
100
0
ns
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DATI
SU,DAT
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time Input
(Note 3)
(Note 3)
(Note 3)
(Note 3)
0
0
Data Set-Up Time
100
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Determined by design, not tested in production.
Note 4: Measure points are 0.3 • V and 0.7 • V
.
CC
CC
Note 5: I test performed with connection circuitry active.
CC
Note 6: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 2: See “Propagation Delays” in the Operations section for a
discussion of t
capacitance.
and t
as a function of pull-up resistance and bus
PHL
PLH
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3
LTC4307-1
TIMING DIAGRAMS
ꢁNABLꢁ, CONNꢁCT, RꢁADY Timing
t
t
PLH_READY
PHL_READY
t
PHL_EN
t
PLH_EN
ENABLE
CONNECT
READY
4307 F01a
Rising and Falling ꢂropagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
t
t
FALL
RISE
t
t
t
t
FALL
PLH
PHL
RISE
SDAIN/SCLIN
SDAOUT/SCLOUT
4307 F01b
Figure 1. Timing Diagrams
43071fa
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LTC4307-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, VCC = 3.3V, unless otherwise indicated.
Input-Output High to Low
ꢂropagation Delay vs Temperature
ICC vs Temperature
ISD vs Temperature
100
80
950
900
850
800
750
700
8.3
8.0
7.7
7.4
V
= 5.5V
CC
V
= 5.5V
CC
V
= 5.5V
= 3.3V
CC
V
= 2.3V
CC
V
CC
= 3.3V
60
V
= 3.3V
= 2.3V
CC
CC
7.1
6.8
V
CC
CC
40
V
6.5
6.2
5.9
20
0
V
= 2.3V
0
C
R
= C
= 50pF
OUT
IN
= R
= 10k
50
PULLUPIN
PULLUPOUT
–50
0
25
75
100
–25
0
50
–50
–25
25
50
75
100
–25
–50
75
100
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4307 G03
4307 G02
4307 G01
Input-Output High to Low
ꢂropagation Delay vs COUT
Connection Circuitry VOUT – VIN
(VOS
)
130
120
110
100
90
85
75
65
55
45
C
= 50pF
PULLUPIN
IN
R
= R
= 10k
PULLUPOUT
V
CC
= 5.5V
V
CC
= 3.3V
80
70
60
0
200
400
600
(pF)
800
1000
1
2
3
4
5
6
7
8
9
10
C
OUT
R
(kΩ)
PULLUP
4307 G04
4307 G05
43071fa
5
LTC4307-1
U
U
U
PI FU CTIO S
ꢁNABLꢁ (ꢂin 1): Connection Enable Input. This is a 1.4V
digital threshold input pin. For normal operation pull or tie
ENABLE high. Driving ENABLE below 0.8V isolates SDAIN
from SDAOUT, SCLIN from SCLOUT and asserts READY
low. A rising edge on ENABLE after a fault has occurred
forces a connection between SDAIN, SDAOUT and SCLIN,
pulls low when ENABLE is low, or when the start-up and
connection sequence described in the Operation section
has not been completed. READY goes high when ENABLE
is high and a connection is made. READY can be used to
control the HDMI HPD signal. Connect a pull-up resistor,
typically 10k, from this pin to V to provide the pull-up.
CC
SCLOUT. Connect to V if unused.
This pin can be floated if unused.
CC
SCLOUT (ꢂin 2): Serial Clock Output. Connect this pin to
the clock line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
SDAIN (ꢂin 6): Serial Data Input. Connect this pin to the
data line of a DDC bus. A pull-up resistor should be con-
nected between this pin and a supply voltage greater than
than or equal to the V voltage.
or equal to the V voltage.
CC
CC
SCLIN (ꢂin 3): Serial Clock Input. Connect this pin to
the clock line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
SDAOUT (ꢂin 7): Serial Data Output. Connect this pin to
the data line of a DDC bus. A pull-up resistor should be
connected between this pin and a supply voltage greater
than or equal to the V voltage.
than or equal to the V voltage.
CC
CC
GND (ꢂin 4): Device Ground. Connect this pin to a ground
plane for best results.
V
(ꢂin8):SupplyVoltageInput.Placeabypasscapacitor
CC
of at least 0.01μF close to V for best results.
CC
RꢁADY (ꢂin 5): Connection READY Status Output. The
READYpinisanopen-drainN-channelMOSFEToutputthat
ꢁxposed ꢂad (ꢂin 9, DFN ꢂacꢀage Only): Exposed Pad
may be left open or connected to device ground.
43071fa
6
LTC4307-1
W
BLOCK DIAGRA
Low Offset Level-Shifting 2-Wire Bus Buffer
V
8
7
CC
CONNECT
SDAIN
6
SDAOUT
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
CONNECT
CONNECT
SCLIN
SCLOUT
3
2
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
+
–
CONNECT
+
0.55V
0.55V
CC
CC
0.55V
0.55V
–
CC
CC
+
–
+
–
LOGIC
READY
5
4
CONNECT
ENABLE
+
–
1
1.4V
GND
95μs
DELAY
CONNECT
UVLO
43071 BD
43071fa
7
LTC4307-1
OPERATION
Start-Up
Input to Output Offset Voltage
When a logic low voltage, V
LTC4307-1’s data or clock pins, the LTC4307-1 regulates
the voltage on the opposite data or clock pins to a slightly
higher voltage, typically 60mV above V
When the LTC4307-1 first receives power on its V pin
, is driven on any of the
LOW1
CC
during power-up, it starts in an undervoltage lockout
(UVLO) state, ignoring any activity on the SDA or SCL
pins until V rises above 2V (typ). This is to ensure that
. This offset is
LOW1
CC
the LTC4307-1 does not try to function until it has enough
practically independent of pull-up current (see the Typical
Performance curves).
voltage to do so.
Once the LTC4307-1 comes out of UVLO, it monitors both
2-wire busses for either a stop bit or bus idle condition to
indicate the completion of data transactions. When both
sides are idle or one side has a stop bit condition while the
otherisidle,theinput-to-outputconnectioncircuitryisacti-
vated, joining SDAIN to SDAOUT and SCLIN to SCLOUT.
ꢂropagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. Users must account for differences in the
RC time constants between the two 2-wire busses and
ensure that all system timing specifications are met on
both busses.
Connection Circuitry
Oncetheconnectioncircuitryisactivated,thefunctionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being
2
low. The LTC4307-1 is tolerant of I C bus DC logic low
There is a finite propagation delay through the connection
circuitry for falling waveforms. Figure 2 shows the falling
edge waveforms for V = 5.5V, a 10k pull-up resistor on
2
voltages up to the 0.3V V I C specification.
CC IL
When the LTC4307-1 senses a rising edge on the bus,
it deactivates its pull-down devices for bus voltages as
low as 0.48V. Care must be taken to ensure that devices
participating in clock stretching or arbitration force logic
low voltages below 0.48V at the LTC4307-1 inputs.
CC
eachside,150pFparasiticcapacitanceontheinputbusand
50pF on the output pins. An external N-channel MOSFET
device pulls down the voltage on the side with 150pF
capacitance; the LTC4307-1 pulls down the voltage on the
opposite side with a delay of 80ns. This delay is always
positive and is a function of supply voltage, temperature
and the pull-up resistors and equivalent bus capacitances
onbothsidesofthebus. TheTypicalPerformanceCharac-
teristics section shows propagation delay as a function of
temperatureandvoltagefor10kpull-upresistorsand50pF
equivalent capacitance on both sides of the part. Also, the
SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT release high.
The same is true for SCLIN and SCLOUT. This important
feature ensures that clock stretching, clock synchroniza-
tion, arbitration and the acknowledge protocol always
work, regardless of how the devices in the system are
tied to the LTC4307-1.
t
vsC curveforV =5.5Vshowsthatincreasingthe
PHL
OUT CC
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the capacitances
of the two 2-wire busses isolated from each other. Plac-
ing an LTC4307-1 close to an HDMI port inside an HDMI
transmitter or receiver allows the HDMI device to pass
the capacitance compliance specification. Because of this
isolation,thewaveformsonSDAINandSCLINlookslightly
different than the corresponding waveforms on SDAOUT
and SCLOUT as described here.
INPUT SIDE
OUTPUT SIDE
50pF
150pF
1V/DIV
1V/DIV
43071 F02
200ns/DIV
Figure 2. Input-Output Falling ꢁdge Waveforms
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LTC4307-1
OPERATION
capacitance from 50pF to 150pF results in a t
increase
ꢁNABLꢁ
PHL
from 81ns to 91ns. Larger output capacitances translate
to longer delays (up to 125ns). Users must quantify the
difference in propagation times for a rising edge versus
a falling edge in their systems and adjust setup and hold
times accordingly.
When the ENABLE pin is driven below 0.8V with respect to
the LTC4307-1’s ground, the input 2-wire bus is discon-
nected from the output 2-wire bus and the READY pin is
internally pulled low. When the pin is driven above 2V,
the part waits for data transactions on both 2-wire bus-
ses to be complete (as described in the Start-Up section)
before connecting the two sides. At this time the internal
pull-down on READY releases.
RꢁADY Digital Output
This pin provides a digital flag which is low when either
ENABLE is low or the start-up sequence described earlier
in this section has not been completed. READY goes high
when ENABLE is high and the input and output 2-wire
busses are connected. The pin is driven by an open-drain
pull-down capable of sinking 3mA while holding 0.4V on
LTC4307 and LTC4307-1 Feature Differences
The LTC4307-1 HDMI level-shifting 2-wire bus buffer is
specifically intended for HDMI applications. Features in
the general purpose LTC4307 device that are not required
in HDMI systems have been removed. In addition, level-
shifting functionality has been added to the LTC4307-1
to allow 3.3V HDMI devices to interface safely to the 5V
HDMI DDC bus. See Table 1 for a list of the differences
between the LTC4307 and LTC4307 -1.
the pin. Connect a resistor to V to provide the pull-up.
CC
READY can be used to control the HDMI hot plug detect
(HPD) signal to prevent the possibility of erroneous at-
tempts by the source to contact the sink before the sink
is ready to communicate.
Table 1. Differences Between the LTC4307 and the LTC4307-1
SꢂꢁCIFICATION
LTC4307
LTC4307-1
No
COMMꢁNTS ON LTC4307-1
Pre-charge
Yes
HDMI DDC Lines are Not Hot Swapped
Yes,
Provides Communication Between 3.3V and 5V DDC Busses,
Level Shifting
No
2.2V to 5.5V Protects 3.3V Devices from 5V Supply
Stuck Bus Disconnect and Recovery
Rise Time Accelerators
Yes
Yes
No
No
Stuck Busses, Not an Issue in HDMI Systems
Complies with HDMI Specification Version 1.3 DDC Capacitance
Requirement
APPLICATIONS INFORMATION
Figure 3 shows the LTC4307-1 in a capacitance buffering
application. Due to the LTC4307-1’s capacitance buffering
feature and sub-10pF input capacitance, this application
circuit passes the HDMI 50pF maximum DDC capacitance
specification easily when the LTC4307-1 is located right at
the HDMI connector interface as shown. The capacitance
of the internal bus connected to the SDAIN and SCLIN
pins may be much larger than 50pF, but because of the
LTC4307-1’s capacitance buffering, the internal bus ca-
pacitance is isolated from the HDMI connector.
In HDMI, the sink device pulls the hot plug detect HPD
signal high to tell the source that it is ready to accept
commandsthroughtheDDC.Thissignalcanbecontrolled
through the READY pin of the LTC4307-1 to prevent the
possibility of erroneous attempts by the source to contact
the sink before the sink is ready to return its extended
display identification data (EDID). The READY pin only
goes high after 5V is applied and the LTC4307-1 ENABLE
pin is pulled high by the HDMI receiver IC, a controller in
the sink, or the 5V line itself.
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9
LTC4307-1
APPLICATIONS INFORMATION
Figure 4 shows the LTC4307-1 being used for capacitance
buffering and 5V to 3.3V level shifting. In this application,
the EEPROM is powered by a backup 3.3V supply that is
available when the component is turned off. The EDID in
the EEPROM should be available for reading even when
a component’s power is off.
Although the applications shown in this section are for
HDMI receive channels, the LTC4307-1 can also be used
in HDMI transmit channels with equal success as shown
in the Typical Application on the last page of this data
sheet.
EEPROM
5V
5V
V
CC
SCL SDA GND
C1
0.1μF
R2
R1
1.8k
R4
R5
1k
3.3V
R9
R6
100k
R7
R8
1.8k
47k
LTC4307-1
READY
10k 10k
R10
V
CC
10k 10k
SDA
SCL
HPD
SDAOUT SDAIN
SCLOUT SCLIN
TO
HDMI
TX IC
HDMI CABLE
HDMI
RX IC
ENABLE
GND
DDC
R3
100k
DDC/CEC
GROUND
HDMI SOURCE
(DVD PLAYER)
HDMI SINK
(DIGITAL TV)
43071 F03
Figure 3. The LTC4307-1 in HDMI Capacitance Buffering Application
SWITCHED
3.3V
BACKUP 3.3V
EEPROM
5V
5V
R1
V
CC
SCL SDA
C1
HDMI
RX IC
R2
R3
47k
R4
47k
0.1μF R5
R6
R7
1.8k 1.8k
LTC4307-1
READY
100k 10k 10k
V
CC
SDA
SCL
TO
HDMI
TX IC
SDAIN SDAOUT
SCLIN SCLOUT
HDMI CABLE
ENABLE
GND
DDC
DDC/CEC
GROUND
μC
HDMI SOURCE
(DVD PLAYER)
HDMI REPEATER
(DIGITAL RECEIVER)
43071 F04
Figure 4. The LTC4307-1 in a Level Shifting and Capacitance Buffering HDMI Application with Bacꢀup 3.3V
43071fa
10
LTC4307-1
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6
5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
0.889 ± 0.127
(.035 ± .005)
0.254
(.010)
GAUGE PLANE
5.23
(.206)
MIN
1
2
4
3
3.20 – 3.45
(.126 – .136)
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
SEATING
PLANE
TYP
0.22 – 0.38
0.1016 ± 0.0508
RECOMMENDED SOLDER PAD LAYOUT
(.009 – .015)
(.004 ± .002)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0307 REV F
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
43071fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4307-1
TYPICAL APPLICATION
HDMI Application with LTC4307-1’s ꢂroviding Capacitance Buffering
On Both the Transmit and Receive Channels
DVD PLAYER (SOURCE)
TV (SINK)
5V
3.3V
EEPROM
C1
0.1μF
C2
0.1μF
R1
10k
R2
10k
R3
R4
R5
R6
10k
R7
10k
10k 1.8k 1.8k
LTC4307-1
LTC4307-1
V
V
CC
READY
SDAOUT
SCLOUT
READY
SDAIN
SCLIN
CC
HDMI
CABLE
<50pF
SDAIN
SCLIN
SDAOUT
SCLOUT
HDMI RX
IC
HDMI TX
IC
ENABLE
ENABLE
μC
GND
GND
DDC GROUND
43071 TA02
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LTC4300A-2: Dual Supply Bus Buffer with READY and ACC
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Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
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Address Expansion, GPIO, Software Controlled
2
LTC4303/LTC4304
LTC4305/LTC4306
LTC4307
Hot Swappable 2-Wire Bus Buffers with Stuck Bus
Provides Automatic Clocking to Free Stuck I C Busses
Recovery
2-/4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, 10kV HBM ESD Tolerance
Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery
ThinSOT is a trademark of Linear Technology Corporation
43071fa
LT 0208 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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