LTC6403CUD-1-TRPBF [Linear]
200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifi er/Driver; 为200MHz ，低噪声，低功耗全差动输入/输出功率放大器器/驱动器
| 型号： | LTC6403CUD-1-TRPBF |
| 厂家： | 
Linear |
| 描述： | 200MHz, Low Noise, Low Power Fully Differential Input/Output Amplifi er/Driver |
| 文件： | 总20页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6403-1
200MHz, Low Noise,
Low Power Fully Differential
Input/Output Amplifier/Driver
FEATURES
DESCRIPTION
The LTC®6403-1 is a precision, very low noise, low dis-
tortion, fully differential input/output amplifier optimized
for 3V to 5V, single supply operation. The LTC6403-1 is
unity gain stable. The LTC6403-1 closed-loop bandwidth
extends from DC to 200MHz. In addition to the normal
unfiltered outputs (+OUT and –OUT), the LTC6403-1 has a
built-in44.2MHzdifferentialsingle-polelowpassfilterand
an additional pair of filtered outputs (+OUTF, and –OUTF).
■
Very Low Distortion: (2V , 3MHz): –95dBc
P-P
■
Fully Differential Input and Output
■
Low Noise: 2.8nV/√Hz Input-Referred
■
200MHz Gain-Bandwidth Product
■
Slew Rate: 200V/μs
■
Adjustable Output Common Mode Voltage
■
Rail-to-Rail Output Swing
■
Input Range Extends to Ground
■
Large Output Current: 60mA (Typ)
⎯
⎯
An input referred voltage noise of 2.8nV/√Hz enables the
LTC6403-1 to drive state-of-the-art 14- to 18-bit ADCs
whileoperatingonthesamesupplyvoltage,savingsystem
costandpower.TheLTC6403-1maintainsitsperformance
for supplies as low as 2.7V. It draws only 10.8mA, and
has a hardware shutdown feature which reduces current
consumption to 170μA.
■
DC Voltage Offset <1.5mV (Max)
■
10.8mA Supply Current
■
2.7V to 5.25V Supply Voltage Range
■
Low Power Shutdown
■
Tiny 3mm × 3mm × 0.75mm 16-Pin QFN Package
APPLICATIONS
The LTC6403-1 is available in a compact 3mm × 3mm
16-pin leadless QFN package and operates over a –40°C
to 85°C temperature range.
■
Differential Input A/D Converter Driver
■
Single-Ended to Differential Conversion/Amplification
■
Common Mode Level Translation
Low Voltage, Low Noise, Signal Processing
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
TYPICAL APPLICATION
Single-Ended Input to Differential Output
with Common Mode Level Shifting
Harmonic Distortion vs Frequency
–30
SINGLE-ENDED INPUT
2V
P-P
V
V
R
R
V
= 3V
OCM
S
–40
–50
= V
= 1.5V
ICM
0V
= R = 402Ω
F
I
V
S
= 800Ω
LOAD
= 2V
OUTDIFF P-P
50Ω
392Ω
402Ω
0.1μF
–60
3V
–70
SECOND
54.9Ω
–80
SIGNAL
1V
P-P
P-P
THIRD
GENERATOR
–90
1.5V
1.5V
+
V
OCM
–100
–110
–120
LTC6403-1
0.01μF
422Ω
–
1V
1
10
FREQUENCY (MHz)
100
64031 TA01
64031 TA01b
402Ω
64031f
1
LTC6403-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
+
–
Total Supply Voltage (V to V )................................5.5V
Input Voltage
+
–
16 15 14 13
⎯
⎯
⎯
⎯
(+IN, –IN, V
Input Current
(+IN, –IN, V
, SHDN) (Note 2)................... V to V
OCM
–
+
+
–
SHDN
1
2
3
4
12
11
10
9
V
V
V
V
+
V
⎯ ⎯ ⎯ ⎯
, SHDN) (Note 2)..................... 10mA
17
OCM
–
V
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range
V
OCM
5
6
7
8
(Note 4) ............................................... –40°C to 85°C
Specified Temperature Range
(Note 5) ............................................... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
= 150°C, θ = 160°C/W, θ = 4.2°C/W
T
JMAX
JA
JC
–
EXPOSED PAD (PIN 17) IS V , MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6403CUD-1#PBF
LTC6403IUD-1#PBF
LTC6403CUD-1#TRPBF LDBM
LTC6403IUD-1#TRPBF LDBM
16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C
16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-
Supply, VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
⎯
⎯
⎯
⎯
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 2.7V
MIN
TYP
MAX
UNITS
●
●
●
V
Differential Offset Voltage (Input Referred)
0.4
0.4
0.4
1.5
1.5
2
mV
mV
mV
OSDIFF
S
V = 3V
S
V = 5V
S
ΔV
/ΔT Differential Offset Voltage Drift (Input Referred)
OSDIFF
V = 2.7V
1
1
1
μV/°C
μV/°C
μV/°C
S
V = 3V
S
V = 5V
S
64031f
2
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-
Supply, VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
⎯
⎯
⎯
⎯
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
I
B
Input Bias Current (Note 6)
V = 2.7V
–25
–25
–25
–7.5
–7.5
–7.5
0
0
0
μA
μA
μA
S
V = 3V
S
V = 5V
S
●
●
●
I
Input Offset Current (Note 6)
Input Resistance
V = 2.7V
0.2
0.2
0.2
5
5
5
μA
μA
μA
OS
S
V = 3V
S
V = 5V
S
R
Common Mode
Differential Mode
1.7
14
MΩ
kΩ
IN
C
Input Capacitance
Differential Mode
f = 1MHz
1
pF
IN
⎯ ⎯
nV/√Hz
e
n
Differential Input Referred Noise Voltage Density
Input Noise Current Density
2.8
1.8
17
⎯ ⎯
pA/√Hz
i
n
f = 1MHz
⎯
⎯
e
Input Referred Common Mode Output Noise
Voltage Density
f = 1MHz, V
Shorted to Ground,
nV/√Hz
nVOCM
OCM
+
–
V = 1.5V, V = –1.5V
●
●
V
ICMR
Input Signal Common Mode Range (Note 7)
V = 3V
S
0
0
1.6
3.6
V
V
S
V = 5V
●
●
CMRRI
CMRRIO
PSRR
Input Common Mode Rejection Ratio
V = 3V, ΔV
= 0.75V
= 1.25V
50
50
72
72
dB
dB
S
ICM
ICM
(Input Referred) ΔV /ΔV
(Note 8)
V = 5V, ΔV
S
ICM
OSDIFF
●
●
●
Output Common Mode Rejection Ratio (Input
Referred) ΔV /ΔV (Note 8)
V = 5V, ΔV
S
= 2V
50
60
45
90
97
63
dB
dB
dB
OCM
OCM
OSDIFF
Differential Power Supply Rejection
(ΔV /ΔV ) (Note 9)
V = 2.7V to 5.25V
S
S
OSDIFF
PSRRCM
Output Common Mode Power Supply Rejection
(ΔV /ΔV ) (Note 9)
V = 2.7V to 5.25V
S
S
OSCM
●
●
G
Common Mode Gain (ΔV
/ΔV
)
V = 5V, ΔV
= 2V
= 2V
1
V/V
%
CM
OUTCM
OCM
S
OCM
OCM
ΔG
Common Mode Gain Error (100 • (G – 1))
V = 5V, ΔV
S
–0.4
–0.1
0.3
CM
CM
BAL
Output Balance (ΔV /ΔV
OUTCM
)
ΔV
= 2V
OUTDIFF
OUTDIFF
Single-Ended Input
Differential Input
●
●
–63
–66
–45
–45
dB
dB
●
●
●
V
Common Mode Offset Voltage (V
– V
)
V = 2.7V
10
10
10
25
25
25
mV
mV
mV
OSCM
OUTCM
OCM
S
V = 3V
S
V = 5V
S
ΔV
/ΔT Common Mode Offset Voltage Drift
OSCM
V = 2.7V
20
20
20
μV/°C
μV/°C
μV/°C
S
V = 3V
S
V = 5V
S
●
●
V
Output Signal Common Mode Range
(Voltage Range for the V Pin) (Note 7)
V = 3V
S
1.1
1.1
2
4
V
V
OUTCMR
S
V = 5V
OCM
●
●
R
Input Resistance, V
Pin
15
23
32
kΩ
INVOCM
OCM
V
V
Voltage at the V
Pin (Self-Biased)
V = 3V, V = Open
OCM
1.45
1.5
1.55
V
OCM
OCM
S
●
●
●
Output Voltage, High, Either Output Pin (Note 10) V = 3V, I = 0
190
190
340
300
300
490
mV
mV
mV
OUT
S
L
V = 3V, I = 5mA
S
L
V = 3V, I = 20mA
S
L
●
●
●
V = 5V, I = 0
170
195
380
300
340
550
mV
mV
mV
S
L
V = 5V, I = 5mA
S
L
V = 5V, I = 20mA
S
L
64031f
3
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-
Supply, VSHDN = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
⎯
⎯
⎯
⎯
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 3V, I = 0
MIN
TYP
MAX
UNITS
●
●
●
V
OUT
Output Voltage, Low, Either Output Pin (Note 10)
150
165
210
220
245
300
mV
mV
mV
S
L
V = 3V, I = –5mA
S
L
V = 3V, I = –20mA
S
L
●
●
●
V = 5V, I = 0
165
175
225
265
275
350
mV
mV
mV
S
L
V = 5V, I = –5mA
S
L
V = 5V, I = –20mA
S
L
●
●
●
I
Output Short-Circuit Current, Either Output Pin
(Note 11)
V = 2.7V
30
30
35
58
60
74
mA
mA
mA
SC
S
V = 3V
S
V = 5V
S
A
Large-Signal Voltage Gain
Supply Voltage Range
Supply Current
V = 3V
90
dB
V
VOL
S
●
V
2.7
5.25
S
●
●
●
I
V = 2.7V
10.7
10.8
11
11.8
11.8
12.1
mA
mA
mA
S
S
V = 3V
S
V = 5V
S
●
●
●
I
Supply Current in Shutdown
V = 2.7V
0.16
0.17
0.26
0.5
0.5
1
mA
mA
mA
⎯ ⎯ ⎯ ⎯
SHDN
S
V = 3V
S
V = 5V
S
+
⎯ ⎯ ⎯ ⎯
SHDN Input Logic Low
⎯ ⎯ ⎯ ⎯
●
●
V
V
V = 2.7V to 5V
V – 2.1
V
V
IL
S
+
SHDN Input Logic High
⎯ ⎯ ⎯ ⎯
V = 2.7V to 5V
S
V – 0.6
40
IH
R
SHDN Pull-Up Resistor
V = 5V, V
S
= 2.9V to 0V
= 0.5V to 3V
= 3V to 0.5V
66
4
90
kΩ
μs
ns
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SHDN
SHDN
t
ON
Turn-On Time
V = 3V, V
S
⎯
⎯
⎯
⎯
SHDN
t
Turn-Off Time
V = 3V, V
S
350
⎯
⎯
⎯
⎯
OFF
SHDN
LTC6403-1 AC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
V
SHDN = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined as
⎯ ⎯ ⎯ ⎯
(V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 3V
MIN
TYP
MAX
UNITS
SR
Slew Rate
200
200
V/μS
V/μS
S
V = 5V
S
GBW
Gain-Bandwidth Product
–3dB Frequency (See Figure 2)
3MHz Distortion
V = 3V
S
200
200
MHz
MHz
S
V = 5V
●
●
f
V = 3V
100
100
200
200
MHz
MHz
3dB
S
V = 5V
S
V = 3V, V
= 2V
S
OUTDIFF
P-P
Single-Ended Input
2nd Harmonic
HD2
HD3
–97
–95
dBc
dBc
3rd Harmonic
3MHz Distortion
V = 3V, V
= 2V
OUTDIFF
S
P-P
Differential Input
2nd Harmonic
3rd Harmonic
HD2
HD3
–106
–94
dBc
dBc
64031f
4
LTC6403-1
LTC6403-1 AC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
V
SHDN = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined as
⎯ ⎯ ⎯ ⎯
(V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
V = 3V, V
MIN
TYP
MAX
UNITS
IMD
Third-Order IMD at 10MHz
f1 = 9.5MHz, f2 = 10.5MHz
= 2V Envelope
–72
dBc
S
OUTDIFF
P-P
OIP3
Equivalent OIP3 at 3MHz (Note 12)
V = 3V
S
48
dBm
t
S
Settling Time
2V Step at Output
V = 3V, Single-Ended Input
S
1% Settling
20
30
ns
ns
0.1% Settling
NF
Noise Figure, f = 3MHz
10.8
dB
R
= 804
Ω
, R = 402
Ω
Ω
,
,
SOURCE
I
R = 402Ω, V = 3V
F
S
8.9
dB
R
= 200Ω, R = 100
I
SOURCE
R = 402Ω, V = 3V
F
S
f
Differential Filter 3dB Bandwidth
44.2
MHz
3dBFILTER
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V pin and testing at
OCM
both mid supply and at the Electrical Characteristics table limits to verify
that the differential gain has not deviated from the mid supply V case
OCM
by more than 1%, and the common mode offset (V ) has not deviated
OSCM
by more than 10mV from the mid supply case.
Note 2: The inputs +IN, –IN are protected by a pair of back-to-back diodes.
If the differential input voltage exceeds 1.4V, the input current should be
⎯
⎯
⎯
⎯
limited to less than 10mA. Input pins (+IN, –IN, V
, and SHDN) are also
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of the
OCM
protected by steering diodes to either supply. If the inputs should exceed
either supply voltage, the input current should be limited to less than
10mA.
change in the voltage at the V
pin to the change in differential input
OCM
referred voltage offset. These specifications are strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
“The Effects of Resistor Pair Mismatch” in the General Applications
Section of this datasheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9: Differential power supply rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common mode power supply rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely. Long term application of output currents in excess of the
absolute maximum ratings may impair the life of the device.
Note 4: The LTC6403-1 is guaranteed functional over the operating
temperature range –40°C to 85°C.
Note 5: The LTC6403C-1 is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6403C-1 is designed, characterized, and
expected to meet specified performance from –40°C to 85°C but is
not tested or QA sampled at these temperatures. The LTC6403I-1 is
guaranteed to meet specified performance from –40°C to 85°C.
Note 6: Input bias current is defined as the average of the input currents
flowing into Pin 6 and Pin 15 (–IN, and +IN). Input offset current is defined
common mode offset, V
– V
.
OUTCM
OCM
Note 10: Output swings are measured as differences between the output
and the respective power supply rail.
as the difference of the input currents flowing into Pin 15 and Pin 6 (I
=
OS
+
–
Note 11: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended. See Note
3 for more details.
Note 12: A resistive load is not required when driving an AD converter with
the LTC6403-1. Therefore, typical output power is very small. In order to
compare the LTC6403-1 with amplifiers that require 50Ω output load, the
I
– I )
B
B
Note 7: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential gain with a 1V differential output
with V = mid-supply, and also with V at the input common mode
ICM
ICM
range limits listed in the Electrical Characteristics table, verifying that the
differential gain has not deviated from the mid supply common mode input
LTC6403-1 output voltage swing driving a given R is converted to OIP3
L
case by more than 1%, and the common mode offset (V
) has not
OSCM
as if it were driving a 50Ω load. Using this modified convention, 2V is
P-P
deviated from the mid-supply case by more than 10mV.
by definition equal to 10dBm, regardless of actual R .
L
64031f
5
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Offset Voltage
vs Temperature
Common Mode Offset Voltage
vs Temperature
Supply Current vs Supply Voltage
8
6
0.8
0.6
12
10
V
V
V
= 3V
S
V
= OPEN
SHDN
= 1.5V
= 1.5V
OCM
ICM
FIVE TYPICAL UNITS
4
0.4
8
6
2
0.2
0
0
–2
–4
–6
–8
–0.2
–0.4
–0.6
–0.8
4
2
0
V
= 3V
S
V
= 1.5V
= 1.5V
OCM
ICM
R = R = 402Ω
T
T
T
= –40°C
= 25°C
= 85°C
V
A
A
A
I
F
FIVE TYPICAL UNITS
20 40
TEMPERATURE (°C)
–60 –40 –20
0
60 80 100
20 40
–60 –40 –20
0
60 80 100
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
64031 G02
64031 G01
64031 G03
Shutdown Supply Current
vs Supply Voltage
Frequency Response
vs Load Capacitance
⎯ ⎯ ⎯ ⎯
Supply Current vs SHDN Voltage
5
0
12
10
8
350
300
–
V
SHDN
= V
T
T
T
= –40°C
= 25°C
= 85°C
A
A
A
C
C
C
= 0pF
= 3.9pF
= 10pF
L
L
L
–5
250
200
150
100
50
–10
–15
–20
–25
–30
–35
–40
6
V
V
= 3V
S
= V
= 1.5V
ICM
OCM
LOAD
4
R
= 800Ω
R = R = 402Ω
I
F
T
T
T
= –40°C
= 25°C
= 85°C
A
A
A
2
CAPACITOR VALUES ARE FROM
EACH OUTPUT TO GROUND.
V
S
= 3V
NO SERIES RESISTORS ARE USED.
0
0
0
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
1
10
100
1000
0.5
SHDN VOLTAGE (V)
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
64031 G06
64031 G04
64031 G05
Frequency Response vs Gain
50
40
A
= 100
V
A (V/V)
V
R (Ω)
I
R (Ω)
F
A
V
= 10
A
1
2
402
402
402
402
402
402
402
806
A
= 20
V
30
= 5
V
20
A
= 2
V
10
5
2k
0
10
20
100
4.02k
8.06k
40.2k
–10
–20
–30
–40
–50
A
= 1
V
V
V
= 3V
S
= V
= 1.5V
ICM
OCM
R
= 800Ω
LOAD
0.1
1
10
FREQUENCY (MHz)
100
1000
64031 G08
64031f
6
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion
Harmonic Distortion vs Frequency
vs Output Amplitude
Harmonic Distortion vs Frequency
–40
–50
–60
–70
–30
–40
DIFFERENTIAL INPUTS
SINGLE-ENDED INPUT
DIFFERENTIAL INPUTS
V
V
= 3V
OCM
V
V
R
R
V
= 3V
OCM
V
V
R
R
V
= 3V
OCM
S
S
S
= V
= 1.5V
= V
= 1.5V
ICM
= V
= 1.5V
ICM
ICM
R
R
f
= R = 402Ω
= R = 402Ω
= R = 402Ω
F
I
–50
F
I
F
I
–60
= 800Ω
= 800Ω
= 800Ω
LOAD
LOAD
LOAD
–80
–90
= 3MHz
–60
= 2V
OUTDIFF P-P
= 2V
IN
OUTDIFF
P-P
–70
THIRD
–70
–80
SECOND
HD3
–80
THIRD
–90
–100
–110
–120
–90
HD2
–100
–110
–120
SECOND
–100
–110
–120
1
10
FREQUENCY (MHz)
100
1
2
3
4
5
1
10
FREQUENCY (MHz)
100
V
(V
)
OUTDIFF P-P
64031 G12
64031 G09
64031 G11
Differential Output Impedance
vs Frequency
Harmonic Distortion
vs Output Amplitude
Input Noise Density vs Frequency
100
10
1
100
10
1
–30
–40
1000
100
10
SINGLE-ENDED INPUT
V
V
= 3V
ICM
V = 3V
S
R = R = 402Ω
I F
S
V
V
R
R
= 3V
OCM
= 1.5V
S
= V
= 1.5V
ICM
= R = 402Ω
–50
F
I
THIRD
= 800Ω
LOAD
–60
f
IN
= 10MHz
i
n
–70
SECOND
–80
1
e
n
–90
–100
–110
0.1
0.01
–120
100
1k
10k
100k
1M
10M
0
1
2
3
5
4
0.1
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz)
V
(V
)
OUTDIFF P-P
64031 G17
64031 G18
64031 G14
Differential Slew Rate
vs Temperature
CMRR vs Frequency
Small Signal Step Response
220
210
200
190
180
170
70
60
50
40
30
20
+OUT
V
V
= 5V
= 3V
S
V
V
= 3V
OCM
S
= V
ICM
= 1.5V
LOAD
S
R
= 800Ω
R = R = 402Ω
I
L
F
C
V
= 0pF
= 180mV
,
IN
P-P
DIFFERENTIAL
V
V
= 3V
OCM
S
= 1.5V
–OUT
R = R = 402Ω
I
F
0.05% FEEDBACK NETWORK RESISTORS
–60 –40 –20
0
20
40 60 80 100
0.1
1
10
100
1000
5ns/DIV
FREQUENCY (MHz)
TEMPERATURE (°C)
64031 G19
64031 G22
64031 G21
64031f
7
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Step Response
Overdrive Transient Response
3.0
2.5
2.0
1.5
V
V
= 3V, R
= 800Ω
LOAD
S
–OUT
= 2V DIFFERENTIAL
P-P
IN
–OUT
V
V
= 3V
OCM
S
= 1.5V
1.0
0.5
0
+OUT
+OUT
50ns/DIV
20ns/DIV
64031 G24
64031 G23
PIN FUNCTIONS
+
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SHDN(Pin1):WhenSHDNisfloatingordirectlytiedtoV ,
ceramic bypass capacitors be placed between Pins 2 and
3, between Pins 11 and 12, and between Pins 10 and 9
with direct short connections. Pins 3, 9 and 10 should be
tieddirectlytoalowimpedancegroundplanewithminimal
routing.Fordual(split)powersupplies,itisrecommended
that at least two additional high quality, 0.1μF ceramic
capacitors are used to bypass pin V to ground and V to
ground,againwithminimalrouting.Fordrivinglargeloads
(<200Ω),additionalbypasscapacitancemaybeneededfor
optimal performance. Keep in mind that small geometry
(e.g.0603)surfacemountceramiccapacitorshaveamuch
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
the LTC6403-1 is in the normal (active) operating mode.
+
When Pin 1 is pulled a minimum of 2.1V below V , the
LTC6403-1 enters into a low power shutdown state. See
Applications Information for more details.
+
–
V , V (Pins 2, 10, 11 and Pins 3, 9, 12): Power Supply
Pins.Threepairsofpowersupplypinsareprovidedtokeep
the power supply inductance as low as possible to prevent
anydegradationofamplifier2ndharmonicperformance.It
is critical that close attention be paid to supply bypassing.
Forsinglesupplyapplications(Pins3, 9and12grounded)
it is recommended that high quality 0.1μF surface mount
+
–
64031f
8
LTC6403-1
PIN FUNCTIONS
V
(Pin 4): Output Common Mode Reference Voltage.
+OUT, –OUT (Pins 7, 14): Unfiltered Output Pins. Each
amplifier output is designed to drive a load capacitance of
10pF. This means the amplifier can drive 10pF from each
output to ground or 5pF differentially. Larger capacitive
loads should be decoupled with at least 25Ω resistors
from each output.
OCM
ThevoltageonV
setstheoutputcommonmodevoltage
OCM
level (which is defined as the average of the voltages on
the +OUT and –OUT pins). The V
pin is the midpoint
OCM
+
of an internal resistive voltage divider between V and
–
V that develops a (default) mid-supply voltage potential
to maximize output signal swing. The V
pin can be
OCM
+OUTF, –OUTF (Pins 8, 13): Filtered Output Pins. These
pins have a series 100Ω resistor connected between the
filtered and unfiltered outputs and three 12pF capacitors.
overdriven by an external voltage reference capable of
driving the input impedance presented by the V pin.
OCM
On the LTC6403-1, the V
pin has an input resistance
–
OCM
Both +OUTF, and –OUTF have 12pF to V , plus an ad-
of approximately 23k to a mid-supply potential. The V
OCM
ditional 12pF differentially between +OUTF and –OUTF.
This filter creates a differential low pass pole with a –3dB
bandwidth of 44.2MHz.
pinshouldbebypassedwithahighqualityceramicbypass
capacitor of at least 0.01μF, (unless you are using split
supplies, then connect directly to a low impedance, low
noise ground plane) to minimize common mode noise
from being converted to differential noise by impedance
mismatches both external and internal to the IC.
+IN, –IN (Pins 15, 6): Non-Inverting and Inverting Input
pins of the amplifier, respectively. For best performance,
it is highly recommended that stray capacitance be kept
to an absolute minimum by keeping printed circuit con-
nections as short as possible and stripping back nearby
surrounding ground plane away from these pins.
NC (Pins 5, 16): No Connection. These pins are not con-
nected internally.
–
ExposedPad(Pin17):TiethepadtoV (Pins3,9,and12).
If split supplies are used, do not tie the pad to ground.
BLOCK DIAGRAM
NC
+IN
–OUT
–OUTF
16
15
14
13
+
V
–
–
+
+
V
V
V
V
–
+
V
V
+
V
12pF
–
V
66k
SHDN
12
1
2
+
V
100Ω
100Ω
–
–
+
+
V
V
V
V
+
–
+
11
V
46k
–
+
12pF
V
V
+
V
OCM
V
–
+
V
V
46k
3
4
10
V
–
–
12pF
V
V
OCM
–
V
9
–
–
+
+
V
V
V
V
–
V
–
+
V
V
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 BD
64031f
9
LTC6403-1
APPLICATIONS INFORMATION
I
L
R
R
I
F
V
V
–OUT
+IN
+
–
V
–OUTF
V
INP
NC
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
–
R
V
BAL
SHDN
–
12
V
V
1
2
SHDN
–
–
0.1μF
0.1μF
0.1μF
+
+
V
V
V
+
+
–
11
V
V
+
V
OUTCM
+
+
V
V
V
0.1μF
V
OCM
CM
–
+
V
V
0.1μF
–
–
3
4
10
V
V
V
–
V
V
OCM
R
BAL
–
V
9
V
OCM
0.1μF
0.01μF
NC
–IN
+OUT
+OUT
+OUTF
–
+
5
6
7
8
64031 F01
V
INM
I
L
R
R
F
V+
I
OUTF
V
V
–IN
Figure 1. DC Test Circuit
APPLICATIONS INFORMATION
0.1μF
0.1μF
R
I
R
340Ω
F
V
+IN
V
–OUT
V
INP
V
–OUTF
R
140Ω
T
NC
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
SHDN
–
V
MINI-CIRCUITS
TCM4-19
–
12
V
50Ω
V
1
SHDN
–
–
0.1μF
M/A-COM
ETC1-1-13
0.1μF
+
+
V
V
V
+
–
+
+
2
11
V
V
+
50Ω
V
IN
+
+
V
V
V
0.1μF
OCM
–
+
V
V
V
0.1μF
–
–
–
3
4
10
V
V
V
–
0.1μF
0.1μF
V
OCM
–
V
9
V
OCM
0.1μF
0.01μF
NC
–IN
+OUT
+OUT
+OUTF
5
6
7
8
64031 F02
0.1μF
R
I
R
F
V
340Ω
+OUTF
V
V
–IN
V
INM
R
140Ω
T
Figure 2. AC Test Circuit (–3dB BW testing)
64031f
10
LTC6403-1
APPLICATIONS INFORMATION
Functional Description
Additional outputs (+OUTF and –OUTF) are available that
providefilteredversionsofthe+OUTand–OUToutputs.An
on-chipsinglepoleRCpassivefilterbandlimitsthefiltered
outputs to a –3dB frequency of 44.2MHz. The user has a
choice of using the unfiltered outputs, the filtered outputs,
or modifying the filtered outputs to adjust the frequency
response by adding additional components (see Output
Filter Considerations and Use section).
The LTC6403-1 is a small outline, wide band, low noise,
andlowdistortionfully-differentialamplifierwithaccurate
output phase balancing. The LTC6403-1 is optimized to
drive low voltage, single-supply, differential input analog-
to-digital converters (ADCs). The LTC6403-1’s output is
capable of swinging rail-to-rail on supplies as low as 2.7V,
which makes the amplifier ideal for converting ground
referenced, single-ended signals into V
referenced
In applications where the full bandwidth of the LTC6403-1
isdesired, theunfilteredoutputs(+OUTand–OUT)should
be used. The unfiltered outputs +OUT and –OUT are
designed to drive 10pF to ground (or 5pF differentially).
Capacitances greater than 10pF will produce excess
peaking, which can be mitigated by placing at least 25Ω
in series with the output.
OCM
differential signals in preparation for driving low voltage,
single-supply, differential input ADCs. Unlike traditional
op amps which have a single output, the LTC6403-1 has
two outputs to process signals differentially. This allows
for two times the signal swing in low voltage systems
when compared to single-ended output amplifiers. The
balanced differential nature of the amplifier also provides
even-order harmonic distortion cancellation, and less
susceptibility to common mode noise (like power supply
noise). TheLTC6403-1canbeusedasasingleendedinput
to differential output amplifier, or as a differential input to
differential output amplifier.
Input Pin Protection
The LTC6403-1’s input stage is protected against differen-
tial input voltages that exceed 1.4V by two pairs of back
to back diodes connected in anti-parallel series between
+IN and –IN (Pins 6 and 15). In addition, the input pins
have steering diodes to either power supply. If the input
pair is over-driven, the current should be limited to under
10mA to prevent damage to the IC. The LTC6403-1 also
The LTC6403-1’s output common mode voltage, defined
as the average of the two output voltages, is independent
of the input common mode voltage, and is adjusted by
has steering diodes to either power supply on the V
,
applying a voltage on the V
pin. If the pin is left open,
OCM
OCM
⎯
⎯
⎯
⎯
and SHDN pins (Pins 4 and 1), and if exposed to voltages
which exceed either supply, they too, should be current
limited to under 10mA.
an internal resistive voltage divider develops a potential
+
–
halfway between the V and V pin voltages. Whenever
is not hard tied to a low impedance ground plane, it
V
OCM
is recommended that a high quality ceramic capacitor is
used to bypass the V pin to a low impedance ground
⎯ ⎯ ⎯ ⎯
SHDN Pin
⎯ ⎯ ⎯ ⎯
OCM
plane (See Layout Considerations in this document). The
LTC6403-1’sinternalcommonmodefeedbackpathforces
accurate output phase balancing to reduce even order
harmonics, and centers each individual output about the
If the SHDN pin (Pin 1), is pulled 2.1V below the positive
supply, the LTC6403-1 will power down. The pin has the
+
Theveninequivalentimpedanceofapproximately66ktoV .
If the pin is left unconnected, an internal pull-up resistor
of 150k will keep the part in normal active operation. Care
should be taken to control leakage currents at this pin to
under 1μA to prevent inadvertently putting the LTC6403-1
into shutdown. In shutdown, all biasing current sources
areshutoff,andtheoutputpins,+OUTand–OUT,willeach
appear as an open collector with a non-linear capacitor in
parallel and steering diodes to either supply. Because of
potential set by the V
pin.
OCM
V+OUT + V–OUT
VOUTCM = VOCM
=
2
The outputs (+OUT and –OUT) of the LTC6403-1 are
capable of swinging rail-to-rail. They can source or sink
up to approximately 60mA of current.
64031f
11
LTC6403-1
APPLICATIONS INFORMATION
thenon-linearcapacitance,theoutputsstillhavetheability
to sink and source small amounts of transient current if
exposed to significant voltage transients. The inputs (+IN
and –IN) appear as anti-parallel diodes which can conduct
if voltage transients at the input exceed 1.4V. The inputs
also have steering diodes to either supply. The turn-on
time between the shutdown and active states is typically
4μs, and turn-off time is typically 350ns.
RF
RI
VOUTDIFF = V+OUT – V–OUT
≈
• V
+
INDIFF
Δβ
βAVG
Δβ
βAVG
• V
–
• VOCM
INCM
where:
R is the average of R , and R , and R is the average
F
F1
F2
I
of R , and R .
I1
I2
General Amplifier Applications
β
is defined as the average feedback factor (or gain)
from the outputs to their respective inputs:
AVG
As levels of integration have increased and correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically operated from a single supply voltage which can
be as low as 3V (2.7V min), and will have an optimal com-
mon mode input range near mid-supply. The LTC6403-1
makes interfacing to these ADCs trivial, by providing both
single ended to differential conversion as well as common
modelevelshifting.Thefrontpageofthisdatasheetshows
a typical application. Referring to Figure 1, the gain to
⎛
⎞
RI1
RI2
RI2 +RF2
1
AVG = •
2
β
+
⎜
⎟
R +R
⎝
⎠
I1
F1
Δβ is defined as the difference in feedback factors:
RI2 RI1
RI2 +RF2 RI1+RF1
is defined as the average of the two input voltages
Δβ =
–
V
V
INCM
, and V (also called the source-referred input com-
V
from V
and V is:
INM INP
INP
INM
OUTDIFF
mon mode voltage):
RF
RI
VOUTDIFF = V+OUT – V–OUT
≈
• VINP – V
(
)
1
2
INM
V
= • VINP + V
(
)
INCM
INM
Note from the above equation, the differential output
voltage (V – V ) is completely independent of
input and output common mode voltages. This makes
the LTC6403-1 ideally suited for pre-amplification, level
shifting and conversion of single-ended input signals to
differential output signals in preparation for driving dif-
ferential input ADCs.
and V
is defined as the difference of the input
INDIFF
voltages:
+OUT
–OUT
V
INDIFF
= V – V
INP INM
R
I2
R
F2
V
+IN
V
–OUT
V
–OUTF
+
V
INP
NC
+IN
–OUT
–OUTF
16
15
14
13
–
LTC6403-1
SHDN
–
Effects of Resistor Pair Mismatch
V
SHDN
–
12
V
V
1
2
SHDN
–
+
+
V
V
Figure 3 shows a circuit diagram with takes into consid-
eration that real world resistors will not perfectly match.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
V
V
0.1μF
0.1μF
+
+
–
V
V
11
+
+
+
V
OCM
V
V
0.1μF
–
+
V
V
–
–
V
3
4
V
10
0.1μF
–
–
V
V
OCM
0.1μF
–
V
VOCM
9
V
0.01μF
–
+
NC
–IN
+OUT
+OUTF
64031 F03
0.1μF
5
6
7
8
V
INM
R
R
F1
I1
V
+OUTF
V
–IN
V
+OUT
Figure 3. Real-World Application with Feedback Resistor
Pair Mismatch
64031f
12
LTC6403-1
APPLICATIONS INFORMATION
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Input Impedance and Loading Effects
The input impedance looking into the V or V
input
INM
INP
INP
Setting the differential input to zero (V
= 0), the de-
of Figure 1 depends on whether the sources V
and
INDIFF
gree of common mode to differential conversion is given
by the equation:
V
are fully differential. For balanced input sources
INM
(V = –V ), the input impedance seen at either input
INP
INM
is simply:
Δβ
VOUTDIFF = V+OUT – V–OUT ≈ VINCM – VOCM
•
(
)
R
INP
= R = R
INM I
βAVG
For single ended inputs, because of the signal imbalance
at the input, the input impedance increases over the bal-
anced differential case. The input impedance looking into
either input is:
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of
both signals and noise. Using 1% resistors or better will
mitigatemostproblems,andwillprovideabout34dBworst
case of common mode rejection. Using 0.1% resistors
will provide about 54dB of common mode rejection. A
low impedance ground plane should be used as a refer-
RI
⎛
RINP =RINM
=
⎛
⎞
⎞
RF
1
1– •
2
⎜
⎟
⎜
⎟
R +R
⎝
⎠
⎝
⎠
I
F
ence for both the input signal source and the V
pin.
OCM
Directly shorting V
OCM
to this ground or bypassing the
OCM
Inputsignalsourceswithnon-zerooutputimpedancescan
alsocausefeedbackimbalancebetweenthepairoffeedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated. If
input impedance matching is required by the source, R1
should be chosen (see Figure 4):
V
with a high quality 0.1μF ceramic capacitor to this
ground plane will further mitigate against common mode
signals being converted to differential.
There may be concern on how feedback ratio mismatch
affectsdistortion.Distortioncausedbyfeedbackratiomis-
match using 1% resistors or better is negligible. However,
in single supply level shifting applications where there is
a voltage difference between the input common mode
voltage and the output common mode voltage, resistor
mismatch can make the apparent voltage offset of the
amplifier appear worse than specified.
RINM •RS
R1=
RINM –RS
According to Figure 4, the input impedance looking into
thedifferentialamp(R )reflectsthesingleendedsource
INM
case, thus:
The apparent input referred offset induced by feedback
ratio mismatch is derived from the above equation:
RI
⎛
RINM
=
⎛
⎞
⎞
RF
1
1– •
2
V
≈ (V
– V
) • Δβ
OCM
OSDIFF(APPARENT)
INCM
⎜
⎟
⎜
⎟
R +R
⎝
⎠
⎝
⎠
I
F
Using the LTC6403-1 in a single supply application on a
single5Vsupplywith1%resistors, andtheinputcommon
R2 is chosen to balance R1 || RS:
mode grounded, with the V
pin biased at mid-supply,
OCM
the worst case mismatch can induce 25mV of apparent
offset voltage. With 0.1% resistors, the worst case appar-
ent offset reduces to 2.5mV.
RI •RS
R2 =
RI +RS
64031f
13
LTC6403-1
APPLICATIONS INFORMATION
R
INM
V
(setting V
to zero), the input common voltage is
INP
INM
R
S
R
I
R
F
approximately:
R1
V
S
–
⎛
⎞
V+IN + V
RI
R +R
+
–
V
=
–IN ≈ VVOCM
•
+
V
OCM
ICM
⎜
⎟
2
⎝
⎠
R1 CHOSEN SO THAT R1 || R
= R
S
+
INM
R2 CHOSEN TO BALANCE R || R1
I
F
S
R
I
R
F
⎛
⎞
⎛
⎞
⎟
RF
V
RF
INP
2
64031 F04
VCM
•
+
•
⎜
⎟
⎜
R2 = R || R1
S
R +R
R +R
⎝
⎠
⎝
⎠
F
I
F
I
Figure 4. Optimal Compensation for Signal Source Impedance
Output Common Mode Voltage Range
Input Common Mode Voltage Range
The output common mode voltage is defined as the aver-
age of the two outputs:
The LTC6403-1’s input common mode voltage (V ) is
ICM
+IN
defined as the average of the two input voltages, V , and
V+OUT + V–OUT
–
+
VOUTCM = VVOCM
The V
=
V
–IN
. It extends from V to 1.4V below V .
2
Forfullydifferentialinputapplications,whereV =–V
,
INP
INM
pin sets this average by an internal common
OCM
the input common mode voltage is approximately (Refer
mode feedback loop. The output common mode range
to Figure 5):
–
+
extends from 1.1V above V to 1V below V . The V
OCM
pin sits in the middle of an internal voltage divider which
⎛
⎞
V+IN + V
RI
R +R
V
=
–IN ≈ VVOCM
•
+
ICM
⎜
⎟
sets the default mid-supply open circuit potential.
2
⎝
⎠
I
F
In single supply applications, where the LTC6403-1 is
used to interface to an ADC, the optimal common mode
input range to the ADC is often determined by the ADC’s
reference. If the ADC makes a reference available for set-
ting the input common mode voltage, it can be directly
⎛
⎞
RF
VCM
•
⎜
⎟
R +R
⎝
⎠
F
I
With singled ended inputs, there is an input signal com-
ponent to the input common mode voltage. Applying only
tied to the V
pin, but must be capable of driving the
OCM
R
R
input impedance presented by the V
as listed in the
I
F
V
OCM
+IN
V
–OUT
V
–OUTF
Electrical Characteristics Table. This impedance can be
assumed to be connected to a mid-supply potential. If an
+
–
V
NC
+IN
–OUT
–OUTF
INP
16
15
14
13
LTC6403-1
external reference drives the V
pin, it should still be
SHDN
OCM
–
V
SHDN
–
bypassed with a high quality 0.01μF or higher capacitor to
a low impedance ground plane to filter any thermal noise
and to prevent common mode signals on this pin from
being inadvertently converted to differential signals.
12
V
V
1
2
SHDN
–
+
+
V
V
V
V
0.1μF
0.1μF
+
+
–
V
V
11
+
V
CM
+
+
V
OCM
V
V
0.1μF
–
+
V
V
–
–
V
3
4
V
10
0.1μF
–
–
V
V
OCM
0.1μF
Output Filter Considerations and Use
–
V
9
V
VOCM
0.01μF
–
+
NC
–IN
+OUT
+OUTF
64031 F05
0.1μF
5
6
7
8
Filtering at the output of the LTC6403-1 is often desired
to provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LTC6403-1 includes an
additional pair of differential outputs (+OUTF and –OUTF)
which incorporate an internal lowpass filter network with
a –3dB bandwidth of 44.2MHz (Figure 6).
V
INM
R
R
F
I
V
+OUTF
V
–IN
V
+OUT
Figure 5. Circuit for Common Mode Range
64031f
14
LTC6403-1
APPLICATIONS INFORMATION
These pins each have an output impedance of 100Ω. In-
+OUTF and –OUTF can also be used, and since it is being
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 36pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one 18pF capacitor could be added between
the filtered outputs, again halving the filter bandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 12pF from each filtered output to
ground plus a 12pF capacitor between the filtered outputs
would also halve the filter bandwidth (Figure 8).
–
ternal capacitances are 12pF to V on each filtered output,
plus an additional 12pF capacitor connected differentially
between the two filtered outputs. This resistor/capacitor
combination creates filtered outputs that look like a se-
ries 100Ω resistor with a 36pF capacitor shunting each
filtered output to AC ground, providing a –3dB bandwidth
of 44.2MHz, and a noise bandwidth of 69.4MHz. The
filter cutoff frequency is easily modified with just a few
external components. To increase the cutoff frequency,
simply add 2 equal value resistors, one between +OUT
and +OUTF and the other between –OUT and –OUTF
(Figure 7). These resistors, in parallel with the internal
100Ω resistors, lower the overall resistance and therefore
increase filter bandwidth. For example, to double the filter
bandwidth, add two external 100Ω resistors to lower the
series filter resistance to 50Ω. The 36pF of capacitance
remains unchanged, so filter bandwidth doubles. Keep in
mind, the series resistance also serves to decouple the
outputs from load capacitance. The unfiltered outputs of
the LTC6403-1 are designed to drive 10pF to ground or
5pF differentially, so care should be taken to not lower the
effective impedance between +OUT and +OUTF or –OUT
and –OUTF below 25Ω.
100Ω
–OUT
–OUTF
14
13
LTC6403-1
12pF
–
V
12
–
–
100Ω
V
+
–
FILTERED OUTPUT
(88.4MHz)
12pF
100Ω
V
–
12pF
V
9
+OUT
+OUTF
7
8
64031 F07
100Ω
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
Figure 7. LTC6403-1 Filter Topology Modified for 2x
Filter Bandwidth (2 External Resistors)
–OUT
–OUTF
–OUT
–OUTF
14
13
14
13
LTC6403-1
12pF
LTC6403-1
12pF
–
V
12pF
–
V
12
12
–
–
100Ω
V
–
–
100Ω
V
+
–
FILTERED OUTPUT
(22.1MHz)
+
–
12pF
FILTERED OUTPUT
(44.2MHz)
12pF
12pF
100Ω
100Ω
V
12pF
–
12pF
V
V
–
12pF
V
9
9
+OUT
+OUTF
+OUT
+OUTF
7
8
64031 F08
7
8
64031 F06
Figure 6. LTC6403-1 Internal Filter Topology
Figure 8. LTC6403-1 Filter Topology Modified for 1/2x
Filter Bandwidth (3 External Capacitors)
64031f
15
LTC6403-1
APPLICATIONS INFORMATION
Noise Considerations
The LTC6403-1’s input referred voltage noise contributes
theequivalentnoiseofa480Ωresistor.Whenthefeedback
network is comprised of resistors whose values are less
than this, the LTC6403-1’s output noise is voltage noise
dominant (See Figure 10.):
The LTC6403-1’s input referred voltage noise is on the
⎯
⎯
order of 2.8nV/√Hz. Its input referred current noise is on
⎯
⎯
the order of 1.8pA/√Hz. In addition to the noise generated
by the amplifier, the surrounding feedback resistors also
contribute noise. A noise model is shown in Figure 9.
The output noise generated by both the amplifier and the
feedback components is governed by the equation:
⎛
⎞
⎟
RF
RI
eno ≈eni • 1+
⎜
⎝
⎠
Feedback networks consisting of resistors with values
greater than about 1k will result in output noise which is
resistor noise and amplifier current noise dominant.
2
⎛
⎞
⎛
⎞
RF
RI
2
eni • 1+
+2• I •R
+
(
)
n
F
⎜
⎟
⎜
⎝
⎟
⎠
⎝
⎠
eno =
2
⎛
⎞
⎛
⎞
⎛
⎞
⎟
RF
RF
RI
eno ≈ 2 • I •R 2 + 1+
• 4•k • T •RF
2
2• enRI
•
+2•enRF
(
)
n
F
⎜
⎟
⎜
⎟
⎜
R
⎝
⎠
⎝
⎠
⎝
⎠
I
Lowerresistorvalues(<400Ω)alwaysresultinlowernoise
at the penalty of increased distortion due to increased
loading of the feedback network on the output. Higher
A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6403-1 is shown
in Figure 10.
2
2
e
e
nRF2
nRI2
R
I2
R
F2
+2
i
n
NC
+IN
–OUT
–OUTF
13
16
15
14
LTC6403-1
SHDN
–
V
SHDN
–
12
V
V
V
1
2
–
–
+
+
V
V
V
+
–
+
–
11
V
V
V
+
+
+
–
2
2
V
V
OCM
e
e
no
nof
–
+
V
V
–
3
4
10
V
2
V
e
ncm
–
V
V
OCM
9
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 F09
–2
i
n
2
e
ni
2
2
e
e
nRF1
nRI1
R
I1
R
F1
Figure 9. Noise Model of the LTC6403-1
64031f
16
LTC6403-1
APPLICATIONS INFORMATION
100
supplies, it is recommended that at least two additional
high quality, 0.1μF ceramic capacitors are used to bypass
+
–
pin V to ground and V to ground, again with minimal
routing.Fordrivinglargeloads(<200Ω),additionalbypass
capacitancemaybeneededforoptimalperformance.Keep
in mind that small geometry (e.g. 0603) surface mount
ceramic capacitors have a much higher self resonant
frequency than do leaded capacitors, and perform best
in high speed applications.
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
10
FEEDBACK RESISTOR
NETWORK NOISE ALONE
1
Any stray parasitic capacitances to ground at the sum-
ming junctions +IN, and –IN should be kept to an absolute
minimum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
100
1k
= R (Ω)
10k
R
F
I
64031 F10
Figure 10. LTC6403-1 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
resistor values >2k in circuits with R = R . Excessive
F
I
resistor values (but still less than 2k) will result in higher
output noise, but improved distortion due to less loading
on the output. The optimal feedback resistance for the
LTC6403-1 runs between 400Ω to 2k.
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around
R . Always keep in mind the differential nature of the
F
LTC6403-1, and that it is critical that the load impedances
seen by both outputs (stray or intended) should be as bal-
anced and symmetric as possible. This will help preserve
the natural balance of the LTC6403-1, which minimizes
the generation of even order harmonics, and preserves
the rejection of common mode signals and noise.
Thedifferentialfilteredoutputs+OUTFand–OUTFwillhave
a little higher spot noise than the unfiltered outputs (due
to the two 100Ω resistors which contribute 1.3nV/√Hz
each), but actually will provide superior signal-to-noise
ratios in noise bandwidths exceeding 69.4Mhz due to the
noise-filtering function the filter provides.
⎯
⎯
It is highly recommended that the V
pin be either hard
OCM
tied to a low impedance ground plane (in split supply
applications), or bypassed to ground with a high quality
ceramic capacitor whose value exceeds 0.01μF. This will
help stabilize the common mode feedback loop as well as
preventthermalnoisefromtheinternalvoltagedividerand
other external sources of noise from being converted to
differential noise due to divider mismatches in the feed-
back networks. It is also recommended that the resistive
feedback networks comprise 1% resistors (or better) to
enhancetheoutputcommonmoderejection.Thiswillalso
Layout Considerations
Because the LTC6403-1 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
Three pairs of power supply pins are provided to keep the
power supply inductance as low as possible to prevent
any degradation of amplifier 2nd Harmonic distortion
performance. It is critical that close attention be paid to
supply bypassing. For single supply applications (Pins
3, 9 and 12 grounded) it is recommended that 3 high
quality 0.1μF surface mount ceramic bypass capacitor be
placed between pins 2 and 3, between pins 11and 12, and
between pins10 and 9 with direct short connections. Pins
3, 9 and 10 should be tied directly to a low impedance
ground plane with minimal routing. For dual (split) power
prevent the V
-referred common mode noise of the
OCM
common mode amplifier path (which cannot be filtered)
from being converted to differential noise, degrading the
differential noise performance.
64031f
17
LTC6403-1
APPLICATIONS INFORMATION
Interfacing the LTC6403-1 to A/D Converters
to help absorb the charge injection that comes out of the
ADC from the sampling process. The capacitance of the
filter network serves as a charge reservoir to provide high
frequencychargingduringthesamplingprocess,whilethe
two resistors of the filter network are used to dampen and
attenuateanychargekickbackfromtheADC.Theselection
of the R-C time constant is trial and error for a given ADC,
but the following guidelines are recommended: Choosing
too large of a resistor in the decoupling network will create
a voltage divider between the dynamic input impedance of
the ADC and the decoupling resistors leaving insufficient
settlingtime. Choosingtoosmallofaresistorwillpossibly
prevent the resistor from properly dampening the load
transient caused by the sampling process, prolonging
the time required for settling. 16-bit applications require
a minimum of 11 R-C time constants to settle. It is rec-
ommended that the capacitor chosen have a high quality
dielectric (for example, C0G multilayer ceramic).
The LTC6403-1’s rail-to-rail output and fast settling time
make the LTC6403-1 ideal for interfacing to low voltage,
singlesupply,differentialinputADCs.Thesamplingprocess
of ADCs creates a sampling glitch caused by switching
in the sampling capacitor on the ADC front end which
momentarily“shorts”theoutputoftheamplifierascharge
is transferred between the amplifier and the sampling
capacitor. The amplifier must recover and settle from
this load transient before this acquisition period ends for
a valid representation of the input signal. In general, the
LTC6403-1 will settle much more quickly from these pe-
riodic load impulses than from a 2V input step, but it is
a good idea to either use the filtered outputs to drive the
ADC (Figure 11 shows an example of this), or to place a
discrete R-C filter network between the differential unfil-
tered outputs of the LTC6403-1 and the input of the ADC
402Ω
402Ω
NC
+IN
–OUT
–OUTF
16
15
14
13
LTC6403-1
SHDN
SHDN
CONTROL
–
V
V
CM
12
2.2μF
1
2
–
–
+
+
V
V
V
D15
•
0.1μF
0.1μF
+
–
+
–
AIN
AIN
11
3.3V
V
V
+
•
+
0.1μF
V
3.3V
LTC2207
GND
V
OCM
D0
–
+
V
V
V
–
3
4
10
3.3V
V
DD
V
–
1μF
V
OCM
9
0.1μF
NC
–IN
+OUT
+OUTF
5
6
7
8
64031 F11
V
IN
, 2V
P-P
402Ω
402Ω
Figure 11. Interfacing the LTC6403-1 to ADC (Shared 3.3V Supply Voltage)
64031f
18
LTC6403-1
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50 0.05
2.10 0.05
1.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 0.05
3.00 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
1
2
1.45 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
64031f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC6403-1
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64031f
LT 0108 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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