LTC6605IDJC-10-TRPBF [Linear]
Dual Matched 10MHz Filter with Low Noise, Low Distortion Differential Amplifi er; 与低噪声双通道匹配滤波器的10MHz ,低失真差分功率放大器儿型号: | LTC6605IDJC-10-TRPBF |
厂家: | Linear |
描述: | Dual Matched 10MHz Filter with Low Noise, Low Distortion Differential Amplifi er |
文件: | 总20页 (文件大小:258K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC6605-10
Dual Matched 10MHz Filter
with Low Noise, Low Distortion
Differential Amplifier
FEATURES
DESCRIPTION
The LTC®6605-10 contains two independent, fully differ-
ential amplifiers configured as matched 2nd order 10MHz
n
Two Matched 10MHz 2nd Order Lowpass Filters
with Differential Amplifiers
Gain Match: 0.ꢀ3dꢁ Maꢂ, ꢃassꢄand
ꢃhase Match: 1.2ꢅ Maꢂ, ꢃassꢄand
Single-Ended or Differential Inputs
lowpass filters. The f
of the filters is adjustable in the
–3dB
range of 9.7MHz to 14MHz.
The internal op amps are fully differential, feature very
low noise and distortion, and are compatible with 16-bit
dynamic range systems. The inputs can accept single-
ended or differential signals. An input pin is provided
for each amplifier to set the common mode level of the
differential outputs.
n
< –90dꢁc Distortion in ꢃassꢄand
n
2.1nV/√Hz Op Amp Noise Density
Pin-Selectable Gain (0dB/12dB/14dB)
Pin-Selectable Power Consumption (0.35mA/
16.2mA/33.1mA)
Rail-to-Rail Output Swing
n
n
n
Internallaser-trimmedresistorsandcapacitorsdetermine
a precise, very well matched (in gain and phase) 10MHz
2nd order filter response. A single optional external re-
sistor per channel can tailor the frequency response for
each amplifier.
Adjustable Output Common Mode Voltage Control
Buffered, Low Impedance Outputs
n
2.7V to 5.25V Supply Voltage
n
Small 22-Pin 6mm × 3mm × 0.75mm DFN Package
Three-state BIAS pins determine each amplifier’s power
consumption, allowing a choice between shutdown, me-
dium power or full power.
APPLICATIONS
n
Broadband Wireless ADC Driver/Filter
n
Antialiasing Filter
The LTC6605-10 is available in a compact 6mm × 3mm
22-pin leadless DFN package and operates over a –40°C
to 85°C temperature range.
n
Single-Ended to Differential Conversion
DAC Smoothing Filter
n
n
Zero-IF Direct Conversion Receivers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dual, Matched 9.7MHz Lowpass Filter
Channel to Channel ꢃhase Matching
120
352 TYPICAL UNITS
+
1
2
22
21
20
19
18
17
16
15
14
13
12
T
f
= 25°C
A
IN
3V
+
–
= 10MHz
100
80
60
40
20
0
–
0.1μF
0.1μF
V
3V
V
3
OUTA
INA
–
+
4
5
LTC6605-10
6
+
7
8
3V
+
–
–
OUTB
+
0.1μF
0.1μF
V
3V
V
9
INB
10
11
–1.0 –0.8–0.6 –0.4–0.2
0 0.2 0.4 0.6 0.8 1.0
–
PHASE MATCH (DEG)
660510 TA01
660510 TA01b
660510f
1
LTC6605-10
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
+
–
Total Supply Voltage (V to V )................................5.5V
Input Current (Note 2).......................................... 10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4).... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
TOP VIEW
+IN4 A
+IN1 A
BIAS A
–IN1 A
–IN4 A
1
2
3
4
5
6
7
8
9
22 –OUT A
+
21
20
19
V
V
V
A
–
OCMA
18 +OUT A
–
–
23
V
17 V
+IN4 B
+IN1 B
BIAS B
16 –OUT B
+
15
14
13
V
V
V
B
–
–IN1 B 10
–IN4 B 11
OCMB
12 +OUT B
DJC PACKAGE
22-LEAD (6mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 46.5°C/W
JMAX
JA
–
EXPOSED PAD (PIN 23) IS V , MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAꢃE AND REEL
ꢃART MARKING*
ꢃACKAGE DESCRIꢃTION
22-Lead (6mm × 3mm) Plastic DFN
22-Lead (6mm × 3mm) Plastic DFN
TEMꢃERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC6605CDJC-10#PBF
LTC6605IDJC-10#PBF
LTC6605CDJC-10#TRPBF 660510
LTC6605IDJC-10#TRPBF 660510
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 23ꢅC. V+ = ꢀV, V– = 0V, VINCM = VOCM = mid-supply, ꢁIAS tied to V+, RL = Open,
RꢁAL = 10k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT
+
V–OUT)/2. VINCM is defined as (VINꢃ + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINꢃ – VINM). See Figure 1.
SYMꢁOL
ꢃARAMETER
CONDITIONS
MIN
TYꢃ
MAX
UNITS
l
V
Differential Offset Voltage (at Op Amp V = 2.7V to 5V
0.25
1
mV
OS
S
Inputs) (Note 6)
+
l
l
ΔV /ΔT
OS
Differential Offset Voltage Drift (at Op BIAS = V
1
1
μV/°C
μV/°C
Amp Inputs)
BIAS = Floating
+
l
l
I
I
Input Bias Current (at Op Amp Inputs) BIAS = V
–60
–30
–25
0
0
μA
μA
B
(Note 7)
BIAS = Floating
–12.5
Input Offset Current
(at Op Amp Inputs) (Note 7)
1
μA
OS
660510f
2
LTC6605-10
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 23ꢅC. V+ = ꢀV, V– = 0V, VINCM = VOCM = mid-supply, ꢁIAS tied to V+, RL = Open,
RꢁAL = 10k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT
+
V–OUT)/2. VINCM is defined as (VINꢃ + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINꢃ – VINM). See Figure 1.
SYMꢁOL
ꢃARAMETER
CONDITIONS
V = 3V
MIN
TYꢃ
MAX
UNITS
l
l
V
Input Common Mode Voltage Range
(Note 8)
–0.2
–0.2
1.7
4.7
V
V
INCM
S
V = 5V
S
l
l
CMRR
PSRR
Common Mode Rejection Ratio
V = 3V; ΔV
= 1.5V
= 2.5V
46
46
74
74
dB
dB
S
INCM
INCM
(ΔV
/ΔV ) (Note 9)
V = 5V; ΔV
S
INCM
OS
l
Power Supply Rejection Ratio
(ΔV /ΔV ) (Note 10)
V = 2.7V to 5V
S
66
95
dB
S
OS
l
l
V
V
V
Common Mode Offset Voltage
(V – V
V = 3V
10
10
15
15
mV
mV
OSCM
OCM
MID
S
)
V = 5V
S
OUTCM
OCM
l
l
Output Common Mode Range
(Valid Range for V Pin) (Note 8)
V = 3V
1.1
1.1
2
4
V
V
S
V = 5V
OCM
S
l
l
Self-Biased Voltage at the V
Pin
V = 3V
S
1.475
12.5
1.5
18
1.525
23.5
V
OCM
R
Input Resistance of V
Pin
OCM
kΩ
VOCM
OUT
l
l
l
V
Output Voltage Swing, High
V = 3V; I = 0mA
245
285
415
450
525
750
mV
mV
mV
S
L
+
(Measured Relative to V )
V = 3V; I = 5mA
S L
V = 3V; I = 20mA
S
L
l
l
l
V = 5V; I = 0mA
350
390
550
625
700
1000
mV
mV
mV
S
L
V = 5V; I = 5mA
S
L
V = 5V; I = 20mA
S
L
l
l
l
Output Voltage Swing, Low
V = 3V; I = 0mA
120
135
195
225
250
350
mV
mV
mV
S
L
–
(Measured Relative to V )
V = 3V; I = –5mA
S L
V = 3V; I = –20mA
S
L
l
l
l
V = 5V; I = 0mA
175
200
270
325
360
475
mV
mV
mV
S
L
V = 5V; I = –5mA
S
L
V = 5V; I = –20mA
S
L
l
l
I
Output Short-Circuit Current (Note 3)
V = 3V
S
40
50
70
95
mA
mA
SC
S
V = 5V
l
V
Supply Voltage
2.7
5.25
V
S
+
l
l
l
I
Supply Current (per Channel)
V = 2.7V to 5V; BIAS = V
S
S
33.1
16.2
0.35
45
26.5
1.6
mA
mA
mA
S
S
V = 2.7V to 5V; BIAS = Floating
–
V = 2.7V to 5V; BIAS = V
–
l
l
l
l
l
BIAS Pin Range for Shutdown
BIAS Pin Range for Medium Power
BIAS Pin Range for Full Power
Referenced to V
0
1
0.4
1.5
V
V
–
Referenced to V
–
Referenced to V
2.3
1.05
100
V
V
S
–
BIAS Pin Self-Biased Voltage (Floating) Referenced to V
BIAS Pin Input Resistance
1.15
150
400
400
1.25
200
V
R
kΩ
ns
ns
BIAS
–
+
–
t
t
Turn-On Time
Turn-Off Time
V = 3V, V
= V to V
ON
OFF
S
BIAS
BIAS
+
V = 3V, V
S
= V to V
660510f
3
LTC6605-10
AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 23ꢅC. V+ = ꢀV, V– = 0V, VINCM = VOCM = mid-supply, VꢁIAS = V+, unless
otherwise noted. Filter configured as in Figure 2, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT
V–OUT)/2. VINCM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (V+IN + V–IN).
+
SYMꢁOL
ꢃARAMETER
CONDITIONS
ΔV 0.125V, DC
= 0.5V , f = 5MHz
MIN
TYꢃ
MAX
UNITS
l
l
l
l
l
l
Gain
Filter Gain
=
–0.25
–1.1
–2.35
–4.05
–11.75
–28
0.05
–0.77
–1.89
–3.5
–11.1
–25.8
0.25
–0.4
–1.45
–3
–10.55
–24.8
dB
dB
dB
dB
dB
dB
IN
V
V
V
V
V
INDIFF
INDIFF
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 7.5MHz
P-P
= 0.5V , f = 10MHz
P-P
= 0.5V , f = 20MHz
P-P
= 0.5V , f = 50MHz
P-P
Phase
ΔGain
Filter Phase
ΔV
=
0.125V, DC
0
Deg
Deg
Deg
Deg
IN
V
V
V
= 0.5V , f = 5MHz
–42.5
–63.2
–81.7
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 7.5MHz
P-P
= 0.5V , f = 10MHz
P-P
l
l
l
l
Gain Match (Channel-to-Channel)
Phase Match (Channel-to-Channel)
ΔV
=
0.125V, DC
–0.2
–0.2
0.05
0.05
0.05
0.05
0.2
0.2
dB
dB
dB
dB
IN
V
V
V
= 0.5V , f = 5MHz
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 7.5MHz
–0.3
0.3
P-P
= 0.5V , f = 10MHz
–0.35
0.35
P-P
l
l
l
ΔPhase
V
V
V
= 0.5V , f = 5MHz
–1.1
–1.2
–1.2
0.2
0.2
0.2
1.1
1.2
1.2
Deg
Deg
Deg
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 7.5MHz
P-P
= 0.5V , f = 10MHz
P-P
l
4V/V Gain
Filter Gain in 4V/V Configuration
Inputs at IN1 Pins, IN4 Pins Floating
ΔV
=
0.125V, DC
11.85
12
12.25
dB
IN
Channel Separation
V
= 1V , f = 5MHz
–96
dB
INDIFF
P-P
+
f
TC
Filter Cut-Off Frequency Temperature
Coefficient
BIAS = V
–80
–260
ppm/°C
ppm/°C
O
BIAS = Floating
Noise
Integrated Output Noise
(BW = 10kHz to 20MHz)
69
μV
RMS
+
Input Referred Noise Density (f = 1MHz) BIAS = V
Figure 4, Gain = 1
Figure 4, Gain = 4
Figure 4, Gain = 5
20
5
4
nV/√Hz
nV/√Hz
nV/√Hz
+
e
Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
2.1
2.6
nV/√Hz
nV/√Hz
n
BIAS = Floating
+
i
Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
3
2.1
pA/√Hz
pA/√Hz
n
BIAS = Floating
+
HD2
HD3
2nd Harmonic Distortion
BIAS = V
–90
–75
dBc
dBc
f
= 5MHz; V = 2V Single-Ended
BIAS = Floating, R
= 400Ω
= 400Ω
IN
IN
P-P
LOAD
LOAD
+
3rd Harmonic Distortion
= 5MHz; V = 2V Single-Ended
BIAS = V
–106
–82
dBc
dBc
f
BIAS = Floating, R
IN
IN
P-P
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-10’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.
Note 3: The LTC6605C is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specified performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specified performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
by the noise gain (1 + GAIN). See Figure 3.
OS
Note ꢀ: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.
Note 7: Input bias current is defined as the average of the currents
flowing into the noninverting and inverting inputs of the internal amplifier
and is calculated from measurements made at the pins of the IC. Input
offset current is defined as the difference of the currents flowing into
the noninverting and inverting inputs of the internal amplifier and is
calculated from measurements made at the pins of the IC.
660510f
4
LTC6605-10
ELECTRICAL CHARACTERISTICS
Note 8: See the Applications Information section for a detailed
discussion of input and output common mode range. Input common
mode range is tested by measuring the differential DC gain with V
Characteristics table verifying that the differential gain has not
deviated from the mid-supply common mode input case by more than
0.5%, and that the common mode offset (V ) has not deviated by
OSCM
INCM
= mid-supply, and again with V
limits listed in the Electrical Characteristics table, with ΔV
verifying that the differential gain has not deviated from the mid-supply
common mode input case by more than 0.5%, and that the common
at the input common mode range
more than 10mV from the mid-supply case.
INCM
= 0.25V,
IN
Note 9: CMRR is defined as the ratio of the change in the input common
mode voltage at the internal amplifier inputs to the change in differential
input referred voltage offset (V ).
OS
mode offset (V
) has not deviated from the mid-supply common
OSCM
Note 10: Power supply rejection ratio (PSRR) is defined as the ratio of
the change in supply voltage to the change in differential input referred
mode offset by more than 10mV.
Output common mode range is tested by measuring the differential
voltage offset (V ).
OS
DC gain with V
= mid-supply, and again with voltage set on the
OCM
V
pin at the output common range limits listed in the Electrical
OCM
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
Filter Gain vs Temperature
37.5
35.0
32.5
30.0
27.5
25.0
22.5
20.0
17.5
15.0
12.5
1.010
1.005
V
V
V
V
V
V
= 2.7V, BIAS = FLOAT
= 3V, BIAS = FLOAT
= 5V, BIAS = FLOAT
S
S
S
S
S
S
+
1.000
0.995
0.990
= 2.7V, BIAS = V
+
= 3V, BIAS = V
+
= 5V, BIAS = V
+
V
V
= 3V, BIAS = V
S
= V
= MID-SUPPLY
5 RANDOM UNITS
INCM
OCM
V
= V
= MID-SUPPLY
OCM
INCM
0
–60
20
60 80
40
–60
60 80
–40 –20
100
–40 –20
0
20
40
100
TEMPERATURE (°C)
TEMPERATURE (°C)
660510 G01
660510 G02
–ꢀdꢁ Frequency vs Temperature
Filter Frequency Response
0
–10
–20
–30
–40
–50
2.5
2.0
V
V
= 3V
INCM
S
= V
= 1.5V
OCM
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
+
BIAS = V
BIAS PIN FLOATING
BIAS = FLOAT
V
V
= 3V
INCM
S
+
BIAS = V
= V
= MID SUPPLY
10
OCM
0.1
1.0
100
1000
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
FREQUENCY (MHz)
660514 G04
660510 G03
660510f
5
LTC6605-10
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion
Harmonic Distortion
Harmonic Distortion
vs Input Amplitude
vs Frequency, ꢁIAS High
vs Frequency, ꢁIAS Floating
–40
–50
–40
–50
–40
–50
DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED
DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUTS, HD2
SINGLE-ENDED INPUTS, HD3
DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUTS, HD2
SINGLE-ENDED
INPUTS, HD2
–60
–60
–60
SINGLE-ENDED
INPUTS, HD3
INPUTS, HD3
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
4
6
1
10
100
1
10
100
1
2
3
5
FREQUENCY (MHz)
= 2V , V = 3V
P-P S
= 400Ω DIFFERENTIAL, GAIN = 1V/V
FREQUENCY (MHz)
= 2V , V = 3V
P-P S
= 400Ω DIFFERENTIAL, GAIN = 1V/V
V
(V
)
IN P-P
660510 G05
660510 G06
660510 G07
+
V
V
IN
L
V
= 3V, BIAS TIED TO V , V
= V
= 1.5V
IN
L
S
INCM
OCM
R
R
R
= 400Ω, f = 3MHz, GAIN = 1V/V
LOAD IN
Harmonic Distortion vs Input
Harmonic Distortion vs Input
Differential Output Noise
vs Frequency
Common Mode Voltage (VS = ꢀV)
Common Mode Voltage (VS = 3V)
–40
–50
1000
100
10
–40
–50
100
DIFFERENTIAL
INPUTS, HD2
DIFFERENTIAL
INPUTS, HD3
SINGLE-ENDED
INPUT, HD2
DIFFERENTIAL INPUTS, HD2
DIFFERENTIAL INPUTS, HD3
SINGLE-ENDED INPUT, HD2
SINGLE-ENDED INPUT, HD3
V
= 3V
S
+
BIAS TIED TO V
–60
–60
–70
–70
SINGLE-ENDED
INPUT, HD3
–80
–80
10
–90
–90
–100
–110
–120
–130
–100
–110
–120
OUTPUT NOISE
SPECTRAL DENSITY
INTEGRATED OUTPUT
NOISE
1
100
1
0.01
–0.5 0
3 3.5
4
–0.5
1.5
INPUT COMMON MODE VOLTAGE (V)
= 2V , V = 1.5V
3
0.5
INPUT COMMON MODE VOLTAGE (V)
= 2V , V = 2.5V
1
1.5
2
2.5
4.5 5
0
0.5
1
2
2.5
0.1
1
10
FREQUENCY (MHz)
660510 G10
V
V
660510 G09
660510 G08
IN
P-P OCM
IN
P-P OCM
BIAS = 3V, f = 3MHz
= 400Ω DIFFERENTIAL, GAIN = 1V/V
BIAS = 5V, f = 3MHz
R = 400Ω DIFFERENTIAL, GAIN = 1V/V
L
R
L
Channel Separation vs Frequency
Overdrive Transient Response
2.0
1.5
–20
–30
+
+OUT
BIAS = V
–OUT
–IN4
+IN4
BIAS = FLOAT
–40
1.0
–50
0.5
–60
0
–70
–80
–0.5
–1.0
–1.5
–2.0
–90
–100
–110
–120
50ns/DIV
= 1.5V
0.1
1
10
100
1000
FREQUENCY (MHz)
V
= 3V, V
OCM
S
660510 G12
660510 G11
V
= 1V , V = 3V
P-P S
= 400Ω DIFFERENTIAL
IN
L
BIAS = 3V, R
= 400Ω
LOAD
R
660510f
6
LTC6605-10
TEST CIRCUITS
I
LTC6605-10
400Ω
L
81.5pF
48.2pF
+
25Ω
V
–OUT
22
400Ω
125Ω
1
2
100Ω
+
+
21
20
19
V
V
INP
R
R
0.1μF
BAL
–
0.1μF
–
+
–
BIAS
3
BIAS
V
OUTCM
V
0.1μF
–
+
V
V
–
+
V
BAL
INM
48.2pF
36k
100Ω
400Ω
125Ω
400Ω
V
4
5
OCM
36k
0.01μF
–
I
L
81.5pF
25Ω
V
+OUT
18
660510 TC01
Figure 1. DC Test Circuit (Channel A Shown)
LTC6605-10
400Ω
1μF
81.5pF
100Ω
V
–OUT
22
1μF
400Ω
V
+IN
1
2
48.2pF
125Ω
100Ω
COILCRAFT
TTWB-4-B
+
21
20
19
V
0.1μF
0.1μF
+
+
–
+
50Ω
–
V
IN
BIAS
3
BIAS
V
–
0.1μF
–
+
V
V
48.2pF
36k
100Ω
400Ω
125Ω
400Ω
V
4
5
OCM
36k
0.01μF
1μF
–
V
–IN
1μF
81.5pF
100Ω
V
+OUT
18
660510 TC02
Figure 2. AC Test Circuit (Channel A Shown)
660510f
7
LTC6605-10
PIN FUNCTIONS
+IN4 A, –IN4 A, +IN4 ꢁ, –IN4 ꢁ (ꢃins 1, 3, 7, 11): Inputs
to Trimmed 400Ω Resistors. Can accept an input signal,
be floated, tied to an output pin, or connected to external
components.
V
, V
(ꢃins 19, 1ꢀ): The voltage applied to these
OCMA OCMꢁ
pins sets the output common mode voltage of each filter
channel. If left floating, V self-biases to a voltage
OCM
+
–
midway between V and V .
+
+
+IN1 A, –IN1 A, +IN1 ꢁ, –IN1 ꢁ (ꢃins 2, 4, 8, 10): Inputs
to Trimmed 100Ω Resistors. Can accept an input signal,
be floated, tied to an output pin, or connected to external
components.
V A, V ꢁ(ꢃins 21, 13):Positive Supply for Filter Channel
A and B, Respectively. These are not connected to each
other internally.
–OUT A, +OUT A, –OUT ꢁ, +OUT ꢁ (ꢃins 22, 18, 16,
12): Differential Output Pins.
ꢁIAS A, ꢁIAS ꢁ (ꢃins ꢀ, 9): Three-State Input to Select
Amplifier Power Consumption. Drive low for shutdown,
drive high for full power, leave floating for medium power.
BIAS presents an input resistance of approximately 150k
Eꢂposed ꢃad (ꢃin 2ꢀ): Always tie the underlying Exposed
–
Pad to V . If split supplies are used, do not tie the pad
to ground.
–
to a voltage 1.15V above V .
–
–
V (ꢃins 6, 14, 17, 20): Negative Supply. All V pins
should be connected to the same voltage, either a ground
plane or a negative supply rail.
660510f
8
LTC6605-10
BLOCK DIAGRAM
81.5pF
48.2pF
–OUT A
22
21
400Ω
100Ω
400Ω
125Ω
+IN4 A
+IN1 A
1
2
+
V
A
+
–
+
–
BIAS A
3
BIAS
20
19
V
V
–
+
V
A
48.2pF
36k
100Ω
400Ω
125Ω
400Ω
–IN1 A
–IN4 A
4
5
OCMA
36k
–
V
81.5pF
18 +OUT A
–
–
6
V
17
16
V
81.5pF
48.2pF
–OUT B
400Ω
100Ω
400Ω
125Ω
+IN4 B
+IN1 B
7
8
+
15
V
B
+
–
+
9
BIAS B
BIAS
–
14
13
V
V
–
+
V
B
48.2pF
36k
100Ω
400Ω
125Ω
400Ω
OCMB
–IN1 B
–IN4 B
10
11
36k
–
V
81.5pF
+OUT B
12
660510 BD
660510f
9
LTC6605-10
APPLICATIONS INFORMATION
Functional Description
capacitances should be decoupled with at least 25Ω of
series resistance from each output.
The LTC6605-10 is designed to make the implementation
of high frequency fully differential filtering functions very
easy. Two very low noise amplifiers are surrounded by
precisionmatchedresistorsandprecisionmatchedcapaci-
torsenablingvariousfilterfunctionstobeimplementedby
hard wiring pins. The amplifiers are wide band, low noise
andlowdistortionfullydifferentialamplifierswithaccurate
output phase balancing. They are optimized for driving
low voltage, single-supply, differential input analog-to-
digital converters (ADCs). The LTC6605-10 operates with
a supply voltage as low as 2.7V and accepts inputs up to
Filter Frequency Response and Gain Adjustment
Figure3showsthefilterarchitecture. TheLaplacetransfer
function can be expressed in the form of the following
generalized equation for a 2nd order lowpass filter:
VOUT(DIFF)
GAIN
=
,
s2
V
s
IN(DIFF)
1+
+
2
2πfO • Q
2πf
(
)
O
with GAIN, f and Q as given in Figure 3.
O
–
325mV below the V power rail, which makes it ideal for
Note that GAIN and Q of the filter are based on component
ratios, which both match and track extremely well over
converting ground referenced, single-ended signals into
differentialsignalsthatarereferencedtotheuser-supplied
common mode voltage. This is ideal for driving low volt-
age, single-supply, differential input ADCs. The balanced
differential nature of the amplifier and matched surround-
ing components provide even-order harmonic distortion
cancellation, and low susceptibility to common mode
noise (like power supply noise). The LTC6605-10 can be
operatedwithasingle-endedinputanddifferentialoutput,
or with a differential input and differential output.
temperature. The corner frequency f of the filter is a
O
function of an RC product. This RC product is trimmed to
1% and is not expected to drift by more than 1% from
nominal over the entire temperature range –40°C to 85°C.
As a result, fully differential filters with tight magnitude,
phase tolerance and repeatability are achieved.
Various values for resistors R1 and R4 can be formed
by pin-strapping the internal 100Ω and 400Ω resis-
tors, and optionally by including one or more external
resistors. Note that non-zero source resistance should be
combined with, and included in, R1.
The outputs of the LTC6605-10 can swing rail-to-rail.
They can source or sink a transient 70mA of current. Load
R2
400Ω
C2
81.5pF
R3
C1
R1
R1
125Ω
48.2pF
+
–
R4A
+
–
+
–
+
V
V
R
IN(DIFF)
OUT(DIFF)
EXT
–
R3
125Ω
R4B
C1
48.2pF
C2
81.5pF
R2
400Ω
R4 = R4A + R4B + R
EXT
660510 F03
Figure ꢀ. Filter Architecture and Equations
660510f
10
LTC6605-10
APPLICATIONS INFORMATION
Setting the passband gain (GAIN = R2/R1) only requires
choosing a value for R1, since R2 is a fixed internal 400Ω.
Therefore,thefollowingthreegainscanbeeasilyconfigured
without external components:
Figure 4 shows three filter configurations with an
–3dB
filters have a Q = 0.61, which is an almost ideal Bessel
characteristic with linear phase.
f
= 9.7MHz, without any external components. These
Figure 5 shows three filter configurations that use some
external resistors, and are tailored for a very flat 0.7dB
11.2MHz passband.
Taꢄle 1. Configuring the ꢃassꢄand Gain Without Eꢂternal
Components
GAIN
(V/V)
GAIN (dꢁ)
R1 (Ω)
INꢃUT ꢃINS TO USE
Manyotherconfigurationsarepossiblebyusingtheequa-
tions in Figure 3. For example, external resistors can be
added to modify the value of R1 to configure GAIN ≠ 1. For
an even more flexible filter IC with similar performance,
consider the LTC6601.
1
0
400
Drive the 400Ω Resistors. Tie
the 100Ω Resisters Together.
4
5
12
14
100
80
Drive the 100Ω Resistors.
Drive the 400Ω and 100Ω
Resistors in Parallel.
The resonant frequency, f , is independent of R1, and
ꢁIAS ꢃin
O
therefore independent of the gain. For any LTC6605-10
Each channel of the LTC6605-10 has a BIAS pin whose
functionistotailorbothperformanceandpower.TheBIAS
pin can be modeled as a voltage source whose potential
filter configuration that conforms to Figure 3, the f is
O
fixed at 11.36MHz. The f
frequency depends on the
combinationoff andQ.Foranyspecificgain,Qisadjusted
–3dB
–
O
is 1.15V above the V supply and that has a Thevenin
by the selection of R4.
equivalentresistanceof150k.Thisthree-statepinhasfixed
–
logiclevelsrelativetoV (seetheElectricalCharacteristics
Setting the f
Frequency
–ꢀdꢁ
table), and can be driven by any external source that can
drive the BIAS pin’s equivalent input impedance.
Using an external resistor (R ), the f
frequency is ad-
EXT
–3dB
justable in the range of 9.7MHz to 14.0MHz (see Figure 3).
The minimum f is set for R equal to 0Ω and the
If the BIAS pin is tied to the positive supply, the part is
in a fully active state configured for highest performance
(lowest noise and lowest distortion).
–3dB
EXT
maximum f
is arbitrarily set for a maximum passband
–3dB
gain peak less than 1dB.
If the BIAS pin is floated (left unconnected), the part is in a
fully active state, but with amplifier currents reduced and
per formance scaled back to preser ve power consumption.
Care should be taken to limit external leakage currents
to this pin to under 1μA to avoid putting the part in an
unexpected state.
Taꢄle 2. REXT Selection GAIN = 1,
R1 = 400ꢆ, R4A = R4ꢁ = 100ꢆ
f
(MHz)
R
Ω
EXT
–ꢀdꢁ
9.7
0
10
10.5
11
5.11
13.3
22.1
31.6
41.2
52.3
64.9
80.6
97.6
–
If the BIAS pin is tied to the most negative supply (V ),
the part is in a low power shutdown mode with amplifier
outputs disabled. In shutdown, all internal biasing current
sources are shut off, and the output pins each appear as
open collectors with a non-linear capacitor in parallel and
steeringdiodestoeithersupply. Becauseofthenon-linear
capacitance, the outputs can still sink and source small
amounts of transient current if exposed to significant
voltagetransients. Usingthisfunctiontowire-ORoutputs
together is not recommended.
11.5
12
12.5
13
13.5
14
660510f
11
LTC6605-10
APPLICATIONS INFORMATION
1
2
4
5
22
1
2
4
5
22
1
2
4
5
22
+
–
+
–
+
–
18
16
18
16
18
16
7
8
7
8
7
8
+
–
+
–
+
–
10
11
10
11
10
11
12
12
12
660510 F04c
660510 F04a
660510 F04b
f
= 9.7MHz
f
= 9.7MHz
f
= 9.7MHz
–3dB
–3dB
–3dB
GAIN = 5V/V (14dB)
= 160Ω
GAIN = 1V/V (0dB)
= 800Ω
GAIN = 4V/V (12dB)
Z = 200Ω
IN
Z
Z
IN
IN
Gain Response
Gain Response
Gain Response
20
10
20
10
20
10
0
0
0
–10
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
–20
–30
–40
–50
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
660510 G04d
660510 G04f
660510 G04e
ꢃhase and Group Delay Response
Small Signal Step Response
0
–20
25
20
15
10
5
GAIN = 1V/V
–40
–60
PHASE
–80
GROUP DELAY
–100
–120
–140
–160
–180
–200
100mV/DIV
0
0.1
1
10
100
1000
20ns/DIV
FREQUENCY (MHz)
660510 G04i
66057 G04j
Figure 4. f–ꢀdꢁ = 9.7MHz Filter Configurations without Eꢂternal Components
660510f
12
LTC6605-10
APPLICATIONS INFORMATION
1
2
4
5
22
1
2
4
5
22
1
2
4
5
22
44.2Ω
44.2Ω
44.2Ω
44.2Ω
+
–
+
–
+
88.7Ω
–
18
16
18
16
18
7
8
7
8
7
8
16
44.2Ω
44.2Ω
44.2Ω
44.2Ω
+
–
+
–
+
88.7Ω
10
11
10
11
10
11
–
12
12
12
660510 F05a
660510 F05b
660510 F05c
0.7dB 11.2MHz PASSBAND
GAIN = 1V/V (0dB)
0.7dB 11.2MHz PASSBAND
GAIN = 2.774V/V (8.9dB)
0.7dB 11.2MHz PASSBAND
GAIN = 3.774V/V (11.5dB)
Z
= 800Ω
Z
= 288Ω
Z
= 212Ω
IN
IN
IN
Gain Response
Gain Response
Gain Response
20
10
20
10
20
10
0
0
0
–10
–10
–20
–30
–40
–10
–20
–30
–40
–50
–20
–30
–40
–50
–50
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
660510 G05e
660510 G05d
660510 G05f
ꢃhase and Group Delay Response
Small Signal Step Response
0
–50
25
20
15
10
5
GAIN = 1V/V
GROUP DELAY
–100
–150
–200
–250
PHASE
100mV/DIV
0
1000
20ns/DIV
0.1
1
10
100
FREQUENCY (MHz)
660510 G05i
66057 G04j
Figure 3. Flat ꢃassꢄand 11.2MHz Filter Configurations with Some Eꢂternal Resistors
660510f
13
LTC6605-10
APPLICATIONS INFORMATION
Input Impedance
the ESD protection diodes on the input pins, neither input
–
should swing further than 325mV below the V power
Calculating the low frequency input impedance depends
on how the inputs are driven.
rail. Therefore, the input common mode voltage should
be constrained to:
Figure 6 shows a simplified low frequency equivalent
ꢂ
ꢅ
V
R1
circuit. For balanced input sources (V
= –V ), the
INDIFF
2
Vꢀ ꢀ 325mV +
• V+ ꢀ1.4V ꢀ
ꢁ V
ꢁ 1+
INP
INM
ꢄ
ꢇ
INCM
low frequency input impedance is given by the equation:
ꢃ
R2ꢆ
ꢂ
ꢅ
R
INP
= R = R1
R1
INM
V
ꢇ
OCM
ꢄ
(
)
ꢃR2ꢆ
Therefore, the differential input impedance is simply:
= 2 • R1
R
ThespecificationsintheElectricalCharacteristicstableare
a special case of the general equation above. For a single
IN(DIFF)
R2
+
–
R
INP
3V power supply, (V = 3V, V = 0V) with V
= 1.5V,
OCM
R1
–
V
+
OUT
ΔV
= 0.25V and R1 = R2, the valid input common
–
INDIFF
R3
R3
V
INP
+
–
mode range is:
–
–
V
OUTDIFF
–200mV ≤ V
≤ 1.7V
INCM
V
INM
R1
+
+
+
–
+
V
Likewise, for a single 5V power supply, (V = 5V, V = 0V)
OUT
R2
R
INM
V
with V
= 2.5V, ΔV
= 0.25V and R1 = R2, the
OCM
OCM
INDIFF
0.1μF
valid input common mode range is:
660510 F06
–200mV ≤ V ≤ 4.7V
INCM
Figure 6. Input Impedance
Output Common Mode and V
ꢃin
For single-ended inputs (V
= 0), the input impedance
OCM
INM
increases over the balanced differential case due to the
fact that the summing node (at the junction of R1, R2
The output common mode voltage is defined as the aver-
age of the two outputs:
and R3) moves in phase with V to bootstrap the input
INP
+
−
VOUT + VOUT
impedance. Referring to Figure 6 with V
impedance looking into either input is:
= 0, the input
INM
VOUTCM = VOCM =
2
R1
ꢁ
ꢃ
RINP = RINM
As the equation shows, the output common mode voltage
is independent of the input common mode voltage, and
ꢇ
ꢊ
ꢄ
1
R2
1ꢀ •
ꢆ
ꢌ
ꢉ
2 ꢂR1+R2ꢅ
ꢈ
ꢋ
is instead determined by the voltage on the V
means of an internal feedback loop.
pin, by
OCM
Input Common Mode Voltage Range
If the V
pin is left open, an internal resistor divider
OCM
The input common mode voltage is defined as the average
of the two inputs into resistor R1:
+
–
develops a potential halfway between the V and V volt-
ages. The V pin can be overdriven to another voltage
if desired. For example, when driving an ADC, if the ADC
OCM
V
INP + V
INM
V
=
INCM
2
makes a reference available for setting the common mode
voltage, it can be directly tied to the V
pin, as long as the
OCM
The input common mode range is a function of the filter
configuration (GAIN), V and the V potential.
ADCiscapableofdrivingtheinputimpedancepresentedby
theV pinaslistedintheElectricalCharacteristicstable
INDIFF
OCM
OCM
Referring to Figure 6, the summing junction where R1, R2
(R
).TheElectricalCharacteristicstablealsospecifies
VOCM
and R3 merge together should not swing within 1.4V of
the valid range that can be applied to the V
pin.
+
OCM
theV powersupply.Additionally,toavoidforwardbiasing
660510f
14
LTC6605-10
APPLICATIONS INFORMATION
Noise
the amplifier, the surrounding feedback resistors also
contribute noise. A noise model is shown in Figure 7a.
The output spot noise generated by both the amplifier
and the feedback components is given in Figure 7b.
When comparing the LTC6605-10’s noise to that of
other amplifiers, be sure to compare similar specifi-
cations. Standalone op amps often specify noise re-
ferred to the inputs of the op amp. The LTC6605-10’s
internal op amp has input referred voltage noise of
only 2.1nV/√Hz. In addition to the noise generated by
Substituting the equation for Johnson noise of a resistor
2
(e = 4kTR) into the equation in Figure 7b and simplify-
nR
ing gives the result shown in Figure 7c.
2
e
nR2
R2
2
e
e
nR1
nR1
R1
R1
+
2
I
n
2
2
2
e
e
e
ni
nR3
nR3
R3
+
–
2
e
no
R3
2
–
2
I
n
2
e
nR2
R2
660510 F07a
Figure 7a. Differential Noise Model
2
2
2
2
⎡
⎤
⎡
⎤
⎛
⎞
⎡
⎤
⎡
⎤
⎞
⎛
⎞
⎡
⎤
⎛
⎞
⎛
R2
R2
R1
R2
R1
R2
R1
2
eno
=
e • 1+
+ 2 • I • R2+R3 • 1+
+ 2 • e
•
+ 2 • e
• 1+
+ 2 • enR2
⎟⎥
⎢
⎥
⎜
⎟
⎢
⎜
⎟⎥
⎢
⎜
⎟⎥
⎢
⎜
ni
n
⎢
⎥
nR1
nR3
R1⎠
⎣
⎦
⎝
⎠
⎦
⎝
⎠
⎦
⎝
⎣
⎦
⎣
⎣
⎝
⎠
⎦
⎣
Figure 7ꢄ
2
2
2
⎡
⎢
⎤
⎡
⎤
⎞
⎤
⎡
⎤
⎛
⎛
⎞
⎡
⎛
⎞
⎛
+ R3 • 1+
⎞
R2
R2
R1
R2
R1
R2
⎥
eno
=
e • 1+
+ 2 • I • R2+R3 • 1+
+ 8 • k • T • R2 • 1+
⎢
⎥
⎟
⎜
⎢
⎜
⎟⎥
⎜
⎟
⎜
⎟
ni
n
⎢
⎥
R1⎠
⎣
⎦
⎠
⎦
⎢
⎝
⎠
⎝
⎠
R1 ⎥
⎦
⎝
⎣
⎦
⎝
⎣
⎣
Figure 7c
660510f
15
LTC6605-10
APPLICATIONS INFORMATION
ꢁoard Layout and ꢁypass Capacitors
At the output, always keep in mind the differential nature
of the LTC6605-10, because it is important that the load
impedances seen by both outputs (stray or intended) be
as balanced and symmetric as possible. This will help pre-
servethebalancedoperationthatminimizesthegeneration
of even-order harmonics and maximizes the rejection of
common mode signals and noise.
For single-supply applications it is recommended that a
highqualityX5RorX7R, 0.1μFbypasscapacitorbeplaced
+
–
–
directly between V and the adjacent V pin. The V pins,
including the Exposed Pad, should be tied directly to a low
impedance ground plane with minimal routing.
For split power supplies, it is recommended that addi-
tional high quality X5R or X7R, 0.1μF capacitors be used
Driving ADCs
+
–
to bypass pin V to ground and V to ground, again with
minimal routing.
The LTC6605-10’s rail-to-rail differential output and
adjustable output common mode voltage make it ideal
for interfacing to differential input ADCs. These ADCs
are typically supplied from a single-supply voltage
which can be as low as 3V (2.7V minimum), and have an
optimal common mode input range near mid-supply. The
LTC6605-10 makes interfacing to these ADCs easy, by
providing antialiasing, single-ended to differential conver-
sion and common mode level shifting.
For driving heavy differential loads (< 200Ω), additional
+
–
bypass capacitance may be needed between V and V for
optimal performance. Keep in mind that small geometry
(e.g.,0603)surfacemountceramiccapacitorshaveamuch
higher self-resonant frequency than do leaded capacitors,
and perform best in high speed applications.
The V
pins should be bypassed to ground with a high
OCM
The sampling process of ADCs creates a transient that is
caused by the switching in of the ADC sampling capaci-
tor. This momentarily “shorts” the output of the amplifier
as charge is transferred between amplifier and sampling
capacitor. The amplifier must recover and settle from this
loadtransientbeforetheacquisitionperiodhasended,fora
validrepresentationoftheinputsignal.TheLTC6605-10will
settle quickly from these periodic load impulses. The RC
network between the outputs of the driver decouples the
quality ceramic capacitor (at least 0.01μF). In split-sup-
ply applications, the V
ground or directly hard wired to ground.
pin can be either bypassed to
OCM
Stray parasitic capacitances to any unused input pins
should be kept to a minimum to prevent deviations from the
ideal frequency response. The best approach is to remove
the solder pads for the unused component pins and strip
away any ground plane underneath. Floating unused pins
does not reduce the reliability of the part.
660510f
16
LTC6605-10
APPLICATIONS INFORMATION
sampling transient of the ADC (see Figure 8). The capaci-
tance serves to provide the bulk of the charge during the
sampling process, while the two resistors at the outputs
of the LTC6605-10 are used to dampen and attenuate
any charge injected by the ADC. The RC filter gives the
additionalbenefitofbandlimitingbroadbandoutputnoise.
The selection of the RC time constant is trial and error
for a given ADC, but the following guidelines are recom-
mended. Choose an RC time constant that is smaller than
thereciprocalofthefiltercutofffrequencyconfiguredbythe
LTC6605-10.Timeconstantsontheorderof2nsdoagood
job of filtering broadband noise. Longer time constants
improve SNR at the expense of settling time. The resistors
inthedecouplingnetworkshouldbeatleast25Ω.Toolarge
of a resistor will leave insufficient settling time. Too small
of a resistor will not properly dampen the load transient
of the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require a
minimum of eleven RC time constants. The 10Ω resistors
at the inputs to the ADC minimize the sampling transients
that charge the RC filter capacitors. For lowest distortion,
choose capacitors with low dielectric absorption, such as
a C0G multilayer ceramic capacitor.
1/2 LTC6605-10
CONTROL
R
C1
1
2
3
4
5
22
21
20
19
18
+
V
D15
•
IN
•
–
3V
10Ω
+
D0
A
0.1μF
10nF
+
–
IN
1μF
C2
C1
10Ω
ADC
–
BIAS
A
IN
3.3V
V
GND
CM
V
1μF
OCM
2.2μF
R
CHANNEL A
660510 F08
τ = R • (C1 + 2 • C2)
Figure 8. Driving an ADC
660510f
17
LTC6605-10
TYPICAL APPLICATIONS
Dual, Matched, 4th Order 10MHz Lowpass Filter
LTC6605-10
LTC6605-10
1
2
22
1
2
4
5
22
+
–
+
–
V
182Ω
V
OUTA
INA
4
5
18
16
18
16
7
8
7
8
+
–
+
–
V
INB
182Ω
V
OUTB
10
11
10
11
12
12
660510 TA02
THREE GAINS ARE POSSIBLE,
AS SHOWN IN FIGURE 4
Gain Magnitude vs Frequency
10
0
–10
–20
–30
–40
–50
–60
–70
0.1
1
10
100
FREQUENCY (MHz)
660510 TA03
660510f
18
LTC6605-10
PACKAGE DESCRIPTION
DJC ꢃackage
22-Lead ꢃlastic DFN (6mm × ꢀmm)
(Reference LTC DWG # 05-08-1714)
0.889
NOTE:
0.70 0.05
1. DIMENSIONS ARE IN MILLIMETERS
2. APPLY SOLDER MASK TO AREAS THAT
ARE NOT SOLDERED
3. DRAWING IS NOT TO SCALE
R = 0.10
0.889
3.60 0.05
1.65 0.05
2.20 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
5.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.40 0.05
22
6.00 0.10
(2 SIDES)
TYP
0.889
12
R = 0.10
TYP
0.889
3.00 0.10
(2 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN #1 NOTCH
R0.30 TYP OR
11
1
0.25mm × 45°
0.25 0.05
CHAMFER
0.75 0.05
0.200 REF
0.50 BSC
5.35 0.10
(2 SIDES)
(DJC) DFN 0605
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
660510f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
19
LTC6605-10
TYPICAL APPLICATION
Dual Matched, ꢀrd Order 7.3MHz Lowpass Filter
LTC6605-10
301Ω
1
2
4
5
22
+
–
270pF
1%
V
INA
V
OUTA
301Ω
301Ω
18
16
7
8
+
–
270pF
1%
V
V
INB
OUTB
10
11
301Ω
12
660510 TA04
Gain Magnitude vs Frequency
10
0
–10
–20
–30
–40
–50
–60
–70
–80
0.1
1
10
100
FREQUENCY (MHz)
660510 TA05
RELATED PARTS
ꢃART NUMꢁER
LT1568
DESCRIꢃTION
4th Order Filter Building Block
COMMENTS
Lowpass and Bandpass Responses Up to 10MHz
1.5nV/√Hz Noise, –95dBc Distortion at 10MHz
LTC6404
Rail-to-Rail Output Differential Op Amp
LTC6406
3GHz Rail-to-Rail Input Differential Op Amp
1.6nV/√Hz Noise, –72dBc Distortion at 50MHz, 18mA
Cut-Off Frequencies of 2.5MHz/5MHz/10MHz/15MHz/20MHz
LT6600-2.5/LT6600-5/ Differential 4th Order Lowpass Filters
LT6600-10/LT6600-15/
LT6600-20
LTC6601
Differential Pin-Configurable 2nd Order Filter
Building Block
7MHz to 25MHz Pin-Configurable
LT6604-2.5/LT6604-5 Dual Differential 4th Order Lowpass Filters
Cut-Off Frequencies of 2.5MHz or 5MHz
660510f
LT 1208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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