LTC6800HMS8 [Linear]
Input and Output, Instrumentation Amplifier; 输入和输出，仪表放大器
| 型号： | LTC6800HMS8 |
| 厂家： | 
Linear |
| 描述： | Input and Output, Instrumentation Amplifier |
| 文件： | 总12页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6800
Rail-to-Rail
Input and Output,
Instrumentation Amplifier
U
FEATURES
DESCRIPTIO
■
116dB CMRR Independent of Gain
The LTC®6800 is a precision instrumentation amplifier.
The CMRR is typically 116dB with a single 5V supply and
is independent of gain. The input offset voltage is guaran-
teed below 100µV with a temperature drift of less than
250nV/°C. The LTC6800 is easy to use; the gain is adjust-
able with two external resistors, like a traditional op amp.
■
Maximum Offset Voltage: 100µV
■
Maximum Offset Voltage Drift: 250nV/°C
■
–40°C to 125°C Operation
■
Rail-to-Rail Input Range
■
Rail-to-Rail Output Swing
■
Supply Operation: 2.7V to 5.5V
The LTC6800 uses charge balanced sampled data tech-
niques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift
operational amplifier.
■
Available in an MS8 and 3mm × 3mm × 0.8mm
DFN Packages
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APPLICATIO S
The differential inputs operate from rail-to-rail and the
singleendedoutputswingsfromrail-to-rail. TheLTC6800
is available in an MS8 surface mount package. For space
limited applications, the LTC6800 is available in a
3mm × 3mm × 0.8mm dual fine pitch leadless package
(DFN).
■
Thermocouple Amplifiers
■
Electronic Scales
■
Medical Instrumentation
Strain Gauge Amplifiers
High Resolution Data Acquisition
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
High Side Power Supply Current Sense
Typical Input Referred Offset vs
Input Common Mode Voltage (VS = 3V)
1.5mΩ
15
V
REGULATOR
V
V
A
= 3V
REF
= 25°C
S
= 0V
10
5
T
–
2
3
8
OUT
7
100mV/A
OF LOAD
CURRENT
LTC6800
+
6
10k
0.1µF
5
0
4
G = 1000
G = 100
I
LOAD
LOAD
–5
–10
–15
G = 10
150Ω
G = 1
2.5
6800 TA01
0
1
1.5
2
3
0.5
INPUT COMMON MODE VOLTAGE (V)
6800 TA02
6800fa
1
LTC6800
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–) .............................. 5.5V
Input Current ...................................................... ±10mA
VIN+ – VREF ........................................................ 5.5V
VIN– – VREF ........................................................ 5.5V
Output Short Circuit Duration .......................... Indefinite
Operating Temperature Range
(Note 7) ................................................ –40°C to 125°C
Storage Temperature Range
MS8 Package ................................... –65°C to 150°C
DD Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
LTC6800HMS8
ORDER PART NUMBER
TOP VIEW
LTC6800HDD
+
NC
–IN
+IN
1
2
3
4
8
7
6
5
V
TOP VIEW
OUT
RG
REF
+
NC
–IN
+IN
1
2
3
4
8 V
7 OUT
6 RG
5 REF
–
V
MS8 PART MARKING
LTADE
DD PART MARKING
LAEP
–
V
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 200°C/W
TJMAX = 125°C, θJA = 160°C/W
UNDERSIDE METAL INTERNALLY
CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, REF = 200mV. Output voltage swing is referenced
to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER
CONDITIONS
= 200mV
MIN
TYP
MAX
UNITS
Input Offset Voltage (Note 2)
Average Input Offset Drift (Note 2)
V
±100
µV
CM
T = –40°C to 85°C
●
●
±250
–2.5
nV/°C
µV/°C
A
T = 85°C to 125°C
A
–1
Common Mode Rejection Ratio
(Notes 4, 5)
A = 1, V = 0V to 3V
●
90
113
dB
V
CM
Integrated Input Bias Current (Note 3)
Integrated Input Offset Current (Note 3)
Input Noise Voltage
V
V
= 1.2V
= 1.2V
4
1
10
3
nA
nA
CM
CM
DC to 10Hz
2.5
116
µV
P-P
Power Supply Rejection Ratio (Note 6)
Output Voltage Swing High
V = 2.7V to 5.5V
●
110
dB
S
–
R = 2k to V
R = 10k to V
●
●
2.85
2.95
2.94
2.98
V
V
L
–
L
Output Voltage Swing Low
Gain Error
●
20
0.1
100
mV
%
A = 1
V
Gain Nonlinearity
A = 1
V
ppm
6800fa
2
LTC6800
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, REF = 200mV. Output voltage swing is referenced
to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mA
Supply Current
No Load
●
1.2
Internal Op Amp Gain Bandwidth
Slew Rate
200
0.2
3
kHz
V/µs
kHz
Internal Sampling Frequency
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V,
V– = 0V, REF = 200mV. Output voltage swing is referenced to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER
CONDITIONS
= 200mV
MIN
TYP
MAX
UNITS
Input Offset Voltage (Note 2)
Average Input Offset Drift (Note 2)
V
±100
µV
CM
T = –40°C to 85°C
●
●
±250
–2.5
nV/°C
µV/°C
A
T = 85°C to 125°C
A
–1
Common Mode Rejection Ratio
(Notes 4, 5)
A = 1, V = 0V to 5V
●
90
116
dB
V
CM
Integrated Input Bias Current (Note 3)
Integrated Input Offset Current (Note 3)
Power Supply Rejection Ratio (Note 6)
Output Voltage Swing High
V
V
= 1.2V
= 1.2V
4
1
10
3
nA
nA
dB
CM
CM
V = 2.7V to 5.5V
●
110
116
S
–
R = 2k to V
R = 10k to V
●
●
4.85
4.95
4.94
4.98
V
V
L
–
L
Output Voltage Swing Low
Gain Error
●
20
0.1
100
1.3
mV
%
A = 1
V
Gain Nonlinearity
A = 1
V
ppm
mA
Supply Current
No Load
●
Internal Op Amp Gain Bandwidth
Slew Rate
200
0.2
3
kHz
V/µs
kHz
Internal Sampling Frequency
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
Note 6: The power supply rejection ratio (PSRR) measurement accuracy
depends on the proximity of the power supply bypass capacitor to the
device under test. Because of this, the PSRR is 100% tested to relaxed
limits at final test. However, their values are guaranteed by design to meet
the data sheet limits.
systems. V is measured to a limit determined by test equipment
OS
capability.
Note 7: The LTC6800H is guaranteed functional over the operating
temperature range of –40°C to 125°C. Specifications over the –40°C to
Note 3: If the total source resistance is less than 10k, no DC errors result
from the input bias currents or the mismatch of the input bias currents or
the mismatch of the resistances connected to –IN and +IN.
125°C range (denoted by
●) are assured by design and characterization
but are not tested or QA sampled at these temperatures.
Note 4: The CMRR with a voltage gain, A , larger than 10 is 120dB (typ).
V
Note 5: At temperatures above 70°C, the common mode rejection ratio
lowers when the common mode input voltage is within 100mV of the
supply rails.
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LTC6800
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TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage
vs Input Common Mode Voltage
Input Offset Voltage
vs Input Common Mode Voltage
Input Offset Voltage
vs Input Common Mode Voltage
15
10
5
15
10
5
20
15
V
V
T
= 3V
REF
= 25°C
V
V
T
= 5V
V
V
= 3V
REF
G = 10
S
S
S
= 0V
= 0V
REF
= 0V
= 25°C
A
A
10
G = 1000
5
0
0
0
G = 1000
G = 10
T
= 70°C
A
G = 100
G = 1
–5
–10
–15
–20
G = 100
G = 1
–5
–10
–15
–5
–10
–15
T
= 25°C
A
G = 10
T
= –55°C
A
0
1.0
1.5
2.0
2.5
3.0
0
2
3
4
5
0.5
1
0
1.0
1.5
2.0
2.5
3.0
0.5
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6800 G01
2053 G02
6800 G03
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
Input Offset Voltage
vs Input Common Mode Voltage
20
15
60
40
60
40
V
V
= 5V
REF
V
V
= 5V
S
= 0V
REF
V
V
= 3V
REF
S
S
= 0V
= 0V
G = 10
G = 10
G = 10
10
20
20
5
0
0
0
T
= 85°C
T
= 85°C
T
= 70°C
A
A
A
–5
–10
–15
–20
–20
–40
–60
–20
–40
–60
T
= 25°C
A
T
= 125°C
A
T
= 125°C
A
T
= –55°C
A
0
2
3
4
5
0
2
3
4
5
1
1
0
1.0
1.5
2.0
2.5
3.0
0.5
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6800 G04
6800 G06
6800 G05
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
Additional Input Offset Due to Input
RS Mismatch vs Input Common
Mode (CIN < 100pF)
30
20
50
40
60
40
V
V
R
C
= 5V
V
V
C
= 3V
V
V
R
C
= 3V
S
S
S
= 0V
= R
R
= 20k
= 0V
REF
= 0V
REF
S
REF
+
–
+
–
= R
+
–
R
–
= 0k, R = 15k
S
< 100pF
IN
= R = R
IN
IN
S
30
< 100pF
G = 10
T = 25°C
A
< 100pF
IN
IN
G = 10
G = 10
= 25°C
20
+
R
= 15k
R
= 0k, R = 10k
–
10
20
S
T
= 25°C
T
A
A
R
= 5k
S
+
10
R
+
= 0k, R = 5k
R
= 10k
S
R
= 0k
S
0
0
0
R
= 5k
S
–
–10
–20
–30
–40
–50
R
= 10k
R
+
= 5k, R = 0k
= 10k, R = 0k
S
+
–
–10
–20
–30
–20
–40
–60
R
R
= 15k
R
R
R
S
S
S
+
–
+
–
+
–
R
S
= 20k
SMALL C
SMALL C
R
SMALL C
R
IN
IN
IN
–
+
–
R
R
=15k, R = 0k
2.0 2.5 3.0
S
S
0
1.0
1.5
0.5
0
2
3
4
5
0
1.0
1.5
2.0
2.5
3.0
1
0.5
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6800 G09
6800 G08
6800 G07
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LTC6800
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Additional Input Offset Due to Input
RS Mismatch vs Input Common
Mode (CIN < 100pF)
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
40
30
40
30
70
50
+
–
V
V
= 3V
S
V
V
C
= 5V
REF
R
= 0k, R = 20k
IN
S
IN
+
R
S
= 10k
= 0V
REF
= 0V
+
–
–
R = 15k
S
R
= R = R
S
< 100pF
R
= 0k, R = 15k
IN
IN
IN
+
C
> 1µF
IN
G = 10
–
20
R
S
= 5k
20
R
+
= 0k, R = 10k
IN
R
= 10k
S
IN
G = 10
30
T
= 25°C
A
–
T
= 25°C
A
R
= 10k, R = 0k
IN
IN
10
10
R
S
= 1k
= 500Ω
R
= 5k
S
10
0
0
R
S
–10
–30
–50
–70
+
–
R
= 15k, R = 0k
IN
IN
R
–10
–20
–30
–40
–10
–20
–30
–40
V
V
= 5V
S
+
–
R
= 20k, R = 0k
+
IN
IN
R
S
R
= 0V
S
REF
+
–
R
C
= R = R
+
–
+
–
S
+
–
BIG C
R
BIG C
R
SMALL C
> 1µF
IN
IN
IN
IN
G = 10
–
T
= 25°C
A
R
S
S
0
1.0
1.5
2.0
2.5
3.0
0.5
0
2
3
4
5
0
2
3
4
5
1
1
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
6800 G11
6800 G12
6800 G10
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
Offset Voltage vs Temperature
200
150
100
50
80
60
200
150
100
50
V
V
T
= 3V
V
V
T
= 5V
S
S
= 0V
= 0V
REF
REF
= 25°C
G = 10
+
–
= 25°C
A
R
= 0Ω, R = 1k
+
–
–
A
R
= 0Ω, R = 1k
G = 10
40
+
–
+
R
= 0Ω, R = 500Ω
R
= 0Ω, R = 500Ω
+
–
R
= 0Ω, R = 100Ω
20
+
–
R
= 0Ω, R = 100Ω
0
0
0
+
–
+
–
V = 3V
S
R
= 100Ω, R = 0Ω
V = 5V
S
R
= 100Ω, R = 0Ω
–50
–100
–150
–200
–50
–20
–40
–60
–80
+
–
+
–
R
= 500Ω, R = 0Ω
R
= 500Ω, R = 0Ω
+
+
R
R
–100
–150
–200
+
–
+
–
+
–
+
–
R
= 1k, R = 0Ω
R
= 1k, R = 0Ω
BIG
C
BIG
C
IN
–
IN
–
R
R
0
1.0
1.5
2.0
2.5
3.0
0.5
1
2
4
–50 –25
0
25
50
75 100 125
0
5
3
INPUT COMMON MODE VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
6800 G13
6800 G14
6800 G15
VOS vs VREF
Gain Nonlinearity, G = 1
Gain Nonlinearity, G = 10
10
8
10
8
30
20
+
–
V
= V = REF
IN
V
V
= ±2.5V
REF
G = 1
= 10k
= 25°C
V
V
= ±2.5V
REF
G = 10
= 10k
= 25°C
IN
G = 10
= 25°C
S
S
= 0V
= 0V
T
A
6
6
R
T
R
T
L
L
4
4
A
A
10
2
2
0
0
0
V
= 5V
S
–2
–4
–6
–8
–10
–2
–4
–6
–8
–10
V
= 3V
S
–10
–20
–30
–2.4
–0.4
0.6
–2.4
–0.4
0.6 1.1
–1.4
1.6
2.6
0
2
3
4
–1.9 –1.4 –0.9
0.1
1.6
1
OUTPUT VOLTAGE (V)
V
(V)
OUTPUT VOLTAGE (V)
REF
6800 G18
6800 G17
6800 G16
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LTC6800
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Voltage Noise Density
vs Frequency
Input Referred Noise in 10Hz
Bandwidth
CMRR vs Frequency
120
120
110
100
90
300
250
200
150
100
50
3
2
V
V
T
= 3V, 5V
G = 10
A
S
= 1V
T
= 25°C
IN
P-P
= 25°C
A
+
–
R
= R = 1k
1
V
= 5V
= 3V
S
+
–
R
= R = 10k
0
V
S
+
–
–
R = 10k, R = 0Ω
+
R = 0Ω, R = 10k
–1
–2
–3
+
R
+
–
80
–
R
70
0
1
10
100
1000
1
10
100
FREQUENCY (Hz)
1000
10000
–5
–3
–1
1
3
5
FREQUENCY (Hz)
TIME (s)
6800 G19
6800 G20
6800 G21
Input Referred Noise in 10Hz
Bandwidth
Output Voltage Swing
vs Output Current
Supply Current vs Supply Voltage
3
2
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
T
= 25°C
V
S
= 5V, SOURCING
A
T
= 125°C
1
A
V
S
= 3V, SOURCING
T
A
= 85°C
0
–1
–2
–3
T
= 0°C
A
T
= –55°C
A
V
S
= 3V, SINKING
V
S
= 5V, SINKING
–5
–3
–1
1
3
5
0.01
1
10
2.5
3.5
4.5
5.5
6
0.1
TIME (s)
OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
6800 G22
6800 G23
6800 G24
Low Gain Settling Time
vs Settling Accuracy
Internal Clock Frequency
vs Supply Voltage
Settling Time vs Gain
35
30
25
20
15
10
5
8
3.40
3.35
3.30
3.25
3.20
3.15
3.10
V
= 5V
V
= 5V
OUT
S
S
dV
= 1V
dV
= 1V
OUT
0.1% ACCURACY
= 25°C
7
6
5
4
3
2
1
G < 100
= 25°C
T
A
T
A
T
= 125°C
A
T
= 85°C
A
T
= 25°C
A
T
= –55°C
A
0
0
0.01
SETTLING ACCURACY (%)
0.0001
0.001
0.1
1
10
100
1000
10000
2.5
3.5
4.5
5.5
6
GAIN (V/V)
SUPPLY VOLTAGE (V)
6800 G25
6800 G26
6800 G27
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LTC6800
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PI FU CTIO S
NC (Pin 1): Not Connected.
–IN (Pin 2): Inverting Input.
+IN (Pin 3): Noninverting Input.
V– (Pin 4): Negative Supply.
RG (Pin 6): Inverting Input of Internal Op Amp. With a
resistor, R2, connected between the OUT pin and the RG
pinandaresistor, R1, betweentheRGpinandtheREFpin,
the DC gain is given by 1 + R2 / R1.
OUT (Pin 7): Amplifier Output.
REF (Pin 5): VoltageReference(VREF)forAmplifierOutput.
V
OUT = GAIN (V+IN – V–IN) + VREF
V+ (Pin 8): Positive Supply.
W
BLOCK DIAGRA
8
+
V
+IN
3
+
OUT
7
C
S
C
H
–IN
2
–
–
REF
RG
V
5
6
4
6800 BD
6800fa
7
LTC6800
U
W
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APPLICATIO S I FOR ATIO
Theory of Operation
where V+IN and V–IN are the voltages of the +IN and –IN
pins respectively, VREF is the voltage at the REF pin and V+
is the positive supply voltage.
The LTC6800 uses an internal capacitor (CS) to sample a
differential input signal riding on a DC common mode
voltage (see Block Diagram). This capacitor’s charge is
transferred to a second internal hold capacitor (CH) trans-
lating the common mode of the input differential signal to
that of the REF pin. The resulting signal is amplified by a
zero-drift op amp in the noninverting configuration. The
RG pin is the negative input of this op amp and allows
external programmability of the DC gain. Simple filtering
can be realized by using an external capacitor across the
feedback resistor.
For example, with a 3V single supply and a 0V to 100mV
differential input voltage, VREF must be between 0V and
1.6V.
Settling Time
The sampling rate is 3kHz and the input sampling period
duringwhichCS ischargedtotheinputdifferentialvoltage
VIN is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to N
bits of accuracy at the op amp noninverting input after N
clock cycles or 333µs(N). The settling time at the OUT pin
is also affected by the settling of the internal op amp.
Since the gain bandwidth of the internal op amp is
typically 200kHz, the settling time is dominated by the
switched capacitor front end for gains below 100 (see
Typical Performance Characteristics).
Input Voltage Range
The input common mode voltage range of the LTC6800 is
rail-to-rail. However, the following equation limits the size
of the differential input voltage:
V– ≤ (V+IN – V–IN) + VREF ≤ V+ – 1.3
SINGLE SUPPLY, UNITY GAIN
5V
8
3
2
V
+
+IN
+
7
V
D
6
–
V
–IN
–
5
4
6800 F01
0V < V < 5V
+IN
0V < V < 5V
–IN
0V < V < 3.7V
D
V
OUT
= V
D
Figure 1
6800fa
8
LTC6800
U
W U U
APPLICATIO S I FOR ATIO
Input Current
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from nonzero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is less
sensitive to source resistance and source resistance mis-
match. When large capacitors are placed across the in-
puts,theinputchargingcurrentsdescribedaboveresultin
larger DC errors, especially with source resistor mis-
matches.
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results in
an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the –IN pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to RSCS. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors
due to source resistance or the source resistance mis-
match between –IN and +IN. With RS less than 10k, no
DC errors occur due to this input current.
Power Supply Bypassing
TheLTC6800usesasampleddatatechniqueandtherefore
contains some clocked digital circuitry. It is therefore sen-
sitivetosupplybypassing.A0.1µFceramiccapacitormust
beconnectedbetweenPin 8(V+)andPin4(V–)withleads
as short as possible.
6800fa
9
LTC6800
U
TYPICAL APPLICATIO S
Precision ÷2
5V
0.1µF
3
2
8
V
IN
+
7
LTC6800
V
OUT
6
–
5
4
V
2
IN
1k
V
=
OUT
0.1µF
6800 TA03
Precision Doubler (General Purpose)
2.5V
0.1µF
3
8
5
V
IN
+
7
LTC6800
V
OUT
2
6
–
4
V
= 2V
IN
OUT
0.1µF
0.1µF
6800 TA04
–2.5V
Precision Inversion (General Purpose)
2.5V
0.1µF
3
8
+
7
LTC6800
V
OUT
2
6
–
V
5
IN
4
V
= –V
IN
OUT
0.1µF
6800 TA05
–2.5V
6800fa
10
LTC6800
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.53 ± 0.152
(.021 ± .006)
0.52
(.0205)
REF
1.10
(.043)
MAX
0.86
(.034)
REF
8
7 6
5
0.889 ± 0.127
(.035 ± .005)
DETAIL “A”
0.18
(.007)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
SEATING
PLANE
4.90 ± 0.152
(.193 ± .006)
5.23
(.206)
MIN
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
1
2
3
4
0.65
(.0256)
BSC
0.42 ± 0.038
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
MSOP (MS8) 0603
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
PIN 1
TOP MARK
PACKAGE
OUTLINE
4
1
0.28 ± 0.05
0.75 ±0.05
0.200 REF
0.28 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. ALL DIMENSIONS ARE IN MILLIMETERS
(DD8) DFN 0203
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
6800fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC6800
U
TYPICAL APPLICATIO
Differential Bridge Amplifier
3V
0.1µF
R < 10k
8
2
–
7
OUT
LTC6800
3
6
+
R2 10k
5
4
0.1µF
R1
10Ω
R2
R1
GAIN = 1 +
6800 TA06
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6800fa
LT/TP 0903 1K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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