LTC6957-2_15 [Linear]
Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter;
| 型号： | LTC6957-2_15 |
| 厂家： | 
Linear |
| 描述： | Low Phase Noise, Dual Output Buffer/Driver/ Logic Converter |
| 文件： | 总36页 (文件大小：1390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual
Output Buffer/Driver/
Logic Converter
FeaTures
DescripTion
n
Low Phase Noise Buffer/Driver
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is
a family of very low phase noise, dual output AC signal
buffer/driver/logic level translators. The input signal can
n
Optimized Conversion of Sine Wave Signals to
Logic Levels
n
be a sine wave or any logic level (≤2V ). There are four
Three Logic Output Types Available
P-P
members of the family that differ in their output logic
signal type as follows:
– LVPECL
– LVDS
– CMOS
Additive Jitter 45fs
LTC6957-1: LVPECL Logic Outputs
n
(LTC6957-1)
RMS
LTC6957-2: LVDS Logic Outputs
n
n
n
n
n
Frequency Range Up to 300MHz
3.15V to 3.45V Supply Operation
Low Skew 3ps Typical
Fully Specified from –40°C to 125°C
12-Lead MSOP and 3mm × 3mm DFN Packages
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
with minimal additive noise, however, the part really ex-
cels at translating sine wave signals to logic levels. The
early amplifier stages have selectable lowpass filtering
to minimize the noise while still amplifying the signal to
increaseitsslewrate. Thisinputstagefiltering/noiselimit-
ing is especially helpful in delivering the lowest possible
phase noise signal with slow slewing input signals such
as a typical 10MHz sine wave system reference.
applicaTions
n
System Reference Frequency Distribution
n
High Speed ADC, DAC, DDS Clock Driver
n
Military and Secure Radio
Low Noise Timing Trigger
Broadband Wireless Transceiver
High Speed Data Acquisition
Medical Imaging
Test and Measurement
n
n
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents 7969189 and 8319551.
n
n
Typical applicaTion
3.3V
0.1µF
Additive Phase Noise at 100MHz
–140
SINGLE-ENDED SINE WAVE INPUT
AT +7dBm (500mV
)
RMS
+
V
SD1
FILTA = FILTB = GND
FILTA
–145
–150
–155
–160
–165
FILTB
TO PLL CHIPS
OR SYSTEM
SAMPLING CLOCKS
OUT1
100MHz
LTC6957-2 (LVDS)
LTC6957-4 (CMOS)
+7dBm
10nF
+
–
SINE WAVE
IN
IN
OCXO
50Ω
10nF
OUT2
LTC6957-3
(CMOS)
GND
SD2
LTC6957-1 (LVPECL)
1k 10k
OFFSET FREQUENCY (Hz)
6957 TA01a
100
100k
1M
69571234 TA01b
6957f
1
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
(Note 1)
absoluTe MaxiMuM raTings
+
Supply Voltage (V or V ) to GND..........................3.6V
Specified Temperature Range
DD
+
–
Input Current (IN , IN , FILTA, FILTB, SD1, SD2)
LTC6957I .............................................–40°C to 85°C
LTC6957H.......................................... –40°C to 125°C
Junction Temperature .......................................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (for MSOP Soldering, 10sec)...300°C
(Note 2) .......................................................... 10mA
LTC6957-1 Output Current ........................ 1mA, –30mA
LTC6957-2 Output Current ................................. 10mA
LTC6957-3, LTC6957-4 Output Current (Note 3).. 30mA
pin conFiguraTion
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
TOP VIEW
1
2
3
4
5
6
12 SD1
1
2
3
4
5
6
12 SD1
FILTA
FILTA
+
–
–
+
+
+
11
OUT1
11
V
DD
V
V
+
+
10 OUT1
10 OUT1
IN
IN
13
GND
13
GND
–
–
9
8
7
9
8
7
OUT2
OUT2
SD2
OUT2
IN
IN
GNDOUT
SD2
GND
GND
FILTB
FILTB
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 58°C/W, θ = 10°C/W
T
= 150°C, θ = 58°C/W, θ = 10°C/W
JMAX
JA
JC
JMAX JA JC
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
TOP VIEW
1
2
3
4
5
6
1
2
3
4
5
6
FILTA
12 SD1
11 OUT1
10 OUT1
FILTA
12 SD1
11
10 OUT1
+
+
–
–
+
+
V
IN
IN
V
IN
IN
V
DD
+
–
+
–
9
8
7
OUT2
OUT2
SD2
9
8
7
OUT2
GNDOUT
SD2
GND
FILTB
GND
FILTB
MS PACKAGE
12-LEAD PLASTIC MSOP
MS PACKAGE
12-LEAD PLASTIC MSOP
T
= 150°C, θ = 145°C/W
T = 150°C, θ = 145°C/W
JMAX JA
JMAX
JA
6957f
2
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
orDer inForMaTion
LEAD FREE FINISH
LTC6957IDD-1#PBF
LTC6957IDD-2#PBF
LTC6957IDD-3#PBF
LTC6957IDD-4#PBF
LTC6957IMS-1#PBF
LTC6957HMS-1#PBF
LTC6957IMS-2#PBF
LTC6957HMS-2#PBF
LTC6957IMS-3#PBF
LTC6957HMS-3#PBF
LTC6957IMS-4#PBF
LTC6957HMS-4#PBF
TAPE AND REEL
PART MARKING*
LFQJ
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
LTC6957IDD-1#TRPBF
LTC6957IDD-2#TRPBF
LTC6957IDD-3#TRPBF
LTC6957IDD-4#TRPBF
LTC6957IMS-1#TRPBF
LTC6957HMS-1#TRPBF
LTC6957IMS-2#TRPBF
LTC6957HMS-2#TRPBF
LTC6957IMS-3#TRPBF
LTC6957HMS-3#TRPBF
LTC6957IMS-4#TRPBF
LTC6957HMS-4#TRPBF
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead (3mm × 3mm) Plastic DFN
12-Lead Plastic MSOP
LFQK
–40°C to 85°C
LFQM
–40°C to 85°C
LFQN
–40°C to 85°C
69571
69571
69572
69572
69573
69573
69574
69574
–40°C to 85°C
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
–40°C to 85°C
12-Lead Plastic MSOP
12-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6957f
3
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-1
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.5
2.06
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
kΩ
pF
IN
C
Input Capacitance, Differential
0.5
IN
BW
Input Section Small Signal Bandwidth (–3dB)
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (LVPECL)
+
+
+
+
+
+
l
l
V
V
V
Output High Voltage
LTC6957I
LTC6957H
V – 1.22 V – 0.98 V – 0.93
V
V
OH
OL
OD
V – 1.22 V – 0.98 V – 0.87
+
+
+
+
+
+
l
l
Output Low Voltage
LTC6957I
LTC6957H
V – 2.1 V – 1.8 V – 1.67
V
V
V – 2.1 V – 1.8 V – 1.62
l
Output Differential Voltage
Output Rise Time
660
810
180
160
965
mV
ps
t
t
t
r
f
Output Fall Time
ps
l
l
l
l
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.35
0.5
0.6
1.1
3.2
0.7
0.8
1.3
4
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
PD
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.1
0.1
0.11
0.15
ps/°C
ps/°C
ps/°C
ps/°C
l
l
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
4
3
50
30
30
ps/V
ps
PD
t
t
Output Skew, Differential, CH1 to CH2
SKEW
+
–
Output Matching (OUTx to OUTx )
See Timing Diagram
2.5
ps
MATCH
Power
+
+
+
l
V
V Operating Supply Voltage Range
R
LOAD
= 50Ω to (V – 2V)
3.15
3.3
3.45
V
I
S
Supply Current
l
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
No Output Loads
18
15
0.7
58
22
19
1.2
72
mA
mA
mA
mA
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L) No Output Loads
Both Outputs Disabled (SD1 = SD2 = H)
Including Output Loads
No Output Loads
+
R
LOAD
= 50Ω to (V – 2V), ×4
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
40
120
20
µs
µs
µs
µs
ENABLE
WAKEUP
DISABLE
SLEEP
20
6957f
4
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-1
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
V
High Level SD or FILT Input Voltage
Low Level SD or FILT Input Voltage
Input Current SD or FILT Pins
V – 0.4
V
V
IH
0.4
10
IL
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
f
f
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
at 10Hz Offset
IN
IN
IN
–130
–140
–150
–157
–157.5
–157.5
123
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
45
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
at 10Hz Offset
–137
–146
–154.6
–157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
–157.2
–157.2
200
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
114
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
at 10Hz Offset
–138
–148.1
–156.8
–160.6
–161
–161
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
90
6957f
5
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-2
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.5
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
2
kΩ
pF
IN
IN
C
Input Capacitance, Differential
Input Section Small Signal Bandwidth
0.5
BW
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (LVDS)
Output Differential Voltage
Delta V
l
l
l
l
l
V
250
360
0.2
450
50
mV
mV
V
OD
∆V
OD
OD
V
Output Offset Voltage
Delta V
1.125
1.25
1.5
1.375
50
OS
∆V
mV
mA
ps
OS
OS
I
t
t
t
Short-Circuit Current
Output Rise Time
Output Fall Time
3.9
6
SC
170
170
r
ps
f
l
l
l
l
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.65
0.84
0.9
1.35
3.5
1.15
1.3
1.8
4.4
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
PD
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.5
0.6
0.7
1.8
ps/°C
ps/°C
ps/°C
ps/°C
l
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
5
3
60
50
ps/V
ps
PD
t
Output Skew, Differential, CH1 to CH2
SKEW
Power
+
+
l
V
V Operating Supply Voltage Range
3.15
3.3
3.45
V
I
Supply Current
S
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
38
26
0.7
45
30
1.2
mA
mA
mA
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
300
400
40
ns
ns
ns
ns
ENABLE
WAKEUP
DISABLE
SLEEP
50
6957f
6
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-2
The ldenotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
High Level SD or FILT Input Voltage
Low Level SD or FILT Input Voltage
Input Current SD or FILT Pins
V – 0.4
V
V
IH
V
IL
0.4
10
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
IN
f
IN
f
IN
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
–124
–134
–143.5
–151.3
–154
–154
183
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
67
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
–132.5
–142.5
–150.7
–156
–157
–157
203
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
116
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
–132
–142
–151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
–157.5
–159.5
–159.5
169
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
RMS
fs
RMS
107
6957f
7
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
–
+
Inputs (IN , IN )
l
l
l
f
Input Frequency Range
300
2
MHz
IN
V
V
Input Signal Level Range, Single-Ended
Input Signal Level Range, Differential
Minimum Input Pulse Width
0.2
0.2
0.8
0.8
0.6
2
V
V
INSE
INDIFF
MIN
P-P
2
P-P
t
High or Low
ns
+
–
l
l
V
Self-Bias Voltage, IN , IN
1.8
1.5
2.3
2.5
V
INCM
R
Input Resistance, Differential
2
kΩ
pF
IN
IN
C
Input Capacitance, Differential
Input Section Small Signal Bandwidth
0.5
BW
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1200
500
160
50
MHz
MHz
MHz
MHz
IN
Outputs (CMOS)
l
l
V
OH
Output High Voltage
No Load
–3mA Load
V
DD
V
DD
– 0.1
– 0.2
V
V
l
l
V
OL
Output Low Voltage
No Load
3mA Load
0.1
0.2
V
V
t
t
t
Output Rise Time
Output Fall Time
Propagation Delay
320
300
ps
ps
r
f
l
l
l
l
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
0.8
0.95
1
1.5
3.6
1.6
1.8
2.4
4.8
ns
ns
ns
ns
PD
l
l
l
l
∆t /∆T Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
1.7
1.7
2
ps/°C
ps/°C
ps/°C
ps/°C
PD
3
+
l
∆t /∆V Propagation Delay Variation vs Supply Voltage
PD
FILTB = FILTA = L, V = V
100
200
ps/V
DD
t
Output Skew, CH1 to CH2
LTC6957-3
LTC6957-4
SKEW
l
l
5
120
35
250
ps
ps
Power
+
+
l
l
V
V Operating Supply Voltage Range
3.15
2.4
3.3
3.3
3.45
3.45
V
V
+
V
V
Operating Supply Voltage Range
V
Must Be ≤V
DD
DD
DD
I
Supply Current, Pin 2
S
l
l
l
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
24
24
0.7
27.5
27.5
1.2
mA
mA
mA
l
l
I
Supply Current, Pin 11, No Load
Static
Dynamic, per Output
0.001
0.056
0.01
0.07
mA
mA/MHz
DD
t
t
t
t
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
200
300
20
ns
ns
ns
ns
ENABLE
WAKEUP
DISABLE
SLEEP
20
6957f
8
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
elecTrical characTerisTics LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD/2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
Digital Logic Inputs
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
l
l
V
V
High Level SD or Filt Input Voltage
Low Level SD or Filt Input Voltage
Input Current SD or Filt Pins
V – 0.4
V
V
IH
0.4
10
IL
I
0.1
µA
IN_DIG
Additive Phase Noise and Jitter
f
IN
f
IN
f
IN
= 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
–123
–133
–143
–152
–156
–156
146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
53
= 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
–132
–142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
–150.6
–156.5
–157.4
–157.4
192
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
109
= 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
–135
–145
–153
–159.8
–161
–161
142
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
fs
fs
RMS
RMS
90
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins IN , IN , FILTA, FILTB, SD1 and SD2 are protected by
steering diodes to either supply. If the inputs go beyond either supply rail,
the input current should be limited to less than 10mA. If pushing current
into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins
(FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies
only at the maximum operating supply voltage of 3.45V; 10mA of input
current with the absolute maximum supply voltage of 3.6V may create
permanent damage from voltage stress.
Note 3: With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA
while high without damage. However, if overdriven or subject to an
inductive load kick outside the supply rails, 30mA can create damaging
+
–
voltage stress and is not guaranteed unless V is limited to 3.15V.
DD
6957f
9
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-1
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
2.20
2.15
2.10
2.05
2.00
1.95
1.90
20
18
16
14
12
10
8
18.6
18.8
18.4
18.2
18.0
17.8
17.4
17.2
17.0
16.8
16.6
+
NO OUTPUT LOADS
NO OUTPUT LOADS
V
= 3.45V
= 3.3V
+
T
A
= 125°C
V
= 3.45V
V
+
V
= 3.3V
+
V
+
= 3.15V
T
= –55°C
A
T
= 25°C
A
+
V
= 3.15V
6
4
2
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
69571234 G03
69571234 G01
69571234 G02
Output Voltage vs Load Current
Output Voltage vs Temperature
Supply Current vs Temperature
2.4
2.2
1.6
1.4
2.55
2.50
2.45
2.40
2.35
2.30
1.60
1.55
1.50
1.45
1.40
1.35
58
56
54
52
50
48
46
+
V
= 3.3V
50Ω LOADS TO 1.3V
+
V
= 3.45V
V
OH
V
OH
+
V
= 3.3V
+
V
= 3.15V
V
OL
V
OL
50Ω “Y” LOAD TO GROUND
ON BOTH CHANNELS
–55 –35 –15
5
25 45 65 85 105 125
–10
–8
–6
–4
–2
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
LOAD CURRENT (mA)
TEMPERATURE (°C)
69571234 G05
69571234 G04
69571234 G06
Enable and Wakeup
Typical Distribution of Skew
Differential Output vs Frequency
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5V
2.0V
1.5V
2.5V
2.0V
1.5V
3.0V
0V
100
80
60
40
20
0
OUT1+ TO OUT2+ RISING EDGE
TYPICAL OF ALL OUTPUT EDGES/PAIRS
WAKE-UP:
OUTPUTS WITH
OTHER CHANNEL OFF
2 LOTS, 400
UNITS EACH,
3 TEMPERATURES
= 125°C
125°C
= 25°C
= –55°C
25°C
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
SD
–55°C
69571234 G07
20ns/DIV
0dBm INPUT
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
–10 –8 –6 –4 –2
0
2
4
6
0
250 500 750 1000 1250 1500 1750
FREQUENCY (MHz)
8
10
2000
t
(ps)
SKEW
69571234 G08
PRODUCTION DATA,
1ps RESOLUTION, ~1-2ps UNCERTAINTY
69571234 G09
6957f
10
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-1
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
–130
–130
–135
–140
–145
–150
–155
–160
–165
–130
–135
–140
–145
–150
–155
–160
–165
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mV
FILTA = FILTB = L
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
SINGLE-ENDED SINE WAVE INPUT,
)
100MHz at 7dBm (500mV
FILTA = FILTB = L
)
RMS
RMS
–135
–140
–145
–150
–155
–160
–165
–10dBm, FILTA = L, FILTB = H
0dBm, FILTA = H, FILTB = L
300MHz
125°C
153.6MHz
25°C
100MHz
+10dBm, FILTA = FILTB = L
–55°C
10k
OFFSET FREQUENCY (Hz)
100
1k
10k
100k
1M
100
1k
10k
100k
1M
100
1k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
69571234 G10
69571234 G11
69571234 G12
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
–130
–135
–140
–145
–150
–155
–160
–165
5
4
–130
–135
–140
–145
–150
–155
–160
–165
f
= 300MHz
= 3.3V
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT
IN
+
V
100MHz at 7dBm (500mV
FILTA = FILTB = L
)
RMS
3
2
1
–55°C
0
0dBm, FILTA = H, FILTB = L
–1
–2
–3
–4
–5
3.45V
3.15V
3.3V
125°C
25°C
7dBm, FILTA = FILTB = L
100 1k 10k
EACH CURVE NORMALIZED TO 0° AT 0dBm
–10 –8 –6 –4 –2 10
100
1k
10k
100k
1M
0
2
4
6
8
100k
OFFSET FREQUENCY (Hz)
1M
OFFSET FREQUENCY (Hz)
INPUT AMPLITUDE (dBm)
69571234 G13
69571234 G15
69571234 G14
tPD vs Supply Voltage and
Termination Voltage
tPD vs Temperature
tPD vs Temperature
0.550
0.525
0.500
0.475
0.450
3.5
3.0
1.0
0.5
0
0.56
0.54
0.52
0.50
0.48
0.46
+
V
= 3.0V, 50Ω LOADS TO 1.3V
FILTA = FILTB = H
+
V
= 3.6V, 50Ω LOADS TO 1.9V
+
50Ω LOADS TO V –2V
FILTA = L, FILTB = H
+
V
= 3.3V, 50Ω LOADS TO 1.3V
FILTA = H, FILTB = L
FILTA = FILTB = L
50Ω LOADS TO FIXED 1.3V
FILTA = FILTB = L
FILTA = FILTB = L
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
3
3.1
3.2
3.3
3.4
3.5
3.6
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
69571234 G17
69571234 G16
69571234 G18
6957f
11
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-2
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
2.20
2.15
2.10
2.05
2.00
1.95
1.90
45
40
35
30
25
20
15
10
5
41.0
40.5
40.0
39.5
39.0
38.5
38.0
37.5
+
V
= 3.45V
+
V
= 3.45V
+
V
= 3.3V
+
T
= 125°C
V
= 3.3V
A
T
= 25°C
A
+
V
= 3.15V
+
V
= 3.15V
T
= –55°C
A
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
SUPPLY VOLTAGE (V)
3
3.3 3.6
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G19
69571234 G20
69571234 G21
Output Voltages vs Load Resistor
Output Voltages vs Temperature
Output Voltages vs Loading
1.5
1.4
1.3
1.2
1.1
1.0
430
420
410
400
390
380
1.8
1.6
1.4
1.2
1.0
0.8
1.5
1.4
1.3
1.2
1.1
1
DC DATA,
+
–
IN > (IN + 50mV)
V
(MEASURED)
OH
125°C
25°C
–55°C
+
OUT
+
OUT
V
(CALCULATED)
(CALCULATED)
OS
V
OD
–
–
OUT
OUT
+
+
+
V
V
V
= 3.6V
= 3.3V
= 3V
V
(MEASURED)
OL
LOAD STRESS PER TIA/EIA-644-A FIGURE 4
0.6 1.2 1.8
LOAD VOLTAGE (V)
–55 –35 –15
5
25 45 65 85 105 125
0
50
100
150
200
250
0
2.4
TEMPERATURE (°C)
LOAD RESISTOR (Ω)
V
TEST
USE OF R
> 150Ω
69571234 G23
69571234 G22
69571234 G24
LOAD
NOT RECOMMENDED
f
MAY BE COMPROMISED
IN
Output Short-Circuit Current
vs Temperature
Enable and Wakeup
Differential Output vs Frequency
4.00
900
800
700
600
500
400
300
200
100
0
WAKE-UP:
2.0V
1.5V
1.0V
2.0V
1.5V
1.0V
–55°C
OUTPUTS WITH
OTHER
+
V
= 3.45V
3.95
3.90
3.85
3.80
3.75
+
CHANNEL OFF
V
= 3.3V
25°C
125°C
+
V
= 3.15V
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
3.0V
0V
SD
10dBm INPUT
69571234 G25
FILTA = FILTB = L
20ns/DIV
ANY ONE (1) OUTPUT
SHORTED TO GROUND
R
LOAD
= 100Ω
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
SD DRIVE ~ 140kHz, ASYNCHRONOUS
–55 –35 –15
5
25 45 65 85 105 125
0
200
400
600
800 1000 1200
TEMPERATURE (°C)
FREQUENCY (MHz)
69571234 G26
69571234 G27
6957f
12
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-2
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
–130
–130
–135
–140
–145
–150
–155
–160
–165
–130
–135
–140
–145
–150
–155
–160
–165
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mV
FILTA = FILTB = L
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
100MHz AT 7dBm (500mV
FILTA = FILTB = L
)
RMS
)
–135
–140
–145
–150
–155
–160
–165
RMS
–10dBm, FILTA = L, FILTB = H
0dBm, FILTA = H, FILTB = L
153.6MHz
300MHz
25°C
125°C
–55°C
100MHz
10dBm, FILTA = FILTB = L
100
1k
10k
100k
1M
100
1k
10k
100k
1M
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
69571234 G30
69571234 G28
69571234 G29
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
–130
–135
–140
–145
–150
–155
–160
–165
–130
–135
–140
–145
–150
–155
–160
–165
5
4
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT
f
= 300MHz
= 3.3V
IN
+
100MHz AT 7dBm (500mV
FILTA = FILTB = L
)
V
RMS
3
2
1
3.45V
–55°C
0
–1
–2
–3
–4
–5
25°C
0dBm, FILTA = H, FILTB = L
7dBm, FILTA = FILTB = L
3.3V
3.15V
125°C
EACH CURVE NORMALIZED TO 0° AT 0dBm
–10 –8 –6 –4 –2
INPUT AMPLITUDE (dBm)
100
1k
10k
100k
1M
100
1k
10k
100k
1M
0
2
4
6
8
10
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
69571234 G31
69571234 G32
69571234 G33
tPD vs Temperature
tPD vs Temperature
tPD vs Supply Voltage
0.96
0.94
0.92
0.90
0.88
0.86
0.84
4.0
3.0
1.5
1.0
0.5
0.950
0.925
0.900
0.875
0.850
0.825
FILTA = FILTB = L
100Ω LOAD
FILTA = FILTB = H
+
V
= 3.0V
125°C
+
V
= 3.6V
25°C
FILTA = L, FILTB = H
+
V
= 3.3V
FILTA = H, FILTB = L
FILTA = FILTB = L
FILTA = FILTB = L
100Ω LOAD
–55°C
100Ω LOAD
3
3.1
3.2
3.3
3.4
3.5
3.6
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105
125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
69571234 G36
69571234 G34
69571234 G35
6957f
13
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-3/LTC6957-4
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
2.20
2.15
2.10
2.05
2.00
1.95
1.90
25
20
15
10
5
21.5
21.0
20.5
20.0
19.5
+
V
= 3.45V
= 3.3V
+
V
= 3.45V
+
V
25°C
+
V
= 3.3V
+
V
= 3.15V
125°C
+
V
= 3.15V
–55°C
2.4
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
0.6
3
–35
25
TEMPERATURE (°C)
85 105
125
0
1.2
1.8
3.6
–55
–15
5
45 65
+
V
VOLTAGE (V)
69571234 G37
69571234 G38
69571234 G39
Additive Phase Noise
vs Supply Voltage
Output Voltages vs Load Current
Output Voltages vs Load Current
V
V
DD
DD
–130
–135
–140
–145
–150
–155
–160
–165
SINGLE-ENDED SINE WAVE INPUT,
100MHz at 7dBm (500mV
OUTPUT HIGH,
SOURCING CURRENT
)
RMS
–55°C
125°C
V
–0.25
–0.5
V
–0.25
–0.5
+
25°C
DD
DD
V
= 3.3V, V AS SHOWN
DD
OUTPUT HIGH,
SOURCING CURRENT
FILTA = FILTB = L
V
V
DD
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3.6V
= 3.3V
= 3V
= 2.7V
= 2.4V
2.4V
V
–0.75
0.50
0.25
0
V
–0.75
0.50
0.25
0
V
= 3.3V
DD
DD
DD
2.7V
125°C
–55°C
OUTPUT LOW,
SINKING CURRENT
3.0V
3.3V
25°C
OUTPUT LOW,
SINKING CURRENT
0
5
10
15
20
0
5
10
15
20
100
1k
10k
100k
1M
LOAD CURRENT (mA)
LOAD CURRENT (mA)
OFFSET FREQUENCY (Hz)
69571234 G40
69571234 G41
69571234 G42
Output Voltage Swing
vs Frequency
Supply Current vs Supply Voltage
Supply Current vs Temperature
3.0
2.5
2.0
1.5
1
5
21
20
19
18
17
100
10
+
V
= V = 3.3V
DD
125°C
4
3
2
1
0
–55°C
25°C
CAUTION: AT VERY
HIGH FREQUENCIES,
THE CMOS OUTPUTS
MAY NOT TOGGLE
AT ALL DEPENDING
ON INPUT FREQ-
UENCY, AMPLITUDE,
SUPPLY VOLTAGE,
OR TEMPERATURE
DYNAMIC, ONE (1)
OUTPUT ACTIVE AT 312.5MHz,
13pF LOAD, LEFT AXIS
1
OTHER OUTPUT DISABLED
10dBm INPUT
FILTA = FILTB = L
IN DC1766A
0.1
0.01
–55°C
25°C
STATIC, NO DC LOAD,
RIGHT (LOGARITHMIC)
AXIS
125°C
R
LOAD
= 133Ω AC-COUPLED
0
100 200 300 400 500 600 700 800 9001000
FREQUENCY (MHz)
0
0.6
1.2
V
1.8
2.4
3
3.6
–55 –35 –15
5
25 45 65 85 105 125
VOLTAGE (V)
TEMPERATURE (°C)
DD
69571234 G45
69571234 G43
69571234 G44
6957f
14
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical perForMance characTerisTics
LTC6957-3/LTC6957-4
Additive Phase Noise
vs Input Frequency
Additive Phase Noise
vs Amplitude
Additive Phase Noise
vs Temperature
–130
–130
–135
–140
–145
–150
–155
–160
–165
–130
–135
–140
–145
–150
–155
–160
–165
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mV
FILTA = FILTB = L
100MHz AT 7dBm (500mV
FILTA = FILTB = L
)
)
RMS
RMS
–135
–140
–145
–150
–155
–160
–165
300MHz
–10dBm, FILTA = L, FILTB = H
0dBm, FILTA = H, FILTB = L
153.6MHz
25°C
100MHz
125°C
–55°C
10dBm, FILTA = FILTB = L
100
1k
10k
100k
1M
100
1k
10k
100k
1M
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
69571234 G47
69571234 G48
69571234 G46
Additive Phase Noise
vs Supply Voltage
Additive Phase Noise at 122.88MHz
AM to PM Conversion
–130
–135
–140
–145
–150
–155
–160
–165
–130
–135
–140
–145
–150
–155
–160
–165
5
4
EACH CURVE NORMALIZED TO 0° AT 0dBm
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT
f
= 300MHz
100MHz AT 7dBm (500mV
)
IN
RMS
+
+
V = V = 3.3V
DD
V
= V
DD
3
FILTA = FILTB = L
2
1
0
3.15V
0dBm, FILTA = H, FILTB = L
–55°C
–1
–2
–3
–4
–5
3.45V
100k
25°C
125°C
7dBm, FILTA = FILTB = L
3.3V
100
1k
10k
1M
100
1k
10k
100k
1M
–10 –8 –6 –4 –2
0
2
4
6
8
10
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
INPUT AMPLITUDE (dBm)
69571234 G49
69571234 G50
69571234 G51
tPD vs Temperature
tPD vs Temperature
tPD vs Supply Voltage
4.0
3.0
1.5
1.0
0.5
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1.06
1.04
1.02
1.00
0.98
0.96
0.94
FILTA = FILTB = H
+
V
= 3.45V
RISING EDGE
FILTA = L, FILTB = H
FILTA = H, FILTB = L
+
V
= V
DD
FALLING EDGE
FILTA = FILTB = L
RISING EDGE
2.4 2.55 2.7 2.85
SUPPLY VOLTAGE (V)
FILTA = FILTB = L
25 45 65 85 105 125
TEMPERATURE (°C)
FALLING EDGE
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
3
3.15 3.3 3.45 3.6
TEMPERATURE (°C)
V
DD
69571234 G52
69571234 G53
69571234 G54
6957f
15
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
pin FuncTions
FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting
Control. These CMOS logic inputs control the bandwidth
of the early amplifier stages. For slow slewing signals
substantially lower phase noise is achieved by using this
feature. SeetheApplicationsInformationsectionformore
details.
LTC6957-2 Only
–
+
OUT1 , OUT1 (Pin 10, Pin 11): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications Infor-
mation section for more details.
–
+
OUT2 , OUT2 (Pin 9, Pin 8): LVDS Outputs, Mostly TIA/
EIA-644-ACompliant.RefertotheApplicationsInformation
section for more details.
+
V (Pin 2): Supply Voltage (3.15V to 3.45V). This sup-
ply must be kept free from noise and ripple. It should be
bypassed directly to GND (Pin 5) with a 0.1µF capacitor.
LTC6957-3/LTC6957-4 Only
+
–
IN , IN (Pin 3, Pin 4): Input Signal Pins. These inputs
are differential, but can also interface with single-ended
signals. The input can be a sine wave signal or a CML,
LVPECL, TTL or CMOS logic signal. See the Applications
Information section for more details.
OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the
Applications Information section for more details.
V
DD
(Pin 11): Output Supply Voltage (2.4V to 3.45V). For
+
best performance connect this to the same supply as V
(Pin 2). If the output needs to be a lower logic rail, this
supply can be separately connected, but this voltage must
be less than or equal to that on Pin 2 for proper operation.
This supply must also be kept free from noise and ripple.
It should be bypassed directly to the GNDOUT pin (Pin 8)
with a 0.1µF capacitor.
GND (Pin 5): Ground. Connect to a low inductance ground
plane for best performance. The connection to the bypass
+
capacitor for V (Pin 2) should be through a direct, low
inductance path.
SD1, SD2 (Pin 12, Pin 7): Output Enable Control. These
CMOS logic inputs control the enabling and disabling of
their respective OUT1 and OUT2 outputs. When both out-
puts are disabled, the LTC6957 is placed in a low power
shutdown state.
GNDOUT (Pin 8): Output Logic Ground. Tie to a low
inductance ground plane for best performance. The con-
nection to the bypass capacitor for V (Pin 11) should
DD
be through a direct, low inductance path.
LTC6957-1 Only
LTC6957-xDD Only
–
+
OUT1 ,OUT1 (Pin10,Pin11):LVPECLOutputs.Differential
Exposed Pad (Pin 13): Always tie the underlying DFN
logic outputs typically terminated by 50Ω connected to a
exposed pad to GND (Pin 5). To achieve the rated θ of
JA
+
supply 2V below the V supply. Refer to the Applications
the DD package, there should be good thermal contact
Information section for more details.
to the PCB.
–
+
OUT2 ,OUT2 (Pin9,Pin8):LVPECLOutputs.Differential
logic outputs typically terminated by 50Ω connected to a
+
supply 2V below the V supply. Refer to the Applications
Information section for more details.
6957f
16
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
block DiagraMs
2
12
+
V
SD1
FILTA
FILTB
1
6
+
OUT1
11
10
–
OUT1
+
IN
3
4
–
IN
–
+
OUT2
OUT2
9
8
GND
SD2
5
7
LTC6957-1 and LTC6957-2
2
12
+
V
SD1
FILTA
FILTB
V
DD
1
6
11
10
OUT1
+
IN
3
4
–
IN
OUT2
9
8
GNDOUT
GND
SD2
6957 BD
5
7
LTC6957-3 and LTC6957-4
6957f
17
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
TiMing DiagraM
SD1
SD2
INPUT
+
OUT1 /OUT1
–
OUT1
+
OUT2 /OUT2
–
OUT2
t
t
SLEEP
ENABLE
t
t
WAKEUP
DISABLE
DETAIL
INPUT
SEE APPLICATIONS INFORMATION FOR
LOGIC BEHAVIOR DURING SHUTDOWN
SPECIFIC TO LVPECL/LVDS/CMOS
t
PD
50%
+
OUT1 /OUT1
–
OUT1
50%
90%
t
MATCH
10%
+
OUT2 /OUT2
t
t
RISE
–
OUT2
6957 TD1
90%
10%
t
FALL
SKEW
6957f
18
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
General Considerations
2
+
V
The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are
low noise, dual output clock buffers that are designed for
demanding,lowphasenoiseapplications.Properlyapplied,
they can preserve phase noise performance in situations
wherealternativesolutionswoulddegradethephasenoise
significantly. They are also useful as logic converters.
FILTA
1
6
FILTERS
FILTB
1.8k
1.2k
However, no buffer device is capable of removing or
reducing phase noise present on an input signal. As with
most low phase noise circuits, improper application of
the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can
result in an increase in the phase noise through a variety
of mechanisms. The information below will, hopefully,
allow a designer to avoid such an outcome.
+
IN
3
4
–
IN
1.2k
2mA
3.2k
GND
5
6957 F01
TheLTC6957isdesignedtobeusedwithhighperformance
clock signals destined for driving the encode inputs of
ADCs or mixer inputs. Such clocks should not be treated
as digital signals. The beauty of digital logic is that there
is noise margin both in the voltage and the timing, before
any deleterious effects are noticed. In contrast, high per-
formance clock signals have no margin for error in the
timing before the system performance is degraded. Us-
ers are encouraged to keep this distinction in mind while
designing the entire clocking signal chain before, during,
and after the LTC6957.
Figure 1
Figure 2a shows how to interface single-ended LVPECL
logic to the LTC6957, while Figure 2b shows how to drive
the LTC6957 with differential LVPECL signals. The capaci-
tors shown are 10nF and can be inexpensive ceramics,
preferably in small SMT cases. For use above 100MHz,
lower value capacitors may be desired to avoid series
resonance, which could increase the noise in Figure 2a
even though the capacitor is just on the DC input. This
comment applies to all capacitors hooked to the inputs
throughout this data sheet.
Input Interfacing
In Figure 2a, the R
implementation is up to the user
TERM
and is to terminate the transmission line. If it is connected
The input stage is the same for all versions of the LTC6957
and is designed for low noise and ease of interfacing to
sine-wave and small amplitude signals. Other logic types
caninterfacedirectly,orwithlittleeffortsincetheypresent
a smaller challenge for noise preservation.
to a V that is passively generated and heavily bypassed
TT
to ground, the 10nF to ground shown on the inverting
LTC6957 input is the appropriate connection to use.
However, if the termination goes to an actively generated
V
voltage, lower noise may be achieved by connecting
TT
Figure 1 shows a simplified schematic of the LTC6957
input stage. The diodes are all for protection, both during
ESD events and to protect the low noise NPN devices from
being damaged by input overdrive.
the capacitor on the inverting input to that V rather than
TT
ground.
In Figure 2b, both inputs to the LTC6957 are driven, in-
creasing the differential input signal size and minimizing
noise from any common mode source such as V , both
of which improve the achievable phase noise.
The resistors are to bias the input stage at an optimal
DC level, but they are too large to leave floating without
increasing the noise. Therefore, for low noise use, always
connect both inputs to a low AC impedance. A capacitor
to ground/return is imperative on the unused input in
single-ended applications.
TT
A variety of termination techniques can be used, and
as long as the two sides use the same termination, the
configuration used won't matter much. In Figure 2b, the
6957f
19
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
R
sareshownina"Y"configurationthatcreatesapas-
TT
have differential outputs and can be terminated with three
50Ω resistors as shown.
Figure 4 shows the interface between current mode logic
(CML) signals and the LTC6957 inputs. The specifics of
terminatingwillbedependentontheparticularCMLdriver
used; Figure 4 shows terminations only at the load end
of the line, but the same LTC6957 interface is appropri-
ate for applications with the source end of the line also
terminated. In Figure 4a, a differential signal interface to
the LTC6957 is shown, which must be AC-coupled due to
the DC input levels required at the LTC6957.
TERM
sive V at the common point. Most 3.3V LVPECL devices
Figure 3 shows a 50Ω RF signal source interface to the
LTC6957. For a pure tone (sine wave) input, Figure 3 can
handle up to 10dBm maximum. A broadband 50Ω match
as shown should suffice for most applications, though
for small amplitude input signals a narrow band reactive
matching network may offer incremental improvements
in performance.
Figure 4b shows a single-ended CML signal driving the
LTC6957.Thisisnotcommonlyusedbecauseofnoiseand
immunity weaknesses compared to the differential CML
case. Because the signal is created by a current pulled
through the termination resistor, the signal is inherently
3.3V
referencedtothesupplyvoltagetowhichR
istied.For
TERM
that reason, the other LTC6957 should be AC-referenced
to that supply voltage as shown.
+
LTC6957
R
TERM
–
The polarity change shown here is for graphic clarity
only, and can be reversed by swapping the LTC6957
input terminals.
6957 F02a
10nF
Figure 2a. Single-Ended LVPECL Input
3.3V
R
TERM
R
TERM
10nF
10nF
+
–
LTC6957
+
6957 F04a
LTC6957
–
6957 F02b
Figure 4a. Differential CML Input
3×
TERM
R
Figure 2b. Differential LVPECL Input
10nF
+
Figure 2
R
LTC6957
TERM 10nF
–
10nF
6957 F04b
50Ω
+
LTC6957
50Ω
–
Figure 4b. Single-Ended CML Input
6957 F03
10nF
SOURCE
Figure 4
Figure 3. Single-Ended 50Ω Input Source
6957f
20
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
Figure 5 shows the LTC6957 being driven by an LVDS
(EIA-644-A) signal pair. This is simply a matter of differ-
entially terminating the pair and AC-coupling as shown
into the LTC6957 whose DC common mode voltage is
incompatible with the LVDS standard.
The LTC6957-3/LTC6957-4 provide CMOS outputs, so it
may seem surprising to read herein that CMOS is a poor
choice for low phase noise applications. However, these
devices should prove useful for designers that recognize
the challenges and limitations of using CMOS signals for
low phase noise applications. See the CMOS Outputs of
theLTC6957-3/LTC6957-4sectionforfurtherinformation.
The choice of 110Ω versus 100Ω termination is arbitrary
(the EIA-644-A standard allows 90Ω to 132Ω) and should
be made to match the differential impedance of the trace
pair. The termination and AC-coupling elements should
be located as close as possible to the LTC6957.
The best method for driving the LTC6957 with CMOS
signals would be to provide differential drive, but if that
is not available, there are few ways to create a differential
CMOS signal without running the risk of corrupting the
skew or creating other problems. Therefore, single-ended
CMOS signals are the norm and care must be taken when
using this to drive the LTC6957.
If DC-coupling is desired, for example to control the
LTC6957 output phasing during times the LVDS input
clocks will be halted, a pair of 3k resistors can parallel the
two capacitors in Figure 5. An EIA/TIA-644-A compliant
driver can drive this load, which is less load stress than
specification4.1.1.ThedifferentialvoltageintotheLTC6957
when clocked (>100kHz) will be full LVDS levels. When
the clocks stop, the DC differential voltage created by the
resistors and the 1.2k internal resistors (Figure 1) will
be 100mV, still sufficient to assure the desired LTC6957
output polarity. Choosing the smallest capacitors needed
for phase noise performance will minimize the settling
transients when the clocks restart.
The primary concern is that all routing should be termi-
nated to minimize reflections. With CMOS logic there is
usuallyplentyofsignal(morethantheLTC6957canhandle
without attenuation) and the amplitude of the LTC6957
input signal will generally be of secondary importance
compared to avoiding the deleterious effects of signal
reflections. The primary concern about terminations is
that the input waveform presented to the LTC6957 should
have full speed slewing at the all important transitions.
If a rising edge is slowed by the destructive addition of
the ringing/settling of a prior edge reflection, or even the
startofthecurrentedge, thephasenoiseperformancewill
suffer. This is true for all logic types, but is particularly
problematic when using CMOS because of the fast slew
rates and because it does not naturally lend itself to clean
terminations.
Interfacing with CMOS Logic
Thelogicfamiliesdiscussedandillustratedtothispointare
generally a better choice for routing and distributing low
phase-noise reference/clock signals than is CMOS logic.
All of the logic types shown so far are well suited for use
with low impedance terminations. Most of the time there
is a differential signal when using LVPECL or CML, and
LVDS always has a differential signal. Differential signals
providelotsofmarginforerrorwhenitcomestopickingup
noise and interference that can corrupt a reference clock.
Point-to-point routing is best, and care should be taken to
avoiddaisy-chainrouting,becausetheterminatedendmay
be the only point along the line that sees clean transitions.
Earlier loads may even see a dwell in the transition region
which will greatly degrade phase noise performance.
CMOSontheotherhandcannotdrive50Ωloads,isusually
routed single-ended, and by its nature is coupled to the
potentially noisy supply voltage half the time.
10nF
+
110Ω
LTC6957
10nF
–
6957 F05
Figure 5. LVDS Input
6957f
21
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
Figure 6 shows a suggested CMOS to LTC6957 interface.
The transmission line shown is the PCB trace and the
component values are for a characteristic impedance of
50Ω, though they could be scaled up or down for other
values of Z0. The R1/R2 divider at the CMOS output cuts
phase noise spectrum related to the other signals pro-
cessed in the driver.
Input Resistors
The LTC6957 input resistors, seen in Figure 1, are present
at all times, including during shutdown. Although they
constitute a large portion of the shutdown current, this
behavior prevents the shutdown and wake-up cycling of
the LTC6957 from “kicking back” into prior stages, which
could create large transients that could take a while to
settle. Particularly in the common case of AC-coupling
where the coupling cap charge is preserved.
the Thevenin voltage in half when the Z
of the driver is
OUT
included. More importantly, it drives the transmission line
with a Thevenin driving resistance of 50Ω, matching the
Z0 of the line. On the other end of the line, a 50Ω load is
presented,minimizingreflections.Thisresultsinasecond
2:1 attenuation in voltage, so the LTC6957 input will be
approximately800mV with3VCMOS;1.25V with5V
P-P
P-P
and 600mV with 2.5V. All of these levels are less than
P-P
the maximum input swing of 2V yet with clean edges
P-P
Input Filtering
and fast slew rates should be able to realize the full phase
TheLTC6957includesinputfilteringwiththreenarrowband
settings in addition to the full bandwidth limitation of the
circuit design.
noise performance of the LTC6957.
CMOS
R1
75Ω
Table 1
+
Z0 = 50Ω
FILTA
Low
High
Low
High
FILTB
Low
BANDWIDTH
1200MHz (Full Bandwidth)
500MHz (–3dB)
50Ω
LTC6957
R2
100Ω
–
R
OUT
≈ 25Ω
Low
6957 F06
High
High
160MHz (–3dB)
50MHz (–3dB)
Figure 6. CMOS Input
Forslowslewingsignals(i.e.,<100MHzsinewavesignals)
substantially lower phase noise can be achieved by using
this feature. Bandwidth limiting is useful because it limits
the impact of all of the spectral energy that will alias down
to (on top of) the fundamental frequency.
The various capacitors are for AC-coupling and should
have Z << 50Ω at the operating frequency. The capacitors
allow the LTC6957 to set its own DC input bias level, and
reduce the DC current drain, which at 12.4mA (for the
case of a driver powered from 3.3V) is significant. This
current drain can be reduced (with some potential for a
noise penalty) by increasing the attenuation at the R1/
R2 network, taking care to keep the Thevenin impedance
equal to the Z0 of the trace.
The best filter setting to use for a given application will
depend on the clock frequency, amplitude, and waveform
shape, with the single biggest determinant being the slew
rate at the input of the LTC6957. Any amplifier noise will
add phase noise inversely proportional to its input slew
rate, just from the dV/dt changing voltage noise to time
base noise. But a fast slew rate may not be possible with
other design constraints, such as the use of sine waves
for EMI/RFI reasons, signal losses, etc. A limiting ampli-
fier such as the LTC6957 should have enough bandwidth
to preserve the slew rate of the input. But any additional
bandwidth will provide no improvement in phase noise
due to slew rate preservation, while incurring a phase
noise penalty from noise aliasing.
When using CMOS logic, it is important to consider how
all of the output drivers, in the same IC, are being used.
For best performance, the entire IC should be devoted to
driving the LTC6957, or if other gates in the same pack-
age must be put to use, they should only carry the same
timing signal (such as for fan-out) or be multiplexed in
time so that only one timing signal is being processed at
a time, such as for multiplexing selective shutdowns of
different segments of a system. Otherwise performance
is likely to suffer with spurs or other interference in the
6957f
22
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
Table 2 has the slew rate ranges most suitable for the four
different filter settings.
settings at various input slew rates. Each of the three
charts has all four filter settings, and one input amplitude;
Figure7ahasa+10dBminput,Figure7bhasa0dBminput,
and Figure 7c has a –10dBm input. The four filter settings
are shown in the same colors throughout.
Table 2
FILTA
Low
High
Low
High
FILTB
Low
INPUT SLEW RATE (V/µs)
>400
125 to 400
40 to 125
<40
With +10dBm at 100MHz, the input slew rate is 628V/µs
and Table 2 indicates the best filter setting to use is FILTA
= FILTB = L, which is seen to be the case in Figure 7a.
Low
High
High
The noise at the next filter setting is only slightly higher,
but for the maximum filtering case there is a full 10dB of
additional noise.
Another way to look at this is to consider the case of sine
waves, for which the frequency ranges will depend on
input amplitudes, as illustrated in Table 3.
With 0dBm at 100MHz, the input slew rate is 198V/µs and
Table 2 indicates the best filter setting to use is FILTA = H,
FILTB = L. Again this is seen to be the case in Figure 7b.
Astheinputwasdecreased10dBfromFigure7atoFigure7b,
thebluetracerose5dBwhilethegreentraceonlyrose3dB.
Table 3
FREQUENCY RANGE
INPUT
AMPLITUDE FILTB = L
FILTA = L,
FILTA = H,
FILTB = L
(MHz)
FILTA = L,
FILTB = H
(MHz)
FILTA = H,
FILTB = H
(MHz)
(dBm)
10
(MHz)
>63
20 to 63
35 to 112
63 to 200
>112
6.3 to 20
11 to 35
20 to 63
35 to 112
63 to 200
<6.3
<11
<20
<35
<63
With–10dBmat100MHz,theinputslewrateis63V/µsand
Table 2 indicates the best filter setting to use is FILTA = L,
FILTB = H. Again this is seen to be the case in Figure 7c. As
the input was decreased 10dB from Figure 7a to Figure 7b,
and again to Figure 7c, the red trace rose just 3dB then
another 4dB, while the green and blue traces rose much
faster.
5
>112
>200
0
–5
–10
>200
Figure 7 has LTC6957-1 100MHz additive phase noise
measurements that illustrate the trade-offs between filter
–140
–145
–150
–155
–160
–165
–140
–140
–145
–150
–155
–160
–165
SINGLE-ENDED SINE WAVE INPUT,
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 10dBm (2V
LTC6957-1
)
100MHz AT 0dBm (632.5mV
LTC6957-1
)
P-P
P-P
FILTA = FILTB = H
FILTA = FILTB = L
–145
–150
–155
–160
–165
FILTA = FILTB = H
FILTA = FILTB = H
FILTA = H, FILTB = L
FILTA = L, FILTB = H
FILTA = L, FILTB = H
FILTA = L, FILTB = H
FILTA = H, FILTB = L
FILTA = FILTB = L
FILTA = H, FILTB = L
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT –10dBm (200mV
LTC6957-1
)
P-P
FILTA = FILTB = L
100
1k
10k
100k
1M
100
1k
10k
100k
1M
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
69571234 F07a
69571234 F07c
69571234 F07b
(a)
(b)
(c)
Figure 7. 100MHz Additive Phase Noise with Varying Input Amplitudes
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
One important observation to take away from Figures 7a
to 7c is that while the worst filter settings for a given set
ofconditionsshouldcertainlybeavoided,itdoesn'tmatter
nearly as much if the optimal or next to optimal filter set-
ting is used, because they are always fairly comparable in
terms of phase noise. So if a design will have an octave or
two range of amplitudes or frequencies, it is sufficient to
choosethefiltersettingwhoserangemostcloselymatches
the application's range when using Tables 2 or 3 and the
noise penalty will not be severe anywhere in the range.
duty cycle is not exactly 50%. The LTC6957 inputs are
internally DC-coupled, and as shown in Figure 1, biasing
is provided at ~64% of the supply voltage. AC-coupled
input signals with a duty cycle of exactly 50% will see
symmetriclevelsofoverdriveforthetwosignaldirections.
If, for example, the input signal is a 100mV
square
P-P
wave with a duty-cycle of 48%, meaning it is high 48%
of the time and low 52% of the time, the DC average will
be 48mV above the low voltage level. This means the ris-
ing edge has 52mV of overdrive, and the falling edge has
48mV of overdrive.
Evidently, the input filtering will not significantly help with
large and fast slewing input signals to the LTC6957. As
seen in Figure 1, the input has a differential pair before the
filters, so the limiting will already have happened before
thefilter.Fortunately,withlargeinputsignals,performance
is typically better than with smaller input signals because
phase noise is a signal-to-noise phenomenon.
As a result of this, the rising edge t will be faster than
PD
the falling edge t . Fortunately, this will make the output
PD
dutycyclecloserto50%thantheinputdutycycle. Figure8
is from measurements on the LTC6957-2, with a 2V to
–
+
2.1V square wave on IN , and with IN set to various
DC voltages between those two levels. The X-axis is the
overdrive level for the t + data, and is 100mV minus
PD
Input Drive and Output Skew
the overdrive level for the t – data, to illustrate the level
PD
of t changes that can unexpectedly occur with AC-
PD
All versions of the LTC6957 have very good output skew;
the specification limits consist almost entirely of test
margins. Even laboratory verification ofthe skew between
different outputs is a challenging exercise, given the need
tomeasurewithin 1ps.Withelectromagneticpropagation
velocity in FR-4 being well known as 6" per nanosecond,
the skew of the LTC6957 will be impacted by PCB trace
routing length differences of just 6mils.
coupling. The lines are dashed where the measurement
uncertainty becomes large, when single digit millivolts
1
and picoseconds are being measured . As can be seen,
the t +/t – mismatch is very good at 50mV where the
PD PD
two overdrive levels are the same.
1500
1400
1300
1200
The LTC6957 t and t
are specified for a 100mV
SKEW
PD
step with 50mV of overdrive. This is common for high
speed comparators, though it may not reflect the typi-
cal application usage of parts such as the LTC6957. The
propagation delay of the LTC6957 will increase with less
overdrive and decrease with more overdrive, as would
that of a high speed comparator. To a lesser extent, hav-
ing the same overdrive but a larger signal (for instance a
differential input step of –200mV to 50mV) will increase
propagation delay, though this effect is smaller and can
usually be ignored.
1100
1000
900
800
700
600
500
t
+
t
–
PD
PD
+
–
IN OFFSETTED 50mV
IN DRIVEN 100mV
FILTA = FILTB = L
DC
P-P
0
10 20 30 40 50 60 70 80 90 100
OVERDRIVE (mV)
6957 F08
Figure 8. LTC6957-2 Propagation Delay vs Overdrive
A consequence of this behavior may be a perceived mis-
match between the propagation delay for rising versus
fallingedgeswhendrivenwithanAC-coupledinputwhose
1
Below 2mV to 3mV, the input offset and the small input hysteresis play a role too. Fortunately,
neither is large enough to be a concern in normal operation.
6957f
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For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
This data is shown for the LTC6957-2, but the effect is
due to the input stage that is common to all versions, so
any other version will have the same general behavior.
that only the current source is cut off during shutdown.
The bases of the output NPNs are still tied to the pull-up
resistors, so both outputs will be pulled high in shutdown,
anditistheuser’sresponsibilitytodisconnecttheexternal
loading if power reduction is to be realized.
The LTC6957-3 and LTC6957-4 CMOS outputs may have
additional t + vs t – discrepancies due to differences
PD
PD
betweentheNMOSandPMOSoutputdevices, particularly
when driving heavy loads. These are independent of input
overdrive, but can change with supply voltage and tem-
perature, and can vary part to part. The complementary
outputs of the LTC6957-4 will therefore be higher skew
than the like edges of the LTC6957-3. Both the LTC6957-3
The simplest way to terminate and bias the LTC6957-1
outputs is to route the differential output to the differen-
tial receiver and terminate the lines at that point with the
three resistor network shown in Figure 9. The differential
terminationwillbe100Ω,whilethecommonmodetermina-
tion will be 75Ω which could result in additional common
mode susceptibility. A bypass capacitor on the midpoint
of the Y can be used to improve this.
+
–
and LTC6957-4 will have large (120ps typ) t
to t
PD
PD
discrepancies compared to LVPECL or LVDS outputs.
If the common mode termination impedance is not an
issue, the three resistor Y configuration can be changed
to a three resistor delta configuration, which is a simpler
layout in most cases.
LVPECL Outputs of the LTC6957-1
Figure 9 shows a simplified schematic of the LTC6957-1
LVPECL output stage. As with most ECL outputs, there are
no internal pull-down devices so the user must provide
both termination and biasing external to the device. Note
+
V
+
V
24Ω
+
V
5Ω
+
V
+
50Ω
PCB ROUTING TRACES
Z0 = 50Ω
50Ω
24Ω
+
V
50Ω
–
5Ω
6957 F09
LTC6957-1
Figure 9. LTC6957-1 LVPECL Outputs
6957f
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For more information www.linear.com/LTC6957-1
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LTC6957-3/LTC6957-4
applicaTions inForMaTion
During transitions to and from shutdown, the LTC6957-1
outputs are not guaranteed to comply with the specified
output levels for any length of time after the rising edge
In any voltage configuration, be aware that the LVPECL
output stage depends on the external load to complete its
biasing and, as such, is susceptible to phase modulation
as the supply voltage changes. The LTC6957-1 is gener-
ally less sensitive to variations in the supply voltage if the
termination voltage tracks the supply rather than ground.
of SD1/SD2, nor for any time before sufficient t
ENABLE
/
WAKEUP
t
subsequent to the falling edge of SD1/SD2. The
output common mode and differential voltage could have
a slow settling time compared to the signal frequency, and
a long string of runt pulses could be seen. The LTC6957-1
shutdown capability should be used as a slow on/off
control, not a logic gating/enable control.
Withallfouroutputsterminatedorotherwisedrivingheavy
loads,theLTC6957-1powerconsumptionandtemperature
rise may be an issue.
Fortunately, the data sheet specification for supply cur-
rent with output loads does not need to be multiplied
by the entire supply voltage to calculate on-chip power
dissipation because most of that current flows through
the loads which will dissipate a significant portion of the
total system power.
Power Supplies for LVPECL Operation
The LTC6957-1 can operate from 3.15V to 3.45V total
supply voltage difference, irrespective of the absolute
level of those voltages. The convention in LVPECL is that
the negative supply is ground, while in ECL the positive
supply may be ground or 2.0V. The LTC6957-1 can work
in all of these situations provided the total supply voltage
difference is within the 3.15V to 3.45V range. No special
supply sequencing will be needed. With a 2V rail the out-
put terminations go to ground, while, with the positive
supply grounded, the outputs can tolerate short circuits
to ground. However, the four CMOS logic input signals
will need to be driven with respect to whatever absolute
levels of supply voltages are used. If FILTA, FILTB, SD1,
and SD2 are fixed, they can be tied to the appropriate rail
and this is not a problem. Interface logic levels could get
tricky if they need to be programmed in-system.
Typically, the internal power consumption will be (20mA •
3.3V = ) 66mW, while the on-chip power dissipation from
theoutputloadingwillbelessthanhalfthatnumber.Witha
totalpowerdissipationon-chipof90mW, thetemperature
riseintheMS-12packagewillbe13°Cgiventheθ ofthat
JA
package. For use to 125°C ambient (H-grade) designers
should be sure to check the temperature rise using their
specific output loading and supply levels. The Absolute
Maximum rating for Junction Temperature is 150°C, and
must be avoided to prevent damaging the device, and as
stated in Note 1: "Exposure to any Absolute Maximum
Rating condition for extended periods of time may affect
device reliability and lifetime."
6957f
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For more information www.linear.com/LTC6957-1
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LVDS Outputs of the LTC6957-2
rising edge of SD1/SD2, nor for any time before sufficient
WAKEUP ENABLE
t
/t
subsequent to the falling edge of SD1/
Figure 10 shows a simplified schematic of the LTC6957-2
LVDS output stage. The TIA/EIA-644-A standard specifies
the generator electrical requirements for this type of in-
terface, and the LTC6957-2 has been verified against that
standard using the following test methods:
SD2. The output common mode voltage (V in 644-A
OS
parlance) could have a slow settling time compared to the
signal frequency, and a long string of runt pulses could
be seen. The LTC6957-2 shutdown capability should be
used as a slow, power-saving on/off control, not a logic
gating/enable control.
SPECIFICATION
LEVEL OF TESTING
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
6a
100% Production Tested
100% Production Tested
100% Production Tested
100% Production Tested*
Lab Verification of Design Only
100% Production Tested
100% Production Tested
100% Production Tested
Power Supplies for LVDS Operation
The LTC6957-2 has a single supply that should be within
the 3.15V to 3.45V range.
The LTC6957-2 power supply voltage can corrupt the
spectral purity of the clock signal, though to a lesser
degree than with any of the other options. See the Typical
6b
6c
Performance Characteristic chart t vs Supply Voltage.
PD
*The t
/t
of the LTC6957-2 are not compliant with the standard so
RISE FALL
as to preserve full phase noise performance. To slow the edge rates, add
differential capacitance across the outputs. 2.7pF is sufficient to meet the
standard.
When using both LVDS channels, the LTC6957-2 power
consumption can exceed 120mW, which results in a
junction-to-ambient rise of 17.4°C in the MS-12 package,
more when operated at 3.45V. Again, it is up to the user
to always avoid junction temperatures above the Absolute
Maximum rating, and to stay comfortably below it for any
extended periods of time.
TheTIA/EIA-644-Astandarddoesnotcoverdrivercharac-
teristics during shutdown nor the transitions to and from
shutdown. The LTC6957-2 outputs are not guaranteed to
comply with the standard for any length of time after the
LTC6957-2
3.7mA
+
V
650Ω
+
PCB ROUTING TRACES
Z0 = 50Ω TO 60Ω
110Ω
+
V
–
650Ω
6957 F10
1.25V
Figure 10. LTC6957-2 LVDS Outputs
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
CMOS Outputs of the LTC6957-3/LTC6957-4
outputs may have one or two errant transitions resulting
in runt pulses being seen. The LTC6957-3/LTC6957-4
shutdown capability should be used as a slow, power-
savingon/offcontrol,notalogicgating/enablecontrol,and
because they can not be put in a high impedance (3-state)
condition, the shutdown functionality is not usable as a
way to multiplex multiple outputs or devices.
Figure11showsasimplifiedschematicoftheLTC6957-3/
LTC6957-4 CMOS output stage. The LTC6957-3 outputs
are driven synchronously in-phase, while the LTC6957-4
outputs are driven differentially out-of-phase.
Although the LTC6957-3/LTC6957-4 are specified for a
resistive load, the outputs can drive capacitive loads as
well. With more than a few picoFarads of load, the rise
and fall times will be degraded in direct proportion to the
load capacitance.
Power Supplies for CMOS Operation
+
The LTC6957-3/LTC6957-4 operate with V from 3.15V
to 3.45V only. If the LTC6957-3/LTC6957-4 are used to
drive CMOS logic at a lower voltage rail, the output stage
can be powered (Pin 11) by a lower voltage, down to
During shutdown, the LTC6957-3 outputs will both be
set to a logic low.
2.4V . Note that significant degradation of the spectral
MIN
During shutdown, the LTC6957-4 OUT1 will be set to a
logic low, while OUT2 will be set to a logic high.
purity could occur if the output supply, V , is not clean,
DD
either because of additional broadband noise or discrete
spectral tones. The nature of a CMOS logic gate forms an
AMmodulatoroflowfrequencydisturbancesonthepower/
ground that modulate the signal propagating through the
CMOS gate. Numerous common phenomena can serve
to convert the AM to PM/FM and, even if the conversion
efficiency is low, corrupt the phase noise to unacceptable
levels in demanding applications.
During transitions to and from shutdown, the LTC6967-3/
LTC6957-4 outputs may not comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient t
ENABLE
/
WAKEUP
t
subsequent to the falling edge of SD1/SD2. The
LTC6957-3/LTC6957-4
Iftwoseparatesuppliesareused,theonlysupplysequenc-
V
DD
ing issue to be aware of is that if the V comes up first,
DD
the OUT1/OUT2 CMOS outputs will be high impedance
+
until V > ~1V. Note that the four CMOS control inputs are
+
all referenced to V , not the output supply. Also note that
during operation the output supply should be equal to or
OUT1
+
lessthanV . TheLTC6957-3/LTC6957-4willfunctionwith
+
V
several hundred millivolts above the V supply, but
DD
depending on the load, this margin for error can largely
be consumed by transient load steps.
When driving capacitive loads at high frequencies, the
OUT2
LTC6957-3/LTC6957-4V powerconsumptioncanjump
DD
+
considerably over the quiescent power taken from V . The
Dynamic current specification is with no load and adds
directly to the current needed to repetitively charge and
discharge a capacitive load.
GND
OUT
+
With 24mA drawn from V at 3.3V, and another 20mA
to 30mA drawn from V (easy to do with two outputs
active at 300MHz), the total power consumption can be
145mWto178mW, resultinginajunction-to-ambientrise
6957f
DD
Figure 11. LTC6957-3/LTC6957-4 CMOS Outputs
28
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
of 21°C to 26°C in the MS-12 package. For use to 125°C
ambient (H-grade) designers should be sure to check the
temperature rise using their specific output frequency,
loading, and supply voltages. The Absolute Maximum
rating for Junction Temperature is 150°C, which must be
avoided to prevent damaging the device, and as stated
in Note 1: "Exposure to any Absolute Maximum Rating
condition for extended periods of time may affect device
reliability and lifetime."
Unfortunately, the term “low jitter” has become so over-
used that it is rendered virtually meaningless. High speed
communicationlinksdoingde-serializationandthelikecan
require jitter on the order of 30ps to 50ps. This is lower
jitterthanrequiredforaclockonamicro-controller,butfor
highfrequencysampling,even1pscanseverelyimpactthe
dynamic range achievable. Therefore, it is best to ignore
the term “low jitter” and look for measured values of jitter,
and preferably phase noise. To analyze and measure true
low noise components, most instruments measure phase
noise (in dBc/Hz) rather than jitter.
Low Phase Noise Design Considerations
Phase noise is a frequency domain representation of the
random variation in phase of a periodic signal. It is char-
acterized as the power at a given offset frequency relative
to the power of the fundamental frequency. Phase noise
is specified in dBc/Hz, decibels relative to the carrier in
a 1Hz bandwidth. It is essentially a frequency dependent
signal-to-noise ratio.
A second consideration when designing for low phase
noise is that any clock signal is an analog signal and
should be thought of and routed as such. They should
not be run through large FPGAs with lots of activities at
multiple frequencies, they should not be routed through
PCB traces alongside digital data lines, and they should
not be routed through clock fan-out devices that have
features such as zero delay or programmable skew. The
specifics of the PCB traces and what surrounds them
should be analyzed as if the clock signals were among
yourmostsensitiveanalogsignals,becauseindemanding
applications that is what your clock signals are. Note that
signalintegritysoftwareintendedforanalyzingcrosstalkin
digital systems may only give yes or no answers and that
clockingperformancecanbecompromised atlevels40dB
to 60dB below what is required to get that “yes” answer.
Designing for low phase noise is challenging, even with a
solidunderstandingofphasenoise.Anydesignerattempt-
ing such a task will find a good working understanding of
what phase noise is, and how it behaves, to be the most
important tool to achieve success. One of the most intui-
tive explanations is found in Chapter 3, “The Relationship
Between Phase Jitter and Noise Density,” of W.P. Robins’
1982 text, “Phase Noise in Signal Sources.”
With a solid base of understanding, the designer will now
see that the entire clocking chain is full of potential phase
modulators. The noise of an amplifier is usually thought
of as an additive term, but for phase noise the bias noise,
to the extent that the amplifier bandwidth is dependent on
the bias level, is not an additive term but a modulating
term. The LTC6957 is a monolithic clock limiting ampli-
fier carefully designed so that users do not have to worry
about such details.
Common pitfalls with clock signals are the same as for
sensitive analog signals: routing near or alongside digital
traces of any kind, crossing digital traces on an adjacent
layer within a sandwich of ground planes, using digital
power planes as part of layer sandwiches, and assuming
all of these are sufficiently mitigated by using differential
clock signaling.
The way to address these issues is also the same as for
sensitive analog signals: routing away from digital traces
wherever possible; routing with shielding of ground,
either planes, adjacent traces, or both; making realistic
assumptions of common mode rejections (30dB to 40dB
at most); and keeping a critical eye out for unintended
couplers during the design and debug phases.
However, users of the LTC6957 still need to pay attention
to external considerations that can result in corruption of
the good phase noise performance available from all the
components used.
Timing jitter is a term used to describe the integration of
phasenoiseoveraspecifiedbandwidthwhichispresented
as a time domain specification.
Even if the world’s cleanest reference clock were used
to feed the LTC6957, simply routing it through a poorly
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LTC6957-3/LTC6957-4
applicaTions inForMaTion
designed system would result in compromised spectral
performance. This often catches designers by surprise
because the mechanisms above are typically additive and
linear,whichresultinfilteringandadditionalspectralcom-
ponents,butdon’tbythemselvescreatephasemodulation.
Unfortunately, any limiter, including the LTC6957, will,
throughitsnonlinearaction, transformadditivetermsinto
phase modulation. When a small tone is added to a large
pure tone, the larger tone will appear to have its amplitude
and phase modulated at a rate equal to the difference of
the two frequencies. Pass this through a limiter and only
the phase modulation remains.
AM to PM Conversion at the LTC6957 Inputs
The LTC6957 input stage has some AM to PM conversion,
but as seen in the Typical Performance Characteristics
section, even at 300MHz this is less than 0.5°/dB. One
source of AM to PM conversion at the LTC6957 input is
theoptionallowpassfiltering, becausetheuppersideband
and the lower sideband will be attenuated by slightly
different amounts. This difference is quite small for low
offset frequencies, but the difference grows both as the
frequency of the modulation increases, and as the carrier
frequencyapproachesthefiltercutofffrequencywherethe
filter has a steeper roll-off.
Inlargecomplexsystems,itmaybeimpracticaltoeliminate
allpotentialcorruptingoftheclocksignals. Insucha case,
a narrow band filter placed at the inputs of the LTC6957
can remove the unwanted spectral components that are
far enough away from the fundamental.
Therefore, ifsmallamountsofAMareknowntobepresent
and an unacceptable level of PM is seen at the LTC6957
output, it may be helpful to change the input filter setting
to a higher cutoff frequency.
Cross Talk from Loading at the LTC6957 Outputs
Close-in spectral anomalies will likely be impervious to
such filtering. Therefore, it is doubly important to keep an
eye out for modulating mechanisms. If the clock is routed
through CMOS logic gates, the power supply used for that
gate will AM modulate the signal at the very least. The
modulation could manifest itself as sideband tones if the
power supply has repetitive disturbances, common with
switching power supplies, or it could manifest itself as
random noise if the noise of a linear regulator is too high.
Another mechanism to be aware of in the LTC6957 is
cross-modulation of the outputs. Except for the CMOS
LTC6957-3/LTC6957-4, there is minimal direct AM or
PM modulation of the outputs by the power supply. In
the CMOS case, the V power supply will directly AM
DD
modulate the outputs, with a small amount of AM to PM
conversion.
The thing to be aware of here is that there can be load-
induced disturbances internal to the LTC6957 that can
modulate the other output. For instance, hooking up one
output to an ADC encode input and the second output to
the FPGA that performs the first DSP on the ADC outputs,
can result in considerable kickback of FPGA generated
signals into the LTC6957. If this cross-modulates over to
the other output, all kinds of deleterious effects may be
seen including tones, images, etc.
Another source of corruption in large systems or labora-
tory measurements is the use of flexible cabling, which
can have a low level piezoelectric effect that modulates the
electrical length in response to mechanical vibration.
Rigid or semi-rigid cabling and PCB routing can be used
to eliminate this source of signal corruption.
TheCMOSLTC6957-3/LTC6957-4aremoresusceptibleto
thisthantheLVPECLandLVDS(LTC6957-1/LTC6957-2).To
prevent this, a buffer can be placed between the LTC6957
and the FPGA, even one that compromises the full jitter
performance considerably. Because it is the ADC that is
doing the sampling—the FPGA clock input has enough
margin for error to qualify as a digital signal.
6957f
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applicaTions inForMaTion
50Ω TERMINATION
2V
N5500A
REF
MINI-CIRCUITS
ZHL-2010+
–1.3V
DUT
1
2
MINI-CIRCUITS
ZFBT-6GW-FT
AGILENT 8644
122.88MHz
12.5dBm
MCL
LFCN
–150
MCL
LFCN
–150
MINI-CIRCUITS
ZX10-2-12-5
SIG
SPUR
INPUT
CAL TONE
MONITOR
3dB
ATTENUATOR
6dB
ATTENUATOR
10dB
ATTENUATOR
10dB
ATTENUATOR
COUPL
COUPL
3dB
ATTENUATOR
6957 F12
OUT
IN
IN
OUT
LINE STRETCHER
ARRA L9428A
MINI-CIRCUITS MINI-CIRCUITS
ZFDC-20-5-5+ ZFDC-20-5-5+
MINI-CIRCUITS
ZHL-2010+
Figure 12. Setup for LTC6957-1 Phase Noise Measurement Using Agilent E5505
In theory, all the phase noise in the signal source will be
rejected with the reading reflecting only the difference in
noise between the two paths. However, the rejection is
not perfect, particularly at very high offset frequencies
where the phase difference between the two paths pro-
gressively increases, thus the successive lowpass filters
on the signal source.
Phase Noise Measurement
Additive (also called residual) phase noise can be particu-
larly challenging to measure. Figure 12 shows a typical
laboratory set-up for testing the LTC6957-1 phase noise.
The LTC6957-1 has the lowest broadband phase noise of
thevariousdashnumbers(equaltothatoftheLTC6957-3/
LTC6957-4) and the lowest close-in noise with a corner
frequency below 2kHz, so it presents the most challeng-
ing case.
The Agilent 5505 measurement system uses the N5500A
frontend,whichincludesamixertocomparethesignaland
reference phases. For amplifier noise, it is appropriate to
feed the DUT path to the signal input, but for clock buffers
that create fast clock edges, it is usually advantageous to
use the reference input, which seems to be sensitive only
to the edges and not noise throughout the period. This is a
reasonable thing to do because the LTC6957 is designed
to drive ADC encode inputs or mixer ports which have the
same qualitative properties.
The various components and their role will be discussed
as this will illustrate both the care that must be taken
to realize the full performance of the LTC6957, and the
demanding nature of making phase noise measurements.
The signal starts with a 122.88MHz CW tone from the
Agilent 8644 synthesizer at a fairly high power level of
12.5dBm. Two series LPFs at 150MHz cut out all the high
frequency noise components that would otherwise con-
tributenoisebecauseofthealiasingcausedbythelimiting
action of the LTC6957. A signal splitter then separates the
signalintwo;onepathwillpropagatethroughtheDUTand
the other won’t, a common method used for measuring
residual phase noise.
Both the signal and reference inputs to the test set need to
be fairly large (15dBm to 20dBm) to realize the best noise
floor,sobothsignalpathsincludeMini-CircuitsZHL-2010+
low noise amplifiers to boost the signal. The LTC6957-1
was operated from 2V/–1.3V supplies so it could drive a
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For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
applicaTions inForMaTion
50Ω load to ground directly, but this creates a DC offset
(the signal is always positive) that the amplifier cannot
take, so a bias tee was included in the DUT signal path.
To calibrate E5505/N5500 measurements, the gain of the
mixer must be known. The surest way to measure it at
the actual frequencies being used is to inject a calibration
tone. For a 10kHz offset, a 122.89MHz low level (–10dBm)
signal is fed into the first coupler port. The requirements
for this signal are not demanding, so a general purpose
synthesizer that can be frequency locked, such as the
HP8657B, can be used.
Only the 122.88MHz sine wave will be in the path without
the DUT, going to the N5500A signal port, until the first
coupler. This coupler allows a spur input to be injected,
while a second coupler allows the size of the spur, relative
to the carrier, to be measured. More on that in a minute.
The three attenuators in this signal path work with the
ZHL-2010+ to manage the dynamic range, while the at-
tenuators on the coupling ports keep these terminals from
degrading the measured noise.
The E5505 measures the amplitude of the resulting 10kHz
mixer output, but to put that in context (so that it can later
calculate results in dBc) it needs to know the size of the
injected spur relative to the carrier. Therefore, that relative
difference is measured using a spectrum analyzer con-
nected to the attenuator on the second coupler.
Finally, an ARRA L9428A line stretcher is used to adjust
for quadrature. One last attenuator helps with impedance
matching between the N5500A input and the line stretcher
outputport.TheE5505Acanautomaticallyadjustthesignal
source phase/frequency for quadrature when measuring
VCOsorsynthesizers,butforadditivenoisethisadjustment
is manual because the adjustment must be made after the
signal is split into the two paths. The line stretcher has a
range of just 166ps, but with 122.88MHz, up to 20ns of
adjustment may be needed (1/4 cycle). Not shown is the
various short lengths of SMA cables and barrel couplers
that can also be added or subtracted to adjust the relative
phase of the two signal paths.
Hopefully the above discussion conveys the meticulous
effort needed to measure additive phase noise of a single
device, at a single operating frequency. While the circuitry
in Figure 12 can be used to measure the entire spectrum
of phase noise (all offset frequencies) as well as the phase
noiseatotherclockfrequencies,everyclockfrequencywill
require manual adjusting for quadrature. The input LPFs
will either need to be changed to match the new clock
frequency, or possibly amplitudes at various places will
have to be adjusted to account for the frequency roll-off
therein.
6957f
32
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical applicaTions
Crystal Oscillator
5V
IN
+
0.01µF
OUT
BP
LT1761-3.3V
3.3V
10µF
1µF
+
TO ALL V POINTS
+
0.1µF
V
2
12
+
V
SD1
0.1µF
50MHz
BANDWIDTH
FILTA
V
+
+
DD
V
V
1
6
11
10
FILTB
OUT1
+
IN
30pF
3
4
–
IN
OUT TO 50Ω
0.3V
450Ω
OUT2
2k
9
8
P-P
SQUARE WAVE
GNDOUT
SD2
LTC6957-3
GND
5
7
100Ω
10MHz
AT CUT
150Ω
75pF
6957 TA02a
Total Phase Noise of 10MHz Crystal Oscillator
–40
MEASURED ON AGILENT E5052A
–50
10 CORRELATIONS
–60
–70
–80
1Hz
–47.34dBc/Hz
10Hz –82dBc/Hz
100Hz –116.36dBc/Hz
1kHz –148.03dBc/Hz
10kHz –154.84dBc/Hz
100kHz –157.58dBc/Hz
1MHz –157.99dBc/Hz
–90
–100
–110
–120
–130
–140
–150
–160
–170
1
10
100
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
6957 TA02b
6957f
33
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD12 Package
12-Lead (3mm × 3mm) Plastic DFN
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 0.05
2.38 0.05
1.65 0.05
3.50 0.05
2.10 0.05
PACKAGE
OUTLINE
0.25 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
0.40 ± 0.10
TYP
7
12
2.38 0.10
1.65 ± 0.10
3.00 ±0.10
(4 SIDES)
PIN 1 NOTCH
PIN 1
TOP MARK
R = 0.20 OR
0.25 × 45°
CHAMFER
(SEE NOTE 6)
6
1
0.23 0.05
0.45 BSC
0.75 ±0.05
0.200 REF
2.25 REF
(DD12) DFN 0106 REV A
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
6957f
34
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
0.889 ±0.127
(.035 ±.005)
5.23
3.20 – 3.45
(.206)
(.126 – .136)
MIN
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.406 ±0.076
(.016 ±.003)
REF
12 11 10 9 8 7
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0° – 6° TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0.254
(.010)
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
1
2 3 4 5 6
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS12) 1107 REV Ø
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6957f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
35
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical applicaTion
10MHz Frequency Reference Input Stage with Dual CMOS Outputs
Additive Phase Noise
vs Input Amplitude
3.3V
3.3V
–140
–145
–150
–155
–160
–165
–170
0.1µF
0.1µF
FILTA = L, FILTB = L
FILTA = H, FILTB = L
FILTA = L, FILTB = H
FILTA = H, FILTB = H
OPTIMUM FILT SETTINGS
LTC6957-3
FILTA SD1OUT
+
1
2
3
4
5
6
12
11
10
9
FILTA
R1
V
V
DD
COILCRAFT
WBC16-1T
0.1µF
0.1µF
0.1µF
100Ω
HSMS-281C
CMOS OUT1,
10MHz
+
10MHz
REF IN
–10dBm to
24dBm
IN
IN
OUT1
OUT2
•
•
–
CMOS OUT2,
10MHz
R2
604k
0.1µF
8
GND
GNDOUT
SD2
7
FILTB
FILTB
R1
100Ω
6957 TA03a
–10 –8 –6 –4 –2
0
2
4
6
8
10
10MHz REFERENCE INPUT POWER
WITH REFERENCE TO 50Ω (dBm)
69571234 TA03b
0.1µF
100Ω
TO PHASE NOISE MEASUREMENT
100Ω
relaTeD parTs
PART NUMBER
LT1715
DESCRIPTION
COMMENTS
4ns, 150MHz Dual Comparator
16-Bit, 160Msps ADC
General Purpose Comparator with Flexible Supply Voltages
High Speed and High Resolution Requires Low Phase Noise Clocks
24dBm IIP3 at 240MHz, 9dB NF, 4dB Conversion Gain
LTC2209
LTC5517
40MHz to 900MHz Quadrature Demodulator
5MHz to 1600MHz Direct I/Q Modulator
LTC5598
27.7dBm OIP3 at 140MHz, –160dBm/Hz, –50.4dBc Image Rejection, –55dBm
Carrier Suppression
LTC6945
350MHz to 6GHz PLL Synthesizer
373MHz to 3.74GHz PLL + VCO
513MHz to 4.91GHz PLL + VCO
640MHz to 5.79GHz PLL + VCO
Integer-N PLL, –226dBc/Hz Normalized In-Band Phase Noise Floor
LTC6946-1
LTC6946-2
LTC6946-3
Integer-N PLL, –157dBc/Hz Wideband Output Phase Noise Floor, –226dBc/Hz
Normalized In-Band Phase Noise Floor, < –100dBc Spurious Output
6957f
LT 0313 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC6957-1
●
●
LINEAR TECHNOLOGY CORPORATION 2013
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