LTM4606EY#PBF [Linear]
LTM4606 - Ultralow EMI 28VIN, 6A DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 133; Temperature Range: -40°C to 85°C;![LTM4606EY#PBF](http://pdffile.icpdf.com/pdf2/p00317/img/icpdf/LTM4606EY-PB_1904901_icpdf.jpg)
型号: | LTM4606EY#PBF |
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描述: | LTM4606 - Ultralow EMI 28VIN, 6A DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 133; Temperature Range: -40°C to 85°C 开关 输出元件 |
文件: | 总28页 (文件大小:599K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LTM4606
Ultralow EMI 28V , 6A
IN
DC/DC µModule Regulator
FeaTures
DescripTion
n
Complete Low EMI Switch Mode Power Supply
The LTM®4606 is a complete EN55022 Class B certified
noisehighvoltage6AswitchingmodeDC/DCpowersupply.
Includedinthepackagearetheswitchingcontroller,power
FETs, inductor, and all support components. The on-board
inputfilterandnoisecancellationcircuitsachievelownoise
operation, thus effectively reducing the electromagnetic
interference (EMI). Operating over an input voltage range
of 4.5V to 28V, the LTM4606 supports an output voltage
range of 0.6V to 5V, set by a single resistor. This high ef-
ficiency design delivers 6A continuous current (8A peak).
Only bulk input and output capacitors are needed to finish
the design.
n
Wide Input Voltage Range: 4.5V to 28V
n
6A DC Typical, 8A Peak Output Current
n
0.6V to 5V Output Voltage Range
n
EN55022 Class B Certified
n
Output Voltage Tracking and Margining
n
PLL Frequency Synchronization
±±.ꢀ5ꢁ Total DC Error
Power Good Output
n
n
n
n
n
n
n
n
n
Current Foldback Protection (Disabled at Start-Up)
Parallel/Current Sharing
Current Mode Control
Up to 93% Efficiency at 5V , 3.3V
IN
OUT
High switching frequency and an adaptive on-time current
mode architecture enables a very fast transient response
to line and load changes without sacrificing stability. The
device supports output voltage tracking and output volt-
age margining.
Furthermore,theµModule® regulatorcanbesynchronized
with an external clock for reducing undesirable frequency
harmonics and allows PolyPhase® operation for high load
currents.
Programmable Soft-Start
Output Overvoltage Protection
–55°C to 125°C Operating Temperature Range
(LTM4606MP)
n
n
SnPb or RoHS Compliant Finish
15mm × 15mm × 2.82mm LGA Package
15mm × 15mm × 3.42mm BGA Package
applicaTions
The LTM4606 is offered in space saving 15mm × 15mm ×
2.82mm LGA and 15mm × 15mm × 3.42mm BGA pack-
ages. The LTM4606 is available with SnPb (BGA) or RoHS
compliant terminal finish.
L, LT, LTC, LTM, µModule, PolyPhase, Linear Technology, the Linear logo are registered
trademarks and UltraFast and LTpowerCAD are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611, 8163643.
n
ASICs or FPGA Transceivers
n
Telecom, Servers and Networking Equipment
Industrial Equipment
n
n
RF Equipment
Radiated Emission Scan at ±2VIN, 2.5VOUT/6A
Typical applicaTion
50
40
30
Ultralow Noise 2.5V/6A Power Supply with 4.5V to 28V Input
4.5V TO 28V
CLOCK SYNC
V
PLLIN
IN
2.5V AT 6A
20
10
V
PGOOD
RUN
COMP
OUT
LTM4606
47pF
FB
ON/OFF
C
OUT
V
FB
R
C
0
IN
INTV
DRV
CC
CC
19.1k
10µF
35V
FCB
–10
–20
–30
MARG0
MARG1
MPGM
f
MARGIN
CERAMIC
x2
SET
TRACK/SS
CONTROL
CONTROL
TRACK/SS
V
D
392k
5% MARGIN
10µF
35V
SGND PGND
30
226.2
128.1 324.3
FREQUENCY (MHz)
422.4
618.6
814.8
1010
520.5
716.7
912.9
4606 TA01a
4606 TA01b
4606fd
1
For more information www.linear.com/LTM4606
LTM4606
absoluTe MaxiMuM raTings
(Note ±)
DRV , V
................................................ –0.3V to 6V
Internal Operating Temperature Range (Note 2)
CC OUT
PLLIN, FCB, TRACK/SS, MPGM, MARG0,
MARG1, PGOOD, RUN ..............–0.3V to INTV + 0.3V
E and I Grades ...................................–40°C to 125°C
MP Grade........................................... –55°C to 125°C
Junction Temperature ........................................... 125°C
Storage Temperature Range .................. –55°C to 125°C
CC
V , COMP................................................ –0.3V to 2.7V
FB
V , V ....................................................... –0.3V to 28V
IN
D
pin conFiguraTion
TOP VIEW
TOP VIEW
V
V
IN
BANK 1
IN
f
f
SET
MARG0
MARG1
SET
BANK 1
V
V
D
D
MARG0
MARG1
SGND
SGND
DRV
DRV
CC
V
FB
PGOOD
SGND
NC
CC
PGND
BANK 2
PGND
BANK 2
V
FB
PGOOD
SGND
NC
V
NC
NC
NC
NC
OUT
V
OUT
BANK 3
BANK 3
FCB
FCB
BGA PACKAGE
133-LEAD (15mm × 15mm × 3.42mm)
LGA PACKAGE
133-LEAD (15mm × 15mm × 2.82mm)
T
= 125°C, θ = 15°C/W, θ
= 6°C/W, θ
= 16°C/W
T
= 125°C, θ = 15°C/W, θ
= 6°C/W, θ = 16°C/W
JCtop
JMAX
θ
JA
JCbottom
JCtop
JMAX
θ
JA
JCbottom
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
JA
JA
WEIGHT = 1.9g
WEIGHT = 1.7g
orDer inForMaTion
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
DEVICE
FINISH CODE
LTM4606EV#PBF
LTM4606IV#PBF
LTM4606MPV#PBF
LTM4606EY#PBF
LTM4606IY#PBF
LTM4606IY
Au (RoHS)
LTM4606V
LTM4606V
LTM4606V
LTM4606Y
LTM4606Y
LTM4606Y
LTM4606Y
LTM4606Y
e4
e4
e4
e1
e1
e0
e1
e0
LGA
LGA
LGA
BGA
BGA
BGA
BGA
BGA
3
3
3
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
Au (RoHS)
Au (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
SAC305 (RoHS)
SnPb (63/37)
LTM4606MPY#PBF
LTM4606MPY
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
• Terminal Finish Part Marking:
www.linear.com/leadfree
4606fd
2
For more information www.linear.com/LTM4606
LTM4606
elecTrical characTerisTics The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = ±2V, unless otherwise noted. Per typical
application (front page) configuration, RFB = 40.2k.
SYMBOL
PARAMETER
CONDITIONS
MIN
4.5
TYP
MAX
28
UNITS
l
l
V
IN(DC)
Input DC Voltage
V
V
V
Output Voltage, Total Variation with
Line and Load
C
V
= 10µF x2, C = 200µF; FCB = 0
OUT
= 5V to 28V, I
1.474
1.5
1.526
OUT(DC)
IN
IN
= 0A to 6A, (Note 4)
OUT
Input Specifications
V
Undervoltage Lockout Threshold
Input Inrush Current at Start-Up
I
I
= 0A
3.2
4
V
IN(UVLO)
OUT
OUT
I
= 0A, C = 10µF x2, C
= 200µF,
INRUSH(VIN)
IN
OUT
V
= 1.5V
OUT
V
V
= 5V
0.6
0.7
A
A
IN
IN
= 12V
I
I
Input Supply Bias Current
Input Supply Current
V
V
= 5V, V = 1.5V, Switching Continuous
OUT
27
25
22
mA
mA
µA
Q(VIN)
S(VIN)
IN
IN
= 12V, V
= 1.5V, Switching Continuous
OUT
Shutdown, RUN = 0, V = 12V
IN
V
V
= 12V, V
= 1.5V, I = 6A
OUT
0.96
2.18
A
A
IN
IN
OUT
= 5V, V
= 1.5V, I
= 6A
OUT
OUT
INTV
V
= 12V, RUN > 2V
No Load
4.7
0
5
5.3
V
CC
IN
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V = 1.5V (Note 4)
OUT
6
A
OUT(DC)
IN
l
l
DV
V
= 1.5V, FCB = 0V, V = 4.5V to 28V,
0.05
0.3
%
OUT(LINE)/ OUT
OUT
OUT
IN
I
= 0A
DV
V
Load Regulation Accuracy
Input Ripple Voltage
V
= 1.5V, FCB = 0V, I
IN
= 0A to 6A
OUT
OUT(LOAD)/ OUT
OUT
V
= 12V (Note 4)
0.3
%
V
V
I
= 0A, C = 10µF X5R Ceramic x3 and
OUT IN
IN(AC)
100µF Electrolytic
V
IN
V
IN
= 5V, V
= 12V, V
= 1.5V
= 1.5V
2
3
mV
mV
OUT
OUT
P-P
P-P
Output Ripple Voltage
I
= 0A, C
= 22µF X5R Ceramic x3 and
OUT(AC)
OUT
OUT
100µF X5R Ceramic
V
V
= 5V, V
= 1.5V
= 1.5V
8
11
mV
mV
IN
IN
OUT
OUT
P-P
P-P
= 12V, V
f
Output Ripple Voltage Frequency
Turn-On Overshoot
I
= 5A, V = 12V, V = 1.5V
OUT
900
kHz
S
OUT
IN
DV
C
= 200µF, V
= 1.5V, I
= 0A,
OUT
OUT(START)
OUT
OUT
TRACK/SS = 10nF
V
V
= 12V
= 5V
20
20
mV
mV
IN
IN
t
Turn-On Time
C
= 200µF; V
= 1.5V, TRACK/SS = Open
START
OUT
OUT
V
V
OUT
I
= 1A Resistive Load
= 5V
0.5
0.5
ms
ms
IN
IN
= 12V
DV
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
OUT(LS)
C
= 22µF Ceramic, 470µF x2
35
25
mV
µs
OUT
V
IN
V
OUT
= 12V
= 1.5V
t
I
Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load,
SETTLE
V
= 12V
IN
Output Current Limit
C
= 200µF
OUT(PK)
OUT
V
V
= 5V, V
= 1.5V
OUT
OUT
10
10
A
A
IN
IN
= 12V, V
= 1.5V
4606fd
3
For more information www.linear.com/LTM4606
LTM4606
elecTrical characTerisTics The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = ±2V, unless otherwise noted. Per typical
application (front page) configuration, RFB = 40.2k.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Control Section
l
V
V
Voltage at V Pin
I
= 0A, V = 1.5V
OUT
0.591
1
0.6
1.5
–1.5
0.6
–1
0.609
1.9
V
V
FB
FB
OUT
RUN Pin On/Off Threshold
Soft-Start Charging Current
Forced Continuous Threshold
Forced Continuous Pin Current
Minimum On Time
RUN
I
V
V
= 0V
TRACK/SS
–1
–2
µA
V
TRACK/SS
V
FCB
0.57
0.63
–2
I
t
t
= 0V
FCB
µA
ns
ns
kW
mA
kW
V
FCB
(Note 3)
(Note 3)
50
100
400
ON(MIN)
OFF(MIN)
Minimum Off Time
250
50
R
PLLIN Input Resistor
PLLIN
I
Current into DRV Pin
V
= 1.5V, I
= 1A, DRV = 5V
15
25
DRVCC
CC
OUT
OUT
CC
R
Resistor Between V
and V Pins
60.098
60.4
5
60.702
FBHI
OUT
FB
V
Maximum RUN Pin Voltage
5.1V Zener Clamp
RUN(MAX)
Margin Section
V
V
Margin Reference Voltage
1.18
1.4
V
V
MPGM
, V
MARG0, MARG1 Voltage Threshold
MARG0 MARG1
PGOOD
DV
DV
DV
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
7
10
–10
1.5
13
%
%
%
V
FBH
FB
Falling
–7
–13
FBL
FB
Returning
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4606E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4606I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. The LTM4606MP
is guaranteed and tested over the –55°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: 100% tested at die level only.
Note 4: See output current derating curves for different V , V
and T .
A
IN OUT
4606fd
4
For more information www.linear.com/LTM4606
LTM4606
Typical perForMance characTerisTics
Efficiency vs Load Current with
5VIN (FCB = 0)
Efficiency vs Load Current with
±2VIN (FCB = 0)
Efficiency vs Load Current with
24VIN (FCB = 0)
100
90
80
70
60
50
100
90
80
70
60
50
100
90
80
70
60
50
0.6V
1.2V
1.8V
2.5V
3.3V
1.2V
1.5V
2.5V
3.3V
5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2.5V
3.3V
5V
OUT
OUT
OUT
OUT
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4606 G01
4606 G02
4606 G03
±.2V Transient Response
±.5V Transient Response
±.8V Transient Response
I
I
OUT
2A/DIV
I
OUT
OUT
2A/DIV
2A/DIV
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
4606 G04
4606 G06
4606 G05
50µs/DIV
50µs/DIV
50µs/DIV
1.2V AT 3.5A/µs LOAD STEP
1.8V AT 3.5A/µs LOAD STEP
1.5V AT 3.5A/µs LOAD STEP
C
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
C
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
C
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
OUT
OUT
OUT
2.5V Transient Response
3.3V Transient Response
–55°C, Start-Up, IOUT = 0A
V
OUT
I
I
OUT
2A/DIV
OUT
0.5V/DIV
2A/DIV
V
V
OUT
100mV/DIV
OUT
I
IN
50mV/DIV
0.5A/DIV
4606 G07
4606 G08
4606 G09
50µs/DIV
50µs/DIV
1ms/DIV
V
V
C
= 12V
OUT
OUT
IN
= 1.5V
2.5V AT 3.5A/µs LOAD STEP
3.3V AT 3.5A/µs LOAD STEP
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
SOFT-START = 3.9nF
C
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
C
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
OUT
OUT
4606fd
5
For more information www.linear.com/LTM4606
LTM4606
Typical perForMance characTerisTics
Start-Up, IOUT = 6A
(Resistive Load)
–55°C, Start-Up, IOUT = 6A
Start-Up, IOUT = 0A
V
OUT
V
V
OUT
OUT
0.5V/DIV
0.5V/DIV
0.5V/DIV
I
IN
0.5A/DIV
I
IN
0.5A/DIV
I
4606 G10
IN
1ms/DIV
V
V
C
= 12V
OUT
OUT
IN
0.5A/DIV
= 1.5V
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
SOFT-START = 3.9nF
4606 G11
4606 G12
1ms/DIV
1ms/DIV
V
V
C
= 12V
OUT
OUT
V
V
C
= 12V
OUT
OUT
IN
IN
= 1.5V
= 1.5V
= 1× 22µF, 6.3V CERAMIC
1× 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
= 1× 22µF, 6.3V CERAMIC
1× 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
Short-Circuit Protection,
IOUT = 0A
Short-Circuit Protection,
IOUT = 6A
Start Into Pre-Biased Output
V
IN
2V/DIV
V
V
OUT
1V/DIV
OUT
V
OUT
2V/DIV
1V/DIV
I
I
IN
2A/DIV
IN
0.2A/DIV
4606 G13a
4606 G13
4606 G14
20ms/DIV
50µs/DIV
50µs/DIV
V
V
C
= 12V
OUT
OUT
V
V
C
= 12V
IN
OUT
OUT
IN
= 2.5V
= 2.5V
V
V
C
= 12V
OUT
OUT
IN
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
SOFT-START = 0.1µF
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
SOFT-START = 0.1µF
= 5V
= 2× 22µF, 10V CERAMIC
1× 100µF, 6.3V CERAMIC
SOFT-START = 0.1µF
V
IN to VOUT Step-Down
Operation Region
VFB vs Temperature
28
24
20
16
12
0.606
0.604
0.602
0.600
0.598
0.596
0.594
SEE FREQUENCY ADJUSTMENT SECTION
FOR OPERATIONS OUTSIDE THIS REGION
OPERATION REGION
WITH DEFAULT FREQUENCY
8
4.5
–55
35
65
95
125
–25
5
0.6 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
TEMPERATURE (°C)
V
OUT
4606 G16
4606 G15
4606fd
6
For more information www.linear.com/LTM4606
LTM4606
Typical perForMance characTerisTics
Input Ripple
Output Ripple
V
OUT
V
IN
2mV/DIV
10mV/DIV
4606 G17
4606 G18
2µs/DIV
2µs/DIV
V
V
C
= 5V
V
V
C
= 5V
IN
OUT
OUT
IN
OUT
IN
= 1V AT 6A
= 1V AT 6A
= 3× 10µF, 25V CERAMIC
1× 150µF BULK
= 2× 22µF, 6.3V CERAMIC
1× 100µF, 6.3V CERAMIC
BW = 300MHz
BW = 300MHz
pin FuncTions
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock with high level
above 2V and below INTV . See the Applications Infor-
CC
V (Bank ±): Power Input Pins. Apply input voltage be-
IN
mation section.
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V pins
IN
FCB(PinM±2):ForcedContinuousInput.Connectthispin
and PGND pins.
to SGND to force continuous synchronization operation at
low load, to INTV to enable discontinuous mode opera-
CC
V
(Bank 3): Power Output Pins. Apply output load
OUT
tion at low load or to a resistive divider from a secondary
between these pins and PGND pins. Recommend placing
outputdecouplingcapacitancedirectlybetweenthesepins
and PGND pins (see Figure 17).
output when using a secondary winding.
TRACK/SS(PinA9):OutputVoltageTrackingandSoft-Start
Pin. When the module is configured as a master output,
then a soft-start capacitor is placed on this pin to ground
to control the master ramp rate. A soft-start capacitor can
be used for soft-start turn-on in a standalone regulator.
Slave operation is performed by putting a resistor divider
from the master output to ground, and connecting the
center point of the divider to this pin. See the Applications
Information section.
PGND (Bank 2): Power Ground Pins for Both Input and
Output Returns.
V (PinsBꢀ, Cꢀ):TopFETDrainPins. Addmorecapacitors
D
between V and ground to handle the input RMS current
D
and reduce the input ripple further.
DRV (Pins C±0, E±±, E±2): These pins normally con-
CC
nect to INTV for powering the internal MOSFET drivers.
CC
They can be biased up to 6V from an external supply with
about 50mA capability, or an external circuit as shown in
Figure 18. This improves efficiency at the higher input
voltages by reducing power dissipation in the module.
MPGM (Pins A±2, B±±): Programmable Margining Input.
A resistor from these pins to ground sets a current that
is equal to 1.18V/R. This current multiplied by 10kW will
equal a value in millivolts that is a percentage of the 0.6V
referencevoltage.SeetheApplicationsInformationsection.
To parallel LTM4606s, each requires an individual MPGM
INTV (Pin Aꢀ): This pin is for additional decoupling of
CC
the 5V internal regulator.
resistor. Do not tie MPGM pins together.
4606fd
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LTM4606
pin FuncTions
f
(Pin B±2): Frequency set internally to 800kHz in
SGND (Pins D9, H±2): Signal Ground Pins. These pins
SET
continuous conducting mode at light load. An external
resistor can be placed from this pin to ground to increase
frequency. See the Applications Information section for
frequency adjustment.
connect to PGND at output capacitor point. See Figure 17.
COMP (Pins A±±, D±±): Current Control Threshold and
Error Amplifier Compensation Point. The current com-
parator threshold increases with this control voltage. The
voltage ranges from 0V to 2.4V with 0.7V corresponding
to zero sense voltage (zero current).
V
(Pin F±2): The Negative Input of the Error Amplifier.
FB
Internally, this pin is connected to V
with a 60.4k preci-
OUT
sionresistor.Differentoutputvoltagescanbeprogrammed
PGOOD (Pin G±2): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within 10% of the regulation point,
after a 25µs power bad mask timer expires.
withanadditionalresistorbetweentheV andSGNDpins.
FB
See the Applications Information section.
MARG0 (Pin C±2): LSB Logic Input for the Margining
Function. Together with the MARG1 pin, the MARG0 pin
will determine if a margin high, margin low, or no margin
state is applied. The pin has an internal pulldown resistor
of 50k. See the Applications Information section.
RUN (Pins A±0, B9): Run Control Pins. A voltage above
1.9V will turn on the module, and below 1V will turn off
the module. A programmable UVLO function can be ac-
complishedwitharesistordividerfromV toground. See
IN
MARG±(PinsC±±, D±2):MSBLogicInputfortheMargin-
ing Function. Together with the MARG0 pin, the MARG1
pins will determine if a margin high, margin low, or no
marginstateisapplied.Thepinshaveaninternalpull-down
resistor of 50k. See the Applications Information section.
Figure 1. This pin has a 5.1V Zener to ground. Maximum
pin voltage is 5V. Limit current into the RUN pin to less
than 1mA.
NC (Pins J±2, K±2, L±2): These pads must be left floating
(electrical open circuit) and are used for enhanced solder
joint strength.
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8
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LTM4606
block DiagraM
V
IN
>1.9V = ON
<1V = OFF
MAX = 5V
R1
V
OUT
RUN
UVLO
FUNCTION
INPUT
FILTER
V
IN
4.5V TO 28V
+
PGOOD
COMP
5.1V
ZENER
1.5µF
R2
C
IN
60.4k
V
D
INTERNAL
COMP
C
D
POWER CONTROL
M1
M2
SGND
1µH
V
OUT
2.5V
MARG1
MARG0
AT 6A
NOISE
CANCEL-
LATION
V
FB
22µF
50k 50k
+
f
SET
R
FB
C
OUT
19.1k
41.2k
PGND
FCB
10k
MPGM
TRACK/SS
PLLIN
C
SS
50k
4.7µF
INTV
DRV
CC
CC
4606 F01
Figure ±. Simplified Block Diagram
Decoupling requireMenTs TA = 25°C. Use Figure ± configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
IN
External Input Capacitor Requirement
IN
I
= 6A
10
µF
OUT
(V = 4.5V to 28V, V
= 2.5V)
OUT
C
External Output Capacitor Requirement
(V = 4.5V to 28V, V = 2.5V)
I
= 6A
100
200
µF
OUT
OUT
IN
OUT
4606fd
9
For more information www.linear.com/LTM4606
LTM4606
operaTion
Power Module Description
Inputfilterandnoisecancellationcircuitsreducethenoise
coupling to I/O sides, and ensure the electromagnetic
interference (EMI) to meet EN55022 Class B limits.
TheLTM4606isastandalonenon-isolatedswitchingmode
DC/DC power supply. It can deliver up to 6A of DC output
current with some external input and output capacitors.
This module provides precisely regulated output voltage
Pulling the RUN pin below 1V forces the controller into its
shutdown state, turning off both M1 and M2. At low load
currents, discontinuous mode (DCM) operation can be
enabled to achieve higher efficiency compared to continu-
ous mode (CCM) by setting the FCB pin higher than 0.6V.
programmable via one external resistor from 0.6V to
DC
5.0V over a 4.5V to 28V input voltage range. The typical
DC
application schematic is shown in Figure 20.
The LTM4606 has an integrated constant on-time current
When the DRV pin is connected to INTV an integrated
CC
CC
mode regulator, ultralow R
FETs with fast switch-
5V linear regulator powers the internal gate drivers. If a
DS(ON)
ing speed and integrated Schottky diodes. With current
mode control and internal feedback loop compensation,
the LTM4606 module has sufficient stability margins and
goodtransientperformanceunderawiderangeofoperat-
ing conditions and with a wide range of output capacitors,
even all ceramic output capacitors.
5V external bias supply is applied on the DRV pin, then
CC
an efficiency improvement will occur due to the reduced
powerlossintheinternallinearregulator.Thisisespecially
true at the higher input voltage range.
The MPGM, MARG0 and MARG1 pins are used to sup-
port voltage margining, where the percentage of margin
is programmed by the MPGM pin, and the MARG0 and
MARG1 selected margining. The PLLIN pin provides fre-
quency synchronization of the device to an external clock.
The TRACK/SS pin is used for power supply tracking and
soft-start programming.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limiting. Besides, foldback current limiting is provided in
an overcurrent condition while V drops. Internal over-
FB
voltageandundervoltagecomparatorspulltheopen-drain
PGOOD output low if the output feedback voltage exits a
10% window around the regulation point. Furthermore,
in an overvoltage condition, internal top FET M1 is turned
off and bottom FET M2 is turned on and held on until the
overvoltage condition clears.
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The typical LTM4606 application circuit is shown in Fig-
ure 20. External component selection is primarily deter-
mined by the maximum load current and output voltage.
RefertoTable2forspecificexternalcapacitorrequirements
for a particular application.
R
resistor on the MPGM pin programs the current.
PGM
Calculate V
:
OUT(MARGIN)
%VOUT
100
VOUT(MARGIN)
where %V
=
• VOUT
is the percentage of V
OUT(MARGIN)
you want to
OUT
OUT
V to V
Step-Down Ratios
IN
OUT
margin, and V
is the margin quantity in volts:
Under the default frequency, there are restrictions in
the maximum V and V step-down ratio that can be
VOUT
1.18V
IN
OUT
RPGM
=
•
• 10k
achieved for a given input voltage. These constraints are
caused by the limitation of the minimum on and off time in
the internal switches. Refer to the Frequency Adjustment
section to change the switching frequency and get wider
input and output ranges. See the Thermal Considerations
and Output Current Derating section in this data sheet for
the current restrictions.
0.6V VOUT(MARGIN)
where R
pin to ground.
is the resistor value to place on the MPGM
PGM
The margining voltage, V
, will be added or
OUT(MARGIN)
subtractedfromthenominaloutputvoltageasdetermined
by the state of the MARG0 and MARG1 pins. See the truth
table below:
Output Voltage Programming and Margining
MARG±
LOW
MARG0
LOW
MODE
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 60.4k internal feedback
NO MARGIN
MARGIN UP
MARGIN DOWN
NO MARGIN
LOW
HIGH
LOW
resistor connects the V
and V pins together. Adding
OUT
FB
HIGH
HIGH
a resistor R from the V pin to the SGND pin programs
FB
FB
HIGH
the output voltage:
60.4k + RFB
Input Capacitors and Input EMI Noise Attenuation
VOUT = 0.6V
or equivalently,
RFB
The LTM4606 is designed to achieve low input conducted
EMInoiseduetothefastswitchingofturn-onandturn-off.
In the LTM4606, a high frequency inductor is integrated
to the input line for noise attenuation. V and V pins
60.4k
RFB =
VOUT
0.6V
– 1
D
IN
are available for external input capacitors to form a high
Table ±. RFB Standard ±ꢁ Resistor Values vs VOUT
frequency π filter. As shown in Figure 19, the ceramic
R
FB
(kΩ)
Open 60.4
0.6 1.2
40.2
1.5
30.1
1.8
25.5
2
19.1
2.5
13.3
3.3
8.25
5
capacitor C1 on the V pins is used to handle most of
D
the RMS current into the converter, so careful attention
V
OUT
(V)
is needed for capacitor C1 selection.
For a buck converter, the switching duty cycle can be
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference
offset for margining. A 1.18V reference divided by the
estimated as:
VOUT
D =
V
IN
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LTM4606
applicaTions inForMaTion
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
meet EN55022 Class B. For different applications, input
capacitance may be varied to meet different radiated EMI
limits.
IOUT(MAX)
ICIN(RMS)
=
• D • 1– D
(
)
η
Output Capacitors
The LTM4606 is designed for low output voltage ripple.
In the above equation, η is the estimated efficiency of the
power module. Note the capacitor ripple current ratings
are often based on temperature and hours of life. This
makes it advisable to properly derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
The bulk output capacitors defined as C
are chosen
OUT
with low enough effective series resistance (ESR) to meet
theoutputvoltagerippleandtransientrequirements. C
OUT
can be a low ESR tantalum capacitor, low ESR polymer
capacitor or ceramic capacitor. The typical capacitance is
200µF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spikeisrequired.Table2showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 3A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.
In a typical 6A output application, one or two very low
ESR X5R or X7R, 10µF ceramic capacitors are recom-
mendedforC1.Thisdecouplingcapacitorshouldbeplaced
directly adjacent to the module V pins in the PCB layout
D
to minimize the trace inductance and high frequency AC
noise. Each 10µF ceramic is typically good for 2 to 3 amps
of RMS ripple current. Refer to your ceramics capacitor
catalog for the RMS current ratings.
Multiphase operation with multiple LTM4606 devices in
parallel will lower the effective output ripple current due
to the phase interleaving operation. Refer to Figure 3
for the normalized output ripple current versus the duty
cycle. Figure 3 provides a ratio of peak-to-peak output
ripple current to the inductor ripple current as functions
of duty cycle and the number of paralleled phases. Pick
the corresponding duty cycle and the number of phases
to get the correct output ripple current value. For example,
each phase’s inductor ripple current DIr at zero duty cycle
is ~2.5A for a 12V to 2.5V design. The duty cycle is about
0.21. The 2-phase curve has a ratio of ~0.58 for a duty
cycle of 0.21. This 0.58 ratio of output ripple current to
the inductor ripple current DIr at 2.5A equals ~1.5A of the
To attenuate high frequency noise, extra input capacitors
should be connected to the V pads and placed before
IN
the high frequency inductor to form the π filter. One of
these low ESR ceramic capacitors is recommended to
be placed close to the connection into the system board.
A large bulk 100µF capacitor is only needed if the input
sourceimpedanceiscompromisedbylonginductiveleads
or traces. Figure 2 shows the radiated EMI test results to
50
40
30
20
output ripple current (∆I ).
L
10
The output ripple voltage has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
The equation is:
0
–10
–20
–30
DIL
8 • f •N • C
30
226.2
128.1 324.3
FREQUENCY (MHz)
422.4
618.6
814.8
1010
DVOUT(P−P)
≈
+ ESR • DI
L
520.5
716.7
912.9
OUT
4606 F02
Figure 2. Radiated Emission Scan with ±2VIN
to 2.5VOUT at 6A (±×±00µF XꢀR Ceramic COUT
where f is the frequency and N is the number of paralleled
)
phases.
4606fd
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1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
IN
4612 F05
O
Figure 3. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
Fault Conditions: Current Limit and Overcurrent
Foldback
A capacitor on this pin will program the ramp rate of the
output voltage. A 1.5µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltage reference plus or minus any margin delta. This will
control the ramp of the internal reference and the output
voltage. The total soft-start time can be calculated as:
LTM4606 has a current mode controller, which inher-
ently limits the cycle-by-cycle inductor current not only
in steady-state operation, but also in transient.
To further limit current in the event of an overload condi-
tion,theLTM4606providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
CSS
1.5µA
tSOFTSTART ≅ 0.8 • 0.6V ± V
•
(
)
OUT(MARGIN)
When the RUN pin falls below 1.5V, then the TRACK/SS
pin is reset to allow for proper soft-start control when the
regulator is enabled again. Current foldback and forced
continuous mode are disabled during the soft-start pro-
cess. The soft-start function can also be used to control
the output ramp up time, so that another regulator can
be easily tracked to it.
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply.
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Output Voltage Tracking
Run Enable
Output voltage tracking can be programmed externally
usingtheTRACK/SSpin. Theoutputcanbetrackedupand
down with another regulator. Figure 4 shows an example
of coincident tracking where the master regulator’s output
is divided down with an external resistor divider that is the
sameastheslaveregulator’sfeedbackdivider.Ratiometric
modes of tracking can be achieved by selecting different
resistor values to change the output tracking ratio. The
master output must be greater than the slave output for
the tracking to work. Figure 5 shows the coincident output
tracking characteristics.
The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with a logic input not to exceed 5V.
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
R1+ R2
VUVLO
=
• 1.5V
R2
See Figure 1, Simplified Block Diagram.
V
IN
Power Good
100k
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point and tracks
with margining.
V
PLLIN
V
IN
D
SLAVE
OUTPUT
2.5V
PGOOD
RUN
V
OUT
C
OUT
V
FB
LTM4606
C
IN
COMP
FCB
MARG0
MARG1
MPGM
INTV
CC
CC
COMP Pin
MASTER
OUTPUT
DRV
R2
f
SET
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application require-
ments. LTpowerCAD™ is available for other control loop
optimization.
60.4k
TRACK
CONTROL
TRACK/SS
SGND PGND
19.1k
R1
19.1k
4606 F04
Figure 4. Coincident Tracking Schematic
FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. FCB pin below the 0.6V threshold
forcescontinuoussynchronousoperation,allowingcurrent
to reverse at light loads and maintain low output ripple.
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT
VOLTAGE
4606 F05
TIME
Figure 5. Coincident Output Tracking Characteristics
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PLLIN
Thermal Considerations and Output Current Derating
Thepowermodulehasaphase-lockedloopcomprisedofan
internal voltage controlled oscillator and a phase detector.
This allows the internal top MOSFET turn-on to be locked
totherisingedgeoftheexternalclock. Thefrequencyrange
is 30% around the operating frequency. A pulse detection
circuit is used to detect a clock on the PLLIN pin to turn
on the phase lock loop. The pulse width of the clock has to
be at least 400ns and the amplitude at least 2V. The PLLIN
pin must be driven from a low impedance source such as
a logic gate located close to the pin. During the start-up of
the regulator, the phase-locked loop function is disabled.
In different applications, LTM4606 operates in a variety of
thermal environments. The maximum output current is
limited by the environment thermal condition. Sufficient
coolingshouldbeprovidedtohelpensurereliableoperation.
When the cooling is limited, proper output current derating
is necessary, considering ambient temperature, airflow,
input/outputcondition,andtheneedforincreasedreliability.
The power loss curves in Figures 6 and 7 can be used
in coordination with the load current derating curves in
Figures 8 to 15 for calculating an approximate θ for the
JA
module. The graphs delineate between no heat sink, and
a BGA heat sink. Each of the load current derating curves
will lower the maximum load current as a function of the
increasedambienttemperaturetokeepthemaximumjunc-
tiontemperatureofthepowermoduleat125°Cmaximum.
Each of the derating curves and the power loss curve that
corresponds to the correct output voltage can be used to
INTV and DRV Connection
CC
CC
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV
CC
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4606
can be directly powered by Vin. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
solve for the approximate θ of the condition. Each figure
JA
has three curves that are taken at three different air flow
conditions. Tables 3 and 4 provide the approximate θ
JA
P
= 20mA • (V – 5V)
IN
for Figures 8 to 15. A complete explanation of the thermal
characteristics is provided in the thermal application note
AN110.
LDO_LOSS
The LTM4606 also provides an external gate driver voltage
pin DRV . If there is a 5V rail in the system, it is recom-
CC
mended to connect DRV pin to the external 5V rail. This is
CC
Safety Considerations
especially true for higher input voltages. Do not apply more
The LTM4606 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
than 6V to the DRV pin. A 5V output can be used to power
CC
the DRV pin with an external circuit as shown in Figure 18.
IN
OUT
CC
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Parallel Operation of the Module
The LTM4606 device is an inherently current mode con-
trolleddevice.Parallelmoduleswillhaveverygoodcurrent
sharing. This will balance the thermals on the design. The
voltage feedback equation changes with the variable N as
modules are paralleled:
Radiated EMI Noise
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make large di/dt change in the converters, which act as
the radiation sources in most systems. The LTM4606
integrates the feature to minimize the radiated EMI noise
for applications with low noise requirements. Optimized
gatedriverfortheMOSFETandnoisecancellationnetwork
are installed inside the LTM4606 to achieve low radiated
EMInoise.Figure16showsatypicalexampleforLTM4606
to meet the Class B of EN55022 radiated emission limit.
4606fd
60.4k
+ RFB
N
VOUT = 0.6V
RFB
N is the number of paralleled modules.
15
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4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
24V LOSS
12V LOSS
1.5
5V LOSS
1.0
12V LOSS
0.5
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4606 F07
4606 F06
Figure 6. ±.5V Power Loss
Figure ꢀ. 3.3V Power Loss
6
5
6
5
4
3
4
3
2
1
0
2
1
0
5V , 1.5V , 0LFM
5V , 1.5V , 0LFM
IN OUT
IN
OUT
5V , 1.5V , 200LFM
5V , 1.5V , 200LFM
IN OUT
IN
IN
OUT
OUT
5V , 1.5V , 400LFM
5V , 1.5V , 400LFM
IN OUT
75
80
85
90
95
75
80
85
90
95
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4606 F08
4606 F09
Figure 8. No Heat Sink
Figure 9. BGA Heat Sink
6
5
6
5
4
3
4
3
2
1
0
2
1
0
12V , 1.5V , 0LFM
IN
OUT
12V , 1.5V , 200LFM
IN
IN
OUT
OUT
12V , 1.5V , 400LFM
70
75
AMBIENT TEMPERATURE (°C)
12V , 1.5V , 0LFM
80
85
90
95
70
75
80
85
90
95
AMBIENT TEMPERATURE (°C)
4606 F10
4606 F11
IN
OUT
12V , 1.5V , 200LFM
IN
OUT
12V , 1.5V , 400LFM
IN
OUT
Figure ±0. No Heat Sink
Figure ±±. BGA Heat Sink
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6
6
5
5
4
3
4
3
2
2
1
0
12V , 3.3V , 0LFM
12V , 3.3V , 0LFM
IN OUT
1
0
IN
OUT
12V , 3.3V , 200LFM
12V , 3.3V , 200LFM
IN OUT
IN
IN
OUT
OUT
12V , 3.3V , 400LFM
12V , 3.3V , 400LFM
IN OUT
70
75
80
85
90
95
70
75
80
85
90
95
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4606 F12
4606 F13
Figure ±2. No Heat Sink
Figure ±3. BGA Heat Sink
6
5
4
3
2
1
0
6
5
4
3
2
1
0
24V , 3.3V , 0LFM
24V , 3.3V , 0LFM
IN
OUT
IN
OUT
24V , 3.3V , 200LFM
24V , 3.3V , 200LFM
IN
IN
OUT
OUT
IN
IN
OUT
OUT
24V , 3.3V , 400LFM
24V , 3.3V , 400LFM
60
65
70
75
80
85
60
65
70
75
80
85
90
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4606 G15
4606 F14
Figure ±4. No Heat Sink
Figure ±5. BGA Heat Sink
50
40
30
20
10
0
–10
–20
–30
30
226.2
128.1 324.3
FREQUENCY (MHz)
422.4
618.6
814.8
1010
520.5
716.7
912.9
4606 F16
Figure ±6. Radiated Emission Scan with ±2VIN
to 2.5VOUT at 6A (±×±00µF XꢀR Ceramic COUT
)
4606fd
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applicaTions inForMaTion
Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20)
TYPICAL MEASURED VALUES
C
VENDORS
PART NUMBER
C
OUT2
VENDORS
PART NUMBER
OUT±
TAIYO YUDEN
TAIYO YUDEN
TDK
JMK316BJ226ML-T501 (22µF, 6.3V)
JMK325BJ476MM-T (47µF, 6.3V)
C3225X5R0J476M (47µF, 6.3V)
SANYO POSCAP
SANYO POSCAP
SANYO POSCAP
6TPE220MIL (220µF, 6.3V)
2R5TPE330M9 (330µF, 2.5V)
4TPE330MCL (330µF, 4V)
V
C
C
C
C
V
(V)
DROOP
(mV)
PEAK TO
PEAK (mV)
RECOVERY
TIME (µs)
LOAD STEP
(A/µs)
R
FB
OUT
IN
IN
OUT±
OUT2
IN
(V)
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
(CERAMIC)
(BULK)
(CERAMIC)
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
(BULK)
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
(kW)
60.4
60.4
60.4
60.4
60.4
60.4
60.4
60.4
40.2
40.2
40.2
40.2
40.2
40.2
40.2
40.2
30.1
30.1
30.1
30.1
30.1
30.1
30.1
30.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
13.3
13.3
13.3
13.3
13.3
13.3
13.3
13.3
8.25
8.25
8.25
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
2 × 10µF 35V 150µF 35V
5
34
22
68
40
30
26
24
18
30
26
24
18
30
30
26
26
30
30
26
26
37
30
26
26
37
30
26
26
40
34
28
12
40
34
28
18
40
32
28
14
40
32
28
22
20
20
20
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
20
40
5
32
60
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
34
68
22
40
20
39
29.5
35
55
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
70
5
25
48
5
24
47.5
68
5
36
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
35
70
25
48
24
45
32.6
38
61.9
76
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
5
29.5
28
57.5
55
5
5
43
80
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
12
12
12
12
5
38
76
28
55
27
52
36.4
38
70
330µF 4V
330µF 4V
220µF 6.3V
NONE
78
5
37.6
39.5
66
74
5
78.1
119
78
5
330µF 4V
330µF 4V
220µF 6.3V
NONE
12
12
12
12
7
38
34.5
35.8
50
66.3
68.8
98
330µF 4V
330µF 4V
220µF 6.3V
NONE
42
86
7
47
89
7
50
94
7
75
141
86
330µF 4V
330µF 4V
220µF 6.3V
NONE
12
12
12
12
12
15
20
42
47
88
50
94
69
131
215
215
217
NONE
110
110
110
5
NONE
5
NONE
4606fd
18
For more information www.linear.com/LTM4606
LTM4606
applicaTions inForMaTion
Table 3. ±.5V Output
DERATING CURVE
Figures 8, 10
Figures 8, 10
Figures 8, 10
Figures 9, 11
Figures 9, 11
Figures 9, 11
V
(V)
POWER LOSS CURVE
Figure 6
AIR FLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
IN
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
13.5
10
9
Figure 6
200
400
0
None
Figure 6
None
Figure 6
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9.5
7
Figure 6
200
400
Figure 6
5
Table 4. 3.3V Output
DERATING CURVE
Figures 12, 14
V
(V)
POWER LOSS CURVE
Figure 7
AIR FLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
IN
12, 24
0
13.5
11
10
10
7
Figures 12, 14
12, 24
12, 24
12, 24
12, 24
12, 24
Figure 7
200
400
0
None
Figures 12, 14
Figure 7
None
Figures 13, 15
Figure 7
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figures 13, 15
Figure 7
200
400
Figures 13, 15
Figure 7
5
Heat Sink Manufacturer
AAVID Thermalloy
PART NUMBER
375424B00034G
WEBSITE
www.aavidthermalloy.com
www.cooinnovations.com
Cool Innovations
4-050503P to 4-050508P
Layout Checklist/Example
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
The high integration of LTM4606 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout con-
siderations are still necessary.
• Place one or more high frequency ceramic capacitors
close to the connection into the system board.
• Use large PCB copper areas for high current path, in-
Figure17givesagoodexampleoftherecommendedlayout.
cluding V , PGND and V . It helps to minimize the
IN
OUT
V
IN
PCB conduction loss and thermal stress.
C
IN
C
IN
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
D
OUT
PGND
high frequency noise.
• Place a dedicated power ground layer underneath the
SIGNAL
GND
unit.
• UseroundcornersforthePCBcopperlayertominimize
C
C
OUT
OUT
the radiated noise.
V
OUT
4606 F17
• To minimize the EMI noise and reduce module thermal
stress, use multiple vias for interconnection between
top layer and other power layers on different locations.
(LGA Shown, for BGA Use Circle Pads)
Figure ±ꢀ. Recommended PCB Layout
• Donotputviasdirectlyonpads,unlesstheyarecapped.
4606fd
19
For more information www.linear.com/LTM4606
LTM4606
applicaTions inForMaTion
Frequency Adjustment
time.Figure18showsanoperatingrangeof10Vto28Vfor
1MHzoperationwitha150kresistortoground,andan8Vto
The LTM4606 is designed to typically operate at 800kHz
16V operating range for f floating. These modifications
SET
across most input conditions. The f
pin is typically
SET
are made to provide wider input voltage ranges for the 5V
output designs while limiting the inductor ripple current,
and maintaining the 400ns minimum off-time.
left open. The switching frequency has been optimized
for maintaining constant output ripple noise over most
operating ranges. The 800kHz switching frequency and
the 400ns minimum off time can limit operation at higher
duty cycles like 5V to 3.3V, and produce excessive induc-
tor ripple currents for lower duty cycle applications like
28V to 5V.
Example for 3.3V Output
LTM4606 minimum on-time = 100ns
t
ON
= ((V
• 10pF)/I
)
OUT
fSET
LTM4606 minimum off-time = 400ns
= t – t , where t = 1/Frequency
Example for 5V Output
t
OFF
ON
LTM4606 minimum on-time = 100ns
Duty Cycle (DC) = t /t or V /V
ON
OUT IN
t
= ((V
• 10pF)/I ), for V
> 4.8V use 4.8V
ON
OUT
fSET
OUT
Equations for setting frequency:
= (V /(3 • R )), for 28V input operation, I =
fSET
LTM4606 minimum off-time = 400ns
= t – t , where t = 1/Frequency
I
fSET
IN
fSET
t
OFF
ON
227µA, t = ((3.3 • 10pF)/I ), t = 145ns, where the
ON
fSET
fSET ON
Duty Cycle = t /t or V /V
internal R
is 41.2k. Frequency = (V /(V • t )) =
ON
OUT IN
OUT IN ON
(3.3V/(28 • 145ns)) ~ 810kHz. The minimum on-time and
minimum-off time are within specification at 146ns and
1089ns. But the 4.5V minimum input for converting 3.3V
output will not meet the minimum off-time specification
Equations for setting frequency:
= (V /(3 • R )), where the internal R is 41.2k.
fSET
I
fSET
IN
fSET
For 28V input operation, I
= 227µA. t = ((4.8 • 10pF)/
ON
fSET
I
),t =211ns.Frequency=(V /(V • t ))=(5V/(28
fSET ON
OUT IN ON
of 400ns. t = 905ns, Frequency = 810kHz, t = 329ns.
ON
OFF
• 211ns)) ~ 850kHz. The inductor ripple current begins to
get high at the higher input voltages due to a larger voltage
across the inductor. The current ripple is ~5A at 20% duty
cycle for the integrated 1µH inductor. The inductor ripple
currentcanbeloweredatthehigherinputvoltagesbyadd-
Solution
Lower the switching frequency at lower input voltages to
allow for higher duty cycles, and meet the 400ns mini-
mum off-time at 4.5V input voltage. The off-time should
be about 500ns with 100ns guard band. The duty cycle
ing an external resistor from f to ground to increase the
SET
switchingfrequency.A4Aripplecurrentischosen,andthe
total peak current is equal to 1/2 of the 4A ripple current
plusthe outputcurrent. For5Voutput, currentis limited to
5A, so the total peak current is less than 7A. This is below
the 8A peak specified value. A 150k resistor is placed from
for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t
or
OFF
(1 – 0.73)/500ns = 540kHz. The switching frequency
needs to be lowered to 540kHz at 4.5V input. t = DC/
ON
frequency, or 1.35µs. The f
pin voltage compliance
SET
is 1/3 of V , and the I
current equates to 36µA with
current needs to be 24µA for
IN
fSET
f
to ground, and the parallel combination of 150k and
SET
the internal 41.2k. The I
fSET
41.2k equates to 32.3k. The I
calculation with 32.3k
fSET
540kHz operation. A resistor can be placed from V
to
OUT
and 28V input voltage equals 289µA. This equates to a t
ON
f
to lower the effective I
current out of the f pin
SET
fSET SET
of 166ns. This will increase the switching frequency from
850kHz to ~1MHz for the 28V to 5V conversion. The
minimum on time is above 100ns at 28V input. Since
the switching frequency is approximately constant over
input and output conditions, then the lower input voltage
range is limited to 8V for the 1MHz operation due to the
to 24µA. The f
pin is 4.5V/3 =1.5V and V
= 3.3V,
OUT
SET
therefore a 150k resistor will source 12µA into the f
SET
node and lower the I
current to 24µA. This enables the
fSET
540kHz operation and the 4.5V to 28V input operation for
down converting to 3.3V output as shown in Figure 19.
The frequency will scale from 540kHz to 950kHz over this
input range. This provides for an effective output current
400ns minimum off time. Equation: t = (V /V ) • (1/
ON
OUT IN
Frequency) equates to a 375ns on time, and a 400ns off
of 5A over the input range.
4606fd
20
For more information www.linear.com/LTM4606
LTM4606
Typical applicaTions
V
OUT
10V TO 28V
C1
10µF
R4
100k
R3
100k
V
V
PLLIN
D
IN
5V AT 5A
V
PGOOD
RUN
COMP
INTV
DRV
OUT
C2
C
22µF
6.3V
C
LTM4606
OUT1
OUT2
100pF
+
ON/OFF
C
10µF
35V
220µF
6.3V
V
FB
IN
R
FB
8.25k
CC
CC
FCB
CERAMIC
x2
MARG0
MARG1
MPGM
f
MARGIN
SET
TRACK/SS
CONTROL
REFER TO TABLE 2
FOR OUTPUT CAPACITOR
SELECTIONS
TRACK/SS
CONTROL
SGND PGND
R1
392k
5% MARGIN
R
fSET
150k
IMPROVE EFFICIENCY
FOR ≥12V INPUT
4606 TA02
Figure ±8. ±0V to 28VIN, 5V at 5A Design
V
OUT
4.5V TO 28V
C1
10µF
R4
100k
R3
V
V
IN
PLLIN
100k
D
3.3V AT 5A
V
PGOOD
RUN
COMP
INTV
DRV
OUT
C2
LTM4606
C
C
OUT2
OUT1
100pF
+
ON/OFF
C
10µF
35V
22µF
6.3V
x2
220µF
V
FB
IN
R
6.3V
FB
13.3k
CC
CC
FCB
CERAMIC
x2
MARG0
MARG1
MPGM
f
MARGIN
SET
TRACK/SS
CONTROL
REFER TO TABLE 2
FOR OUTPUT CAPACITOR
SELECTIONS
R
fSET
150k
SGND PGND
R1
392k
5% MARGIN
TRACK/SS
CONTROL
V
OUT
4606 TA03
Figure ±9. 3.3V at 5A Design
4606fd
21
For more information www.linear.com/LTM4606
LTM4606
Typical applicaTions
V
OUT
4.5V TO 28V
CLOCK SYNC
C1
10µF
R4
100k
R3
100k
V
V
PLLIN
D
IN
2.5V AT 6A
V
PGOOD
RUN
COMP
INTV
DRV
OUT
C2
C
22µF
6.3V
C
LTM4606
OUT1
OUT2
100pF
+
ON/OFF
220µF
6.3V
V
FB
R
FB
19.1k
CC
CC
FCB
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
C
10µF
35V
CERAMIC
x2
IN
C4
0.01µF
SGND PGND
R1
392k
5% MARGIN
4606 TA04
Figure 20. Typical 4.5V to 28VIN, 2.5V at 6A Design
V
OUT
V
IN
4.5V TO 28V
C1
10µF
CLOCK SYNC
0° PHASE
R2
100k
R4
V
D
V
IN
PLLIN
100k
2.5V AT 12A
PGOOD
RUN
COMP
V
OUT
C6
C
22µF
6.3V
LTM4606
OUT1
+
C
OUT2
220pF
220µF
6.3V
V
FB
FCB
INTV
CC
CC
C2
10µF
35V
DRV
f
MARG0
MARG1
MPGM
MARGIN
CONTROL
SET
TRACK/SS
C5
100µF
35V
+
C4
0.33µF
R1
392k
R
FB
9.53k
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
V
OUT1
GND OUT2
SET MOD
C7
0.1µF
R5
118k
C3
10µF
LTC6908-1
CLOCK SYNC
180° PHASE
R3
100k
V
V
PLLIN
D
IN
V
PGOOD
RUN
OUT
C
22µF
6.3V
LTM4606
OUT3
C
+
OUT4
220µF
6.3V
V
FB
COMP
C8
10µF
35V
FCB
INTV
CC
MARG0
MARG1
MPGM
DRV
CC
f
SET
TRACK/SS
R6
392k
SGND PGND
5% MARGIN
4606 TA05
Figure 2±. 2-Phase, Parallel 2.5V at ±2A Design
4606fd
22
For more information www.linear.com/LTM4606
LTM4606
Typical applicaTions
3.3V
V
IN
5V TO 28V
C3
10µF
CLOCK SYNC
0° PHASE
R4
R2
100k
V
D
V
IN
PLLIN
100k
3.3V AT 6A
C
PGOOD
RUN
COMP
V
OUT
C6
C
LTM4606
OUT1
+
OUT2
22pF
100µF
6.3V
220µF
V
FB
FCB
6.3V
INTV
CC
CC
DRV
C2
10µF
35V
f
MARG0
MARG1
MPGM
MARGIN
SET
TRACK/SS
CONTROL
C5
100µF
35V
+
R1
392k
R
FB1
13.3k
C7
0.15µF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
3.3V
V
OUT1
GND OUT2
SET MOD
C9
0.1µF
R5
118k
C4
10µF
LTC6908-1
CLOCK SYNC
180° PHASE
R7
100k
R3
100k
V
V
PLLIN
D
IN
2.5V AT 6A
V
OUT
PGOOD
RUN
C1
22pF
C
OUT3
LTM4606
C
+
OUT4
100µF
6.3V
220µF
6.3V
V
FCB
COMP
FB
C8
10µF
35V
INTV
CC
3.3V TRACK
R8
MARG0
MARG1
MPGM
MARGIN
CONTROL
DRV
CC
60.4k
f
SET
TRACK/SS
R6
392k
R
FB2
19.1k
R9
19.1k
SGND PGND
4606 TA06
Figure 22. 2-Phase, 3.3V and 2.5V Outputs at 6A with Tracking and Margining
1.8V
4.5V TO 28V
C3
10µF
CLOCK SYNC
0° PHASE
R4
100k
R2
100k
V
D
V
IN
PLLIN
1.8V AT 6A
C
PGOOD
RUN
COMP
V
OUT
C6
100pF
C
LTM4606
OUT1
+
OUT2
100µF
6.3V
220µF
V
FB
FCB
6.3V
INTV
DRV
CC
C2
CC
10µF
35V
f
MARG0
MARG1
MPGM
MARGIN
SET
TRACK/SS
CONTROL
C5
100µF
35V
+
R1
392k
R
FB1
30.1k
C7
0.15µF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
1.8V
V
OUT1
GND OUT2
SET MOD
C9
0.1µF
R5
182k
C4
10µF
LTC6908-1
CLOCK SYNC
180° PHASE
R7
100k
R3
100k
V
V
PLLIN
D
IN
1.5V AT 6A
V
OUT
PGOOD
RUN
C1
100pF
C
22µF
6.3V
LTM4606
OUT3
C
+
OUT4
220µF
6.3V
V
FCB
COMP
FB
C8
10µF
35V
INTV
CC
1.8V TRACK
R8
MARG0
MARG1
MPGM
DRV
MARGIN
CONTROL
CC
60.4k
f
SET
TRACK/SS
R6
392k
R
FB2
40.2k
R9
40.2k
SGND PGND
4606 TA07
Figure 23. 2-Phase, ±.8V and ±.5V Outputs at 6A with Tracking and Margining
4606fd
23
For more information www.linear.com/LTM4606
LTM4606
package DescripTion
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
PIN NAME
PGND
PIN NAME
PIN NAME
A1
A2
A3
A4
A5
A6
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
D1
D2
D3
D4
D5
D6
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
A7
INTV
CC
PLLIN
PGND
PGND
PGND
PGND
PGND
A8
A9
TRACK/SS
RUN
A10
A11
A12
COMP
MPGM
B1
B2
B3
B4
B5
B6
V
V
V
V
V
V
E1
E2
E3
E4
E5
E6
E7
E8
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
B7
V
-
IN
IN
IN
IN
IN
IN
D
B8
B9
RUN
-
B10
B11
B12
MPGM
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
V
V
V
V
V
V
V
V
V
V
V
f
SET
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
C1
C2
C3
C4
C5
C6
V
V
V
V
V
V
C7
V
-
IN
IN
IN
IN
IN
IN
D
C8
F1
F2
F3
F4
F5
F6
F7
F8
F9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C9
-
C10
C11
C12
DRV
CC
MARG1
MARG0
D7
-
-
D8
D9
SGND
-
D10
D11
D12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
V
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
COMP
MARG1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E9
-
-
E10
E11
E12
DRV
DRV
CC
CC
F10
F11
F12
-
-
V
FB
G12
H12
J12
K12
L12
M12
PGOOD
SGND
NC
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
V
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
NC
NC
FCB
4606fd
24
For more information www.linear.com/LTM4606
LTM4606
package DescripTion
/ / b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4606fd
25
For more information www.linear.com/LTM4606
LTM4606
package DescripTion
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4606fd
26
For more information www.linear.com/LTM4606
LTM4606
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
3/10
Change to Features.
1
Change to Absolute Maximum Ratings.
Changes to Electrical Characteristics.
Changes to Related Parts.
2
2, 3
25
B
C
3/11
Text updated throughout the data sheet.
Graph replaced on the front page, Figure 2, and Figure 16.
Added value of 1µH to inductor on Figure 1.
Updated Related Parts.
1-28
1, 12, 17
9
28
10/13 Add BGA Package Option
Add Start Into Pre-Bias Output Graph
1, 2, 19, 25, 28
6
Clarify Voltage Margining function
Add Recommended External Heat Sink Vendors
Update LGA Package Outline Drawing
Added SnPb package option
11
19
26
1, 2
D
2/14
4606fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM4606
package phoTograph
2.82mm
3.42mm
15mm
15mm
15mm
15mm
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM4601/
LTM4601A
12A DC/DC µModule Regulator with PLL, Output
Tracking/Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has No
Remote Sensing, LGA Package
LTM4618
6A DC/DC µModule Regulator with PLL,
Output Tracking
4.5V ≤ V ≤ 26.5V, 0.8V ≤ V
≤ 5V, Synchronizable, 9mm × 15mm × 4.3mm
IN
OUT
LGA Package
LTM4604A
LTM4608A
LTM4612
LTM4613
LTM4627
Low V 4A DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 9mm × 15mm × 2.3mm LGA Package
≤ 5V, 9mm × 15mm × 2.8mm LGA Package
IN
IN
OUT
Low V 8A DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.6V ≤ V
IN
IN
OUT
Low Noise 5A, 15V
Low Noise 8A, 15V
DC/DC µModule Regulator
DC/DC µModule Regulator
Low Noise, with PLL, Output Tracking and Margining, LTM4606 Pin-Compatible
Low Noise, with PLL, Output Tracking and Margining, EN55022B Compliant
OUT
OUT
15A DC/DC µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V
≤ 5V, 1.5% Total DC Output Accuracy,
IN
OUT
15mm × 15mm × 4.32mm LGA Package
EN55022 Class B Certified DC/DC µModule Regulators
LTM8020
LTM8021
High V 0.2A DC/DC Step-Down µModule Regulator 4V ≤ V ≤ 36V, 1.25V ≤ V
≤ 5V, 6.25mm × 6.25mm × 2.3mm LGA Package
IN
IN
OUT
High V 0.5A DC/DC Step-Down µModule Regulator 3V ≤ V ≤ 36V, 0.8V ≤ V ≤ 5V, 6.25mm × 11.25mm × 2.8mm LGA Package
OUT
IN
IN
LTM8022/
LTM8023
36V , 1A and 2A DC/DC µModule Regulators
Pin Compatible, 4.5V ≤ V ≤ 36V, 9mm × 11.25mm × 2.8mm LGA Package
IN
IN
LTM8031/
LTM8032
1A, 2A EMC DC/DC µModule Regulators
3A EMC DC/DC µModule Regulator
EN55022 Class B Compliant, 3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V,
IN
OUT
Pin Compatible, 9mm × 15mm × 2.82mm LGA Package
LTM8033
3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 24V, 11.25mm × 15mm × 4.32mm LGA Package
OUT
IN
4606fd
LT 0214 REV D • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2008
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4606
相关型号:
![](http://pdffile.icpdf.com/pdf1/p00127/img/page/LTM46_703758_files/LTM46_703758_1.jpg)
![](http://pdffile.icpdf.com/pdf1/p00127/img/page/LTM46_703758_files/LTM46_703758_2.jpg)
LTM4607EV#PBF
LTM4607 - 36Vin, 24Vout High Efficiency Buck-Boost DC/DC µModule (Power Module); Package: LGA; Pins: 141; Temperature Range: -40°C to 85°C
Linear
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