LTM4606V_技术文档

LTM4606

Ultralow EMI 28V , 6A

IN

DC/DC µModule

FEATURES

DESCRIPTION

The LTM^®4606 is a complete ultralow noise high voltage

6A switching mode DC/DC power supply. Included in the

packagearetheswitchingcontroller,powerFETs,inductor,

and all support components. The on-board input ﬁlter and

noisecancellationcircuitsachievelownoiseoperation,thus

effectivelyreducingtheelectromagneticinterference(EMI).

Operating over an input voltage range of 4.5V to 28V, the

LTM4606 supports an output voltage range of 0.6V to 5V,

set by a single resistor. This high efﬁciency design deliv-

ers 6A continuous current (8A peak). Only bulk input and

output capacitors are needed to ﬁnish the design.

n

Complete Low EMI Switch Mode Power Supply

n

Wide Input Voltage Range: 4.5V to 28V

n

6A DC Typical, 8A Peak Output Current

n

0.6V to 5V Output Voltage Range

n

Low Input and Output Referred Noise

n

Output Voltage Tracking and Margining

n

PLL Frequency Synchronization

±±.5ꢀ Total DC Error

Power Good Output

n

Current Foldback Protection (Disabled at Start-Up)

n

Parallel/Current Sharing

n

Ultrafast Transient Response

High switching frequency and an adaptive on-time current

mode architecture enables a very fast transient response

to line and load changes without sacriﬁcing stability. The

device supports output voltage tracking and output volt-

age margining.

n

Current Mode Control

n

Up to 93% Efﬁciency at 5V , 3.3V

IN

OUT

n

Programmable Soft-Start

Output Overvoltage Protection

–55°C to 125°C Operating Temperature Range

(LTM4606MPV)

Furthermore, the μModule™ can be synchronized with an

externalclockforreducingundesirablefrequencyharmonics

and allows PolyPhase^®operation for high load currents.

n

Small Surface Mount Footprint, Low Proﬁle Package

(15mm × 15mm × 2.8mm)

The LTM4606 is offered in a space saving and thermally

enhanced 15mm × 15mm × 2.8mm LGA package, which

enables utilization of unused space on the bottom of

PC boards for high density point of load regulation. The

LTM4606 is Pb-free and RoHS compliant.

APPLICATIONS

n

ASICs or FPGA Transceivers

n

Telecom, Servers and Networking Equipment

n

Industrial Equipment

L, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology Corporation.

μModule is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

n

Rf Equipment

TYPICAL APPLICATION

Radiated Emission Scan at ±2V_IN,

2.5V_OUT/6A

Ultralow Noise 2.5V/6A Power Supply with 4.5V to 28V Input

100

90

4.5V TO 28V

CLOCK SYNC

V

PLLIN

80

IN

2.5V AT 6A

V

PGOOD

RUN

COMP

OUT

70

LTM4606

47pF

FB

ON/OFF

C

OUT

60

50

40

30

20

10

0

V

FB

R

CISPR.22, CLASS B, 3 METERS

C

10μF

35V

IN

INTV

DRV

CC

19.1k

FCB

MARG0

MARG1

MPGM

f

MARGIN

CERAMIC

x2

SET

TRACK/SS

CONTROL

TRACK/SS

V

D

392k

5% MARGIN

10μF

35V

SGND PGND

4606 TA01

0

100 200 300 400 500 600 700 800 9001000

FREQUENCY (MHz)

4606 TA01b

4606f

1

LTM4606

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note ±)

TOP VIEW

DRV , V

................................................–0.3V to 6V

CC OUT

PLLIN, FCB, TRACK/SS, MPGM, MARG0,

MARG1, PGOOD, RUN ..........–0.3V to INTV + 0.3V

12

11

10

9

8

7

6

5

4

3

MPGM

COMP

CC

V , f , COMP........................................–0.3V to 2.7V

FB SET

RUN

SGND

V , V .......................................................–0.3V to 28V

IN

D

TRACK/SS

V

Internal Operating Temperature Range (Note 2)

PLLIN

D

INTV

CC

E and I Grades ...................................–40°C to 125°C

MP Grade...........................................–55°C to 125°C

Junction Temperature ........................................... 125°C

Storage Temperature Range...................–45°C to 125°C

2

1

A

B

C

D

E

F

G

H

J

K

V

L

M

V

IN

PGND

BANK 2

OUT

BANK 3

BANK 1

LGA PACKAGE

133-LEAD (15mm × 15mm × 2.8mm)

T

= 125°C, θ = 15°C/W, θ = 6°C/W

JA JC

JMAX

θ

JA

DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS

WEIGHT = 1.7g

ORDER INFORMATION

LEAD FREE FINISH

LTM4606EV#PBF

LTM4606IV#PBF

LTM4606MPV#PBF

TRAY

PART MARKING*

LTM4606V

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTM4606EV#PBF

LTM4606IV#PBF

LTM4606MPV#PBF

133-Lead (15mm × 15mm × 2.8mm) LGA

LTM4606V

–40°C to 125°C

LTM4606MPV

–55°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://linear.com/packaging/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±2V, unless otherwise noted. Per typical application

(front page) conﬁguration, R_FB= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

4.5

TYP

MAX

28

UNITS

l

V

IN(DC)

Input DC Voltage

V

Output Voltage, Total Variation with

Line and Load

C

IN

V

IN

= 10μF x2, C = 200μF; FCB = 0

OUT

= 5V to 28V, I

1.478

1.5

1.522

OUT(DC)

= 0A to 6A, (Note 4)

OUT

Input Speciﬁcations

V

Undervoltage Lockout Threshold

Input Inrush Current at Start-Up

I

= 0A

3.2

4

V

IN(UVLO)

OUT

I

= 0A, C = 10μF x2, C

= 200μF,

INRUSH(VIN)

OUT

IN

OUT

V

= 1.5V

OUT

V

= 5V

0.6

0.7

A

IN

= 12V

4606f

2

LTM4606

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±2V, unless otherwise noted. Per typical application

(front page) conﬁguration, R_FB= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Input Supply Bias Current

V

= 5V, No Switching

1.5

27

mA

μA

Q(VIN)

IN

= 5V, V

= 1.5V, Switching Continuous

OUT

= 12V, No Switching

= 12V, V = 1.5V, Switching Continuous

2.5

25

OUT

Shutdown, RUN = 0, V = 12V

22

IN

I

Input Supply Current

S(VIN)

V

IN

V

IN

= 12V, V

= 1.5V, I = 6A

OUT

0.96

2.18

A

OUT

= 5V, V

= 1.5V, I

= 6A

OUT

INTV

V

= 12V, RUN > 2V

No Load

4.7

0

5

5.3

V

CC

IN

Output Speciﬁcations

I

Output Continuous Current Range

Line Regulation Accuracy

V

= 12V, V = 1.5V (Note 4)

OUT

6

A

OUT(DC)

IN

l

= 1.5V, FCB = 0V, V = 4.5V to 28V,

0.05

0.3

%

ΔV

V

OUT

IN

OUT(LINE)/ OUT

I

= 0A

Load Regulation Accuracy

Input Ripple Voltage

V

OUT

V

= 1.5V, FCB = 0V, I

IN

= 0A to 6A

ΔV

V

OUT

OUT(LOAD)/ OUT

= 12V (Note 4)

0.3

%

V

I

= 0A, C = 10μF X5R Ceramic x3 and

IN(AC)

OUT IN

100μF Electrolytic

V

= 5V, V

= 1.5V

2

3

mV

IN

OUT

P-P

= 12V, V

Output Ripple Voltage

I

= 0A, C

= 22μF X5R Ceramic x3 and

OUT(AC)

OUT

100μF X5R Ceramic

V

= 5V, V

= 1.5V

8

11

mV

IN

OUT

P-P

= 12V, V

f

S

Output Ripple Voltage Frequency

I

= 5A, V = 12V, V = 1.5V

OUT

900

kHz

OUT

IN

Turn-On Overshoot,

TRACK/SS = 10nF

C

= 200μF, V

IN

= 1.5V, I

OUT

= 0A

ΔV

OUT

V

OUT

OUT(START)

= 12V

= 5V

20

mV

t

Turn-On Time, TRACK/SS = Open

C

= 200μF; V

= 1.5V, I

OUT OUT

= 1A

START

OUT

Resistive Load

V

= 5V

0.5

ms

IN

= 12V

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load

ΔV

OUT(LS)

C

= 22μF Ceramic, 470μF x2

35

25

mV

μs

OUT

V

IN

V

OUT

= 12V

= 1.5V

t

I

Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load,

SETTLE

V

= 12V

V

= 12V

IN

Output Current Limit

C

= 200μF

OUT(PK)

OUT

V

= 5V, V

= 1.5V

OUT

10

A

IN

= 12V, V

= 1.5V

Control Section

l

V

Voltage at V Pin

I

= 0A, V = 1.5V

OUT

0.594

1

0.6

1.5

0.606

1.9

V

FB

OUT

RUN Pin On/Off Threshold

Soft-Start Charging Current

RUN

I

V

= 0V

–1

–1.5

–2

μA

SS/TRACK

4606f

3

LTM4606

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= ±2V, unless otherwise noted. Per typical application

(front page) conﬁguration, R_FB= 40.2k.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

0.6

–1

MAX

0.63

–2

UNITS

V

FCB

Forced Continuous Threshold

Forced Continuous Pin Current

Minimum On Time

0.57

I

t

V

= 0V

FCB

μA

ns

FCB

(Note 3)

50

100

400

ON(MIN)

OFF(MIN)

Minimum Off Time

250

50

ns

R

PLLIN

PLLIN Input Resistor

kΩ

mA

kΩ

V

I

Current into DRV Pin

V

OUT

= 1.5V, I = 1A

OUT

15

25

DRVCC

CC

R

Resistor Between V

and V Pins

60.098

60.4

5

60.702

FBHI

OUT

FB

RUN

Volts From RUN to GND Maximum

5.1V Zener Clamp

MAX

Margin Section

MPGM

Margin Reference Voltage Sets a

Current

1.18

1.4

V

MARG0, MARG1

Voltage Thresholds

PGOOD

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Hysteresis

V

Rising

7

10

–10

1.5

13

%

V

ΔV

FB

FBH

Falling

–7

–13

ΔV

FB

FBL

Returning

ΔV

FB

FB(HYS)

V

PGOOD Low Voltage

I

= 5mA

0.15

0.4

PGL

PGOOD

Note ±: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4606E is guaranteed to meet performance speciﬁcations

over the 0°C to 125°C internal operating temperature range. Speciﬁcations

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4606I is guaranteed to meet speciﬁcations over the

–40°C to 125°C internal operating temperature range. The LTM4606MP

is guaranteed and tested over the –55°C to 125°C internal operating

temperature range. Note that the maximum ambient temperature is

determined by speciﬁc operating conditions in conjunction with board

layout, the rated package thermal resistance and other environmental

factors.

Note 3: 100% tested at die level only.

Note 4: See output current derating curves for different V , V

and T .

A

IN OUT

4606f

4

LTM4606

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency vs Load Current with

5V_IN(FCB = 0)

Efﬁciency vs Load Current with

±2V_IN(FCB = 0)

Efﬁciency vs Load Current with

24V_IN(FCB = 0)

100

90

80

70

60

50

100

90

80

70

60

50

100

90

80

70

60

50

0.6V

1.2V

1.8V

2.5V

3.3V

1.2V

1.5V

2.5V

3.3V

5V

OUT

2.5V

3.3V

5V

OUT

0

1

2

3

4

5

6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

LOAD CURRENT (A)

4606 G01

4606 G02

4606 G03

±.2V Transient Response

±.5V Transient Response

±.8V Transient Response

I

OUT

2A/DIV

OUT

2A/DIV

V

OUT

50mV/DIV

OUT

50mV/DIV

4606 G04

4606 G05

4606 G06

50μs/DIV

1.2V AT 3.5A/μs LOAD STEP

1.5V AT 3.5A/μs LOAD STEP

1.8V AT 3.5A/μs LOAD STEP

C

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

C

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

C

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

OUT

2.5V Transient Response

3.3V Transient Response

–55°C, Start-Up, I_OUT= 0A

V

OUT

I

0.5V/DIV

OUT

2A/DIV

V

OUT

100mV/DIV

OUT

I

IN

50mV/DIV

0.5A/DIV

4606 G07

4606 G08

4606 G16

1ms/DIV

50μs/DIV

V

C

= 12V

IN

OUT

= 1.5V

2.5V AT 3.5A/μs LOAD STEP

3.3V AT 3.5A/μs LOAD STEP

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

SOFT-START = 3.9nF

C

OUT

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

C

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

OUT

4606f

5

LTM4606

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up, I_OUT= 6A

(Resistive Load)

–55°C, Start-Up, I_OUT= 6A

Start-Up, I_OUT= 0A

V

OUT

V

OUT

0.5V/DIV

I

IN

0.5A/DIV

I

IN

0.5A/DIV

I

4606 G17

IN

1ms/DIV

V

C

= 12V

OUT

IN

0.5A/DIV

= 1.5V

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

SOFT-START = 3.9nF

4606 G09

4606 G10

1ms/DIV

V

C

= 12V

OUT

1ms/DIV

V

C

= 12V

OUT

IN

= 1.5V

= 1x 22μF, 6.3V CERAMIC

1x 330μF, 4V SANYO POSCAP

SOFT-START = 3.9nF

V_INto V_OUTStep-Down

Operation Region

Short-Circuit Protection,

I_OUT= 0A

Short-Circuit Protection,

I_OUT= 6A

28

24

20

16

12

SEE FREQUENCY ADJUSTMENT SECTION

FOR OPERATIONS OUTSIDE THIS REGION

V

OUT

2V/DIV

1V/DIV

I

IN

I

IN

2A/DIV

OPERATION REGION

WITH DEFAULT FREQUENCY

0.2A/DIV

4606 G11

4606 G12

50μs/DIV

V

C

= 12V

OUT

V

C

= 12V

OUT

IN

= 2.5V

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

= 2x 22μF, 10V CERAMIC

1x 100μF, 6.3V CERAMIC

8

SOFT-START = 0.1μF

4.5

0.6 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V

OUT

(V)

4606 G13

V_FBvs Temperature

Input Ripple

Output Ripple

0.606

0.604

0.602

0.600

0.598

0.596

0.594

V

OUT

V

IN

2mV/DIV

10mV/DIV

4606 G14

4606 G15

2μs/DIV

V

C

= 5V

V

C

= 5V

IN

OUT

IN

= 1V AT 6A

OUT

= 3x 10μF, 25V CERAMIC

1x 150μF BULK

= 2x 22μF, 6.3V CERAMIC

1x 100μF, 6.3V CERAMIC

BW = 300MHz

–55

35

65

95

125

–25

5

TEMPERATURE (°C)

4606 G18

4606f

6

LTM4606

PIN FUNCTIONS

V (Bank ±): Power Input Pins. Apply input voltage be-

low load, to INTV to enable discontinuous mode opera-

tion at low load or to a resistive divider from a secondary

output when using a secondary winding.

IN

CC

tween these pins and PGND pins. Recommend placing

input decoupling capacitance directly between V pins

IN

and PGND pins.

TRACK/SS(PinA9):OutputVoltageTrackingandSoft-Start

Pin. When the module is conﬁgured as a master output,

then a soft-start capacitor is placed on this pin to ground

to control the master ramp rate. A soft-start capacitor can

be used for soft-start turn-on as a standalone regulator.

Slave operation is performed by putting a resistor divider

from the master output to ground, and connecting the

center point of the divider to this pin. See the Applications

Information section.

V

(Bank 3): Power Output Pins. Apply output load

OUT

between these pins and PGND pins. Recommend placing

outputdecouplingcapacitancedirectlybetweenthesepins

and PGND pins (see ﬁgure below).

PGND (Bank 2): Power Ground Pins for Both Input and

Output Returns.

V (PinsB7, C7):TopFETDrainPins. Addmorecapacitors

D

between V and ground to handle the input RMS current

D

MPGM (Pins A±2, B±±): Programmable Margining Input.

A resistor from these pins to ground sets a current that

is equal to 1.18V/R. This current multiplied by 10kΩ will

equal a value in millivolts that is a percentage of the 0.6V

referencevoltage.SeetheApplicationsInformationsection.

To parallel LTM4606s, each requires an individual MPGM

resistor. Do not tie MPGM pins together.

and reduce the input ripple further.

DRV (PinsC±0,E±±,E±2):Thesepinsnormallyconnect

CC

to INTV for powering the internal MOSFET drivers. They

CC

can be biased up to 6V from an external supply with about

50mA capability, or an external circuit as shown in Figure

18. This improves efﬁciency at the higher input voltages

by reducing power dissipation in the modules.

f

(Pin B±2): Frequency set internally to 800kHz. An

SET

INTV (Pin A7): This pin is for additional decoupling of

external resistor can be placed from this pin to ground

to increase frequency. This pin can be decoupled with a

1000pFcapacitor.SeetheApplicationsInformationsection

for frequency adjustment.

CC

the 5V internal regulator.

PLLIN(PinA8):ExternalClockSynchronizationInputtothe

Phase Detector. This pin is internally terminated to SGND

with a 50k resistor. Apply a clock above 2V and below

V

(Pin F±2): The Negative Input of the Error Ampliﬁer.

FB

INTV . See the Applications Information section.

Internally, this pin is connected to V

with a 60.4k preci-

CC

OUT

sionresistor.Differentoutputvoltagescanbeprogrammed

FCB(PinM±2):ForcedContinuousInput.Connectthispin

to SGND to force continuous synchronization operation at

withanadditionalresistorbetweentheV andSGNDpins.

FB

See the Applications Information section.

TOP VIEW

MARG0 (Pin C±2): LSB Logic Input for the Margining

Function. Together with the MARG1 pin, the MARG0 pin

will determine if a margin high, margin low, or no margin

state is applied. The pin has an internal pulldown resistor

of 50k. See the Applications Information section.

12

11

10

9

MPGM

COMP

RUN

SGND

TRACK/SS

PLLIN

INTV

CC

MARG±(PinsC±±, D±2):MSBLogicInputfortheMargin-

ingFunction.TogetherwiththeMARG0pin,theMARG1pins

will determine if a margin high, margin low, or no margin

stateisapplied.Thepinshaveaninternalpulldownresistor

of 50k. See the Applications Information section.

V

8

7

6

5

4

3

2

D

1

SGND (Pins D9, H±2): Signal Ground Pins. These pins

connect to PGND at output capacitor point.

A

B

C

D

E

F

G

H

J

K

V

L

M

V

PGND

BANK 2

IN

OUT

BANK 3

BANK 1

4606f

7

LTM4606

PIN FUNCTIONS

COMP(PinsA±±,D±±):CurrentControlThresholdandEr-

rorAmpliﬁerCompensationPoint.Thecurrentcomparator

threshold increases with this control voltage. The voltage

ranges from 0V to 2.4V with 0.7V corresponding to zero

sense voltage (zero current).

output voltage is not within 10% of the regulation point,

after a 25μs power bad mask timer expires.

RUN (Pins A±0, B9): Run Control Pins. A voltage above

1.9V will turn on the module, and below 1V will turn off

the module. A programmable UVLO function can be ac-

PGOOD (Pin G±2): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

complished with a resistor from V to this pin that has a

IN

5.1V zener to ground. Maximum pin voltage is 5V.

BLOCK DIAGRAM

>1.9V = ON

<1V = OFF

MAX = 5V

V

OUT

RUN

PGOOD

COMP

INPUT

FILTER

V

IN

4.5V TO 28V

+

5.1V

ZENER

1.5μF

C

IN

60.4k

V

D

INTERNAL

COMP

C

D

POWER CONTROL

M1

M2

SGND

V

OUT

2.5V

MARG1

MARG0

AT 6A

NOISE

CANCEL-

LATION

V

FB

22μF

50k 50k

+

f

SET

R

FB

C

OUT

19.1k

41.2k

PGND

FCB

10k

MPGM

TRACK/SS

PLLIN

C

SS

50k

4.7μF

INTV

DRV

CC

4606 F01

Figure ±. Simpliﬁed Block Diagram

DECOUPLING REQUIREMENTS ^T_A^{= 25°C. Use Figure ± conﬁguration.}

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

External Input Capacitor Requirement

IN

I

= 6A

10

μF

IN

OUT

(V = 4.5V to 28V, V

= 2.5V)

OUT

C

OUT

External Output Capacitor Requirement

(V = 4.5V to 28V, V = 2.5V)

I

= 6A

100

200

μF

OUT

IN

OUT

4606f

8

LTM4606

OPERATION

Power Module Description

and bottom FET M2 is turned on and held on until the

overvoltage condition clears.

TheLTM4606isastandalonenon-isolatedswitchingmode

DC/DC power supply. It can deliver up to 6A of DC output

current with some external input and output capacitors.

This module provides precisely regulated output voltage

Inputﬁlterandnoisecancellationcircuitsreducethenoise

coupling to I/O sides, and ensure the electromagnetic

interference (EMI) to meet the limits of CISPR 22 and

CISPR 25.

programmable via one external resistor from 0.6V to

DC

5.0V over a 4.5V to 28V input voltage range. The typical

DC

Pulling the RUN pin below 1V forces the controller into

its shutdown state, turning off both M1 and M2. At low

load currents, discontinuous mode (DCM) operation

can be enabled to achieve higher efﬁciency compared to

continuous mode (CCM) by setting the FCB pin higher

than 0.6V.

application schematic is shown in Figure 20.

The LTM4606 has an integrated constant on-time current

mode regulator, ultralow R

FETs with fast switching

DS(ON)

speed and integrated Schottky diodes. The typical switch-

ing frequency is 800kHz. With current mode control and

internalfeedbackloopcompensation,theLTM4606module

has sufﬁcient stability margins and good transient per-

formance under a wide range of operating conditions and

with a wide range of output capacitors, even all ceramic

output capacitors.

When the DRV pin is connected to INTV an integrated

CC

5V linear regulator powers the internal gate drivers. If a

5V external bias supply is applied on the DRV pin, then

CC

an efﬁciency improvement will occur due to the reduced

powerlossintheinternallinearregulator.Thisisespecially

true at the higher input voltage range.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limiting.Besides,foldbackcurrentlimitingisprovidedinan

overcurrentconditionwhileV drops.Internalovervoltage

andundervoltagecomparatorspulltheopen-drainPGOOD

output low if the output feedback voltage exits a 10%

window around the regulation point. Furthermore, in an

overvoltage condition, internal top FET M1 is turned off

The MPGM, MARG0, and MARG1 pins are used to sup-

port voltage margining, where the percentage of margin

is programmed by the MPGM pin, and the MARG0 and

MARG1 selected margining. The PLLIN pin provides fre-

quency synchronization of the device to an external clock.

The TRACK/SS pin is used for power supply tracking and

soft-start programming.

FB

4606f

9

LTM4606

APPLICATIONS INFORMATION

The typical LTM4606 application circuit is shown in

Figure 20. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 2 for speciﬁc external capacitor

requirements for a particular application.

where RPGM is the resistor value to place on the MPGM

pin to ground.

The output margining will be margining of the value.

This is controlled by the MARG0 and MARG1 pins. See

the truth table below:

V to V

Step-Down Ratios

MARG±

LOW

MARG0

LOW

MODE

IN

OUT

NO MARGIN

MARGIN UP

MARGIN DOWN

NO MARGIN

There are restrictions in the maximum V and V

step-

IN

OUT

LOW

HIGH

LOW

down ratio that can be achieved for a given input voltage.

These constraints are caused by the limitation of the

minimum on and off time in the internal switches. Refer

totheFrequencyAdjustmentsectiontochangetheswitch-

ing frequency and get wider input and output ranges. See

the Thermal Considerations and Output Current Derating

section in this data sheet for the current restrictions.

HIGH

Input Capacitors and Input EMI Noise Attenuation

The LTM4606 is designed to achieve the low input con-

ducted EMI noise due to the fast switching of turn-on

and turn-off. In the LTM4606, a high frequency inductor

Output Voltage Programming and Margining

is integrated to the input line for noise attenuation. V

D

and V pins are available for external input capacitors to

IN

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

As shown in the Block Diagram, a 60.4k internal feedback

form a high frequency ∏ ﬁlter. As shown in Figure 19, the

ceramiccapacitorC1ontheV pinsisusedtohandlemost

D

resistor connects the V

and V pins together. Adding

OUT

FB

of the RMS current into the converter, so careful attention

a resistor R from the V pin to the SGND pin programs

FB

is needed for capacitor C1 selection.

the output voltage:

For a buck converter, the switching duty-cycle can be

estimated as:

60.4k +R_FB

V_OUT= 0.6V

R_FB

V_OUT

D=

Table ±. R_FBStandard ±ꢀ Resistor Values vs V_OUT

V

IN

R

FB

(kΩ)

Open 60.4

0.6 1.2

40.2

1.5

30.1

1.8

25.5

2

19.1

2.5

13.3

3.3

8.25

5

Without considering the inductor ripple current, the RMS

current of the input capacitor can be estimated as:

V

OUT

(V)

I_OUT(MAX)

The MPGM pin programs a current that when multiplied

by an internal 10k resistor sets up the 0.6V reference

offset for margining. A 1.18V reference divided by the

RPGM resistor on the MPGM pin programs the current.

I_CIN(RMS)

=

• D• 1–D

(

)

η

In the above equation, η is the estimated efﬁciency of the

power module. Note the capacitor ripple current ratings

are often based on temperature and hours of life. This

makes it advisable to properly derate the capacitor, or

choose a capacitor rated at a higher temperature than

required. Always contact the capacitor manufacturer for

derating requirements.

Calculate V

:

OUT(MARGIN)

%V_OUT

100

V_OUT(MARGIN)

=

• V_OUT

where%V isthepercentageofV youwanttomargin,

OUT

OUT(MARGIN)

OUT

and V

is the margin quantity in volts:

In a typical 6A output application, one or two very low

ESR X5R or X7R, 10μF ceramic capacitors are recom-

mendedforC1.Thisdecouplingcapacitorshouldbeplaced

V_OUT

1.18V

R_PGM

=

•

•10k

0.6V V_OUT(MARGIN)

4606f

10

LTM4606

APPLICATIONS INFORMATION

directly adjacent to the module V pins in the PCB layout

spikeisrequired.Table2showsamatrixofdifferentoutput

voltages and output capacitors to minimize the voltage

droop and overshoot during a 3A/μs transient. The table

optimizes total equivalent ESR and total bulk capacitance

to maximize transient performance.

D

to minimize the trace inductance and high frequency AC

noise. Each 10μF ceramic is typically good for 2 to 3 amps

of RMS ripple current. Refer to your ceramics capacitor

catalog for the RMS current ratings.

To attenuate high frequency noise, extra input capacitors

Multiphase operation with multiple LTM4606 devices in

parallel will lower the effective output ripple current due

to the phase interleaving operation. Refer to Figure 3

for the normalized output ripple current versus the duty

cycle. Figure 3 provides a ratio of peak-to-peak output

ripple current to the inductor ripple current as functions

of duty cycle and the number of paralleled phases. Pick

the corresponding duty cycle and the number of phases

to get the correct output ripple current value. For example,

each phase’s inductor ripple current DIr at zero duty cycle

is ~2.5A for a 12V to 2.5V design. The duty cycle is about

0.21. The 2-phase curve has a ratio of ~0.58 for a duty

cycle of 0.21. This 0.58 ratio of output ripple current to

the inductor ripple current DIr at 2.5A equals ~1.5A of the

should be connected to the V pads and placed before

IN

the high frequency inductor to form the ∏ ﬁlter. One of

these low ESR ceramic capacitors is recommended to

be placed close to the connection into the system board.

A large bulk 100μF capacitor is only needed if the input

source impedance is compromised by long inductive

leads or traces. Figure 2 shows the conducted EMI

testing results to meet the level 5 of CISPR 25. For differ-

ent applications, input capacitance may be varied to meet

different conducted EMI limits.

80

70

60

50

output ripple current (ΔI ).

L

The output voltage ripple has two components that are

related to the amount of bulk capacitance and effective

series resistance (ESR) of the output bulk capacitance.

The equation is:

CIS25QP

40

30

20

10

0

⎛

⎝

⎞

⎠

ΔI_L

8 • f •N • C

ΔV_OUT(P−P)

≈

+ ESR • ΔI_L

⎜

⎟

OUT

0.15

1

10

30

FREQUENCY (MHz)

4606 F02

Where f is the frequency and N is the number of paral-

leled phases.

Figure 2. Conducted Emission Scan with ±2V_INto 2.5V_OUTat 6A

(3× ±0μF Ceramic Capacitors on V_INpads and ±× ±0μF Ceramic

Capacitor on V_DPads)

Fault Conditions: Current Limit and Overcurrent

Foldback

Output Capacitors

LTM4606 has a current mode controller, which inher-

ently limits the cycle-by-cycle inductor current not only

in steady-state operation, but also in transient.

The LTM4606 is designed for low output voltage ripples.

The bulk output capacitors deﬁned as C

are chosen

OUT

with low enough effective series resistance (ESR) to meet

theoutputvoltagerippleandtransientrequirements. C

To further limit current in the event of an overload condi-

tion,theLTM4606providesfoldbackcurrentlimiting.Ifthe

output voltage falls by more than 50%, then the maximum

output current is progressively lowered to about one sixth

of its full current limit value.

OUT

can be a low ESR tantalum capacitor, low ESR polymer

capacitor or ceramic capacitor. The typical capacitance is

200μF if all ceramic output capacitors are used. Additional

output ﬁltering may be required by the system designer,

if further reduction of output ripple or dynamic transient

4606f

11

LTM4606

APPLICATIONS INFORMATION

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

IN

4612 F05

O

Figure 3. Normalized Output Ripple Current vs Duty Cycle, Dlr = V_OT/L_I

Soft-Start and Tracking

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider. Figure 4

shows an example of coincident tracking. Ratiometric

modes of tracking can be achieved by selecting different

resistor values to change the output tracking ratio. The

master output must be greater than the slave output for

the tracking to work. Figure 5 shows the coincident output

tracking characteristics.

The TRACK/SS pin provides a means to either soft-start

the regulator or track it to a different power supply. A

capacitor on this pin will program the ramp rate of the

output voltage. A 1.5μA current source will charge up the

external soft-start capacitor to 80% of the 0.6V internal

voltagereferenceminusanymargindelta.Thiswillcontrol

the ramp of the internal reference and the output voltage.

The total soft-start time can be calculated as:

V

IN

C_SS

t_SOFTSTART≅ 0.8• 0.6V – V

•

(

)

OUT(MARGIN)

100k

1.5µA

V

IN

PLLIN

V

D

SLAVE

OUTPUT

2.5V

PGOOD

RUN

V

OUT

When the RUN pin falls below 2.5V, then the SS pin is reset

to allow for proper soft-start control when the regulator is

enabledagain.Currentfoldbackandforcecontinuousmode

are disabled during the soft-start process. The soft-start

functioncanalsobeusedtocontroltheoutputrampuptime,

so that another regulator can be easily tracked to it.

C

V

FB

OUT

LTM4606

C

COMP

FCB

MARG0

MARG1

MPGM

IN

INTV

CC

MASTER

OUTPUT

DRV

R2

60.4k

f

SET

TRACK

CONTROL

TRACK/SS

SGND PGND

19.1k

R1

19.1k

Output Voltage Tracking

4606 F04

Output voltage tracking can be programmed externally

usingtheTRACK/SSpin. Theoutputcanbetrackedupand

Figure 4. Output Voltage Coincident Tracking

4606f

12

LTM4606

APPLICATIONS INFORMATION

operation where the bottom MOSFET turns off when in-

ductor current reverses. FCB pin below the 0.6V threshold

forcescontinuoussynchronousoperation,allowingcurrent

to reverse at light loads and maintain low output ripple.

MASTER OUTPUT

SLAVE OUTPUT

OUTPUT

VOLTAGE

PLLIN

Thepowermodulehasaphase-lockedloopcomprisedofan

internal voltage controlled oscillator and a phase detector.

This allows the internal top MOSFET turn-on to be locked

totherisingedgeoftheexternalclock. Thefrequencyrange

is 30% around the operating frequency. A pulse detection

circuit is used to detect a clock on the PLLIN pin to turn on

the phase lock loop. The pulse width of the clock has to be

at least 400ns and 2V in amplitude. During the start-up of

the regulator, the phase-lock loop function is disabled.

4606 F05

TIME

Figure 5. Coincident Tracking Characteristics

Run Enable

The RUN pin is used to enable the power module. The

pin has an internal 5.1V zener to ground. The pin can be

driven with a logic input not to exceed 5V.

INTV and DRV Connection

CC

The RUN pin can also be used as an undervoltage lock out

(UVLO) function by connecting a resistor divider from the

input supply to the RUN pin:

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRV

for driving the internal power MOSFETs. Therefore, if

the system does not have a 5V power rail, the LTM4606

can be directly powered by Vin. The gate driver current

through the LDO is about 20mA. The internal LDO power

dissipation can be calculated as:

CC

R1+R2

V_UVLO

=

•1.5V

R2

where R2 is the bottom resistor of the divider, R1 is the

top resistor of the divider.

P

= 20mA • (V – 5V)

IN

LDO_LOSS

TheLTM4606alsoprovidesanexternalgatedrivervoltagepin

Power Good

DRV . If there is a 5V rail in the system, it is recommended

CC

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a 10% window around the regulation point and tracks

with margining.

toconnectDRV pintotheexternal5Vrail.Thisisespecially

CC

true for higher input voltages. Do not apply more than 6V to

the DRV pin. A 5V output can be used to power the DRV

CC

pin with an external circuit as shown in Figure 18.

COMP Pin

Parallel Operation of the Module

This pin is the external compensation pin. The module

has already been internally compensated for most output

voltages. Table 2 is provided for most application require-

ments. A Linear Technology μModule design tool will be

provided for other control loop optimization.

The LTM4606 device is an inherently current mode con-

trolleddevice.Parallelmoduleswillhaveverygoodcurrent

sharing. This will balance the thermals on the design. The

voltage feedback equation changes with the variable N as

modules are paralleled:

60.4k

FCB Pin

+R_FB

N

V_OUT= 0.6V

The FCB pin determines whether the bottom MOSFET

remains on when current reverses in the inductor. Tying

this pin above its 0.6V threshold enables discontinuous

R_FB

N is the number of paralleled modules.

4606f

13

LTM4606

APPLICATIONS INFORMATION

Thermal Considerations and Output Current Derating

will lower the maximum load current as a function of the

increasedambienttemperaturetokeepthemaximumjunc-

tiontemperatureofthepowermoduleat125°Cmaximum.

Each of the derating curves and the power loss curve that

corresponds to the correct output voltage can be used to

In different applications, LTM4606 operates in a variety

of thermal environments. The maximum output current is

limited by the environment thermal condition. Sufﬁcient

cooling should be provided to help ensure reliable opera-

tion. When the cooling is limited, proper output current

derating is necessary, considering ambient temperature,

airﬂow, input/output condition, and the need for increased

reliability.

solve for the approximate θ of the condition. Each ﬁgure

JA

has three curves that are taken at three different air ﬂow

conditions. Tables 3 and 4 provide the approximate θ

JA

for Figures 8 to 15. A complete explanation of the thermal

characteristics is provided in the thermal application note

AN110.

The power loss curves in Figures 6 and 7 can be used

in coordination with the load current derating curves in

Figures 8 to 15 for calculating an approximate θ for the

Safety Considerations

JA

module. The graphs delineate between no heat sink, and

TheLTM4606modulesdonotprovideisolationfromV to

IN

a BGA heat sink. Each of the load current derating curves

V

OUT

.Thereisnointernalfuse.Ifrequired,aslowblowfuse

6

5

2.5

2.0

1.5

1.0

0.5

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

24V LOSS

12V LOSS

4

3

5V LOSS

12V LOSS

2

5V , 1.5V , 0LFM

IN

OUT

1

0

5V , 1.5V , 200LFM

5V , 1.5V , 400LFM

IN

75

80

85

90

95

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

AMBIENT TEMPERATURE (°C)

OUTPUT CURRENT (A)

4606 F08

4606 F06

4606 F07

Figure 6. ±.5V Power Loss

Figure 7. 3.3V Power Loss

Figure 8. No Heat Sink

6

5

6

5

6

5

4

3

4

3

4

3

2

1

0

2

1

0

2

1

0

12V , 1.5V , 0LFM

5V , 1.5V , 0LFM

IN

OUT

IN

OUT

12V , 1.5V , 200LFM

5V , 1.5V , 200LFM

IN

OUT

IN

OUT

12V , 1.5V , 400LFM

5V , 1.5V , 400LFM

70

75

80

85

90

95

70

75

80

85

90

95

75

80

85

90

95

AMBIENT TEMPERATURE (°C)

4606 F11

4606 F10

4606 F09

12V , 1.5V , 0LFM

IN

OUT

12V , 1.5V , 200LFM

Figure ±±. BGA Heat Sink

Figure 9. BGA Heat Sink

12V , 1.5V , 400LFM

IN

Figure ±0. No Heat Sink

4606f

14

LTM4606

APPLICATIONS INFORMATION

6

5

6

5

4

3

4

3

2

1

0

2

12V , 3.3V , 0LFM

IN

OUT

1

0

IN

OUT

12V , 3.3V , 200LFM

IN

OUT

IN

OUT

12V , 3.3V , 400LFM

70

75

80

85

90

95

70

75

80

85

90

95

AMBIENT TEMPERATURE (°C)

4606 F13

4606 F12

Figure ±2. No Heat Sink

Figure ±3. BGA Heat Sink

6

5

6

5

4

3

2

1

0

4

3

2

1

0

24V , 3.3V , 0LFM

IN

OUT

IN

OUT

24V , 3.3V , 200LFM

IN

OUT

24V , 3.3V , 400LFM

IN

60

65

70

75

80

85

60

65

70

75

80

85

90

AMBIENT TEMPERATURE (°C)

4606 F14

4606 G15

Figure ±5. BGA Heat Sink

Figure ±4. No Heat Sink

100

90

80

70

60

50

40

30

20

10

0

with a rating twice the maximum input current needs to be

provided to protect each unit from catastrophic failure.

Radiated EMI Noise

High radiated EMI noise is a disadvantage for switching

regulators by nature. Fast switching turn-on and turn-off

make large di/dt change in the converters, which act as

the radiation sources in most systems. The LTM4606 in-

tegrates the feature to minimize the radiated EMI noise for

applications with low-noise requirements. Optimized gate

driver for the MOSFET and noise cancellation network are

installed inside the LTM4606 to achieve low radiated EMI

noise. Figure 16 shows a typical example for LTM4606 to

meet the Class B of CISPR 22 radiated emission limit.

0

100 200 300 400 500 600 700 800 9001000

FREQUENCY (MHz)

4606 F16

Figure ±6. Radiated Emission Scan with ±2V_INto 2.5V_OUTat 6A.

CISPR.22 Class B Chase 6±4± BiLog, RG-8 ±.5 Meters Chase

CPA923±A Horizontal, 3 Meters All Sides, 30MHz to ±000MHz,

RES BW ±20kHz, SWP 455ms.

4606f

15

LTM4606

APPLICATIONS INFORMATION

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20)

TYPICAL MEASURED VALUES

C

VENDORS

PART NUMBER

C

OUT2

VENDORS

PART NUMBER

OUT±

TAIYO YUDEN

TDK

JMK316BJ226ML-T501 (22μF, 6.3V)

JMK325BJ476MM-T (47μF, 6.3V)

C3225X5R0J476M (47μF, 6.3V)

SANYO POSCAP

6TPE220MIL (220μF, 6.3V)

2R5TPE330M9 (330μF, 2.5V)

4TPE330MCL (330μF, 4V)

V

C

V

(V)

DROOP

(mV)

PEAK TO

PEAK (mV)

RECOVERY

TIME (μs)

LOAD STEP

(A/μs)

R

FB

OUT

IN

OUT±

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

5

(CERAMIC)

2 × 10μF 35V

(BULK)

(CERAMIC)

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

1 × 22μF 6.3V

1 × 47μF 6.3V

2 × 47μF 6.3V

4 × 47μF 6.3V

(BULK)

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

(kΩ)

60.4

40.2

30.1

19.1

13.3

8.25

150μF 35V

5

34

22

68

40

30

26

24

18

30

26

24

18

30

26

30

26

37

30

26

37

30

26

40

34

28

12

40

34

28

18

40

32

28

14

40

32

28

22

20

3

5

20

40

5

32

60

2 × 10μF 35V 150μF 35V

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

12

5

34

68

22

40

20

39

29.5

35

55

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

70

5

25

48

5

24

47.5

68

5

36

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

12

5

35

70

25

48

24

45

32.6

38

61.9

76

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

5

29.5

28

57.5

55

5

43

80

330μF 4V

330μF 2.5V

220μF 6.3V

NONE

12

5

38

76

28

55

27

52

36.4

38

70

330μF 4V

220μF 6.3V

NONE

78

5

37.6

39.5

66

74

5

78.1

119

78

5

330μF 4V

220μF 6.3V

NONE

12

7

38

34.5

35.8

50

66.3

68.8

98

330μF 4V

220μF 6.3V

NONE

42

86

7

47

89

7

50

94

7

75

141

86

330μF 4V

220μF 6.3V

NONE

12

15

20

42

47

88

50

94

69

131

215

217

NONE

110

5

NONE

4606f

16

LTM4606

APPLICATIONS INFORMATION

Table 3. ±.5V Output

DERATING CURVE

Figures 8, 10

Figures 9, 11

V

(V)

POWER LOSS CURVE

Figure 6

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

5, 12

0

13.5

10

9

Figure 6

200

400

0

None

Figure 6

None

Figure 6

BGA Heat Sink

9.5

7

Figure 6

200

400

Figure 6

5

Table 4. 3.3V Output

DERATING CURVE

Figures 12, 14

V

(V)

POWER LOSS CURVE

Figure 7

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

12, 24

0

13.5

11

10

7

Figures 12, 14

12, 24

Figure 7

200

400

0

None

Figures 12, 14

Figure 7

None

Figures 13, 15

Figure 7

BGA Heat Sink

Figures 13, 15

Figure 7

200

400

Figures 13, 15

Figure 7

5

Heat Sink Manufacturer

Wakeﬁeld Engineering

Part No: LTN20069

Phone: 603-635-2800

Layout Checklist/Example

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

The high integration of LTM4606 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout con-

siderations are still necessary.

• Place one or more high frequency ceramic capacitors

close to the connection into the system board.

• Use large PCB copper areas for high current path, in-

cluding V , PGND and V . It helps to minimize the

Figure 17 gives a good example of the recommended

layout. For load current below 3A, decouple the input

and output grounds. Use vias to connect GND pads to the

bottom layer, then connect to the right side of the module

as the output GND.

IN

OUT

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the V , PGND and V

pins to minimize

D

OUT

high frequency noise.

V

IN

C

IN

• Place a dedicated power ground layer underneath the

unit.

GND

• UseroundcornersforthePCBcopperlayertominimize

the radiated noise.

SIGNAL

GND

• To minimize the EMI noise and reduce module thermal

stress,usemultipleviasforinterconnectionbetweentop

layer and other power layers on different locations.

C

OUT

V

OUT

4606 F17

• Do not put vias directly on pads, unless they are

capped.

Figure ±7. Recommended PCB Layout

4606f

17

LTM4606

APPLICATIONS INFORMATION

Frequency Adjustment

operating range of 10V to 28V for 1MHz operation with a

150k resistor to ground, and an 8V to 16V operating range

The LTM4606 is designed to typically operate at 800kHz

for f ﬂoating. These modiﬁcations are made to provide

SET

across most input conditions. The f pin is typically left

SET

wider input voltage ranges for the 5V output designs while

limiting the inductor ripple current, and maintaining the

400ns minimum off time.

open or decoupled with an optional 1000pF capacitor. The

switching frequency has been optimized for maintaining

constant output ripple noise over most operating ranges.

The 800kHz switching frequency and the 400ns minimum

off time can limit operation at higher duty cycles like 5V

to 3.3V, and produce excessive inductor ripple currents

for lower duty cycle applications like 28V to 5V.

Example for 3.3V Output

LTM4606 minimum on-time = 100ns;

t

ON

= ((3.3 • 10pF)/I

)

fSET

LTM4606 minimum off-time = 400ns;

= t – t , where t = 1/Frequency

Example for 5V Output

t

OFF

ON

LTM4606 minimum on-time = 100ns;

Duty Cycle (DC) = t /t or V /V

ON

OUT IN

t

= ((4.8 • 10pf)/I

)

ON

fSET

Equations for setting frequency:

= (V /(3 • R )), for 28V input operation, I =

fSET

LTM4606 minimum off-time = 400ns;

= t – t , where t = 1/Frequency

I

fSET

IN

fSET

t

OFF

ON

227μA, t = ((3.3 • 10pf)/I ), t = 145ns, where the

ON

fSET

fSET ON

Duty Cycle = t /t or V /V

internal R

is 41.2k. Frequency = (V /(V • t )) =

ON

OUT IN

OUT IN ON

(3.3V/(28 • 145ns)) ~ 810kHz. The minimum on-time and

minimum-off time are within speciﬁcation at 146ns and

1089ns. But the 4.5V minimum input for converting 3.3V

outputwillnotmeettheminimumoff-timespeciﬁcationof

400ns. t = 905ns, Frequency = 810kHz, t = 329ns.

Equations for setting frequency:

= (V /(3 • R )), where the internal R is 41.2k.

fSET

I

fSET

IN

fSET

For 28V input operation, I

= 227μA. t = ((4.8 • 10pF)/

ON

fSET

I

),t =211ns.Frequency=(V /(V •t ))=(5V/(28

fSET ON

OUT IN ON

ON

OFF

• 211ns)) ~ 850kHz. The inductor ripple current begins to

get high at the higher input voltages due to a larger voltage

across the inductor. The current ripple is ~5A at 20% duty

cycle if the integrated inductor is 1μH. The inductor ripple

current can be lowered at the higher input voltages by add-

Solution

Lower the switching frequency at lower input voltages to

allow for higher duty cycles, and meet the 400ns mini-

mum off-time at 4.5V input voltage. The off-time should

be about 500ns with 100ns guard band. The duty cycle

ing an external resistor from f to ground to increase the

SET

switching frequency. A 4A ripple current is chosen, and the

total peak current is equal to 1/2 of the 4A ripple current

plus the output current. For 5V output, current is limited to

5A, so the total peak current is less than 7A. This is below

the 8A peak speciﬁed value. A 150k resistor is placed from

for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t

or

OFF

(1 – 0.73)/500ns = 540kHz. The switching frequency

needs to be lowered to 540kHz at 4.5V input. t = DC/

ON

frequency, or 1.35μs. The f

pin voltage compliance

SET

is 1/3 of V , and the I

current equates to 36μA with

current needs to be 24μA for

IN

fSET

f

to ground, and the parallel combination of 150k and

SET

the internal 41.2k. The I

fSET

41.2k equates to 32.3k. The I

calculation with 32.3k

fSET

540kHz operation. A resistor can be placed from V

to

OUT

and 28V input voltage equals 289μA. This equates to a t

ON

f

to lower the effective I

current out of the f pin

SET

fSET SET

of 166ns. This will increase the switching frequency from

850kHzto~1MHzforthe28Vto5Vconversion.Theminimum

on time is above 100ns at 28V input. Since the switching

frequency is approximately constant over input and output

conditions, then the lower input voltage range is limited to

8V for the 1MHz operation due to the 400ns minimum off

to 24μA. The f

pin is 4.5V/3 =1.5V and V

= 3.3V,

OUT

SET

therefore an 150k resistor will source 12μA into the f

SET

node and lower the I

current to 24μA. This enables the

fSET

540kHz operation and the 4.5V to 28V input operation for

down converting to 3.3V output as shown in Figure 19.

The frequency will scale from 540kHz to 950kHz over this

input range. This provides for an effective output current

time. Equation:t =(V /V )•(1/Frequency)equatesto

ON

OUT IN

a 375ns on time, and a 400ns off time. Figure 18 shows an

of 5A over the input range.

4606f

18

LTM4606

TYPICAL APPLICATIONS

V

OUT

10V TO 28V

C1

10μF

R4

100k

R3

100k

V

PLLIN

D

IN

5V AT 5A

V

PGOOD

RUN

COMP

INTV

DRV

OUT

C2

C

22μF

6.3V

C

OUT2

220μF

6.3V

LTM4606

OUT1

100pF

+

ON/OFF

C

10μF

35V

V

FB

IN

R

FB

8.25k

CC

FCB

CERAMIC

x2

MARG0

MARG1

MPGM

f

MARGIN

SET

TRACK/SS

CONTROL

REFER TO TABLE 2

FOR OUTPUT CAPACITOR

SELECTIONS

TRACK/SS

CONTROL

SGND PGND

R1

392k

5% MARGIN

R

fSET

150k

4606 TA02

IMPROVE EFFICIENCY

FOR ≥12V INPUT

Figure ±8. ±0V to 28V_IN, 5V at 5A Design

V

OUT

4.5V TO 28V

C1

10μF

R4

100k

R3

100k

V

D

V

IN

PLLIN

3.3V AT 5A

V

PGOOD

RUN

COMP

OUT

C2

100pF

LTM4606

C

OUT2

220μF

6.3V

OUT1

+

ON/OFF

C

10μF

35V

22μF

6.3V

x2

V

FB

IN

R

FB

13.3k

INTV

CC

FCB

DRV

CERAMIC

x2

MARG0

MARG1

MPGM

f

MARGIN

SET

CONTROL

TRACK/SS

REFER TO TABLE 2

FOR OUTPUT CAPACITOR

SELECTIONS

R

fSET

150k

SGND PGND

R1

392k

5% MARGIN

TRACK/SS

CONTROL

V

OUT

4606 TA03

Figure ±9. 3.3V at 5A Design

4606f

19

LTM4606

TYPICAL APPLICATIONS

V

OUT

4.5V TO 28V

CLOCK SYNC

C1

10μF

R4

100k

R3

100k

V

PLLIN

D

IN

2.5V AT 6A

V

PGOOD

RUN

COMP

INTV

DRV

OUT

C2

C

22μF

6.3V

C

LTM4606

OUT1

OUT2

100pF

+

ON/OFF

220μF

6.3V

V

FB

R

FB

19.1k

CC

FCB

MARG0

MARG1

MPGM

f

MARGIN

SET

CONTROL

TRACK/SS

C

10μF

35V

CERAMIC

x2

IN

C4

0.01μF

SGND PGND

R1

392k

5% MARGIN

4606 TA04

Figure 20. Typical 4.5V to 28V_IN, 2.5V at 6A Design

V

OUT

V

IN

4.5V TO 28V

C1

10μF

CLOCK SYNC

0° PHASE

R2

100k

R4

V

D

V

IN

PLLIN

100k

2.5V AT 12A

PGOOD

RUN

COMP

V

OUT

C6

220pF

C

22μF

6.3V

LTM4606

OUT1

+

C

OUT2

220μF

6.3V

V

FB

FCB

INTV

CC

C2

10μF

35V

DRV

f

MARG0

MARG1

MPGM

MARGIN

CONTROL

SET

TRACK/SS

C5

100μF

35V

+

C4

0.33μF

R1

392k

R

FB

9.53k

SGND PGND

2-PHASE

OSCILLATOR

+

5% MARGIN

V

OUT1

GND OUT2

SET MOD

C7

0.1μF

R5

118k

C3

10μF

LTC6908-1

CLOCK SYNC

180° PHASE

R3

100k

V

PLLIN

D

IN

V

PGOOD

RUN

OUT

C

22μF

6.3V

LTM4606

OUT3

C

+

OUT4

220μF

6.3V

V

FB

COMP

C8

10μF

35V

FCB

INTV

CC

MARG0

MARG1

MPGM

DRV

CC

f

SET

TRACK/SS

R6

392k

SGND PGND

4606 TA05

5% MARGIN

Figure 2±. 2-Phase, Parallel 2.5V at ±2A Design

4606f

20

LTM4606

TYPICAL APPLICATIONS

3.3V

V

IN

5V TO 28V

C3

10μF

CLOCK SYNC

0° PHASE

R4

R2

100k

V

IN

PLLIN

100k

D

3.3V AT 6A

PGOOD

RUN

COMP

V

OUT

C6

C

LTM4606

OUT1

C

+

OUT2

22pF

100μF

6.3V

220μF

6.3V

V

FB

FCB

INTV

CC

DRV

C2

10μF

35V

f

MARG0

MARG1

MPGM

MARGIN

SET

TRACK/SS

CONTROL

C5

100μF

35V

+

R1

392k

R

FB1

13.3k

C7

0.15μF

SGND PGND

2-PHASE

OSCILLATOR

+

5% MARGIN

3.3V

V

OUT1

GND OUT2

SET MOD

C9

0.1μF

R5

118k

C4

10μF

LTC6908-1

CLOCK SYNC

180° PHASE

R7

100k

R3

100k

V

PLLIN

D

IN

2.5V AT 6A

V

OUT

PGOOD

RUN

C1

22pF

C

OUT3

LTM4606

C

+

OUT4

100μF

6.3V

220μF

6.3V

V

FCB

COMP

FB

C8

10μF

35V

INTV

CC

3.3V TRACK

R8

MARG0

MARG1

MPGM

MARGIN

CONTROL

DRV

CC

60.4k

f

SET

TRACK/SS

R6

392k

R

FB2

19.1k

R9

19.1k

SGND PGND

4606 TA06

Figure 22. 2-Phase, 3.3V and 2.5V Outputs at 6A with Tracking and Margining

1.8V

4.5V TO 28V

C3

10μF

CLOCK SYNC

0° PHASE

R4

100k

R2

100k

V

IN

PLLIN

D

1.8V AT 6A

PGOOD

RUN

COMP

V

OUT

C6

100pF

C

LTM4606

OUT1

C

+

OUT2

100μF

6.3V

220μF

6.3V

V

FB

FCB

INTV

DRV

CC

C2

CC

10μF

35V

f

MARG0

MARG1

MPGM

MARGIN

SET

TRACK/SS

CONTROL

C5

100μF

35V

+

R1

392k

R

FB1

30.1k

C7

0.15μF

SGND PGND

2-PHASE

OSCILLATOR

+

5% MARGIN

1.8V

V

OUT1

GND OUT2

SET MOD

C9

0.1μF

R5

182k

C4

10μF

LTC6908-1

CLOCK SYNC

180° PHASE

R7

100k

R3

100k

V

PLLIN

D

IN

1.5V AT 6A

V

OUT

PGOOD

RUN

C1

100pF

C

22μF

6.3V

LTM4606

OUT3

C

+

OUT4

220μF

6.3V

V

FCB

COMP

FB

C8

10μF

35V

INTV

CC

1.8V TRACK

R8

MARG0

MARG1

MPGM

DRV

MARGIN

CONTROL

CC

60.4k

f

SET

TRACK/SS

R6

392k

R

FB2

40.2k

R9

40.2k

SGND PGND

4606 TA07

Figure 23. 2-Phase, ±.8V and ±.5V Outputs at 6A with Tracking and Margining

4606f

21

LTM4606

PACKAGE DESCRIPTION

Pin Assignment Tables

(Arranged by Pin Function)

PIN NAME

PGND

PIN NAME

A1

A2

A3

A4

A5

A6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

D1

D2

D3

D4

D5

D6

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A7

INTV

CC

PLLIN

PGND

A8

A9

TRACK/SS

RUN

A10

A11

A12

COMP

MPGM

B1

B2

B3

B4

B5

B6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

E1

E2

E3

E4

E5

E6

E7

E8

PGND

B7

V

D

-

B8

B9

RUN

-

B10

B11

B12

MPGM

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

f

SET

C1

C2

C3

C4

C5

C6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

C7

V

-

D

C8

F1

F2

F3

F4

F5

F6

F7

F8

F9

PGND

C9

-

C10

C11

C12

DRV

CC

MARG1

MARG0

D7

-

D8

D9

SGND

-

D10

D11

D12

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

COMP

MARG1

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

PGND

E9

-

E10

E11

E12

DRV

CC

DRV

CC

F10

F11

F12

-

V

FB

G12

H12

J12

K12

L12

M12

PGOOD

SGND

NC

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

PGND

NC

FCB

4606f

22

LTM4606

PACKAGE DESCRIPTION

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

4606f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTM4606

PACKAGE PHOTOGRAPH

RELATED PARTS

PART NUMBER

LTC2900

DESCRIPTION

COMMENTS

Quad Supply Monitor with Adjustable Reset Timer

10A DC/DC μModule

Monitors Four Supplies; Adjustable Reset Timer

Basic 10A DC/DC μModule, LGA Package

Guaranteed Operation from –55°C to 125°C Ambient, LGA Package

LTM4600

LTM4600HVMP

Military Plastic 10A DC/DC μModule

LTM4601/

LTM4601A

12A DC/DC μModule with PLL, Output Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version has no

Remote Sensing, LGA Package

LTM4602

LTM4603

6A DC/DC μModule

Pin Compatible with the LTM4600, LGA Package

6A DC/DC μModule with PLL and Outpupt Tracking/ Synchronizable, PolyPhase Operation, LTM4603-1 Version has no Remote

Margining and Remote Sensing

Sensing, Pin Compatible with the LTM4601, LGA Package

LTM4604/

LTM4604A

Low V 4A DC/DC μModule

2.375V ≤ V ≤ 5.5V, 0.8V ≤ V ≤ 5V, 9mm × 15mm × 2.3mm LGA Package

IN

OUT

LTM4608/

LTM4608A

Low V 8A DC/DC μModule

2.375V ≤ V ≤ 5.5V; 0.6V ≤ V

≤ 5V; 9mm × 15mm × 2.8mm LGA Package

IN

OUT

LTM4612

LTM8020

LTM8021

Low Noise 4.5A, 15V

DC/DC μModule

Low Noise, with PLL, Output Tracking and Margining, LTM4606 Pin-Compatible

OUT

High V 0.2A DC/DC Step-Down μModule

4V ≤ V ≤ 36V, 1.25V ≤ V

≤ 5V 6.25mm × 6.25mm × 2.3mm LGA Package

OUT

IN

High V 0.5A DC/DC Step-Down μModule

3V ≤ V ≤ 36V, 0.8V ≤ V

≤ 5V 6.25mm × 11.25mm × 2.8mm LGA Package

OUT

IN

LTM8022/LTM8023 36V , 1A and 2A DC/DC μModule

Pin Compatible; 4.5V ≤ V ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package

IN

4606f

LT 0708 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTM4606V
厂家：	Linear
描述：	Ultralow EMI 28VIN, 6A DC/DC μModule 超低EMI 28VIN ， 6A DC / DC微型模块
文件：	总24页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4606V [Linear]

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