LTM4611 [Linear]
Ultralow VIN, 15A DC/DC μModule Regulator; 超低VIN ， 15A DC / DC微型模块稳压器
| 型号： | LTM4611 |
| 厂家： | 
Linear |
| 描述： | Ultralow VIN, 15A DC/DC μModule Regulator |
| 文件： | 总28页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4611
Ultralow V , 15A DC/DC
IN
µModule Regulator
FeaTures
DescripTion
n
Complete Switch Mode Power Supply
The LTM4611 is a high density 15A output, switch mode
DC/DC buck converter power supply capable of operating
fromverylowvoltageinputsupplies. Includedinthepack-
age are the buck switching controller, power FETs, induc-
tor and loop-compensation components. The LTM4611
delivers up to 15A continuous current at high efficiency
n
Input Voltage Range: 1.5V to 5.5V
n
15A DC Output
n
Output Voltage Range: 0.8V to 5V
n
1.5ꢀ ꢁotal DC Output Error
n
Differential Remote Sensing for Precision
Regulation
from an input voltage of 1.5V up to 5.5V . The output
IN
IN
n
Current Mode Control/ Fast ꢁransient Response
voltage is set between 0.8V and 5V by a resistor. Only a
n
Overcurrent Foldback Protection
few input and output capacitors are needed.
Parallel Multiple LꢁM®4611s for Current Sharing
n
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing
operation, Burst Mode operation and output voltage
tracking for supply rail sequencing.
n
Frequency Synchronization
Selectable Pulse-Skipping or Burst Mode® Operation
n
n
Soft-Start/Voltage Tracking
n
Up to 94% Efficiency
n
Output Overvoltage Protection
n
Small 15mm × 15mm × 4.32mm LGA Package
The LTM4611 is available in a thermally enhanced 15mm
×15mm×4.32mmLGApackage. TheLTM4611isPB-free
and RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, PolyPhase and µModule are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258,
6304066, 6476589, 6774611, 6677210.
applicaTions
n
Telecom Servers and Networking Equipment
n
Storage and ATCA Cards
n
General Purpose Point of Load Regulation
Typical applicaTion
1.5VIN to 5.5VIN, 15A Step-Down DC/DC µModule® Regulator
Efficiency vs Load Current
V
96
IN
1.5V TO 5.5V
22µF
s3
94
C
SS
0.1µF
V
PGOOD
IN
**
V
92
90
88
86
84
82
80
OUT
STEP-DOWN
15A
TRACK/SS
RUN
V
OUT
C
*
FF
5V , 3.3V
IN
LTM4611
V
OUT
FB
3.3V , 2.5V
IN
OUT
OUT
OUT
OUT
OUT
100µF*
V
OUT_LCL
2.5V , 1.5V
IN
s4
2.5V , 1.2V
IN
MODE_PLLIN
DIFFV
OUT
+
3.3V , 1V
IN
1.5V , 0.9V
V
V
IN
OSNS
5V , 1V
IN
OUT
–
OSNS
SGND GND
C *
P
R
**
FB
*SEE TABLE 5
**SEE TABLE 1
78
4611 TA01
0
5
15
10
LOAD CURRENT (A)
4611 TA01b
4611f
ꢀ
LTM4611
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
Terminal Voltages
INTV
TRACK/SS
CC
MODE_PLLIN
V
V ........................................................... –0.2V to 6V
RUN COMP
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
V
OUT
with
A
B
C
D
E
DIFF AMP....–0.1V to the Lesser of (V + 0.1V) or 4V
IN
V
IN
PLLFLTR/f
MTP1-9
SET
V
OUT
without
DIFF AMP..–0.1V to the Lesser of (V + 0.1V) or 5.5V
IN
RUN, INTV , V
..........................................6V
CC OUT_LCL
INTV
CC
MODE_PLLIN, PLLFLTR/f
,
SET
F
V
FB
GND
TRACK/SS, V
–, V
+,
OSNS
OSNS
PGOOD
SGND
G
H
J
PGOOD ................................................. –0.3V to 5.5V
COMP, V ............................................. –0.3V to 2.7V
FB
V
OSNS
+
Terminal Currents
K
L
DIFFV
OUT
V
OUT
DIFFV ............................................. –10mA to 1mA
OUT
V
OUT_LCL
Temperatures
V
–
M
OSNS
Operating Junction Temperature Range
(Note 2) ............................................ –40°C to 125°C
Storage Temperature Range .............. –55°C to 125°C
Peak Solder Reflow Body Temperature
(Note 3) ............................................................ 250°C
LGA PACKAGE
133-LEAD (15mm s 15mm s 4.32mm)
T
= 125°C
J(MAX)
θ
JCtop
= 26°C/W, θ = 2.3°C/W, θ = 10°C/W, θ = 14°C/W
JCbottom JB JA
θ VALUES DETERMINED PER JESD51-12
WEIGHT = 2.6 GRAMS
orDer inForMaTion
LEAD FREE FINISH
LTM4611EV#PBF
LTM4611IV#PBF
ꢁRAY
PARꢁ MARKING*
LTM4611V
PACKAGE DESCRIPꢁION
ꢁEMPERAꢁURE RANGE
–40°C to 125°C
LTM4611EV#PBF
LTM4611IV#PBF
133-Lead (15mm × 15mm × 4.32mm) LGA
133-Lead (15mm × 15mm × 4.32mm) LGA
LTM4611V
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
4611f
ꢁ
LTM4611
elecTrical characTerisTics ꢁhe l denotes the specifications which apply over the full internal operating
junction temperature range, otherwise specifications are at ꢁA = 25°C, VIN = 3.3V, per the typical application in Figure 21.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
Input Specifications
l
l
V
V
V
V
Input DC Voltage
1.5
1.1
5.5
V
V
IN
RUN Pin On Threshold
RUN Pin On Hysteresis
RUN Pin Voltage when Floating
V
Rising
1.22
80
1.35
RUN
RUN
mV
V
RUNHYS
RUN(FLOAT)
RUN(UP,1V)
3.4
3.65
1.1
4
I
I
I
I
RUN Pin Pull-Up Current
(RUN = 1V)
µA
RUN Pin Pull-Up Current
(RUN = 1.5V)
10
1
µA
nA
RUN(UP,1.5V)
RUN(DOWN,5V)
Q
RUN Pin Pull-Down Current
(RUN = 5V)
Input Supply Bias Current
V
V
V
= 1.5V, Burst Mode Operation, I
= 0.1A
= 0.1A
= 0.1A
70
140
145
1.1
mA
mA
mA
mA
OUT
OUT
OUT
OUT
OUT
OUT
= 1.5V, Pulse-Skipping Mode, I
= 1.5V, Switching Continuous, I
Shutdown, RUN = 0V
I
Input Supply Current
V
V
V
V
= 2.5V, V
= 3.3V, V
= 1.5V, I
= 1.5V, I
= 15A
= 15A
10.4
7.9
A
A
A
A
S(VIN)
IN
IN
IN
IN
OUT
OUT
OUT
OUT
= 5V, V
= 1.5V, I
= 15A
OUT
5.3
OUT
= 1.5V, V
= 0.8V, I
= 15A
10.2
OUT
OUT
Output Specifications
V
Output Voltage, Total Variation
with Line and Load
Utilizing DIFF_AMP, R = Not Used, V = 1.5V to
0.785
0.781
0.797
0.797
0.809
0.813
V
V
OUT(DC)
FB
IN
l
5.5V, I
= 0A to 15A (Note 4), R Electrically
OUT
FB
Floating, MODE_PLLIN = GND
(Example See Figure 21)
(Example See Figure 20)
V
Utilizing DIFF_AMP
3.7
5.4
15
V
V
OUT(RANGE)
OUT(DC)
Not Utilizing DIFF_AMP
Output Continuous Current Range
Line Regulation Accuracy
I
V
OUT
V
OUT
= V (Note 4)
0
A
FB
l
l
= V , V from 1.5V to 5.5V, I
= 0A
OUT
0.3
%
∆V
(Line)
OUT
FB IN
OUT
V
Load Regulation Accuracy
Output Ripple Voltage
Turn-On Overshoot
Turn-On Time
V
= 1.5V, I
= 0A to 15A, V = 3.3V
0.2
8
0.5
%
∆V
(Load)
OUT
OUT
OUT
IN
OUT
V
(Note 4)
V
mV
I
= 0A, C
= 100µF ×4 X5R Ceramic,
OUT
OUT(AC)
P-P
OUT
IN
V
= 3.3V, V
= 1.5V
OUT
5
mV
µs
∆V
C
= 100µF ×4 X5R Ceramic, V
= 0A, V = 3.3V, C = 1nF
IN SS
= 1.5V,
OUT
OUT(START)
OUTLS
OUT
OUT
I
t
500
60
C
C
= 100µF ×4 X5R Ceramic, No Load,
START
OUT
SS
= 1nF, V = 3.3V, V = 1.5V
OUT
IN
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
= 3.3V, V = 1.5V, C = 100µF ×4
mV
∆V
V
IN
OUT
FF
OUT
X5R Ceramic, C = 100pF
t
I
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
= 3.3V, V = 1.5V, C = 100µF ×4
40
µs
SETTLE
V
IN
OUT
OUT
X5R Ceramic, C = 100pF
FF
Output Current Limit
V
V
= 5V, V = 1.5V
OUT
30
30
A
A
OUT(PK)
IN
IN
= 3.3V, V
= 1.5V
OUT
4611f
ꢂ
LTM4611
elecTrical characTerisTics ꢁhe l denotes the specifications which apply over the full internal operating
junction temperature range, otherwise specifications are at ꢁA = 25°C, VIN = 3.3V, per the typical application in Figure 21.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
Control Section
l
l
V
Voltage at V Pin
I
= 0A, V
= V
FB
0.783
0.797
–10
0.811
V
nA
V
FB
FB
OUT
OUT
I
FB
V
Feedback Overvoltage Lockout
0.84
0.9
0.87
1.4
0.89
1.9
OVL
I
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
(Note 5)
µA
TRACK/SS
t
Minimum On-Time
90
ns
ON(MIN)
R
Resistor Between V
60.05
60.40
60.75
kΩ
FBHI
OUT_LCL
and V Pins
FB
+
V
V
,
Common Mode Input Range
V
V
= 3.3V, Run > 1.5V
0
0
INTV – 1
V
OSNS
IN
IN
CC
–
OSNS CM RANGE
DIFFV
Range
DIFF_AMP Output Voltage Range
= 3.3V, DIFFV
Load = 100k
INTV
CC
V
OUT
OUT
V
DIFF_AMP Input Offset Voltage
Magnitude
1.25
2
mV
mV
OS
l
A
V
DIFF_AMP Differential Gain
PGOOD Trip Level
1
V/V
V
V
with Respect to Set Output
PGOOD
FB
–7.5
7.5
%
%
%
%
V
V
V
V
Ramping Positive, PGOOD Transitioning
Ramping Positive, PGOOD Transitioning
Ramping Negative, PGOOD Transitioning
Ramping Negative, PGOOD Transitioning
–10
5
–5
10
10
–5
FB
FB
FB
FB
7.5
5
–7.5
–10
SR
DIFF_AMP Slew Rate
2
3
V/µs
MHz
GBP
DIFF_AMP Gain-Bandwidth
Product
CMRR
DIFF_AMP Common Mode
Rejection
100
dB
R
DIFF_AMP Input Resistance
V
+ to GND
19.9
4.8
20.0
20.1
5.2
kΩ
IN
OSNS
INꢁV Linear Regulator
CC
V
V
Internal V Voltage
1.5V < V < 5.5V
5
V
INTVCC
INTVCC
CC
IN
Load Reg INTV Load Regulation
I
= 0 to 50mA
CC
0.5
%
CC
Oscillator and Phase-Locked Loop
f
Output Ripple Voltage Frequency
V
= 3.3V, V = 1.5V,
OUT
280
360
835
710
kHz
kHz
S
IN
0.85V ≤ PLLFLTR/f
≤ 2.0V
SET
f
SYNC Capture Range
SYNC
4611f
ꢃ
LTM4611
elecTrical characTerisTics ꢁhe l denotes the specifications which apply over the full internal operating
junction temperature range, otherwise specifications are at ꢁA = 25°C, VIN = 3.3V, per the typical application in Figure 21.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
PLLFLTR/f
PLLFLTR/f
Voltage
Open-Circuit
PLLFLTR/f
Pin Voltage When Floating
1.23
V
SET(FLOAT)
SET
SET
Frequency Nominal Nominal Frequency
PLLFLTR/f
PLLFLTR/f
PLLFLTR/f
Floating
= 0.85V
= 2.0V
500
330
780
kHz
kHz
kHz
SET
SET
SET
Frequency Low
Frequency High
Lowest Frequency
Highest Frequency
I
PLLFLTR
Sourcing Capability
Sinking Capability
PLLFLTR
Mode_PLLIN Frequency > f
Mode_PLLIN Frequency < f
–13
13
µA
µA
OSC
OSC
R
Mode_PLLIN Input Resistance
Clock Input Level High
250
kΩ
V
MODE(PLLIN)
V
V
2.0
40
IH
IL
Clock Input Level Low
0.6
60
V
Mode_PLLIN
Clock
Clock Input Duty Cycle Range
50
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Consistent with Pb-free 260°C peak IR reflow soldering profiles.
See Application Note 100.
Note 4: See output current derating curves for different V , V
and T .
A
IN OUT
Note 5: The minimum on-time condition is specified for a peak-to-peak
Note 2: The LTM4611 is tested under pulsed load conditions such that
inductor ripple current of ~40% of I
section)
Load. (See the Typical Applications
MAX
T ≈ T . The LTM4611E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C operating junction temperature (T ) range.
J
Specifications over the full –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LTM4611I is guaranteed to meet
specifications over the full –40°C to 125°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
4611f
ꢄ
LTM4611
Typical perForMance characTerisTics
Efficiency vs Load Current at
1.8VIN, Forced Continuous Mode
Efficiency vs Load Current at
2.5VIN, Forced Continuous Mode
Efficiency vs Load Current at
1.5VIN, Forced Continuous Mode
95
90
85
80
75
95
90
85
80
75
95
90
85
80
75
1.2V
1.0V
0.9V
0.8V
OUT
OUT
OUT
OUT
1.5V
1.2V
1.0V
0.9V
0.8V
OUT
OUT
OUT
OUT
OUT
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
OUT
OUT
OUT
OUT
OUT
OUT
0
3
6
9
12
15
3
9
0
6
12
15
3
9
0
6
12
15
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4611 G01
4611 G02
4611 G03
Efficiency vs Load Current at
5VIN, Forced Continuous Mode
Efficiency vs Load Current at
Burst Mode Efficiency
3.3VIN, Forced Continuous Mode
95
90
85
80
75
95
90
85
80
75
95
90
85
80
75
70
65
60
55
50
45
40
35
30
3.3V TO 1.5V
IN
OUT
5V TO 1V
IN
OUT
2.5V
OUT
1.2V
1.0V
0.9V
0.8V
3.3V
2.5V
1.8V
1.5V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1.8V
1.5V
1.2V
1.0V
0.9V
0.8V
OUT
OUT
OUT
OUT
OUT
OUT
3
6
9
12
10
0
3
6
9
12
15
0
15
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4611 G14
4611 G05
4611 G04
Pulse-Skipping Mode Efficiency
1V ꢁransient Response, 3.3VIN
1V ꢁransient Response, 5VIN
95
90
85
80
75
70
65
60
55
50
45
40
35
30
V
V
OUT
OUT
50mV/DIV
50mV/DIV
3.3V TO 1.5V
IN
OUT
AC-COUPLED
AC-COUPLED
5V TO 1V
IN
OUT
I
I
LOAD
LOAD
5A/DIV
5A/DIV
4611 G06
4611 G07
20µs/DIV
20µs/DIV
V
= 3.3V, V
= 1V, USING DIFF AMP
V
= 5V, V
= 1V, USING DIFF AMP
OUT
IN
OUT
IN
4 s 100µF CERAMIC OUTPUT CAPACITORS
4 s 100µF CERAMIC OUTPUT CAPACITORS
= 47pF, C = NONE
C
FF
= 47pF, C = NONE
P
C
FF
P
7.5A LOAD STEP AT 7.5A/µs
7.5A LOAD STEP AT 7.5A/µs
0.1
1
10
OUTPUT CURRENT (A)
4611 G15
4611f
ꢅ
LTM4611
Typical perForMance characTerisTics
Start-Up, 15A Load
Start-Up, No Load
3.3V ꢁransient Response, 5VIN
V
IN
1V/DIV
V
OUT
V
IN
50mV/DIV
1V/DIV
V
OUT
AC-COUPLED
500mV/DIV
V
I
OUT
LOAD
500mV/DIV
5A/DIV
I
LOAD
I
I
5A/DIV
IN
IN
5A/DIV
1A/DIV
4611 G09
4611 G12
4611 G08
1ms/DIV
= 1.5V, NO LOAD
3 s 22µF CERAMIC INPUT CAPACITORS
= 10nF
1ms/DIV
20µs/DIV
= 3.3V, USING DIFF AMP
V
= 3.3V, V
V
= 3.3V, V = 1.5V, 100mΩ LOAD
V
= 5V, V
IN
OUT
IN
OUT
IN
OUT
3 s 22µF CERAMIC INPUT CAPACITORS
2 s 100µF CERAMIC OUTPUT CAPACITORS
C
C
= 10nF
C
= 10pF, C = NONE
P
7.5A LOAD STEP AT 7.5A/µs
SS
SS
FF
4 s 100µF CERAMIC OUTPUT CAPACITORS
= 33pF, C = 10pF
4 s 100µF CERAMIC OUTPUT CAPACITORS
C = 33pF, C = 10pF
FF
C
FF
P
P
Start-Up, Pre-Bias
Short-Circuit, 15A
Short-Circuit, No Load
V
OUT
V
V
500mV/DIV
OUT
OUT
500mV/DIV
500mV/DIV
I
LOAD
2mA/DIV
I
IN
I
IN
1A/DIV
I
IN
1A/DIV
2A/DIV
RUN
5V/DIV
4611 G10
4611 G13
4611 G11
20µs/DIV
= 1.5V
2ms/DIV
20µs/DIV
V
= 3.3V, V
= 1.5V, 0.75V PRE-BIAS LOAD
V
= 3.3V, V
= 1.5V
OUT
V
= 3.3V, V
OUT
IN
OUT
IN
IN
3 s 22µF CERAMIC INPUT CAPACITORS
= 10nF
NO LOAD PRIOR TO SHORT
15A LOAD PRIOR TO SHORT
C
SS
4 s 100µF CERAMIC OUTPUT CAPACITORS
= 33pF, C = 10pF
C
FF
P
pin FuncTions
SGND:(G11, H11, H12)SignalGroundPin. Returnground
path for all analog and low power circuitry. Tie a single
connection to the output capacitor GND in the application.
See the layout guidelines in Figure 17.
V : (A1-A6, B1-B6, C1-C6) Power Input Pins. Apply input
IN
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between
V pins and GND pins.
IN
MODE_PLLIN:(A8)ForcedContinuousMode,BurstMode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to GND to force continuous mode
V
: (J1-J10, K1-K11, L1-L11, M1-M11) Power Output
OUꢁ
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 5.
operation. Connect to INTV to enable pulse-skip-
CC
GND: (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,
H1-H9) Power Ground Pins for Both Input and Output
Returns.
ping mode operation. Leaving the pin floating will
enable Burst Mode operation. A clock on this pin will
enablesynchronizationwithforcedcontinuousoperation.
See the Applications Information section.
PGOOD:(F11,G12)OutputVoltagePowerGoodIndicator.
Open-drain logic output that is pulled to ground when the
output voltage exceeds a 5% regulation window. Both
pins are tied together internally.
4611f
ꢆ
LTM4611
pin FuncTions
INꢁV : (A7, D9) Internal 5V LDO for Driving the Control
Circuitry and the Power MOSFET Drivers. Both pins are
internally connected.
PLLFLꢁR/f : (B12) Phase-Locked Loop Lowpass Filter
CC
SEꢁ
fortheInternalPhaseDetector.LTM4611’sdefaultswitch-
ing frequency is 500kHz. Its switching frequency can be
increasedbyconnectingaresistorfromthispintoINTV ,
or decreased by connecting a resistor from this pin to
SGND. See the Applications Information section.
CC
V
: (L12) This pin connects to V
through a 1M
OUꢁ_LCL
OUT
resistorandtoV witha60.4kresistor. Theremotesense
FB
amplifier output DIFFV
is connected to V
, and
OUT
OUT_LCL
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
V : (F12) The Negative Input of the Error Amplifier.
FB
Internally, this pin is connected to V
with a 60.4k
OUT_LCL
the DIFF_V
effectively eliminates the 1MΩ from V
precision resistor. Different output voltages can be pro-
OUT
OUT
to V
. When the remote sense amplifier is not used,
grammed with an additional resistor between the V and
OUT_LCL
FB
GND pins. In PolyPhase® operation, tying the V pins
then connect V
to V
directly.
OUT_LCL
OUT
FB
togetherallowsforparalleloperation.SeetheApplications
Information section for details.
+
V
: (J12) (+) Input to the Remote Sense Amplifier.
OSNS
This pin connects to the output remote sense point. The
remote sense amplifier is used for V
> 3.7V, tie V
sense amplifier.
≤ 3.7V. For V
ꢁRACK/SS: (A9) Output Voltage Tracking Pin and Soft-
Start Inputs. The pin has a 1.4µA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. Tie all TRACK/SS pins
together for parallel operation. See the Applications In-
formation section.
OUT
OUT
+
to GND to rail the output of the remote
OSNS
–
V
OSNS
: (M12) (–) Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remotesenseamplifierisusedforV
3.7V, tie V
sense amplifier.
≤3.7V. ForV
>
OUT
OUT
–
to INTV to rail the output of the remote
OSNS
CC
DIFFV : (K12) Output of the Remote Sense Amplifier.
OUꢁ
This pin connects to the V
pin for remote sense
OUT_LCL
COMP:(A11)CurrentControlThresholdandErrorAmplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together for parallel operation. The device is internally
compensated.
applications. Otherwise float when not used.
MꢁP1:A12, MꢁP2:B11, MꢁP3:C10, MꢁP4:C11, MꢁP5:
C12, MꢁP6:D10, MꢁP7:D11, MꢁP8:D12, MꢁP9:E12:
Extra mounting pads used for increased solder integrity
strength. Leave electrically open circuit.
RUN: (A10) Run Control Pin. A voltage above 1.35V will
turnoninthemodule.TheV undervoltagelockout(UVLO)
IN
of the LTM4611 must be set with resistor networks from
V to RUN and optionally from RUN to GND. Tie all RUN
IN
pins together for parallel operation.
4611f
ꢇ
LTM4611
block DiagraM
INTV
CC
1M
V
OUT_LCL
10k
V
OUT
PGOOD
V
IN
>1.35V = ON
<1.1V = OFF
ABS MAX = 6V
R1
R2
V
IN
RUN
V
µPOWER BIAS
GENERATOR
IN
1.5V TO 5.5V
+
+
2µF
COMP
C
IN
0.5%
60.4k
M1
INTERNAL
COMP
AS NEEDED
V
0.2µH
OUT
V
OUT
1V
SGND
POWER
CONTROL
15A
10µF
V
FB
C
OUT
M2
PLLFLTR/f
SET
GND
240k
INTV
CC
INTERNAL
10k
LOOP
FILTER
10k
10k
V
–
–
+
OSNS
OSNS
+
–
TRACK/SS
V
+
MODE_PLLIN
C
SS
INTV
CC
10k
C
DIFFV
OUT
4611 F01
Figure 1. Simplified LꢁM4611 Block Diagram
ꢁA = 25°C. Use Figure 1 configuration.
Decoupling reQuireMenTs
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
C
External Input Capacitor Requirement
IN
I
= 15A
66
µF
IN
OUT
(V = 1.5V to 5.5V, V
= 1V)
OUT
C
External Output Capacitor Requirement
(V = 1.5V to 5.5V, V = 1V)
I
= 15A
400
µF
OUT
OUT
IN
OUT
4611f
ꢈ
LTM4611
operaTion
Power Module Description
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for program-
ming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
The LTM4611 is a high performance single output stand-
alone nonisolated switching mode DC/DC power supply.
It can provide a 15A output with few external input and
output capacitors. This module provides precisely regu-
latedoutputvoltagesprogrammableviaexternalresistors
The LTM4611 is internally compensated to be stable over
all operating conditions. Table 5 provides a guideline for
input and output capacitances for several operating con-
ditions. The Linear Technology µModule Power Design
Tool will be provided for transient and stability analysis.
from 0.8V to 5V over a 1.5V to 5.5V input range. The
DC
DC
typical application schematic is shown in Figure 21.
The LTM4611 has an integrated constant-frequency cur-
rent mode regulator, power MOSFETs, 0.2µH inductor
and other supporting discrete components. The nominal
switching frequency range isfrom330kHzto 780kHz, and
the default operating frequency is 500kHz. For switching
noise-sensitive applications, it can be externally syn-
chronized from 360kHz to 710kHz. See the Applications
Information section.
The V pin is used to program the output voltage with a
FB
single external resistor to ground.
Aremotesenseamplifierisprovidedforaccuratelysensing
output voltages ≤3.7V at the load point.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See the Typical Applications.
With current mode control and internal feedback loop
compensation, the LTM4611 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light-load features will accommodate battery
operation. Efficiency graphs are provided for light-load
operation in the Typical Performance Characteristics
section.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >7.5%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
4611f
ꢀ0
LTM4611
applicaTions inForMaTion
The typical LTM4611 application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
is used, then DIFFV
is connected to the V
pin.
OUT_LCL
OUT
OUT_LCL
If the remote sense amplifier is not used, then V
connects to V . The output voltage will default to 0.8V
OUT
with no feedback resistor. Adding a resistor R from V
FB
FB
to GND programs the output voltage:
60.4k+RFB
V to V
Step-Down Ratios
IN
OUꢁ
VOUT = 0.8V •
RFB
There are restrictions in the V to V
step-down
IN
OUT
ratio that can be achieved for a given input voltage. The
V to V minimum dropout is still a function of its load
ꢁable 1. VFB Resistor ꢁable vs Various Output Voltages
0.8V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V
(kΩ) Open 243 121 68.1 47.5 28.0 19.1 11.5
V
IN
OUT
OUꢁ
current at very low input voltages. A dropout voltage of
300mV from input to output of LTM4611 is achievable
at 15A load, but reflected input voltage ripple and noise
should be taken into consideration in such applications.
Additionally,thetransient-handlingcapabilityofthesource
supply feeding LTM4611 can become an important factor
in truly achieving ultralow dropout at high output current.
R
FB
For parallel operation of N LTM4611s, the following equa-
tion can be used to solve for R :
FB
60.4k /N
RFB =
VOUT
–1
0.8V
For example, V can sag or overshoot dramatically when
IN
Tie the V pins together for each parallel output. The
FB
LTM4611 responds to heavy transient step loads on its
output, if insufficient input bypass capacitance is used in
combination with a sluggish source supply.
COMP, TRACK/SS, V
tied together as shown in Figures 18 and 19.
, and RUN pins must also be
OUT_LCL
For parallel applications, best noise immunity can be
When V
is expected to be within 600mV of V , or
IN
OUT
achievedbyplacingcapacitorsofvalueC fromV toGND,
P
FB
when the caliber of the source supply is in question, it
is recommended to evaluate the amount and quality of
input bypass capacitance needed to maintain one’s target
dropout voltage with the source supply that will be used
in the end application. Demo Board DC1588A can be used
for such evaluation.
and value C from V
to V , local to each µModule.
FF
OUT
FB
If space limitations impede realizing this, then placement
of capacitors of value N • C from V to GND, and value
P
FB
FB
N • C from V
to the bussed V signal, can suffice.
FF
OUT
Input Capacitors
At very low duty cycles the minimum specified on-time
must be maintained. See the Frequency Adjustment sec-
tion and temperature derating curves.
The LTM4611 module should be connected to a low
AC impedance DC source. Additional input capacitors
are needed for the RMS input ripple current rating. The
To prevent overstress to the µpower bias generator, do
I
equation which follows can be used to calculate
CIN(RMS)
not ramp up V at a rate exceeding 5V/µs (in practice, it
IN
the input capacitor requirement. Typically 22µF X7R ce-
ramics are a good choice with RMS ripple current ratings
of ~2A each. A 100µF to 150µF surface mount aluminum
electrolytic bulk capacitor can be used for more input
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
is difficult to violate this guideline.) There is no restriction
on how rapidly V may be discharged.
IN
Output Voltage Programming
ThePWMcontrollerhasaninternal0.8V 1.75%reference
voltage over temperature. As shown in the Block Diagram,
a 60.4k internal feedback resistor connects the V
OUT_LCL
and V pins together. When the remote sense amplifier
FB
4611f
ꢀꢀ
LTM4611
applicaTions inForMaTion
For a buck converter, the switching duty cycle can be
estimated as:
Burst Mode Operation
The LTM4611 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
wheremaximizingtheefficiencyatverylightloadsisahigh
priority,BurstModeoperationshouldbeapplied.Toenable
Burst Mode operation, simply leave the MODE_PLLIN pin
floating. During Burst Mode operation, the peak current of
the inductor is set to approximately 33% of the maximum
peak current value in normal operation even though the
V
OUT
VIN
D=
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
IOUT(MAX)
ICIN(RMS)
=
• D•(1–D)
η%
voltage at the I pin indicates a lower value. The voltage
TH
at the I pin drops when the inductor’s average current is
TH
Intheaboveequation,η%istheestimatedefficiencyofthe
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor or a Polymer capacitor.
greaterthantheloadrequirement.AstheI voltagedrops
TH
below0.5V,theburstcomparatortrips,causingtheinternal
sleep line to go high and turn off both power MOSFETs.
Output Capacitors
In this sleep mode, the internal circuitry is partially turned
off, reducing the LTM4611’s quiescent current while the
load current is supplied by the output capacitors. When
The LTM4611 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
are
OUT
the output voltage drops–causing I to rise–the internal
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
TH
sleep line goes low and the LTM4611 resumes normal
operation. The next oscillator cycle turns on the top power
MOSFET and the switching cycle repeats.
ments. C
can be the low ESR tantalum capacitor, the
OUT
low ESR Polymer capacitor or ceramic capacitors. The
typical output capacitance range is from 200µF to 800µF.
Additional output filtering may be required by the system
designer, if further reduction of output ripple or dynamic
transient spikes is required. Table 5 shows a matrix of dif-
ferent output voltages and output capacitors to minimize
the voltage droop and overshoot during a 7A/µs transient.
The table optimizes total equivalent ESR and total bulk
capacitancetooptimizethetransientperformance.Stabil-
ity criteria are considered in the Table 5 matrix, and the
Linear Technology µModule Power Design Tool will be
provided for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
a function of stability and transient response. The Linear
Technology µModule Power Design Tool can calculate the
output ripple reduction as the number of implemented
phase’s increases by N times.
Pulse-Skipping Mode Operation
In applications where low output ripple and high effi-
ciencyatintermediatecurrentsaredesired,pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4611 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTV enables pulse-skipping
CC
operation. With pulse-skipping mode at light load, the
internalcurrentcomparatormayremaintrippedforseveral
cycles,thusskippingoperationcycles.Thismodehaslower
ripple than Burst Mode operation and maintains a higher
frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
4611f
ꢀꢁ
LTM4611
applicaTions inForMaTion
enabled by tying the MODE_PLLIN pin to GND. In this
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used. See Application Note 77.
mode, inductor current is allowed to reverse during low
output loads, the I voltage is in control of the current
TH
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4611’s output
voltage is in regulation.
The LTM4611 device is an inherently current mode con-
trolled device, so parallel modules will have good current
sharing. This will balance the thermals on the design.
Tie the COMP, V
and V pins of each LTM4611
OUT_LCL
FB
Multiphase Operation
together to share the current evenly. In addition, tie the
respectiveTRACK/SSandRUNpinsofparalleledLTM4611
devices together, to ensure proper start-up and shutdown
behavior. Figures 18 and 19 show schematics of LTM4611
devices operating in parallel.
For outputs that demand more than 15A of load current,
multiple LTM4611 devices can be paralleled to provide
more output current without increasing input and output
voltageripples.TheMODE_PLLINpinallowstheLTM4611
to be synchronized to an external clock (between 360kHz
to 710kHz) and the internal phase-locked loop allows the
LTM4611 to lock onto input clock phase as well. The PLL-
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases
(see Figure 2).
FLTR/f pin has the onboard loop filter for the PLL. See
SET
Figures 18 and 19 for a synchronizing example circuit.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
0.60
1 PHASE
2 PHASE
0.55
3 PHASE
4 PHASE
6 PHASE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
OUT IN
4617#3EM F02
Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six µModules (Phases)
4611f
ꢀꢂ
LTM4611
applicaTions inForMaTion
PLL, Frequency Adjustment and Synchronization
The default switching frequency of the LTM4611–with
benefit due to the high inductor ripple currents associated
withthatoperatingcondition.SeetheTypicalApplications
sectionforsynchronizationexamples.TheLTM4611mini-
mum on-time is limited to 90ns. Guardband the on-time
to 130ns. The on-time can be calculated as:
PLLFLTR/f
PLLFLTR/f
left floating–is 500kHz, nominally. The
pin is driven to 1.23V through a high im-
SET
SET
pedance (>350kΩ) network. If desired, a resistor (R
)
fSET
can be connected from the PLLFLTR/f
pin to INTV
SET
CC
V
1
OUT
tON(MIN)
=
•
to increase the switching frequency to as high as 780kHz,
nominally. Alternatively, R can instead be connected
FREQ
VIN
fSET
from PLLFLTR/f
to signal ground (SGND) to decrease
SET
Output Voltage ꢁracking and Soft-Start Functions
theswitchingfrequencytoaslowastheminimumspecified
valueof330kHz,nominally.Inpracticalterms,however,be
advised that switching frequencies below 400kHz may be
of limited benefit due to the high inductor ripple currents
associated with that operating condition. See Figure 3.
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4611 uses an
accurate60.4kresistorinternallyforthetopfeedbackresis-
tor. Figure 4 shows an example of coincident tracking.
There exists a fundamental trade-off between switch
mode DC/DC power conversion efficiency and switching
frequency: higher operating module switching frequency
enables the smallest overall solution size (minimized
output capacitance) for a given application; whereas,
lower switching frequency enables the highest efficiency
for a given application (to the extent that peak and RMS
inductor currents can be supported), but requires more
outputcapacitancetomaintaincomparableoutputvoltage
ripple and noise characteristics.
60.4k
RFB2
VOUT _ SLAVE = 1+
• VTRACK
V
V
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.8V, or the internal
TRACK
TRACK
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, thentheslavewillcoincidenttrackwiththemaster
until it reaches its final value. The master will continue
to its final value from the slave’s regulation point. Volt-
TheLTM4611canbesynchronizedfrom360kHzto710kHz
with an input clock that has a high level above 2V and a
low level below 0.6V. Again in practical terms, be advised
thatswitchingfrequenciesbelow400kHzmaybeoflimited
age tracking is disabled when V is more than 0.8V.
2.05
1.91
1.78
1.64
1.50
1.37
1.23
1.09
0.96
0.82
0.68
0.55
0.41
800
750
700
650
600
550
500
450
400
350
300
250
200
TRACK
R
in Figure 4 will be equal to the R
for coincident
TA
FB2
R
CONNECTED
CC
fSET
TO INTV
tracking.
R
fSET
The TRACK/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator
canbeusedtodevelopthatmasterramp.TheLTM4611can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.4µA current source
is used to charge the soft-start capacitor. The following
equation can be used:
NOT USED
R
CONNECTED
fSET
TO GND
SWITCHING FREQUENCY
PLLFLTR/f VOLTAGE
SET
0.1
1
10
100
VALUE OF RESISTOR ON PLLFLTR/f
PIN (MΩ)
4611 F03
SET
CSS
1.4µA
tSOFTSTART = 0.8V •
Figure 3. Relationship Between Oscillator Frequency,
PLLFLꢁR/fSEꢁ Voltage, and External RISEꢁ Value and
Connection
4611f
ꢀꢃ
LTM4611
applicaTions inForMaTion
V
IN
1.8V TO 5.5V
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN1
IN2
IN3
SOFT-START
CAPACITOR
PGOOD
CC
V
INTV
IN
V
1.5V
15A
OUT
COMP
V
C
OUT
SS
C
*
R2
10k
+
C
*
OUT2
OUT1
TRACK/SS
RUN
V
OUT_LCL
100µF
6.3V
470µF
6.3V
LTM4611
DIFFV
OUT
+
PLLFLTR/f
V
V
SET
OSNS
CONTINUOUS MODE
–
MODE_PLLIN
OSNS
C
*
FF1
V
FB
SGND
GND
R
C *
P1
47pF
FB1
69.8k
V
IN
1.8V TO 5.5V
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN4
IN5
IN6
MASTER RAMP
OR OUTPUT
PGOOD
CC
V
INTV
IN
V
1.2V
15A
OUT
R
TB
R
TA
COMP
V
OUT
V
OUT_LCL
60.4k
121k
R1
10k
+
C
*
C
*
OUT3
OUT4
TRACK/SS
RUN
470µF
6.3V
100µF
LTM4611
6.3V
DIFFV
OUT
+
PLLFLTR/f
V
V
SET
OSNS
CONTINUOUS MODE
–
MODE_PLLIN
OSNS
C
*
FF2
V
FB
SGND
GND
R
C *
P2
FB2
121k
47pF
4611 F04
*SEE TABLE 5
Figure 4. Dual Outputs (1.5V and 1.2V) With ꢁracking
minimum to 9.8ms maximum. Tracking a rail in a man-
ner such that TRACK/SS ramps up at a rate faster than
210V/s may also warrant special attention, as explained
in the following.
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT
VOLTAGE
Fasterturn-onandtrackingratesareachievable,ifneeded:
one need only decrease the default PLLFLTR/f RC time
SET
constant. Recall that the PLLFLTR/f
pin is biased to
SET
1.23Vviaahighimpedancesource(>350kΩ);alsobeaware
4611 F05
TIME
that the internal PLL filter contains an initially discharged
Figure 5. Output Voltage Coincident ꢁracking
10nF capacitor prior to INTV being established.
CC
Requiring the output voltage to power up rapidly without
Even for applications that do not require tracking or
attention to the PLLFLTR/f
time-constant results in
SET
sequencing, a minimum recommended value for C is
SS
an initial switching frequency of operation that is initially
10nF (X7R MLCC, 10% tolerance, nominal; X5R material
may be substituted if the capacitor temperature will not
exceed85°C),yieldingextremeturn-onrisetimesof3.8ms
lower than expected (~250kHz)—only during the early
stagesofstart-up—untilthePLLFLTR/f voltagereaches
SET
steady-state value (1.23V by default).
4611f
ꢀꢄ
LTM4611
applicaTions inForMaTion
Decreasing the PLLFLTR/f
RC time constant can be
Inratiometrictracking,adifferentslewratemaybedesired
SET
accomplished, for example, by driving the PLLFLTR/f
for the slave regulator. R can be solved for when SR is
SET
TB
pin with an external, lower impedance resistor divider
network from INTV and GND to PLLFLTR/f —in the
slower than MR. Make sure that the slave supply slew rate
ischosentobefastenoughsothattheslaveoutputvoltage
will reach its final value before the master output.
CC
SET
simplest of implementations, by shorting PLLFLTR/f
SET
to INTV (therebyprogramming the switching frequency
CC
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then R
= 75k. Solve for R to equal to 87k.
TB
to 780kHz, nominal), or by driving the PLLFLTR/f
from a low impedance voltage source.
pin
SET
TA
Beware that without any kind of soft-start ramp up, it is
important to provide thorough input filter capacitance to
handle input surge currents at start-up, so as to avoid
excessive input line sag and power supply motor boating.
Leavingprovisionforatleastasoft-startcapacitorinone’s
application is strongly recommended.
When,inadditiontoneedingfasterturn-ontime,oneisalso
synchronizingtoanexternalclocksignal, oneneedbearin
mind: the PLL’s sink and source current is recommended
for not more than 8µA loading, and the PLL will need
to successfully drive any external PLLFLTR/f
network
SET
impedance to achieve phase lock; and lastly, some phase
shiftinclocksynchronizationwilloccurasexternalloading
Overcurrent and Overvoltage Protection
on PLLFLTR/f
becomes heavier.
SET
The LTM4611 has overcurrent protection (OCP) in a
short circuit. The internal current comparator threshold
folds back during a short to reduce the output current.
An overvoltage condition (OVP) above 7.5% of the regu-
lated output voltage will force the top MOSFET off and
the bottom MOSFET on until the condition is cleared. An
input electronic circuit breaker or fuse can be sized to be
tripped or cleared when the bottom MOSFET is turned on
toprotectagainsttheovervoltage.Foldbackcurrentlimiting
is disabled during soft-start or tracking start-up.
Tobeclear,usingaC valueof10nF(orhigher)eliminates
SS
the need for any of the above special considerations or
provisions.
Ratiometric tracking can be achieved by a few simple
calculationsandtheslewratevalueappliedtothemaster’s
TRACK/SSpin.Asmentionedabove,theTRACK/SSpinhas
a control range from 0V to 0.8V. The master’s TRACK/SS
pin slew rate is directly equal to the master’s output slew
rate in volts/time. The equation:
MR
SR
Run Enable
•60.4k= RTB
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.22V. The
RUN pin must be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus R
TB
is equal to 60.4k. R is derived from equation:
TA
R1
R2=
0.8V
RTA =
VUVLO
–1
VFB
VFB VTRACK
+
–
1.22V
60.4k RFB2
RTB
To achieve the lowest possible UVLO, 1.22V, leave R2
unpopulated. R1 can be 10k, or if R2 is unpopulated, R1
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.8V. Since R is equal to the 60.4k
TB
TRACK
may be replaced with a hardwired connection from V
to RUN.
IN
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then R is equal to R with
TA
FB2
V
= V
. Therefore R = 60.4k, and R = 121k in
TRACK TB TA
FB
Figure 4.
4611f
ꢀꢅ
LTM4611
applicaTions inForMaTion
See the Block Diagram for the example of use. When
RUN is below its threshold, TRACK/SS is pulled low by
internal circuity.
For increased accuracy and fidelity to the actual applica-
tion, many designers use finite element analysis (FEA)
to predict thermal performance. To that end, the Pin
Configuration section of the data sheet typically gives
four thermal coefficients:
INꢁV Regulator
CC
TheLTM4611hasaninternallyregulatedbiassupplycalled
. θ : thermal resistance from junction to ambient.
1
JA
INTV . This regulator output has a 4.7µF ceramic capaci-
CC
2. θ
: thermal resistance from junction to the bot-
JCbottom
tom of the product case.
tor internal. This regulator powers the internal controller
and MOSFET drivers. The gate driver current is ~13mA for
500kHz operation and ~20mA for 780kHz operation; the
regulator loss is ~40mW and ~60mW, respectively.
3. θ : thermal resistance from junction to top of the
JCtop
product case.
Stability Compensation
4. θ : thermal resistance from junction to the printed
JB
circuit board.
The module has already been internally compensated
for all output voltages. Table 5 is provided for most ap-
plication requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased in the following:
1. θ is the natural convection junction-to-ambient air
JA
ꢁhermal Considerations and Output Current Derating
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
air to move. This value is determined with the part
mounted to a JESD 51-9 defined test board, which does
not necessarily reflect an actual application or viable
operating condition.
The LTM4611 output current may need to be derated if it
is required to operate in a high ambient temperature or
deliver a large amount of continuous power. Some factors
that influence derating are input voltage, output power,
ambient temperature, airflow, and elevation (air density).
The power loss curves in Figures 7 to 9 and current de-
rating curves in Figures 10 to 16 can be used as a guide.
These curves were generated by an LTM4611 mounted to
a 95mm × 76mm 4-layer FR4 printed circuit board (PCB)
1.6mm thick with two ounce copper for the outer layers
and one ounce copper for the two inner layers. Boards of
other sizes and layer count can exhibit different thermal
behavior, so it is ultimately incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental operating conditions.
2. θ
is the junction-to-board thermal resistance
JCbottom
with all of the component power dissipation flow-
ing through the bottom of the package. In the typical
µModule, the bulk of the heat flows out the bottom of
the package, but there is always heat flow out into the
ambientenvironment.Asaresult,thisthermalresistance
valuemaybeusefulforcomparingpackagesbutthetest
conditionsdon’tgenerallymatchtheuser’sapplication.
3. θ
is determined with nearly all of the component
JCtop
ThethermalresistancenumberslistedinthePinConfigura-
tion section of the data sheet are based on modeling the
µModule package mounted on a test board specified per
JESD51-9 (“Test Boards for Area Array Surface Mount
Package Thermal Measurements”). The thermal coef-
ficients provided are based on JESD 51-12 (“Guidelines
for Reporting and Using Electronic Package Thermal
Information”).
power dissipation flowing through the top of the pack-
age.AstheelectricalconnectionsofthetypicalµModule
are on the bottom of the package, it is rare for an ap-
plication to operate such that most of the heat flows
from the junction to the top of the part. As in the case
of θ
, this value may be useful for comparing
JCbottom
packages but the test conditions don’t generally match
the user’s application.
4611f
ꢀꢆ
LTM4611
applicaTions inForMaTion
the printed circuit board. Consequently, a poor printed
circuit board design can cause excessive heating, result-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions
4. θ is the junction-to-board thermal resistance where
JB
almost all of the heat flows through the bottom of the
µModule and into the board, and is really the sum of
the θ
and the thermal resistance of the bottom
JCbottom
of the part through the solder joints and through a por-
tion of the board. The board temperature is measured
a specified distance from the package, using a two
sided, two layer board. This board is described in JESD
51-9.
The 1.2V, 2.5V and 3.3V power loss curves in Figures 7
and 8 can be used in coordination with the load current
derating curves in Figures 9 to 16 for calculating an
approximate θ thermal resistance for the LTM4611
JA
with various heat sinking and air flow conditions, as
evaluated on the aforementioned 4-layer FR4 PCB. The
power loss curves are taken at room temperature, and
are increased with multiplicative factors with ambient
temperature. Theseapproximatefactorsare:1upto50°C;
1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 15A and the ambient temperature at 55°C. The
output voltages are 1.2V, 2.5V and 3.3V. These are chosen
to include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a
controlled temperature chamber along with thermal mod-
eling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
air flow, and with and without a heat sink attached with
thermally conductive adhesive tape. The BGA heat sinks
evaluated in Table 5 yield very comparable performance
in laminar airflow despite being visibly different in con-
struction and form factor. The power loss increase with
Given these definitions, it should now be apparent that
none of these thermal coefficients reflects an actual
physical operating condition of a µModule. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
given in the product’s data sheet. The only appropriate
way to use the coefficients is to run a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 5.
The blue resistances are contained within the µModule,
and the green are outside.
The die temperature of the LTM4611 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM4611. The bulk of the heat flow out of the LTM4611 is
through the bottom of the module and the LGA pads into
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
µMODULE
A
t
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
BOARD-TO-AMBIENT
RESISTANCE
RESISTANCE
4611 F06
Figure 6
4611f
ꢀꢇ
LTM4611
applicaTions inForMaTion
16
4.0
3.5
3.0
2.5
4.0
3.5
3.0
2.5
5V TO 2.5V
IN
5V
OUT
OUT
OUT
IN
5V TO 3.3V
3.3V
2.5V
1.8V
1.5V
14
12
IN
IN
IN
IN
IN
3.3V TO 2.5V
IN
10
8
2.0
1.5
2.0
1.5
6
4
1.0
0.5
0
1.0
0.5
0
400LFM
200LFM
0LFM
2
0
65
75
95 105 115 125
55
85
3
6
12
3
6
12
0
15
0
15
9
9
AMBIENT TEMPERATURE (°C)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4611 F09
4611 F08
4611 F07
Figure 9. 5VIN to 1.2VOUꢁ No Heat Sink
Figure 7. 1.2VOUꢁ Power Loss
Figure 8. 2.5VOUꢁ and 3.3VOUꢁ Power Loss
16
16
16
14
12
14
12
14
12
10
8
10
8
10
8
6
6
6
4
4
4
400LFM
400LFM
400LFM
200LFM
0LFM
2
2
2
200LFM
200LFM
0LFM
0LFM
0
0
0
65
75
95 105 115 125
55
85
65
75
95 105 115 125
55
85
65
75
95 105 115 125
55
85
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4611 F11
4611 F12
4611 F10
Figure 10. 5VIN to 1.2VOUꢁ with Heat Sink Figure 11. 3.3VIN to 1.2VOUꢁ No Heat Sink Figure 12. 3.3VIN to 1.2VOUꢁ with Heat Sink
16
16
16
14
12
14
12
14
12
10
8
10
8
10
8
6
6
6
4
4
4
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
2
2
2
0
0
0
65
75
95 105 115 125
65
75
95 105 115 125
55
85
55
85
65
75
95 105 115 125
55
85
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4611 F13
4611 F14
4611 F15
Figure 13. 3.3VIN to 2.5VOUꢁ No Heat Sink Figure 14. 3.3VIN to 2.5VOUꢁ with Heat Sink Figure 15. 5VIN to 3.3VOUꢁ No Heat Sink
4611f
ꢀꢈ
LTM4611
applicaTions inForMaTion
16
ambient temperature change is factored into the derating
curves. The junctions are maintained at 115°C maximum
while lowering output current or power while increasing
ambient temperature. The decreased output current will
decreasetheinternalmodulelossasambienttemperature
isincreased.Themonitoredjunctiontemperatureof115°C
minus the ambient operating temperature specifies how
much module temperature rise can be allowed. As an
example in Figure 11, the load current is derated to ~12A
at ~75°C with no air or heat sink and the power loss for
the 3.3V to 1.2V at 12A output is a 2.82W loss. The 2.82W
loss is calculated with the ~2.4W room temperature loss
from the 3.3V to 1.2V power loss curve at 12A (Figure 7),
and the 1.175 multiplying factor at 75°C ambient. If the
14
12
10
8
6
4
400LFM
200LFM
0LFM
2
0
65
75
95 105 115 125
55
85
AMBIENT TEMPERATURE (°C)
4611 F16
Figure 16. 5VIN to 3.3VOUꢁ with Heat Sink
ꢁable 2. 1.2V Output
DERAꢁING
POWER LOSS
CURVE
AIR FLOW
CURVE
V
(LFM)
HEAꢁ SINK
None
θ
(°C/W)
14
IN
JA
JA
JA
Figures 9, 11
Figures 9, 11
Figures 9, 11
Figures 10, 12
Figures 10, 12
Figures 10, 12
5V, 3.3V
5V, 3.3V
5V, 3.3V
5V, 3.3V
5V, 3.3V
5V, 3.3V
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
0
200
400
0
None
11.5
10.6
11.5
8.4
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
200
400
7.5
ꢁable 3. 2.5V Output
DERAꢁING
CURVE
POWER LOSS
CURVE
AIR FLOW
(LFM)
V
HEAꢁ SINK
None
θ
(°C/W)
15.5
12.7
12.1
IN
Figures 13
Figures 13
Figures 13
Figures 14
Figures 14
Figures 14
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
0
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
12.6
10.6
8.9
200
400
ꢁable 4. 3.3V Output
DERAꢁING
CURVE
POWER LOSS
CURVE
AIR FLOW
(LFM)
V
HEAꢁ SINK
None
θ
(°C/W)
14
IN
Figures 15
Figures 15
Figures 15
Figures 16
Figures 16
Figures 16
5V
5V
5V
5V
5V
5V
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
0
200
400
0
None
11.5
10.2
12
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
200
400
10.1
9.3
4611f
ꢁ0
LTM4611
applicaTions inForMaTion
75°C ambient temperature is subtracted from the 115°C
junction temperature, then the difference of 40°C divided
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature.Roomtemperaturepowerlosscanbederived
from the efficiency curves in the Typical Performance
Characteristics section and adjusted with the above ambi-
ent temperature multiplicative factors.
by2.82Wyieldsathermalresistance,θ ,of14.2°C/W—in
JA
good agreement with Table 2. Tables 2, 3 and 4 provide
equivalent thermal resistances for 1.2V, 2.5V and 3.3V
outputs with and without air flow and heat sinking. The
derived thermal resistances in Tables 2, 3 and 4 for the
ꢁable 5. Output Voltage Response Versus Component Matrix, 0A to 7.5A Load Step
ꢁYPICAL MEASURED VALUES
C
VENDORS
PARꢁ NUMBER
C
VENDORS
OUꢁ2
PARꢁ NUMBER
OUꢁ1
AVX
12106D107MAT2A (100µF, 6.3V, 1210 Case Size)
JMK325BJ107MM-T (100µF, 6.3V, 1210 Case Size)
C3225X5R0J107MT (100µF, 6.3V, 1210 Case Size)
1206D226MAT (22µF, 6.3V, 1206 Case Size)
JMK316BJ226ML-T (22µF, 6.3V, 1206 Case Size)
C3216X5R0J226MT (22µF, 6.3V, 1206 Case Size)
Sanyo POSCAP
Sanyo POSCAP
6TPF330M9L (330µF, 6.3V, 9mΩ ESR, D3L Case Size)
2R5TPE470M9 (470µF, 2.5V, 9mΩ ESR, D2E Case Size)
Taiyo Yuden
TDK
AVX
Taiyo Yuden
TDK
ꢁRANSIENꢁ
DROOP,
0A ꢁO 7.5A PEAK-ꢁO-PEAK,
LOAD
SꢁEP
SLEW
ꢁRANSIENꢁ
USING
V
V
C
*
C
*
C
C
DIFF
LOAD SꢁEP 0A ꢁO 7.5A ꢁO 0A RECOVERY RAꢁE
R
SEꢁ
OUꢁ IN
IN
IN
OUꢁ2
OUꢁ1
(V) (V) (CERAMIC) (BULK) (CERAMIC) (BULK)
C
C
AMP FIGURE
(mV)
65
63
65
60
64
54
65
50
55
47
61
70
62
68
60
66
61
63
52
57
53
62
82
70
75
64
72
58
65
(mV ꢁIME (µs) (A/µs) (kΩ)
)
P-P
FF
P
0.9 1.5
0.9 1.5
0.9 1.8
0.9 1.8
0.9 1.8
0.9 2.5
0.9 2.5
0.9 3.3
0.9 3.3
470µF
470µF
220µF
220µF
220µF
150µF
150µF
150µF
150µF
150µF
150µF
680µF
680µF
330µF
330µF
330µF
150µF
150µF
150µF
150µF
150µF
150µF
1000µF
1000µF
470µF
470µF
470µF
220µF
220µF
None 220pF None
470µF 22pF None
None 220pF None
470µF 47pF None
330µF 22pF None
None 33pF 10pF
330µF None 22pF
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
118
15
25
20
25
30
20
20
25
20
20
20
20
25
20
30
30
25
25
30
20
25
25
20
30
25
30
30
30
25
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
481
481
481
481
481
481
481
481
481
481
481
243
243
243
243
243
243
243
243
243
243
243
121
121
121
121
121
121
121
4611f
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
5 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
5 × 100µF
7 × 22µF
4 × 100µF
7 × 22µF
4 × 100µF
6 × 22µF
5 × 100µF
3 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
4 × 100µF
7 × 22µF
4 × 100µF
7 × 22µF
4 × 100µF
6 × 22µF
6 × 100µF
2 × 22µF
4 × 100µF
3 × 22µF
4 × 22µF
4 × 100µF
5 × 22µF
122
119
113
119
108
123
104
109
102
116
128
121
123
115
123
115
115
106
111
108
119
145
133
136
126
137
114
122
None
330µF
None
47pF None
10pF 10pF
47pF None
10pF 10pF
0.9
0.9
1
1
1
1
1
1
1
5
5
330µF
1.5
1.5
1.8
1.8
1.8
2.5
2.5
3.3
3.3
5
None 220pF None
470µF 33pF None
None 220pF None
470µF 33pF None
330µF 22pF None
None
330µF
None
330µF
None
47pF None
10pF 10pF
47pF None
10pF 10pF
47pF None
10pF 10pF
1
1
1
1
5
330µF
1.2 1.5
1.2 1.5
1.2 1.8
1.2 1.8
1.2 1.8
1.2 2.5
1.2 2.5
None 220pF None
470µF 47pF None
None 220pF None
470µF 22pF None
330µF 22pF None
None 100pF None
330µF
10pF 10pF
ꢁꢀ
LTM4611
applicaTions inForMaTion
ꢁRANSIENꢁ
DROOP,
LOAD
SꢁEP
SLEW
ꢁRANSIENꢁ
USING
0A ꢁO 7.5A PEAK-ꢁO-PEAK,
V
V
C
*
C
*
C
C
DIFF
LOAD SꢁEP 0A ꢁO 7.5A ꢁO 0A RECOVERY RAꢁE R
SEꢁ
OUꢁ IN
IN
IN
OUꢁ2
OUꢁ1
(V) (V) (CERAMIC) (BULK) (CERAMIC) (BULK)
C
C
AMP FIGURE
(mV)
60
63
47
(mV )
ꢁIME (µs) (A/µs) (kΩ)
FF
P
P-P
1.2 3.3
1.2 3.3
150µF 4 x 100µF
None
330µF
None
330µF
None 220pF None
470µF 47pF None
None 220pF None
330µF 22pF 10pF
None
330µF 22pF None
None 33pF 10pF
330µF None 10pF
None 220pF None
330µF 22pF None
None
330µF 22pF None
None 33pF 10pF
33pF 10pF
10pF 10pF
47pF None
10pF 10pF
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
20
20
116
30
20
30
25
25
40
40
30
30
30
30
30
45
35
40
30
40
30
45
40
50
45
50
40
40
50
60
45
30
40
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5 28.4
7.5 28.4
7.5 28.4
7.5 28.4
7.5 28.4
7.5 28.4
7.5
7.5
7.5
7.5
7.5
7.5
121
121
121
121
69
69
69
69
69
69
69
69
48.1
48.1
48.1
48.1
48.1
48.1
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
2 × 47µF
150µF
150µF
150µF
1000µF
1000µF
220µF
220µF
150µF
150µF
150µF
150µF
330µF
330µF
150µF
150µF
150µF
150µF
330µF
330µF
330µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
680µF
680µF
117
105
123
147
135
122
133
123
124
122
131
137
145
118
137
127
133
143
123
128
134
115
160
274
143
119
193
511
431
7 × 22µF
4 × 100µF
6 × 22µF
6 × 100µF
2 × 22µF
4 × 100µF
5 × 22µF
4 × 100µF
4 × 22µF
4 × 100µF
6 × 22µF
4 × 100µF
5 × 22µF
4 × 100µF
4 × 22µF
4 × 100µF
6 × 22µF
3 × 100µF
4 × 100µF
3 × 22µF
3 × 100µF
4 × 100µF
5 × 22µF
2 × 100µF
3 × 100µF
4 × 100µF
5 × 22µF
1 × 100µF
7 × 22µF
1.2
1.2
5
5
64
83
71
64
68
66
67
59
67
73
76
57
69
64
69
71
66
67
60
54
81
137
67
56
95
264
218
1.5 1.8
1.5 1.8
1.5 2.5
1.5 2.5
1.5 3.3
1.5 3.3
33pF 10pF
1.5
1.5
5
5
1.8 2.5
1.8 2.5
1.8 3.3
1.8 3.3
47pF 10pF
1.8
1.8
5
5
330µF None 10pF
None 100pF None
None 100pF None
2.5 3.3
2.5 3.3
2.5 3.3
330µF
47pF None
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
5
5
5
5
5
5
5
5.5
5.5
None 100pF None
None 100pF None
330µF 22pF None
None
None
None 100pF None
330µF 22pF None
None
None
22pF None
47pF None
19.3
19.3
19.3
19.3
11.5
11.5
10pF None
None None
5
HEAꢁ SINK MANUFACꢁURER
Wakefield Engineering
AAVID Thermalloy
PARꢁ NUMBER
WEBSIꢁE
LTN20069
www.wakefield.com
375424B00034G
www.aavidthermalloy.com
ꢁHERMALLY CONDUCꢁIVE ADHESIVE
ꢁAPE MANUFACꢁURER
PARꢁ NUMBER
WEBSIꢁE
Chromerics
T411
www.chromerics.com
*Thequantityandqualityofbulkinputbypasscapacitance
needed, particularly for low dropout scenarios (V – V
< 600mV) is mainly dependent on the output impedance
and dynamic response of the power source feeding the
LTM4611(s). Consider, in the extreme: for a heavy load
step, the full transient on LTM4611’s output is directly
referred to its input, and the LTM4611 can only deliver
to its output whatever the source supply and local input
caps can provide. Sluggish source supplies will call for
more bulk capacitance placed locally to the LTM4611’s
input, to assist the source supply in riding through severe
IN
OUT
transient load steps.
4611f
ꢁꢁ
LTM4611
applicaTions inForMaTion
Safety Considerations
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
The LTM4611 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support overvoltage
protection and overcurrent protection.
• Do not put vias directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
Layout Checklist/Example
• For parallel modules, tie the respective COMP, V ,
FB
The high integration of LTM4611 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
V
, TRACK/SS and RUN pins together. Use an
OUT_LCL
internal layer to closely connect these pins together.
Figure 17 gives a good example of the recommended
layout. Figures 18 and 19 show schematics of the
LTM4611 devices operating in parallel.
• Use large PCB copper areas for high current paths,
including V , GND and V . It helps to minimize the
IN
OUT
• To facilitate stuffing verification, test and debug activi-
ties, consider routing control signals of the LTM4611
with short traces to localized test points, test pads or
test vias–as PCB layout space permits. Both in-house
and contract manufacturers enjoy gaining electrical
access to all non low impedance (>10Ω) pins of an
IC or µModule device to improve in-circuit test (ICT)
coverage.
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
tors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
V
IN
CONTROL
C
C
IN
IN
GND
SIGNAL
GROUND
C
C
OUT
OUT
V
V
OUT
OUT
4611 F17
Figure 17. Recommended PCB Layouts
4611f
ꢁꢂ
LTM4611
Typical applicaTions
V
IN
INTV
CC
V
1.2V
60A
OUT
1.5V TO 5.5V
C
22µF
10V
C
22µF
10V
IN1
IN2
V
INTV
PGOOD
IN
CC
CC
CC
CC
C
SS
0.1µF
R1
10k
COMP
V
OUT
V
OUT_LCL
+
C
*
C
*
OUT2
OUT1
TRACK/SS
RUN
470µF
6.3V
100µF
6.3V
DIFFV
OUT
+
LTM4611
PLLFLTR/f
V
V
SET
OSNS
C
C
*
FF1
–
MODE_PLLIN
OSNS
V
FB
SGND
GND
R
FB
*
P1
30.1k
R2
100k
4-PHASE CLOCK
INTV
CC
+
SET
LTC6902
V
C1
1µF
MOD
DIV
C
22µF
10V
C
22µF
10V
IN3
IN4
GND
PH
V
IN
INTV
PGOOD
OUT4
OUT3
OUT1
OUT2
COMP
V
OUT
V
OUT_LCL
+
+
+
C
*
*
*
C
*
OUT3
470µF
6.3V
OUT4
100µF
6.3V
TRACK/SS
RUN
C
*
FF2
DIFFV
OUT
+
LTM4611
PLLFLTR/f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
INTV
CC
V
FB
SGND
GND
C
*
P2
C
22µF
10V
C
22µF
10V
IN5
IN6
V
IN
INTV
LTM4611
GND
PGOOD
COMP
V
OUT
V
OUT_LCL
C
C
*
OUT5
470µF
6.3V
OUT6
100µF
6.3V
TRACK/SS
RUN
C
C
*
FF3
DIFFV
OUT
+
PLLFLTR/f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
INTV
CC
V
FB
SGND
*
P3
C
22µF
10V
C
22µF
10V
IN7
IN8
V
IN
INTV
PGOOD
COMP
V
OUT
V
OUT_LCL
C
C
*
OUT8
100µF
6.3V
OUT7
470µF
6.3V
TRACK/SS
RUN
C
*
FF4
DIFFV
OUT
+
LTM4611
PLLFLTR/f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
INTV
CC
V
FB
SGND
GND
C
*
P4
4611 F18
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH
CONNECTIONS AMONGST ALL PARALLELED LTM4611s
V
FB
Figure 18. 1.2V, 60A, Current Sharing with 4-Phase Operation
4611f
ꢁꢃ
LTM4611
Typical applicaTions
V
IN
INTV
CC
1.5V TO 5.5V
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN1
IN2
IN3
V
INTV
PGOOD
IN
CC
V
C
SS
OUT
1V
0.1µF
COMP
V
OUT
V
OUT_LCL
30A
+
R1
10k
C
*
C
*
OUT1
OUT2
TRACK/SS
RUN
470µF
6.3V
100µF
6.3V
LTM4611
DIFFV
OUT
+
INTV
CC
PLLFLTR/f
V
V
SET
OSNS
C
C
*
FF1
CLOCK SYNC 0 PHASE
–
+
MODE_PLLIN
OUT1
V
OSNS
C1
1µF
R2
LTC6908-1
V
FB
OUT2
MOD
GND
SET
SGND
GND
R
FB
121k
*
P1
200k
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN4
IN5
IN6
V
IN
INTV
PGOOD
CC
COMP
V
OUT
V
OUT_LCL
+
C
*
C
*
OUT3
OUT4
TRACK/SS
RUN
C
*
FF2
470µF
6.3V
100µF
6.3V
LTM4611
DIFFV
OUT
+
PLLFLTR/f
V
V
SET
OSNS
CLOCK SYNC 180 PHASE
–
INTV
*
MODE_PLLIN
CC
OSNS
V
FB
SGND
GND
C
P2
4611 F19
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH
CONNECTIONS AMONGST ALL PARALLELED LTM4611s
V
FB
Figure 19. 1V at 30A LꢁM4611 ꢁwo Parallel Outputs with 2-Phase Operation
5V
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN1
IN2
IN3
V
INTV
PGOOD
IN
CC
C
SS
0.1µF
3.3V
15A
COMP
V
OUT
V
OUT_LCL
R1
10k
+
C
*
C
47µF
6.3V
*
OUT1
OUT2
TRACK/SS
RUN
C *
FF
220µF
6.3V
DIFFV
OUT
+
LTM4611
PLLFLTR/f
V
V
SET
OSNS
–
INTV
CC
MODE_PLLIN
CONTINUOUS
MODE
OSNS
V
FB
SGND
GND
R
FB
19.1k
C *
P
*SEE TABLE 5
4611 F20
Figure 20. 3.3V at 15A Design, Example of Not Using Differential Remote Sense
4611f
ꢁꢄ
LTM4611
package phoTograph
package DescripTion
Pin Assignment ꢁable
(Arranged by Pin Number)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
E1 GND
PIN NAME
F1 GND
A1
A2
A3
A4
A5
A6
V
V
V
V
V
V
B1
B2
B3
B4
B5
B6
V
V
V
V
V
V
C1
C2
C3
C4
C5
C6
V
V
V
V
V
V
D1 GND
D2 GND
D3 GND
D4 GND
D5 GND
D6 GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
E2 GND
E3 GND
E4 GND
E5 GND
E6 GND
E7 GND
F2 GND
F3 GND
F4 GND
F5 GND
F6 GND
F7 GND
F8 GND
F9 GND
A7 INTV
B7 GND
A8 MODE_PLLIN B8
C7 GND
C8
D7
-
CC
-
-
D8 GND
D9 INTV
E8
-
A9 TRACK/SS
A10 RUN
B9 GND
B10
C9 GND
C10 MTP3
C11 MTP4
C12 MTP5
E9 GND
CC
-
D10 MTP6
D11 MTP7
D12 MTP8
E10
E11
-
-
F10
F11 PGOOD
F12
-
A11 COMP
A12 MTP1
B11 MTP2
B12 PLLFLTR/f
E12 MTP9
V
FB
SET
PIN NAME
G1 GND
G2 GND
G3 GND
G4 GND
G5 GND
G6 GND
G7 GND
G8 GND
G9 GND
PIN NAME
H1 GND
H2 GND
H3 GND
H4 GND
H5 GND
H6 GND
H7 GND
H8 GND
H9 GND
PIN NAME
PIN NAME
PIN NAME
PIN NAME
J1
V
V
V
V
V
V
V
V
V
V
-
K1
V
V
V
V
V
V
V
V
V
V
V
L1
V
V
V
V
V
V
V
V
V
V
V
V
M1
M2
M3
M4
M5
M6
M7
M8
M9
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT_LCL
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OSNS
J2
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L2
L3
L4
J3
J4
J5
L5
L6
L7
J6
J7
J8
L8
L9
L10
L11
L12
J9
G10
-
H10
-
J10
J11
J12
M10 V
M11 V
M12 V
G11 SGND
H11 SGND
H12 SGND
+
–
G12 PGOOD
V
K12 DIFFV
OUT
OSNS
4611f
ꢁꢅ
LTM4611
package DescripTion
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4611f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
ꢁꢆ
LTM4611
Typical applicaTion
V
IN
INTV
CC
1.5V TO 5.5V*
C
22µF
10V
C
22µF
10V
C
22µF
10V
IN1
IN2
IN3
PGOOD
CC
V
INTV
IN
C
V
SS
OUT
0.1µF
1V
COMP
V
OUT
V
OUT_LCL
C
*
15A
OUT2
R1
10k
+
C
*
OUT1
TRACK/SS
RUN
22µF
6.3V
s2
C
*
FF
220µF
6.3V
LTM4611
DIFFV
OUT
+
PLLFLTR/f
V
V
SET
OSNS
CONTINUOUS MODE
–
MODE_PLLIN
OSNS
V
FB
SGND
GND
R
FB
C *
P
240k
4611 F21
*SEE TABLE 5
Figure 21. 1.5V to 5.5VIN, 1V at 15A Design
relaTeD parTs
PARꢁ NUMBER
DESCRIPꢁION
COMMENꢁS
LTM4600
10A DC/DC µModule
Basic 10A DC/DC µModule
LTM4601A
12A DC/DC µModule with PLL, Output Tracking/
Margining and Remote Sensing
Synchronizable, PolyPhase Operation to 48A, Pin Compatible with the
LTM4611 and LTM4617
LTM4602
LTM4603
6A DC/DC µModule
Pin Compatible with the LTM4600
6A DC/DC µModule with PLL and Output Tracking/
Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4603-1 Version has no
Remote Sensing, Pin Compatible with the LTM4601
LTM4604A
4A Low Voltage DC/DC µModule
2.375V ≤ V ≤ 5.5V; 0.8V ≤ V
≤ 5V,
OUT
IN
9mm × 15mm × 2.3mm (Ultrathin) LGA Package
LTM4605
LTM4606
LTM4607
LTM4608A
LTM4609
LTM4612
LTM8023
LTM8032
Buck-Boost DC/DC µModule Family
Ultralow Noise 6A DC/DC µModule
Buck-Boost DC/DC µModule Family
8A Low Voltage DC/DC µModule
Buck-Boost DC/DC µModule Family
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
OUT
IN
4.5V ≤ V ≤ 28V, 0.6V ≤ V
≤ 5V, 15mm × 15mm × 2.8mm Package
OUT
IN
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
OUT
IN
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V; 9mm × 15mm × 2.8mm LGA Package
OUT
IN
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
OUT
IN
Ultralow Noise High V
DC/DC µModule
5A, 5V ≤ V ≤ 36V, 3.3V ≤ V
≤ 15V, 15mm × 15mm × 2.8mm Package
OUT
OUT
IN
36V, 2A DC/DC µModule
Ultralow Noise 36V, 2A DC/DC µModule
3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, 9mm × 11.25mm × 2.8mm Package
OUT
IN
EN55022 Class B Compliant; 0.8V ≤ V
9mm × 15mm × 2.8mm
≤ 10V; 3.6V ≤ V ≤ 36V;
IN
OUT
4611f
LT 0510 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢁꢇ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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