LTM4612V [Linear]
Ultralow Noise 36VIN, 15VOUT, 5A, DC/DC μModule; 超低噪声36VIN ， 15VOUT ， 5A ， DC / DC微型模块
| 型号： | LTM4612V |
| 厂家： | 
Linear |
| 描述： | Ultralow Noise 36VIN, 15VOUT, 5A, DC/DC μModule |
| 文件： | 总24页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4612
Ultralow Noise
36V , 15V , 5A,
IN
OUT
Module
DC/DC
µ
FEATURES
DESCRIPTION
The LTM®4612 is a complete, ultralow noise, high voltage
inputandoutput,5AswitchingmodeDC/DCpowersupply.
Includedinthepackagearetheswitchingcontroller,power
FETs, inductor and all support components. Operating
over an input voltage range of 5V to 36V, the LTM4612
supports an output voltage range of 3.3V to 15V, set by a
single resistor. Only bulk input and output capacitors are
needed to finish the design.
n
Complete Low EMI Switch Mode Power Supply
n
CISPR 22 Class B Compliant
n
Wide Input Voltage Range: 5V to 36V
n
5A DC, 7A Peak Output Current
n
3.3V to 15V Output Voltage Range
n
Low Input and Output Referred Noise
n
Output Voltage Tracking and Margining
n
PLL Frequency Synchronization
n
1.5% Set Point Accuracy
High switching frequency and an adaptive on-time current
mode architecture enables a very fast transient response
to line and load changes without sacrificing stability.
n
Power Good Tracks with Margining
n
Current Foldback Protection (Disabled at Start-Up)
n
Parallel/Current Sharing
n
The onboard input filter and noise cancellation circuits
achieve low noise coupling, thus effectively reducing the
electromagnetic interference (EMI)—see Figures 4 and 8.
Furthermore, the DC/DC μModuleTM can be synchronized
with an external clock for reducing undesirable frequency
harmonics and allows PolyPhase® operation for high load
currents.
Ultrafast Transient Response
n
Current Mode Control
n
Programmable Soft-Start
n
Output Overvoltage Protection
n
–55°C to 125°C Operating Temperature Range
(LTM4612MPV)
n
Small Surface Mount Footprint, Low Profile
(15mm × 15mm × 2.8mm) LGA Package
The LTM4612 is offered in a space saving and thermally
enhanced 15mm × 15mm × 2.8mm LGA package, which
enables utilization of unused space on the bottom of PC
boards for high density point-of-load regulation. The
LTM4612 is Pb-free and RoHS compliant.
APPLICATIONS
n
Telecom and Networking Equipment
n
Industrial and Avionic Equipment
n
RF Systems
, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology
Corporation. μModule is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Efficiency vs Load Current at 12V Output
12V/5A Ultralow Noise μModule with 22V to 36V Input
100
95
CLOCK SYNC
V
IN
22V
90
TO 36V
2M
100k
V
PLLIN
V
12V
5A
IN
85
80
75
70
65
60
55
50
OUT
V
OUT
PGOOD
RUN
LTM4612
100pF
5.23k
C
OUT
COMP
V
FB
INTV
DRV
CC
CC
C
IN
FCB
f
SET
MARG0
MARG1
MPGM
MARGIN
CONTROL
TRACK/SS
V
D
24V 12V
IN
OUT
OUT
OUT
0.01μF
28V 12V
IN
10μF
392k
5% MARGIN
36V 12V
IN
SGND PGND
0
1
2
3
4
5
4612 TA01
OUTPUT CURRENT (A)
4612 TA01b
4612f
1
LTM4612
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
INTV DRV .............................................–0.3V to 6V
CC,
CC
V
...........................................................–0.3V to 16V
OUT
PLLIN, FCB, TRACK/SS, MPGM, MARG0,
MARG1, PGOOD, f ...........–0.3V to INTV + 0.3V
A
B
C
D
E
V
IN
SET
CC
f
SET
MARG0
MARG1
V
BANK 1
D
RUN .............................................................–0.3V to 5V
SGND
V , COMP................................................–0.3V to 2.7V
FB
DRV
CC
PGND
BANK 2
V , V .......................................................–0.3V to 36V
F
V
IN
D
FB
G
H
J
K
L
PGOOD
SGND
NC
NC
NC
Internal Operating Temperature Range (Note 2)
E and I Grades ...................................–40°C to 125°C
MP Grade...........................................–55°C to 125°C
Junction Temperature ........................................... 125°C
Storage Temperature Range...................–55°C to 125°C
V
OUT
BANK 3
FCB
M
1
2 3 4 5 6 7 8 9 10 11 12
LGA PACKAGE
133-LEAD (15mm × 15mm × 2.8mm)
T
= 125°C, θ = 15°C/W, θ = 6°C/W
JA JC
JMAX
θ
JA
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
WEIGHT = 1.7g
ORDER INFORMATION
LEAD FREE FINISH
LTM4612EV#PBF
LTM4612IV#PBF
LTM4612MPV#PBF
TRAY
PART MARKING*
LTM4612V
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTM4612EV#PBF
LTM4612IV#PBF
LTM4612MPV#PBF
133-Lead (15mm × 15mm × 2.8mm) LGA
133-Lead (15mm × 15mm × 2.8mm) LGA
133-Lead (15mm × 15mm × 2.8mm) LGA
LTM4612V
–40°C to 125°C
LTM4612MPV
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted. Per Typical Application
(front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Input DC Voltage
Output Voltage
5
36
V
IN(DC)
V
C
IN
= 10μF × 3, C
= 300μF; FCB = 0
OUT
OUT(DC)
l
l
11.89
11.89
12.07
12.07
12.25
12.25
V
V
V
V
= 24V, V
= 12V, I
= 0A
IN
OUT
OUT
= 36V, V =12V, I
= 0A
IN
OUT
OUT
Input Specifications
V
I
Undervoltage Lockout Threshold
Input Inrush Current at Start-Up
I
I
= 0A
3.2
4.8
V
IN(UVLO)
OUT
= 0A; C = 10μF × 2, C
= 200μF;
INRUSH(VIN)
OUT
IN
OUT
V
= 12V
OUT
0.6
0.7
A
A
V
V
= 24V
= 36V
IN
IN
4612f
2
LTM4612
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted. Per Typical Application
(front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input Supply Bias Current
V
V
V
V
= 36V, No Switching
4.5
57
mA
mA
mA
mA
μA
Q(VIN)
IN
IN
IN
IN
= 36V, V
= 12V, Switching Continuous
OUT
= 24V, No Switching
= 24V, V = 12V, Switching Continuous
3.5
48
OUT
Shutdown, RUN = 0, V = 36V
50
IN
I
Input Supply Current
V
IN
V
IN
= 36V, V
= 24V, V
= 12V, I
= 12V, I
= 5A
= 5A
1.85
2.72
A
A
S(VIN)
OUT
OUT
OUT
OUT
V
Internal V Voltage
V
= 36V, RUN > 2V, I = 0A
OUT
4.7
0
5
5.3
V
INTVCC
CC
IN
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 24V, V
= 12V (Note 4)
OUT
5
A
OUT(DC)
IN
= 12V, FCB = 0V, V = 22V to 36V,
ΔV
OUT
OUT
IN
OUT(LINE)
l
I
= 0A
0.05
0.3
%
V
OUT
Load Regulation Accuracy
Input Ripple Voltage
V
= 12V, FCB = 0V, I
IN
IN
= 0A to 5A (Note 4)
OUT
ΔV
OUT
V
V
OUT(LOAD)
l
l
= 36V
= 24V
0.3
0.3
0.6
0.6
%
%
V
OUT
V
V
I
= 0A,
IN(AC)
OUT
IN
C
= 2 × 10μF X5R Ceramic and 1 × 100μF
Electrolytic, 1 × 10μF X5R Ceramic on V Pins
D
V
V
= 24V, V
= 24V, V
= 5V
= 12V
7.2
3.4
mV
mV
IN
IN
OUT
OUT
P-P
P-P
Output Ripple Voltage
I
= 0A,
OUT(AC)
OUT
OUT
C
= 2 × 22μF, 2 × 47μF X5R Ceramic
V
V
= 24V, V
= 24V, V
= 5V
= 12V
17.5
12.5
mV
mV
IN
IN
OUT
OUT
P-P
P-P
f
S
Output Ripple Voltage Frequency
I
= 1A, V = 24V, V = 12V
OUT
940
kHz
OUT
IN
Turn-On Overshoot,
TRACK/SS = 10nF
C
= 200μF, V
IN
IN
= 12V, I
= 0A
ΔV
OUT
V
V
OUT
OUT
OUT(START)
= 36V
= 24V
20
20
mV
mV
t
Turn-On Time, TRACK/SS = Open
C
= 300μF, V
OUT
= 12V, I
= 1A
START
OUT
OUT
Resistive Load
V
V
= 36V
= 24V
0.5
0.5
ms
ms
IN
IN
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
= 2 × 22μF Ceramic, 150μF Bulk
ΔV
OUT(LS)
C
OUT
V
153
37
mV
μs
= 24V, V
= 12V
OUT
IN
t
I
Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V = 24V
IN
SETTLE
Output Current Limit
C
= 200μF
IN
IN
OUT(PK)
OUT
V
V
= 36V, V
= 24V, V
= 12V
= 12V
9
9
A
A
OUT
OUT
Control Section
l
V
V
Voltage at V Pin
I
= 0A, V = 12V
OUT
0.594
1
0.6
1.5
–1.5
0.6
–1
0.606
1.9
V
V
FB
FB
OUT
RUN Pin On/Off Threshold
Soft-Start Charging Current
Forced Continuous Threshold
Forced Continuous Pin Current
Minimum On-Time
RUN
I
V
V
= 0V
–1
–2
μA
V
SS/TRACK
SS/TRACK
V
0.57
0.63
–2
FCB
I
t
t
= 0V
FCB
μA
ns
ns
FCB
(Note 3)
(Note 3)
50
100
400
ON(MIN)
OFF(MIN)
Minimum Off-Time
250
4612f
3
LTM4612
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the –40°C to 85°C
operating temperature range, otherwise specifications are at TA = 25°C, VIN = 24V, unless otherwise noted. Per Typical Application
(front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
50
MAX
UNITS
kΩ
mA
kΩ
V
R
PLLIN
PLLIN Input Resistor
I
Current into DRV Pin
V
OUT
= 12V, I = 1A
OUT
22
30
DRVCC
CC
R
FBHI
Resistor Between V
and V Pins
99.5
100
1.18
1.4
100.5
OUT
FB
V
V
Margin Reference Voltage
MPGM
, V
MARG0, MARG1 Voltage Thresholds
V
MARG0 MARG1
PGOOD
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
Falling
7
10
–10
1.5
13
%
%
%
V
ΔV
FB
FBH
–7
–13
ΔV
FB
FBL
Returning
ΔV
FB
FB(HYS)
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4612E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4612I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. The LTM4612MP
is guaranteed and tested over the full –55°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: 100% tested at die level only.
Note 4: See the Output Current Derating curves for different V , V
IN OUT
and T .
A
4612f
4
LTM4612
TYPICAL PERFORMANCE CHARACTERISTICS (Refer to Figure 18)
Efficiency vs Load Current with
3.3VOUT (FCB = 0)
Efficiency vs Load Current with
5VOUT (FCB = 0)
Efficiency vs Load Current with
12VOUT (FCB = 0)
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5V 3.3V
20V 12V
IN
IN
OUT
OUT
OUT
OUT
OUT
12V 3.3V
12V 5V
24V 12V
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
24V 3.3V
24V 5V
28V 12V
IN
IN
IN
36V 3.3V
IN
36V 5V
IN
36V 12V
IN
0
1
2
3
4
5
0
1
2
3
5
0
1
2
3
4
5
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4612 G02
4612 G03
4612 G01
Efficiency vs Load Current with
15VOUT (FCB = 0, Refer to Figure 20)
Transient Response from 12VIN
to 3.3VOUT
Transient Response from 12VIN
to 5VOUT
100
95
90
85
80
75
70
65
60
2A/DIV
2A/DIV
100mV/DIV
100mV/DIV
28V 15V
IN
OUT
OUT
OUT
32V 15V
IN
36V 15V
IN
50μs/DIV
LOAD STEP: 0A to 3A
4612 G05
0
1
2
3
4
5
50μs/DIV
4612 G06
LOAD CURRENT (A)
LOAD STEP: 0A to 3A
4612 G04
C
= 2 s 22μF CERAMIC CAPACITORS AND
C
= 2 s 22μF CERAMIC CAPACITORS AND
OUT
OUT
2 s 47μF CERAMIC CAPACITORS
2 s 47μF CERAMIC CAPACITORS
Transient Response from 24VIN
to 12VOUT
Start-Up with 24VIN to 12VOUT
at IOUT = 0A
Start-Up with 24VIN to 12VOUT at
IOUT = 5A
I
IN
2A/DIV
0.2A/DIV
I
IN
1A/DIV
200mV/
DIV
V
OUT
V
OUT
5V/DIV
5V/DIV
50μs/DIV
4612 G07
500μs/DIV
4612 G08
500μs/DIV
4612 G09
LOAD STEP: 0A to 3A
SOFT-START CAPACITOR: 3.9nF
SOFT-START CAPACITOR: 3.9nF
C
= 2 s 22μF CERAMIC CAPACITORS AND
C
= 3 s 10μF CERAMIC CAPACITORS AND
C
= 3 s 10μF CERAMIC CAPACITORS AND
OUT
IN
IN
2 s 47μF CERAMIC CAPACITORS
1 s 47μF OSCON CAPACITOR
1 s 47μF OSCON CAPACITOR
4612f
5
LTM4612
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 24VIN to 12VOUT at
Short-Circuit with 24VIN to 12VOUT
at IOUT = 0A
Short-Circuit with 24VIN to 12VOUT
at IOUT = 5A
I
OUT = 5A, TA = –55°C
I
IN
2A/DIV
I
IN
V
OUT
0.2A/DIV
5V/DIV
V
OUT
V
OUT
5V/DIV
5V/DIV
I
IN
1A/DIV
50μs/DIV
4612 G11
500μs/DIV
4612 G10
20μs/DIV
4612 G12
C
= 2 s 22μF CERAMIC CAPACITORS AND
SOFT-START CAPACITOR: 3.9nF
C
= 2 s 22μF CERAMIC CAPACITORS AND
OUT
OUT
2 s 47μF CERAMIC CAPACITORS
C
= 3 s 10μF CERAMIC CAPACITORS AND
2 s 47μF CERAMIC CAPACITORS
IN
1 s 47μF OSCON CAPACITOR
VIN to VOUT Step-Down Ratio
Input Ripple
Output Ripple
36
30
24
18
12
6
SEE FREQUENCY ADJUSTMENT SECTION
FOR OPERATIONS OUTSIDE THIS REGION
OPERATING REGION
WITH DEFAULT FREQUENCY
50mV/DIV
10mV/DIV
0
1μs/DIV
4612 G14
1μs/DIV
4612 G15
6
8
V
10
(V)
12
14 15
3.3
4
V
V
C
= 24V
V
V
C
= 24V
IN
OUT
OUT
OUT
IN
OUT
IN
4612 G13
= 12V AT 5A RESISTIVE LOAD
= 3 s 10μF 50V CERAMIC 1 s 100μF BULK
= 12V AT 5A RESISTIVE LOAD
= 2 s 22μF 16V CERAMIC AND
2 s 47μF 16V CERAMIC
4612f
6
LTM4612
PIN FUNCTIONS (See Package Description for Pin Assignments)
V (Bank 1): Power Input Pins. Apply input voltage be-
low load, to INTV to enable discontinuous mode opera-
tion at low load or to a resistive divider from a secondary
output when using a secondary winding.
IN
CC
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V pins
IN
and PGND pins.
TRACK/SS(PinA9):OutputVoltageTrackingandSoft-Start
Pin. When the module is configured as a master output,
then a soft-start capacitor is placed on this pin to ground
to control the master ramp rate. A soft-start capacitor can
be used for soft-start turn-on as a standalone regulator.
Slave operation is performed by putting a resistor divider
from the master output to the ground, and connecting the
center point of the divider to this pin. See the Applications
Information section.
PGND (Bank 2): Power Ground Pins for Both Input and
Output Returns.
V
(Bank 3): Power Output Pins. Apply output load
OUT
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these
pins and GND pins (see the LTM4612 Pin Configuration
below).
V (Pins B7, C7): Top FET Drain Pins. Add more capa-
D
MPGM (Pins A12, B11): Programmable Margining Input.
A resistor from these pins to ground sets a current that is
equal to 1.18V/R. This current multiplied by 10k will equal
a value in millivolts that is a percentage of the 0.6V refer-
ence voltage. See the Applications Information section.
To parallel LTM4612s, each requires an individual MPGM
resistor. Do not tie MPGM pins together.
citors between V and ground to handle the input RMS
D
current and reduce the input ripple further.
DRV (Pins C10, E11, E12): These pins normally con-
CC
nect to INTV for powering the internal MOSFET drivers.
CC
They can be biased up to 6V from an external supply with
about 50mA capability. This improves efficiency at the
higher input voltages by reducing power dissipation in
the module.
f
(Pin B12): Frequency Set Internally to 850kHz at 12V
SET
Output. An external resistor can be placed from this pin to
ground to increase frequency. This pin can be decoupled
with a 1000pF capacitor. See the Applications Information
section for frequency adjustment.
INTV (Pin A7): This pin is for additional decoupling of
CC
the 5V internal regulator.
PLLIN(PinA8):ExternalClockSynchronizationInputtothe
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor. Apply a clock above 2V and below
V
(Pin F12): The Negative Input of the Error Amplifier.
FB
Internally, this pin is connected to V
with a 100k preci-
OUT
INTV . See the Applications Information section.
CC
sionresistor.Differentoutputvoltagescanbeprogrammed
FCB(PinM12):ForcedContinuousInput.Connectthispin
to SGND to force continuous synchronization operation at
TOP VIEW
withanadditionalresistorbetweentheV andSGNDpins.
FB
See the Applications Information section.
MARG0 (Pin C12): LSB Logic Input for the Margining
Function. Together with the MARG1 pin, the MARG0 pin
will determine if a margin high, margin low, or no margin
state is applied. The pin has an internal pull-down resistor
of 50k. See the Applications Information section.
A
V
IN
f
B
C
D
E
SET
V
BANK 1
D
MARG0
MARG1
DRV
SGND
CC
PGND
BANK 2
F
V
MARG1(PinsC11, D12):MSBLogicInputfortheMargin-
ingFunction.TogetherwiththeMARG0pin,theMARG1pin
will determine if a margin high, margin low, or no margin
stateisapplied.Thepinshaveaninternalpull-downresistor
of 50k. See the Applications Information section.
FB
G
H
J
K
L
PGOOD
SGND
NC
NC
NC
V
OUT
BANK 3
FCB
M
1
2 3 4 5 6 7 8 9 10 11 12
SGND (Pins D9, H12): Signal Ground Pins. These pins
LGA PACKAGE
133-LEAD (15mm × 15mm × 2.8mm)
connect to PGND at output capacitor point.
LTM4612 Pin Configuration
4612f
7
LTM4612
PIN FUNCTIONS
COMP (Pins A11, D11): Current Control Threshold and
Error Amplifier Compensation Point. The current com-
parator threshold increases with this control voltage. The
voltage ranges from 0V to 2.4V with 0.7V corresponding
to zero sense voltage (zero current).
RUN (Pins A10, B9): Run Control Pins. A voltage above
1.9V will turn on the module, and below 1V will turn off
the module. A programmable UVLO function can be ac-
complished with a resistor from V to this pin that is has
IN
a 5.1V zener to ground. Maximum pin voltage is 5V.
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within 10% of the regulation point,
after a 25μs power bad mask timer expires.
NC (Pins J12, K12, L12): No Connect Pins.
BLOCK DIAGRAM
> 1.9V = ON
< 1V = OFF
MAX = 5V
V
OUT
RUN
PGOOD
COMP
INPUT
FILTER
V
IN
20V TO 36V
+
5.1V
ZENER
1μF
C
C
IN
100k
V
D
INTERNAL
COMP
D
POWER CONTROL
M1
M2
SGND
V
OUT
12V
MARG1
MARG0
AT 4A
NOISE
CANCEL-
LATION
V
FB
10μF
50k 50k
+
f
SET
R
FB
5.23k
C
OUT
93.1k
PGND
FCB
10k
MPGM
TRACK/SS
PLLIN
C
SS
50k
4.7μF
INTV
DRV
CC
CC
Figure 1. Simplified Block Diagram
DECOUPLING REQUIREMENTS Specifications are at TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
External Input Capacitor Requirement
I
= 4A
10
μF
IN
OUT
(V = 20V to 36V, V
= 12V)
IN
OUT
C
OUT
External Output Capacitor Requirement
(V = 20V to 36V, V = 12V)
I
= 4A
100
150
μF
OUT
IN
OUT
4612f
8
LTM4612
OPERATION
Power Module Description
Input filter and noise cancellation circuitry reduce the
noise coupling to I/O sides, and ensure the electromag-
netic interference (EMI) meets the limits of CISPR 22 and
CISPR 25.
The LTM4612 is a standalone nonisolated switching mode
DC/DC power supply. It can deliver 5A of DC output
current with some external input and output capacitors.
This module provides precisely regulated output voltage
Pulling the RUN pin below 1V forces the controller into its
shutdown state, turning off both M1 and M2. At low load
currents, discontinuous mode (DCM) operation can be
enabled to achieve higher efficiency compared to continu-
ous mode (CCM) by setting FCB pin higher than 0.6V.
programmable via one external resistor from 3.3V to
DC
15V over a 5V to 36V wide input voltage. The typical
DC
application schematic is shown in Figure 18.
The LTM4612 has an integrated constant on-time current
mode regulator, ultralow R
FETs with fast switch-
WhentheDRV pinisconnectedtoINTV , anintegrated
CC CC
DS(ON)
ing speed and integrated Schottky diodes. The typical
switching frequency is 850kHz at full load. With current
mode control and internal feedback loop compensation,
the LTM4612 module has sufficient stability margins and
good transient performance under a wide range of operat-
ing conditions and with a wide range of output capacitors,
even all ceramic output capacitors.
5V linear regulator powers the internal gate drivers. If a
5V external bias supply is applied on DRV pin, then an
CC
efficiencyimprovementwilloccurduetothereducedpower
loss in the internal linear regulator. This is especially true
at the higher input voltage range.
The MPGM, MARG0, and MARG1 pins are used to sup-
port voltage margining, where the percentage of margin
is programmed by the MPGM pin, and the MARG0 and
MARG1 selected margining. The PLLIN pin provides fre-
quency synchronization of the device to an external clock.
The TRACK/SS pin is used for power supply tracking and
soft-start programming.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limiting. Moreover, foldback current limiting is provided
in an overcurrent condition while V drops. Internal
overvoltage and undervoltage comparators pull the open-
drainPGOODoutputlowiftheoutputfeedbackvoltageexits
a 10%windowaroundtheregulationpoint.Furthermore,
in an overvoltage condition, internal top FET M1 is turned
off and bottom FET M2 is turned on and held on until the
overvoltage condition clears.
FB
4612f
9
LTM4612
APPLICATIONS INFORMATION
The typical LTM4612 application circuit is shown in
Figure 18. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for specific external capacitor
requirements for a particular application.
The output margining will be margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
MARG1
LOW
MARG0
LOW
MODE
NO MARGIN
MARGIN UP
MARGIN DOWN
NO MARGIN
LOW
HIGH
LOW
V to V
Stepdown Ratios
IN
OUT
HIGH
HIGH
There are restrictions in the maximum V and V
step
IN
OUT
HIGH
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Operating Frequency
Characteristic curve labeled “V to V
Step-Down
OUT
IN
The operating frequency of the LTM4612 is optimized to
achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
As shown in Figure 2, the frequency is linearly increased
with larger output voltages to keep the low output cur-
rent ripple. Figure 3 shows the inductor current ripple ΔI
with different output voltages. In most applications, no
additional frequency adjusting is required.
Ratio.” Note that additional thermal derating may be ap-
plied. See the Thermal Considerations and Output Current
Derating section in this data sheet.
Output Voltage Programming and Margining
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 100k internal feedback
resistorconnectstheV
andV pinstogether. Addinga
OUT
FB
1200
1000
800
resistor, R , from the V pin to the SGND pin programs
FB
FB
the output voltage.
100k +RFB
VOUT = 0.6V •
RFB
600
Table 1. RFB Standard 1% Resistor Values vs VOUT
V
(V)
3.3
5
6
8
10
12
14
15
OUT
400
22.1 13.7
11
8.06 6.34 5.23 4.42 4.12
R
(kΩ)
FB
200
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference
offset for margining. A 1.18V reference divided by the
10
14
16
2
4
6
8
12
V
(V)
OUT
4612 F02
Figure 2. Operating Frequency vs Output Voltage
R
resistor on the MPGM pin programs the current.
PGM
Calculate V
:
3.5
3.0
OUT(MARGIN)
%VOUT
100
VOUT(MARGIN)
=
• VOUT
V
= 36V
IN
2.5
2.0
1.5
1.0
0.5
Where %V
and V
is the percentage of V
OUT(MARGIN)
to be margined,
OUT
OUT
V
= 28V
IN
is the margin quantity in volts:
V
= 20V
IN
VOUT
1.18V
•10k
RPGM
=
•
0.6V VOUT(MARGIN)
6
8
10
(V)
12
14
16
2
4
Where R
is the resistor value to place on the MPGM
PGM
pin to ground.
V
OUT
4612 F03
Figure 3. Inductor Current Ripple vs Output Voltage
4612f
10
LTM4612
APPLICATIONS INFORMATION
If lower output ripple is required, the operating frequency
In this equation, η is the estimated efficiency of the
power module. Note the capacitor ripple current ratings
are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
f can be increased by adding a resistor R
pin and SGND, as shown in Figure 19.
between f
fSET
SET
VOUT
f =
1.5 • 10−10
R
(
|| 93.1k
fSET
)
For output voltages more than 12V, the frequency can be
higherthan1MHz,thusreducingtheefficiencysignificantly.
Additionally, the minimum off time 400ns normally limits
the operation when the input voltage is close to the output
voltage. Therefore, it is recommended to lower the fre-
In a typical 5A output application, one very low ESR, X5R
or X7R, 10μF ceramic capacitor is recommended for C1.
This decoupling capacitor should be placed directly adja-
cent to the module V pins in the PCB layout to minimize
D
quencyintheseconditionsbyconnectingaresistor(R
)
fSET
the trace inductance and high frequency AC noise. Each
10μF ceramic is typically good for 2A to 3A of RMS ripple
current. Refer to your ceramics capacitor catalog for the
RMS current ratings.
from the f pin to V , as shown in Figure 20.
SET
IN
VOUT
f =
⎛
⎞
3 •RfSET • 93.1k
5 • 10−11
⎜
⎟
Toattenuatethehighfrequencynoise,extrainputcapacitors
R
− 3 • 93.1k
⎝
⎠
fSET
should be connected to the V pads and placed before the
IN
high frequency inductor to form the π filter. One of these
low ESR ceramic input capacitors is recommended to be
close to the connection into the system board. A large
bulk 100μF capacitor is only needed if the input source
impedance is compromised by long inductive leads or
traces. Figure 4 shows the conducted EMI testing results
to meet the Level 5 of the CISPR 25 limit. For different
applications, input capacitance may be varied to meet
different conducted EMI limits.
Theloadcurrentcanaffectthefrequencyduetoitsconstant
on-time control. If constant frequency is a necessity, the
PLLIN pin can be used to synchronize the frequency of
the LTM4612 to an external clock, as shown in Figures
21 to 23.
Input Capacitors
LTM4612 is designed to achieve the low input conducted
EMInoiseduetothefastswitchingofturn-onandturn-off.
In the LTM4612, a high-frequency inductor is integrated
80
into the input line for noise attenuation. V and V pins
D
IN
70
are available for external input capacitors to form a high
CIS25QP
60
frequency π filter. As shown in Figure 18, the ceramic
50
40
30
20
10
0
capacitor C1 on the V pins is used to handle most of
D
the RMS current into the converter, so careful attention
is needed for capacitor C1 selection.
For a buck converter, the switching duty cycle can be
estimated as:
VOUT
0.15
1
10
30
D=
V
FREQUENCY (MHz)
4612 F04
IN
Figure 4. Conducted Emission Scan with 24VIN to
12VOUT at 5A (3 10μF Ceramic Capacitors on VIN
Pads and 1 10μF Ceramic Capacitor on VD Pads).
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
×
×
IOUT(MAX)
ICIN(RMS)
=
• D• 1–D
(
)
η
4612f
11
LTM4612
APPLICATIONS INFORMATION
Output Capacitors
ripple current to the inductor ripple current as functions
of duty cycle and the number of paralleled phases. Pick
the corresponding duty cycle and the number of phases
to get the correct output ripple current value. For example,
each phase’s inductor ripple current DIr at zero duty cycle
is ~4.3A for a 36V to 12V design. The duty cycle is about
0.33. The 2-phase curve has a ratio of ~0.33 for a duty
cycle of 0.33. This 0.33 ratio of output ripple current to
the inductor ripple current DIr at 4.3A equals 1.4A of the
The LTM4612 is designed for low output voltage ripple.
The bulk output capacitors defined as C
are chosen
OUT
with low enough effective series resistance (ESR) to meet
theoutputvoltagerippleandtransientrequirements. C
OUT
can be low ESR tantalum capacitor, low ESR polymer
capacitor or ceramic capacitor. The typical capacitance is
150μF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spikeisrequired.Table2showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 2A/μs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.
output ripple current (ΔI ).
L
The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
The equation is:
⎛
⎝
⎞
⎠
ΔIL
8 • f •N • C
ΔVOUT(P−P)
≈
+ ESR • ΔIL
⎜
⎟
Multiphase operation with multiple LTM4612 devices in
parallel will also lower the effective output ripple current
due to the phase interleaving operation. Refer to Figure 5
for the normalized output ripple current versus the duty
cycle. Figure 5 provides a ratio of peak-to-peak output
OUT
Where f is the frequency and N is the number of paral-
leled phases.
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
IN
4612 F05
O
Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
4612f
12
LTM4612
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and
Overcurrent Foldback
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider.
Figure 6 shows an example of coincident tracking. Ra-
tiometric modes of tracking can be achieved by selecting
differentresistorvaluestochangetheoutputtrackingratio.
The master output must be greater than the slave output
for the tracking to work. Figure 7 shows the coincident
output tracking.
LTM4612 has a current mode controller, which inherently
limitsthecycle-by-cycleinductorcurrentnotonlyinsteady
state operation, but also in transient.
To further limit current in the event of an overload condi-
tion,theLTM4612providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.5μA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltagereferenceminusanymargindelta.Thiswillcontrol
the ramp of the internal reference and the output voltage.
The total soft-start time can be calculated as:
RUN Enable
The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with 5V logic levels.
The RUN pin can also be used as an undervoltage lockout
(UVLO) function by connecting a resistor divider from
the input supply to the RUN pin. The equation for UVLO
threshold:
CSS
1.5µA
tSOFTSTART ≅ 0.8 • 0.6V – V
•
(
)
OUT(MARGIN)
R1+R2
VUVLO
=
•1.5V
R2
If the RUN pin falls below 2.5V, then the soft-start pin
is reset to allow for the proper soft-start again. Current
foldback and force continuous mode are disabled during
the soft-start process. The soft-start function can also
be used to control the output ramp rising time, so that
another regulator can be easily tracked.
where R1 is the top resistor, and R2 is the bottom resistor.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point, and tracks
with margining.
V
IN
10μF
100k
V
V
PLLIN
V
OUT
D
IN
SLAVE
OUTPUT
MASTER OUTPUT
PGOOD
RUN
V
FB
C
OUT
C
COMP
FCB
MARG0
MARG1
MPGM
IN
LTM4612
SLAVE OUTPUT
INTV
CC
CC
OUTPUT
VOLTAGE
MASTER
OUTPUT
DRV
R2
100k
f
SET
TRACK/SS
SGND PGND
TRACK
CONTROL
5.23k
R1
5.23k
4612 F06
4612 F07
TIME
Figure 6. Coincident Tracking
Figure 7. Coincident Output Tracking
4612f
13
LTM4612
APPLICATIONS INFORMATION
COMP Pin
Parallel Operation
The pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. An Excel design tool from Linear Technology will
be provided for more control loop optimization.
The LTM4612 device is an inherently current mode con-
trolled device. This allows the paralleled modules to have
very good current sharing and balanced thermal on the
design.Figure21showsaschematicoftheparalleldesign.
The voltage feedback equation changes with the variable
N as modules are paralleled. The equation:
FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. FCB pin below the 0.6V threshold
forcescontinuoussynchronousoperation,allowingcurrent
to reverse at light loads and maintaining high frequency
operation.
100k
+RFB
N
VOUT = 0.6V
RFB
N is the number of paralleled modules.
Radiated EMI Noise
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make the large di/dt change in the converters, which act
as the radiation sources in most systems. LTM4612 inte-
grates the feature to minimize the radiated EMI noise to
meet the most applications with low noise requirements.
An optimized gate driver for the MOSFET and a noise
cancellation network are installed inside the LTM4612
to achieve the low radiated EMI noise. Figure 8 shows a
typical example for the LTM4612 to meet the Class B of
CISPR 22 radiated emission limit.
PLLIN Pin
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of the external clock.
The frequency range is 30% around the set operating
frequency. A pulse detection circuit is used to detect a
clock on the PLLIN pin to turn on the phase-locked loop.
The pulse width of the clock has to be at least 400ns, and
2V in amplitude. During the start-up of the regulator, the
phase-locked loop function is disabled.
90
70
INTV and DRV Connection
CC
CC
50
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV
CISPR22, CLASS B
CC
30
10
0
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4612
can be directly powered by V . The gate driver current
IN
through the LDO is about 20mA. The internal LDO power
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
4612 F08
dissipation can be calculated as:
Figure 8. Radiated Emission Scan with 24VIN to
12VOUT at 5A Measured in 10 Meter Chamber
P
= 20mA • (V – 5V)
IN
LDO_LOSS
TheLTM4612alsoprovidestheexternalgatedrivervoltage
Thermal Considerations and Output Current Derating
pin DRV . If there is a 5V rail in the system, it is recom-
CC
In different applications, LTM4612 operates in a variety
of thermal environments. The maximum output current is
limited by the environment thermal condition. Sufficient
mended to connect the DRV pin to the external 5V rail.
CC
This is especially true for higher input voltages. Do not
apply more than 6V to the DRV pin.
CC
cooling should be provided to help ensure reliable opera-
4612f
14
LTM4612
APPLICATIONS INFORMATION
tion. When the cooling is limited, proper output current
derating is necessary, considering ambient temperature,
airflow, input/output condition, and the need for increased
reliability.
125°C maximum. This will maintain the maximum operat-
ing temperature below 125°C. Each of the derating curves
and the power loss curve that corresponds to the correct
output voltage can be used to solve for the approximate
θ of the condition. Each figure has three curves that are
JA
The power loss curves in Figures 9 and 10 can be used
in coordination with the load current derating curves in
taken at three different air flow conditions. Each of the
derating curves in Figures 11 to 16 can be used with the
appropriate power loss curve in either Figure 9 or Figure
Figures 11 to 16 for calculating an approximate θ for
JA
the module. Graph designation delineates between no
heat sink, and a BGA heat sink. Each of the load current
derating curves will lower the maximum load current as a
function of the increased ambient temperature to keep the
maximum junction temperature of the power module at
10 to derive an approximate θ . Table 3 provides the ap-
JA
proximateθ forFigures11to16.Acompleteexplanation
JA
of the thermal characteristics is provided in the thermal
application note, AN110.
6
5
4
3
2
1
0
6
5
4
3
2
1
0
5.0
200
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
LFM
36V TO 15V
IN
OUT
0LFM
400LFM
36V TO 5V
IN
OUT
24V TO 12V
IN
OUT
2
3
4
5
0
1
2
3
4
5
0
1
25 35
55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
45
LOAD CURRENT (A)
LOAD CURRENT (A)
4612 F10
4612 F09
4612 F11
Figure 9. Power Loss at
12VOUT and 15VOUT
Figure 10. Power Loss at 5VOUT
Figure 11. No Heat Sink
with 36VIN to 5VOUT
5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
200
200
200
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
LFM
LFM
LFM
0LFM
400LFM
0LFM
400LFM
0LFM
400LFM
25 35
55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
25 35
55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
25 35
55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
45
45
45
4612 F12
4612 F13
4612 F14
Figure 12. BGA Heat Sink
with 36VIN to 5VOUT
Figure 13. No Heat Sink
with 24VIN to 12VOUT
Figure 14. BGA Heat Sink
with 24VIN to 12VOUT
4612f
15
LTM4612
APPLICATIONS INFORMATION
5.0
4.5
4.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
25
35
45
55
65
75
85
95
25
35
45
55
65
75
85
95
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4612 F15
4612 F16
Figure 15. No Heat Sink
with 36VIN to 15VOUT
Figure 16. BGA Heat Sink
with 36VIN to 15VOUT
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20)
TYPICAL MEASURED VALUES
VENDORS
Murata
PART NUMBER
VENDORS
Murata
TDK
PART NUMBER
GRM32ER61C476KEI5L (47μF, 16V)
GRM32ER61C226KE20L (22μF, 16V)
GRM32ER71H106K (10μF, 50V)
C3225X5RIC226M (22μF, 16V)
Murata
V
(V)
C
C
C
C
V
DROOP
(mV)
PEAK-TO-
PEAK (mV)
RECOVERY
TIME (μs)
LOAD STEP
(A/μs)
R
FB
OUT
IN
IN
OUT1
OUT2
IN
(CERAMIC)
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
2 × 10μF 50V
(BULK)
(CERAMIC)
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
2 × 22μF 16V
4 × 47μF 16V
(BULK)
150μF 25V
None
(V)
12
12
24
24
36
36
24
24
36
36
24
36
28
36
(kΩ)
13.7
13.7
13.7
13.7
13.7
13.7
6.34
6.34
6.34
6.34
5.23
5.23
4.12
4.12
5
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
100μF 50V
86
156
178
166
169
178
172
209
325
197
288
281
375
338
250
26
14.8
27
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
86
5
150μF 25V
None
83
5
86
14.8
25
5
150μF 25V
None
86
5
86
15.2
30
10
10
10
10
12
12
15
15
150μF 25V
None
111
171
108
153
153
184
178
134
35
150μF 25V
None
35
39
150μF 25V
None
37
34.4
70
150μF 25V
None
70
Table 3. 12V and 15V Outputs
DERATING CURVE
Figures 11, 13, 15
V
(V)
POWER LOSS CURVE
Figure 9
AIR FLOW (LFM)
HEAT SINK
θ
JA
(°C/W)
IN
24, 36
24, 36
24, 36
24, 36
24, 36
24, 36
0
None
None
None
13
9.3
8.3
Figures 11, 13, 15
Figure 9
200
400
0
Figures 11, 13, 15
Figure 9
Figures 12, 14, 16
Figure 9
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
12.2
8.6
Figures 12, 14, 16
Figure 9
200
400
Figures 12, 14, 16
Figure 9
7.7
4612f
16
LTM4612
APPLICATIONS INFORMATION
Table 4. 5V Output
DERATING CURVE
Figures 18, 21
V
IN
(V)
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
36
0
14.9
11.1
10
Figures 18, 21
36
36
36
36
36
Figure 10
200
400
0
None
Figures 18, 21
Figure 10
None
Figures 10, 13, 16
Figures 10, 13, 16
Figures 10, 13, 16
Figure 10
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
14
Figure 10
200
400
10.4
9.3
Figure 10
Heat Sink Manufacturer
Wakefield Engineering
Part No: LTN20069
Phone: 603-635-2800
Safety Considerations
• Do not put vias directly on pads.
The LTM4612 modules do not provide isolation from V
• If vias are placed onto the pads, the the vias must be
capped.
IN
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic
failure.
• Interstitialvia placementcan also beused if necessary.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
Layout Checklist/Example
• Place one or more high frequency ceramic capacitors
close to the connection into the system board.
The high integration of LTM4612 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
Figure 17 gives a good example of the recommended
layout.
• Use large PCB copper areas for high current path, in-
cluding V , PGND and V . It helps to minimize the
IN
OUT
V
IN
C
C
IN
PCB conduction loss and thermal stress.
IN
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
D
OUT
GND
high frequency noise.
SIGNAL
GND
• Place a dedicated power ground layer underneath the
unit.
• UseroundcornersforthePCBcopperlayertominimize
the radiated noise.
C
OUT
C
OUT
V
OUT
4612 F17
• To minimize the EMI noise and reduce module thermal
stress, use multiple vias for interconnection between
top layer and other power layers.
Figure 17. Recommended PCB Layout
4612f
17
LTM4612
APPLICATIONS INFORMATION
V
OUT
CLOCK SYNC
V
IN
22V TO 36V
C1
10μF
50V
R4
100k
R3
100k
R5
2M
V
V
IN
PLLIN
D
V
12V
5A
OUT
V
OUT
PGOOD
RUN
COMP
C3
C
22μF
16V
C
OUT2
220μF
16V
LTM4612
OUT1
22pF
+
ON/OFF
V
FB
R
FB
5.23k
INTV
CC
CC
FCB
DRV
MARG0
MARG1
MPGM
f
MARGIN
SET
C
IN
CONTROL
TRACK/SS
REFER TO TABLE 2
10μF
50V CERAMIC
C4
0.01μF
SGND PGND
R1
392k
5% MARGIN
4612 F18
Figure 18. Typical 22V to 36VIN, 12V at 5A Design
V
OUT
CLOCK SYNC
V
IN
5V TO 36V
C1
10μF
50V
R4
100k
R3
100k
V
V
PLLIN
D
IN
V
3.3V
5A
OUT
V
OUT
PGOOD
RUN
COMP
C3
C
C
22μF
6.3V
C
IN
OUT1
OUT2
22pF
+
ON/OFF
10μF
50V CERAMIC
220μF
6.3V
V
FB
LTM4612
R
FB
22.1k
INTV
CC
FCB
DRV
EXTERNAL 5V SUPPLY
IMPROVES EFFICIENCY—
ESPECIALLY FOR HIGH
INPUT VOLTAGES
CC
REFER TO TABLE 2
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
R
191k
1%
fSET
SGND PGND
R1
392k
5% MARGIN
C4
0.01μF
4612 F19
Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency
4612f
18
LTM4612
APPLICATIONS INFORMATION
V
OUT
CLOCK SYNC
V
IN
26V TO 36V
C1
10μF
50V
R4
100k
R3
100k
V
V
PLLIN
D
IN
V
15V
4A
OUT
V
PGOOD
RUN
COMP
OUT
C3
C
22μF
16V
C
OUT2
220μF
16V
LTM4612
OUT1
22pF
+
ON/OFF
V
FB
R
FB
4.12k
INTV
DRV
CC
CC
R
fSET
FCB
806k, 1%
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
C
IN
10μF
SGND PGND
R1
392k
5% MARGIN
50V
CERAMIC
C4
0.01μF
4612 F20
Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency
V
OUT
V
IN
20V TO 36V
C1
10μF
50V
CLOCK SYNC
0° PHASE
R2
100k
R4
100k
V
OUT
12V, 10A
V
V
PLLIN
V
OUT
D
IN
PGOOD
RUN
COMP
INTV
DRV
C6
47pF
LTM4612
C3
22μF
16V
+
C4
V
FB
FCB
220μF
16V
CC
CC
C2
10μF
50V
f
MARG0
MARG1
MPGM
MARGIN
CONTROL
SET
TRACK/SS
C5
100μF
50V
+
C7
0.33μF
R1
392k
R
FB
2.61k
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
100k/N + R
V
OUT1
FB
V
OUT
= 0.6V •
R
FB
GND OUT2
SET MOD
C11
0.1μF
R5
124k
C11
10μF
50V
LTC6908-1
CLOCK SYNC
180° PHASE
V
D
V
IN
PLLIN
V
OUT
PGOOD
RUN
LTM4612
C9
22μF
16V
C10
220μF
16V
+
V
FCB
COMP
INTV
CC
FB
C8
10μF
50V
MARG0
MARG1
MPGM
DRV
CC
f
SET
TRACK/SS
R6
392k
SGND PGND
4612 F21
Figure 21. 2-Phase, Parallel 12V at 10A Design
4612f
19
LTM4612
APPLICATIONS INFORMATION
12V
V
IN
22V TO 36V
C1
10μF
50V
CLOCK SYNC
0° PHASE
R4
100k
R2
100k
V
V
IN
PLLIN
D
12V AT 5A
PGOOD
RUN
COMP
V
OUT
C6
22pF
C3
22μF
16V
LTM4612
C4
220μF
16V
+
V
FB
FCB
INTV
CC
CC
DRV
C2
10μF
50V
f
MARG0
MARG1
MPGM
MARGIN
SET
CONTROL
TRACK/SS
C5
100μF
50V
+
R1
392k
R
FB1
5.23k
C7
0.15μF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
10V
V
OUT1
GND OUT2
SET MOD
C11
0.1μF
R5
118k
C11
10μF
50V
LTC6908-1
CLOCK SYNC
180° PHASE
R7
100k
R3
100k
V
V
PLLIN
D
IN
10V AT 5A
V
PGOOD
RUN
OUT
C1
22pF
C9
22μF
16V
LTM4612
C10
220μF
16V
+
V
COMP
FB
FCB
INTV
CC
12V TRACK
MARG0
MARG1
MPGM
MARGIN
DRV
R8
CC
C8
10μF
50V
CONTROL
100k
f
SET
TRACK/SS
R6
392k
R
R9
6.24k
FB2
SGND PGND
6.24k
4612 F22
Figure 22. 2-Phase, 12V and 10V at 5A Design
4612f
20
LTM4612
APPLICATIONS INFORMATION
5V
V
IN
7V TO 36V
C1
CLOCK SYNC
0° PHASE
10μF
50V
R4
100k
R2
100k
V
V
PLLIN
OUT
D
IN
5V AT 5A
V
PGOOD
RUN
C6
22pF
LTM4612
C3
22μF
6.3V
C4
220μF
6.3V
+
V
FB
COMP
INTV
CC
C2
FCB
10μF
50V
DRV
CC
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
C5
100μF
50V
+
R
fSET1
150k
R1
392k
R
FB1
13.7k
C7
0.15μF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
3.3V
V
OUT1
GND OUT2
SET MOD
C11
0.1μF
R5
200k
C11
10μF
50V
CLOCK SYNC
180° PHASE
LTC6908-1
R7
100k
R3
100k
V
V
PLLIN
D
IN
3.3V AT 5A
V
PGOOD
RUN
OUT
C1
22pF
C9
22μF
6.3V
C10
220μF
6.3V
+
V
COMP
FB
LTM4612
FCB
INTV
CC
5V TRACK
MARG0
MARG1
MPGM
MARGIN
DRV
R8
CC
C8
10μF
50V
CONTROL
100k
f
SET
TRACK/SS
R6
392k
R
R9
R
fSET2
FB2
SGND PGND
22.1k
22.1k 100k
4612 F23
Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency
4612f
21
LTM4612
PACKAGE DESCRIPTION
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
PIN NAME
PGND
PIN NAME
PIN NAME
A1
A2
A3
A4
A5
A6
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
D1
D2
D3
D4
D5
D6
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
A7
INTV
CC
PLLIN
PGND
PGND
PGND
PGND
PGND
A8
A9
TRACK/SS
RUN
A10
A11
A12
COMP
MPGM
B1
B2
B3
B4
B5
B6
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
E1
E2
E3
E4
E5
E6
E7
E8
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
B7
V
-
D
B8
B9
RUN
-
B10
B11
B12
MPGM
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
f
SET
C1
C2
C3
C4
C5
C6
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
C7
V
-
D
C8
F1
F2
F3
F4
F5
F6
F7
F8
F9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C9
-
C10
C11
C12
DRV
CC
MARG1
MARG0
D7
-
-
D8
D9
SGND
-
D10
D11
D12
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
COMP
MARG1
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
E9
-
-
E10
E11
E12
DRV
CC
DRV
CC
F10
F11
F12
-
-
V
FB
G12
H12
J12
K12
L12
M12
PGOOD
SGND
NC
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
NC
NC
FCB
4612f
22
LTM4612
PACKAGE DESCRIPTION
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4612f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTM4612
PACKAGE PHOTOGRAPH
15mm
2.8mm
15mm
4612 F24
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC2900
Quad Supply Monitor with Adjustable Reset Timer
10A DC/DC μModule
Monitors Four Supplies; Adjustable Reset Timer
Basic 10A DC/DC μModule, LGA Package
LTM4600
LTM4600HVMP
Military Plastic 10A DC/DC μModule
Guaranteed Operation from –55°C to 125°C Ambient, LGA Package
LTM4601/
LTM4601A
12A DC/DC μModule with PLL, Output Tracking/
Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version Has
No Remote Sensing, LGA Package
LTM4602
LTM4603
6A DC/DC μModule
Pin Compatible with the LTM4600, LGA Package
6A DC/DC μModule with PLL and Output Tracking/ Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No Remote
Margining and Remote Sensing
Sensing, Pin Compatible with the LTM4601, LGA Package
LTM4604A
LTM4606
Low V 4A DC/DC μModule
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V ≤ 5V, 9mm × 15mm × 2.3mm LGA Package
IN
IN
OUT
Ultralow Noise 6A, DC/DC μModule
Ultralow Noise, with PLL, Output Tracking and Margining, LTM4612
Pin Compatible
LTM4608A
LTM8020
LTM8021
Low V 8A DC/DC μModule
2.4V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V; 9mm × 15mm × 2.8mm LGA Package
OUT
IN
IN
High V 0.2A DC/DC Step-Down μModule
4V ≤ V ≤ 36V, 1.25V ≤ V
≤ 5V 6.25mm × 6.25mm × 2.3mm LGA Package
≤ 5V 6.25mm × 11.25mm × 2.8mm LGA Package
OUT
IN
IN
OUT
High V 0.5A DC/DC Step-Down μModule
3V ≤ V ≤ 36V, 0.8V ≤ V
IN
IN
LTM8022/LTM8023 36V , 1A and 2A DC/DC μModule
Pin Compatible; 4.5V ≤ V ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package
IN
IN
4612f
LT 0808 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTM4613
符合 EN55022B 規格的36VIN、15VOUT、8A、DC/DC μModule 穩壓器,LTM®4613 是一款完整、超低噪聲、8A 開關模式 DC/DC電源。
Linear
LTM4613EV#PBF
LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 133; Temperature Range: -40°C to 85°C
Linear
LTM4613IV#PBF
LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 133; Temperature Range: -40°C to 85°C
Linear
LTM4613IY
LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 133; Temperature Range: -40°C to 85°C
Linear
LTM4613MPV#PBF
LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 133; Temperature Range: -55°C to 125°C
Linear
©2020 ICPDF网 联系我们和版权申明