LTM4620A [Linear]
Dual 13A or Single 26A DC/DC μModule Regulator Frequency Synchronization; 双路13A或26A单DC / DC稳压器μModule频率同步
| 型号： | LTM4620A |
| 厂家： | 
Linear |
| 描述： | Dual 13A or Single 26A DC/DC μModule Regulator Frequency Synchronization |
| 文件： | 总36页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4620A
Dual 13A or Single 26A
DC/DC µModule Regulator
FeaTures
DescripTion
n
Dual 13A or Single 26A Output
TheLTM®4620Aisacompletedual13A,orsingle26Aoutput
n
Wide Input Voltage Range: 4.5V to 16V
switchingmodeDC/DCpowersupplywithwiderV range
OUT
n
Output Voltage Range: 0.6V to 5.3V
and higher efficiency than the LTM4620. Included in the
packagearetheswitchingcontroller,powerFETs,inductors
and all supporting components. Operating from an input
voltage range of 4.5V to 16V, the LTM4620A supports two
outputs each with an output voltage range of 0.6V to 5.3V,
set by a single external resistor. Its high efficiency design
deliversupto13Acontinuouscurrentforeachoutput.Only
a few input and output capacitors are needed.
n
1.5ꢀ Maꢁiꢂuꢂ ꢃotal DC Output Error
n
Multiphase Current Sharing with Multiple
LꢃM4620As Up to 100A
n
Higher Efficiency and Wider V
Range Than LTM4620
OUT
n
n
n
n
n
n
n
n
Differential Remote Sense Amplifier
Current Mode Control/Fast Transient Response
Adjustable Switching Frequency
Overcurrent Foldback Protection
Thedevicesupportsfrequencysynchronization,multiphase
operation, Burst Mode® operation and output voltage
tracking for supply rail sequencing and has an onboard
temperaturediodefordevicetemperaturemonitoring.High
switchingfrequencyandacurrentmodearchitectureenable
a very fast transient response to line and load changes
without sacrificing stability.
Frequency Synchronization
Internal Temperature Sensing Diode Output
Output Overvoltage Protection
Pin Compatible with the LTM4628 (Dual 8A) and
LTM4620 (Dual 13A)
15mm × 15mm × 4.41mm LGA Package
n
Fault protection features include overvoltage and over-
current protection. The power module is offered in a
proprietary space saving and thermally enhanced 15mm
× 15mm × 4.41mm LGA package. The LTM4620A is
RoHS compliant.
applicaTions
n
Telecom and Networking Equipment
n
Industrial Equipment
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
Typical applicaTion
26A, 5V Output DC/DC µModule® Regulator
INTV
INTV
CC
CC
5V Efficiency vs IOUꢃ
4.7µF
5k
100
V
OUT
PGOOD
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
V
95
IN
7V TO 16V
V
IN
V
OUT1
100µF
6.3V
×2
22µF
25V
×4
TEMP
V
10k*
120k
INTV
OUTS1
RUN1
DIFFOUT
90
220pF
RUN2
SW1
TRACK1
TRACK2
V
V
FB1
FB2
LTM4620A
5.1V*
8.25k
85
80
f
0.1µF
COMP1
COMP2
CC
SET
8V TO 5V EFF (650kHz)
12V TO 5V EFF (750kHz)
PHASMD
V
OUTS2
V
OUT
1
3
5
8
10 12 14 16 19 21 23
* PULL-UP RESISTOR AND
ZENER ARE OPTIONAL
V
5V
OUT2
SW2
100µF
6.3V
×2
TOTAL OUTPUT CURRENT (A)
26A
4620A TA01b
PGOOD2
SGND
GND
DIFFP
DIFFN
PGOOD
4620A TA01a
4620af
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For more information www.linear.com/4620A
LTM4620A
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V (Note 8).................................................–0.3V to 18V
SW1 SW2
IN
TEMP
EXTV
CC
V
, V
....................................................–1V to 18V
M
L
PGOOD1, PGOOD2, RUN1, RUN2,
V
INTV , EXTV .......................................... –0.3V to 6V
IN
CC
CC
K
J
MODE_PLLIN, f , TRACK1, TRACK2,
SET
DIFFOUT, PHASMD...............................–0.3V to INTV
OUT1 OUT2 OUTS1 OUTS2
CC
H
G
F
INTV
SW2
CC
CLKOUT
SW1
V
, V
, V
, V
..................... –0.3V to 6V
PGOOD1
PGOOD2
RUN2
DIFFP, DIFFN .........................................–0.3V to INTV
PHASMD
RUN1
SGND
CC
MODE_PLLIN
COMP1, COMP2, V , V (Note 6)........ –0.3V to 2.7V
DIFFOUT
GND
COMP1 COMP2
FB1 FB2
DIFFP
E
DIFFN
TRACK1
INTV Peak Output Current................................100mA
V
TRACK2
GND
SGND FB2
CC
V
FB1
D
C
B
A
V
Internal Operating Temperature Range
f
SGND OUTS2
SET
V
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Temperature
OUTS1
V
V
OUT1
OUT2
GND
1
2
3
4
5
6
7
8
9
10
11
12
(Mount on Top Side of PCB Only) ......................... 245°C
LGA PACKAGE
144-LEAD (15mm × 15mm × 4.41mm)
T
= 125°C, Θ = 7°C/W, Θ = 1.5°C/W, Θ
= 3.7°C/W,
JMAX
JA
Θ
JCbottom
JCtop
+ Θ ≅ 7°C/W, weight = 3.037g
JB
JBA
Θ VALUES DEFINED PER JESD 51-12
orDer inForMaTion
LEAD FREE FINISH
LTM4620AEV#PBF
LTM4620AIV#PBF
ꢃRAY
PARꢃ MARKING*
LTM4620AV
PACKAGE DESCRIPꢃION
ꢃEMPERAꢃURE RANGE
–40°C to 125°C
LTM4620AEV#PBF
LTM4620AIV#PBF
144-Lead (15mm × 15mm × 4.41mm) LGA
144-Lead (15mm × 15mm × 4.41mm) LGA
LTM4620AV
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
elecTrical characTerisTics ꢃhe l denotes the specifications which apply over the specified internal
operating teꢂperature range. Specified as each individual output channel. ꢃA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 26.
SYMBOL
PARAMEꢃER
CONDIꢃIONS
MIN
4.5
ꢃYP
MAX
16
UNIꢃS
l
l
l
V
V
Input DC Voltage
Output Voltage
V
V
V
IN
(Note 8)
0.6
5.3
OUT
V
V
,
Output Voltage, Total Variation with
Line and Load
C
= 22µF × 3, C = 100µF × 1 Ceramic,
OUT
1.477
1.5
1.523
OUT1(DC)
OUT2(DC)
IN
220µF POSCAP
Input Specifications
V
V
, V
RUN Pin On/Off Threshold
RUN Pin On Hysteresis
RUN Rising
1.1
1.25
150
1
1.40
V
mV
A
RUN1 RUN2
, V
RUN1HYS RUN2HYS
I
Input Inrush Current at Start-Up
I
= 0A, C = 22µF ×3, C = 0.01µF,
OUT
= 12V
INRUSH(VIN)
OUT
C
V
IN
SS
= 100µF ×3, V
= 1.5V, V
= 1.5V,
OUT2
OUT1
IN
4620af
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For more information www.linear.com/4620A
LTM4620A
elecTrical characTerisTics ꢃhe l denotes the specifications which apply over the specified internal
operating teꢂperature range. Specified as each individual output channel. ꢃA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 26.
SYMBOL
PARAMEꢃER
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
I
Input Supply Bias Current
V
V
V
= 12V, V
= 12V, V
= 1.5V, Burst Mode Operation
= 1.5V, Pulse-Skipping Mode
5
mA
mA
mA
µA
Q(VIN)
IN
IN
IN
OUT
OUT
15
65
50
= 12V, V = 1.5V, Switching Continuous
OUT
Shutdown, RUN = 0, V = 12V
IN
I
Input Supply Current
V
IN
V
IN
= 5V, V
= 1.5V, I = 13A
OUT
OUT
4.6
1.853
A
A
S(VIN)
OUT
= 12V, V
= 1.5V, I
= 13A
OUT
Output Specifications
, I
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V
= 1.5V (Notes 7, 8)
0
13
A
OUT1(DC) OUT2(DC)
IN
OUT
l
l
ΔV
ΔV
/V
= 1.5V, V from 4.75V to 16V
0.01
0.35
15
0.025
%/V
OUT1(LINE) OUT1
OUT
IN
/V
I
= 0A for Each Output,
OUT
OUT2(LINE) OUT2
ΔV
ΔV
/V
Load Regulation Accuracy
Output Ripple Voltage
For Each Output, V
V = 12V (Note 7)
IN
= 1.5V, 0A to 13A
0.5
%
OUT1 OUT1
OUT
/V
OUT2 OUT2
V
, V
For Each Output, I
= 0A, C
= 100µF ×3/
mV
P-P
OUT1(AC) OUT2(AC)
OUT
OUT
X7R/Ceramic, 470µF POSCAP, V = 12V,
IN
V
OUT
= 1.5V, Frequency = 400kHz
f (Each Channel)
Output Ripple Voltage Frequency
SYNC Capture Range
V
IN
= 12V, V
= 1.5V, f = 1.25V (Note 4)
500
kHz
kHz
S
OUT
SET
f
400
780
SYNC
(Each Channel)
ΔV
Turn-On Overshoot
Turn-On Time
C
V
= 100µF/X5R/Ceramic, 470µF POSCAP,
10
10
mV
mV
OUTSTART
OUT
OUT
(Each Channel)
= 1.5V, I
= 0A V = 12V
OUT IN
t
C
= 100µF/X5R/Ceramic, 470µF POSCAP,
5
5
ms
ms
START
OUT
(Each Channel)
No Load, TRACK/SS with 0.01µF to GND,
V
= 12V
IN
ΔV
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
30
mV
OUT(LS)
(Each Channel)
C
= 22µF ×3/X5R/Ceramic, 470µF POSCAP
OUT
V
= 12V, V
= 1.5V
IN
OUT
t
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load,
20
20
µs
A
SETTLE
(Each Channel)
V
= 12V, C
= 100µF, 470µF POSCAP
IN
OUT
I
Output Current Limit
V
IN
= 12V, V
= 1.5V
OUT(PK)
OUT
(Each Channel)
Control Section
l
l
V
, V
Voltage at V Pins
I
= 0A, V
= 1.5V
0.592
0.600
–5
0.606
–20
V
nA
V
FB1 FB2
FB
OUT
OUT
I
FB
(Note 6)
V
OVL
Feedback Overvoltage Lockout
0.64
1
0.66
1.25
0.68
1.5
TRACK1 (I),
TRACK2 (I)
Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V
µA
UVLO
Undervoltage Lockout
V
IN
V
IN
Falling
Rising
3.3
3.9
V
V
UVLO Hysteresis
0.6
90
V
ns
t
Minimum On-Time
(Note 6)
ON(MIN)
R
, R
Resistor Between V
, V
59.90
60.4
60.75
0.3
5
kΩ
FBHI1 FBHI2
OUTS1 OUTS2
and V , V Pins for Each Output
FB1 FB2
V
, V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
V
PGOOD1 PGOOD2
PGOOD
Low
I
PGOOD Leakage Current
PGOOD Trip Level
V
V
µA
PGOOD
PGOOD
V
with Respect to Set Output Voltage
Ramping Negative
Ramping Positive
PGOOD
FB
V
V
–10
10
%
%
FB
FB
4620af
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For more information www.linear.com/4620A
LTM4620A
elecTrical characTerisTics ꢃhe l denotes the specifications which apply over the specified internal
operating teꢂperature range. Specified as each individual output channel. ꢃA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted. Per the typical application in Figure 26.
SYMBOL
PARAMEꢃER
CONDIꢃIONS
MIN
ꢃYP
MAX
UNIꢃS
INꢃV Linear Regulator
CC
V
V
Internal V Voltage
6V < V < 16V
4.8
5
5.2
2
V
INTVCC
CC
IN
INTV Load Regulation
I
CC
= 0mA to 50mA
0.5
%
INTVCC
Load Regulation
CC
V
V
V
EXTV Switchover Voltage
EXTV Ramping Positive
4.5
4.7
50
V
mV
mV
EXTVCC
CC
CC
EXTV Dropout
I
CC
= 20mA, V = 5V
EXTVCC
100
EXTVCC(DROP)
EXTVCC(HYST)
CC
EXTV Hysteresis
200
CC
Oscillator and Phase-Locked Loop
Frequency Nominal Nominal Frequency
f
f
f
= 1.2V
450
210
700
9
500
250
780
10
550
290
860
11
kHz
kHz
kHz
µA
SET
SET
SET
Frequency Low
Frequency High
Lowest Frequency
= 0V (Note 5)
> 2.4V, Up to INTV
Highest Frequency
CC
f
Frequency Set Current
MODE_PLLIN Input Resistance
SET
R
250
kΩ
MODE_PLLIN
CLKOUT
Phase (Relative to V
)
PHASMD = GND
PHASMD = Float
PHASMD = INTV
60
90
120
Deg
Deg
Deg
OUT1
CC
CLK High
CLK Low
Clock High Output Voltage
Clock Low Output Voltage
2
V
V
0.2
3
Differential Aꢂplifier
A Differential
Gain
1
V
V
Amplifier
R
Input Resistance
Measured at DIFFP Input
= V = 1.5V, I
80
kΩ
mV
dB
IN
V
OS
Input Offset Voltage
V
DIFFP
= 100µA
DIFFOUT
DIFFOUT
PSRR Differential
Amplifier
Power Supply Rejection Ratio
5V < V < 16V
90
2
IN
I
CL
Maximum Output Current
Maximum Output Voltage
Gain Bandwidth Product
Diode Connected PNP
Temperature Coefficient
mA
V
V
I
= 300µA
INTV – 1.4
CC
OUT(MAX)
DIFFOUT
GBW
3
MHz
V
V
TEMP
I = 100µA
0.6
2.2
l
TC
mV/C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable from 400kHz to 750kHz.
Note 5: The LTM4620A is designed to operate from 400kHz to 750kHz
Note 6: These parameters are tested at wafer sort.
Note 2: The LTM4620A is tested under pulsed load conditions such that
T ≈ T . The LTM4620AE is guaranteed to meet specifications from
J
A
Note 7: See output current derating curves for different V , V
and T .
A
IN OUT
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4620AI is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 8: Output current limitations. For 10V ≤ V ≤ 16V, the 5V output
IN
current needs to be limited to 12A/channel, switching frequency = 750kHz.
Derating curves apply. For 7V ≤ V ≤ 9V, the 5V output current needs
IN
to be limited to 13A/channel, switching frequency = 750kHz. Derating
curves apply. All other input and output combinations are 13A/channel
with recommended switching frequency included in the efficiency graphs.
Derating curves apply.
4620af
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For more information www.linear.com/4620A
LTM4620A
Typical perForMance characTerisTics
Efficiency vs Output Current,
VIN = 5V
Efficiency vs Output Current,
IN = 8V
Efficiency vs Output Current,
VIN = 12V
V
100
95
90
85
80
75
70
100
95
90
85
80
75
70
100
95
90
85
80
75
70
8V TO 1V (400kHz)
8V TO 1.2V (400kHz)
8V TO 1.5V (500kHz)
8V TO 1.8V (600kHz)
8V TO 2.5V (650kHz)
8V TO 3.3V (700kHz)
8V TO 5V (750kHz)
12V TO 1V (400kHz)
12V TO 1.2V (400kHz)
12V TO 1.5V (500kHz)
12V TO 1.8V (600kHz)
12V TO 2.5V (650kHz)
12V TO 3.3V (700kHz)
12V TO 5V (750kHz)
5V TO 1V (400kHz)
5V TO 1.2V (400kHz)
5V TO 1.5V (400kHz)
5V TO 1.8V (500kHz)
5V TO 2.5V (500kHz)
5V TO 3.3V (500kHz)
TIE 5V
TO EXTV
OUT
CC
TIE 5V
TO EXTV
OUT CC
1
3.8 5.2 6.6 8.0 9.4 10.8 12.2
OUTPUT CURRENT (A)
2.4
1
3.8 5.2 6.6 8.0 9.4 10.8 12.2
OUTPUT CURRENT (A)
1
3.8 5.2 6.6 8.0 9.4 10.8 12.2
OUTPUT CURRENT (A)
2.4
2.4
4620A G01
4620A G02
4620A G03
12V to 1V Load Step Response
12V to 1.2V Load Step Response
12V to 1.5V Load Step Response
20mV/DIV
20mV/DIV
50mV/DIV
5A/DIV
6A/µs STEP
5A/DIV
6A/µs STEP
5A/DIV
6A/µs STEP
4620A G06
4620A G04
4620A G05
50µs/DIV
50µs/DIV
50µs/DIV
C
C
= 47pF
C
C
= 150pF
C
C
= 150pF
FF
FF
FF
= 220µF 9mΩ POSCAP
= 2 × 470µF 9mΩ EACH POSCAP
= 2 × 470µF 9mΩ EACH POSCAP
OUT
OUT
OUT
100µF CERAMIC
1 × 100µF CERAMIC
1 × 100µF CERAMIC
12V to 1.8V Load Step Response
12V to 2.5V Load Step Response
12V to 3.3V Load Step Response
50mV/DIV
50mV/DIV
100mV/DIV
5A/DIV
6A/µs STEP
5A/DIV
6A/µs STEP
5A/DIV
6A/µs STEP
4620A G07
4620A G08
4620A G09
50µs/DIV
50µs/DIV
= 220µF 9mΩ POSCAP
50µs/DIV
= 100µF 15mΩ POSCAP
C
C
= 33pF
C
C
= 100pF
C
C
= 33pF
FF
OUT
FF
FF
= 220µF 9mΩ POSCAP
OUT
OUT
100µF CERAMIC
100µF CERAMIC
100µF CERAMIC
4620af
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For more information www.linear.com/4620A
LTM4620A
Typical perForMance characTerisTics
12V to 5V Load Step Response
Output Current Sharing
12V to 1.5V Start-Up, No Load
12
11
10
500mV/DIV
9
8
7
100mV/DIV
6
5
4
3
2
1
0
5A/DIV
6A/µs STEP
4620A G10
4620A G12
50µs/DIV
= 100µF CERAMIC X7R
10ms/DIV
AT NO LOAD
C
C
= 47pF
OUT
12V , 1.5V
OUT
FF
IN
OUT
C
= 2 × 470µF, 4V SANYO POSCAP,
1 × 100µF, 6.3V CERAMIC
I
I
OUT1
OUT2
SOFT-START CAPACITOR = 0.01µF
USE RUN PIN TO CONTROL START-UP
2
4
6
8
11 16 19 22
TOTAL OUTPUT CURRENT (A)
4620A G11
12V to 1.5V, 0A Load
Short-Circuit ꢃesting
12V to 1.5V, 13A No Load
Short-Circuit ꢃesting
Single Phase Start-Up, 13A Load
500mV/DIV
500mV/DIV
1A/DIV
500mV/DIV
10A/DIV
4620A G13
4620A G14
4620A G15
10ms/DIV
25ms/DIV
25ms/DIV
12V , 1.5V
AT 13A LOAD
12V , 1.5V
AT 0A LOAD
12V , 1.5V
AT 13A LOAD
IN
OUT
IN
OUT
IN
OUT
C
= 2 × 470µF, 4V SANYO POSCAP,
1 × 100µF, 6.3V CERAMIC
C
= 2 × 470µF, 4V SANYO POSCAP,
1 × 100µF, 6.3V X5R CERAMIC
C
= 2 × 470µF, 4V SANYO POSCAP,
1 × 100µF, 6.3V X5R CERAMIC
OUT
OUT
OUT
SOFT-START CAPACITOR = 0.01µF
SOFT-START CAPACITOR = 0.01µF
SOFT-START CAPACITOR = 0.01µF
USE RUN PIN TO CONTROL START-UP
USE RUN PIN TO CONTROL START-UP
USE RUN PIN TO CONTROL START-UP
4620af
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For more information www.linear.com/4620A
LTM4620A
(Recoꢂꢂended to Use ꢃest Points to Monitor Signal Pin Connections.)
pin FuncTions
PACKAGE ROW AND COLUMN LABELING MAY VARY
V
, V
(D5, D7): The Negative Input of the Error
FB1
FB2
AMONG µModule PRODUCꢃS. REVIEW EACH PACKAGE
LAYOUꢃ CAREFULLY.
Amplifier for Each Channel. Internally, this pin is con-
nected to V or V with a 60.4kΩ precision
OUTS1
OUTS2
resistor. Different output voltages can be programmed
V
(A1-A5, B1-B5, C1-C4): Power Output Pins. Apply
OUꢃ1
with an additional resistor between V and GND pins. In
FB
outputloadbetweenthesepinsandGNDpins.Recommend
placing output decoupling capacitance directly between
these pins and GND pins. Review Table 5. See Note 8 in
the Electrical Characteristics section for output current
guideline.
PolyPhase® operation, tying the V pins together allows
FB
for parallel operation. See the Applications Information
section for details.
ꢃRACK1, ꢃRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave out-
put’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
V
OUꢃ2
(A8-A12, B8-B12, C9-C12): Power Output Pins.
Apply output load between these pins and GND pins.
Recommend placing output decoupling capacitance di-
rectly between these pins and GND pins. Review Table 5.
See Note 8 in the Electrical Characteristics section for
output current guideline.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
V
, V
(C5, C8): This pin is connected to the top
OUꢃS1 OUꢃS2
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
DIFFP (E8): Positive input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output voltage. Diffamp can be used for ≤3.3V outputs.
See the Applications Information section.
is used. In paralleling modules, one of the V
pins is
OUTS
connectedtotheDIFFOUTpininremotesensingordirectly
to V with no remote sensing. It is very important to
OUT
connect these pins to either the DIFFOUT or V
since
OUT
this is the feedback path, and cannot be left open. See the
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. Diffamp can be used for ≤3.3V outputs. See
the Applications Information section.
Applications Information section.
f
(C6): Frequency Set Pin. A 10µA current is sourced
SEꢃ
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
force continuous mode of operation. Connect to INTV
CC
SGND(C7, D6, G6-G7, F6-F7):SignalGroundPin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the ap-
plication. See layout guidelines in Figure 25.
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
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LTM4620A
pin FuncTions (Recoꢂꢂended to Use ꢃest Points to Monitor Signal Pin Connections.)
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related chan-
nel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
INꢃV (H8): Internal 5V Regulator Output. The control
CC
circuits and internal gate drivers are powered from this
voltage. Decouple this pin to PGND with a 4.7µF low ESR
tantalumorceramic.INTV isactivatedwheneitherRUN1
CC
or RUN2 is activated.
ꢃEMP (J6): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
DIFFOUꢃ (F8): Internal Remote Sense Amplifier Output.
Connect this pin to V
or V
depending on which
OUTS1
OUTS2
output is using remote sense. In parallel operation con-
EXꢃV (J7): External power input that is enabled through
CC
nect one of the V
pin to DIFFOUT for remote sensing.
Diffamp can be used for ≤3.3V outputs.
OUTS
a switch to INTV whenever EXTV is greater than 4.7V.
CC
CC
Do not exceed 6V on this input, and connect this pin to
V when operating V on 5V. An efficiency increase will
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, or otherwise leave floating. See the Applications
Information section.
IN
IN
occur that is a function of the (V – INTV ) multiplied
IN
CC
by power MOSFET driver current. Typical current require-
ment is 30mA. V must be applied before EXTV , and
IN
CC
EXTV must be removed before V . A 5V output can be
CC
IN
tied to this pin to increase efficiency. See Applications
PHASMD(G4):ConnectthispintoSGND,INTV ,orfloat-
CC
Information section.
ing this pin to select the phase of CLKOUT to 60 degrees,
120 degrees, and 90 degrees respectively.
V (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
IN
Power Input Pins. Apply input voltage between these pins
CLKOUꢃ (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
and GND pins. Recommend placing input decoupling
capacitance directly between V pins and GND pins.
IN
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within 7.5% of
the regulation point.
4620af
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For more information www.linear.com/4620A
LTM4620A
siMpliFieD block DiagraM
PGOOD1
TRACK1
V
IN
SS
CAP
C
22µF
25V
C
22µF
25V
IN1
IN2
1µF
GND
R
T
V
R
TEMP
CLKOUT
RUN1
IN
= 100µA
V
IN
MTOP1
MBOT1
T
SW1
V
0.56µH
OUT1
V
OUT1
1.5V/13A
+
MODE_PLLIN
PHASEMD
2.2µF
C
OUT1
GND
V
OUTS1
COMP1
60.4k
V
FB1
INTERNAL
COMP
R
FB1
40.2k
SGND
POWER
CONTROL
PGOOD2
TRACK2
V
IN
INTV
SS
CAP
CC
C
22µF
25V
C
22µF
25V
IN3
IN4
1µF
4.7µF
EXTV
GND
SW2
CC
MTOP2
MBOT2
0.56µH
V
OUT2
V
OUT2
1.2V/13A
+
RUN2
2.2µF
C
OUT2
GND
V
OUTS2
60.4k
COMP2
V
FB2
+
–
R
FB2
INTERNAL
COMP
60.4k
f
SET
INTERNAL
FILTER
R
FSET
SGND
DIFFOUT
DIFFN
DIFFP
4620A F01
Figure 1. Siꢂplified LꢃM4620A Block Diagraꢂ
ꢃA = 25°C. Use Figure 1 configuration.
CONDIꢃIONS
Decoupling requireMenTs
SYMBOL
PARAMEꢃER
MIN
ꢃYP
MAX
UNIꢃS
External Input Capacitor Requirement
C
C
C
(V = 4.75V to 16V, V
= 1.5V)
= 1.2V)
I
I
= 13A
= 13A (Note 8)
22
22
µF
µF
IN1, IN2
IN1
OUT1
OUT2
OUT1
OUT2
C
(V = 4.75V to 16V, V
IN3, IN4
IN2
External Output Capacitor Requirement
C
OUT1
C
OUT2
(V = 4.75V to 16V, V
= 1.5V)
= 1.2V)
I
I
= 13A
= 13A (Note 8)
300
300
µF
µF
IN1
OUT1
OUT2
OUT1
OUT2
(V = 4.75V to 16V, V
IN2
4620af
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LTM4620A
operaTion
Power Module Description
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
The LTM4620A is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
13A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
TheLTM4620Aisinternallycompensatedtobestableover
all operating conditions. Table 5 provides a guide line for
input and output capacitances for several operating con-
ditions. The Linear Technology µModule Power Design
Tool will be provided for transient and stability analysis.
resistors from 0.6V to 5.3V over 4.5V to 16V input
DC
DC
voltages. The typical application schematic is shown in
Figure 26. See Note 8 in the Electrical Characteristics
section for output current guideline.
The V pin is used to program the output voltage with a
FB
single external resistor to ground. A differential remote
sense amplifier is available for sensing the output voltage
accuratelyononeoftheoutputsattheloadpoint, orinpar-
alleloperationsensingtheoutputvoltageattheloadpoint.
TheLTM4620Ahasdualintegratedconstant-frequencycur-
rent mode regulators and built-in power MOSFET devices
withfastswitchingspeed. Thetypicalswitchingfrequency
is 500kHz. For switching-noise sensitive applications, it
can be externally synchronized from 400kHz to 780kHz.
A resistor can be used to program a free run frequency
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12
phases can be cascaded to run simultaneously with re-
spect to each other by programming the PHMODE pin to
different levels. See the Applications Information section.
on the f pin. See the Applications Information section.
SET
With current mode control and internal feedback loop
compensation, the LTM4620A module has sufficient
stability margins and good transient performance with
a wide range of output capacitors, even with all ceramic
output capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping opera-
tion using the MODE pin. These light load features will
accommodate battery operation. Efficiency graphs are
providedforlightloadoperationintheTypicalPerformance
Characteristics section. See the Applications Information
section for details.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limitandfoldbackcurrentlimitinanovercurrentcondition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltage exits a 10% window around the regulation point.
As the output voltage exceeds 10% above regulation, the
bottom MOSFET will turn on to clamp the output voltage.
ThetopMOSFETwillbeturnedoff.Thisovervoltageprotect
is feedback voltage referred.
Atemperaturediodeisincludedinsidethemoduletomoni-
tor the temperature of the module. See the Applications
Information section for details.
Theswitchingnodepinsareavailableforfunctionalopera-
tion monitoring and a resistor-capacitor snubber circuit
can be careful placed on the switching node pin to ground
to dampen any high frequency ringing on the transition
edges.SeetheApplicationsInformationsectionfordetails.
Pulling the RUN pins below 1.1V forces the regulators into
ashutdownstate,byturningoffbothMOSFETs.TheTRACK
pinsareusedforprogrammingtheoutputvoltagerampand
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LTM4620A
applicaTions inForMaTion
The typical LTM4620A application circuit is shown in
Figure 26. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 5 for specific external capacitor
requirements for particular applications.
resistors to the output. All of the V pins tie together with
FB
one programming resistor as shown in Figure 2.
Inparalleloperation,theV pinshaveanI currentof20nA
FB
FB
maximumeachchannel.To reduceoutputvoltageerrordue
to this current, an additional V
pin can be tied to V
,
OUTS
OUT
andanadditionalR resistorcanbeusedtolowerthetotal
FB
V to V
Step-Down Ratios
IN
OUꢃ
Thevenin equivalent resistance seen by this current. For
exampleinFigure2,thetotalTheveninequivalentresistance
There are restrictions in the maximum V and V
step-
IN
OUT
down ratio that can be achieved for a given input voltage.
EachoutputoftheLTM4620Aiscapableof95%dutycycle
of the V pin is (60.4k//R ), which is 30.2k where R is
FB
FB
FB
equal to 60.4k for a 1.2V output. Four phases connected
in parallel equates to a worse case feedback current of
at 500kHz, but the V to V
minimum dropout is still
IN
OUT
shown as a function of its load current and will limit output
current capability related to high duty cycle on the top side
4 • I = 80nA maximum. The voltage error is 80nA • 30.2k
FB
= 2.4mV. If V
is connected, as shown in Figure 2, to
OUTS2
switch.Minimumon-timet
isanotherconsideration
V
, and another 60.4k resistor is connected from V
OUT
ON(MIN)
FB2
in operating at a specified duty cycle while operating at
a certain frequency due to the fact that t < D/f
to ground, then the voltage error is reduced to 1.2mV. If
the voltage error is acceptable then no additional connec-
tions are necessary. The onboard 60.4k resistor is 0.5%
,
SW
ON(MIN)
where D is duty cycle and f is the switching frequency.
SW
t
is specified in the electrical parameters as 90ns.
See Note 8 in the Electrical Characteristics section for
accurate and the V resistor can be chosen by the user to
ON(MIN)
FB
be as accurate as needed. All COMP pins are tied together
for current sharing between the phases. The TRACK pins
can be tied together and a single soft-start capacitor can
be used to soft-start the regulator. The soft-start equation
willneedtohavethesoft-startcurrentparameterincreased
by the number of paralleled channels. See TRACK/Soft-
Start Pin section.
output current guideline.
Output Voltage Prograꢂꢂing
ThePWM controllerhasaninternal0.6Vreferencevoltage.
AsshownintheBlockDiagram,a60.4kΩinternalfeedback
resistor connects between the V
to V and V
OUTS1
FB1 OUTS2
to V . It is very important that these pins be connected
FB2
4 PARALLELED OUTPUTS
FOR 1.2V AT 50A
LTM4620A
V
V
COMP1
COMP2
OUT1
OUT2
to their respective outputs for proper feedback regulation.
OvervoltagecanoccuriftheseV
andV
pinsare
OUTS1
OUTS2
60.4k
V
OUTS1
OUTS2
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
either V or V . Adding a resistor R from V pin to
V
OPTIONAL CONNECTION
V
FB1
60.4k
TRACK1
TRACK2
FB1
FB2
FB
FB
V
FB2
GND programs the output voltage:
OPTIONAL
60.4k + RFB
VOUT = 0.6V •
RFB
R
FB
60.4k
LTM4620A
60.4k
V
COMP1
COMP2
OUT1
OUT2
V
USE TO LOWER
V
V
ꢃable 1. VFB Resistor ꢃable vs Various Output Voltages
0.6V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V
Open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k
OUTS1
OUTS2
TOTAL EQUIVALENT
RESISTANCE TO LOWER
V
5V
OUꢃ
I
FB
VOLTAGE ERROR
V
FB1
R
FB
60.4k
TRACK1
TRACK2
For parallel operation of multiple channels the same feed-
back setting resistor can be used for the parallel design.
V
FB2
0.1µF
R
FB
4620A F02
60.4k
This is done by connecting the V
to the output as
OUTS1
shown in Figure 2, thus tying one of the internal 60.4k
Figure 2. 4-Phase Parallel Configurations
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LTM4620A
applicaTions inForMaTion
Input Capacitors
Output Capacitors
The LTM4620A module should be connected to a low ac-
impedance DC source. For the regulator input four 22µF
input ceramic capacitors are used for RMS ripple current.
A47µFto100µFsurfacemountaluminumelectrolyticbulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedanceiscompromisedbylonginductiveleads,traces
ornotenoughsourcecapacitance.Iflowimpedancepower
planes are used, then this bulk capacitor is not needed.
The LTM4620A is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as C
are chosen with low enough
OUT
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
OUT
ESR tantalum capacitor, the low ESR polymer capacitor
orceramiccapacitor.Thetypicaloutputcapacitancerange
for each output is from 200µF to 470µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes
is required. Table 5 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 7A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
tooptimizethetransientperformance.Stabilitycriteriaare
consideredintheTable5matrix,andtheLinearTechnology
µModule Power Design Tool will be provided for stability
analysis.Multiphaseoperationwillreduceeffectiveoutput
ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output
ripple current cancellation, but the output capacitance
should be considered carefully as a function of stability
and transient response. The Linear Technology µModule
Power Design Tool can calculate the output ripple reduc-
tion as the number of implemented phases increases by
N times. A small value 10Ω to 50Ω resistor can be place
For a buck converter, the switching duty-cycle can be
estimated as:
VOUT
D =
V
IN
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
IOUT(MAX)
ICIN(RMS)
=
• D • 1− D
(
)
η%
In the above equation, η% is the estimated efficiency of
the power module. The bulk capacitor can be a switcher-
rated electrolytic aluminum capacitor, Polymer capacitor.
in series from V
to the V
pin to allow for a bode
OUT
OUTS
plot analyzer to inject a signal into the control loop and
validate the regulator stability. The same resistor could
be place in series from V
to DIFFP and a bode plot
OUT
analyzer could inject a signal into the control loop and
validate the regulator stability.
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LTM4620A
applicaTions inForMaTion
Burst Mode Operation
Forced Continuous Operation
The LTM4620A is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate in-
termittently based on load demand, thus saving quiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
should be applied. Burst Mode operation is enabled with
the MODE/PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal opera-
tion even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
BURST comparator trips, causing the internal sleep line
to go high and turn off both power MOSFETs.
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
outputrippleisdesired,forcedcontinuousoperationshould
be used. Forced continuous operation can be enabled by
tying the MODE/PLLIN pin to GND. In this mode, induc-
tor current is allowed to reverse during low output loads,
the COMP voltage is in control of the current comparator
thresholdthroughout,andthetopMOSFETalwaysturnson
witheachoscillatorpulse.Duringstart-up,forcedcontinu-
ous mode is disabled and inductor current is prevented
from reversing until the LTM4620A’s output voltage is in
regulation. Either regulator can be configured for force
continuous mode.
Multiphase Operation
For output loads that demand more than 13A of current,
two outputs in LTM4620A or even multiple LTM4620As
can be paralleled to run out of phase to provide more
output current without increasing input and output volt-
age ripples. The MODE/PLLIN pin allows the LTM4620A
to synchronize to an external clock (between 400kHz and
780kHz) and the internal phase-locked-loop allows the
LTM4620A to lock onto an incoming clock phase as well.
The CLKOUT signal can be connected to the MODE/PLLIN
pin of the following stage to line up both the frequency
and the phase of the entire system. Tying the PHMODE
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
outpu2t2. The load current is now being supplied from the
output capacitors. When the output voltage drops, caus-
ing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4620A resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
Pulse-Skipping Mode Operation
pin to INTV , SGND, or (floating) generates a phase
CC
In applications where low output ripple and high effi-
ciencyatintermediatecurrentsaredesired,pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4620A to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
difference (between MODE/PLLIN and CLKOUT) of 120
degrees, 60 degrees, or 90 degrees respectively. A total
of 12 phases can be cascaded to run simultaneously with
respect to each other by programming the PHMODE pin
of each LTM4620A channel to different levels. Figure 3
shows a 2-phase design, 4-phase design and a 6-phase
design example for clock phasing with the PHASMD table.
the MODE/PLLIN pin to INTV enables pulse-skipping
CC
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFETtostayoffforseveralcycles,thusskippingcycles.
The inductor current does not reverse in this mode. This
modewillmaintainhighereffectivefrequenciesthuslower
output ripple and lower noise than Burst Mode operation.
Eitherregulatorcanbeconfiguredforpulse-skippingmode.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
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LTM4620A
applicaTions inForMaTion
2-PHASE DESIGN
PHASMD SGND FLOAT INTV
CC
FLOAT
CONTROLLER1
CONTROLLER2
CLKOUT
0
0
0
CLKOUT
180
60
180
90
240
120
MODE_PLLIN
0 PHASE
180 PHASE
V
OUT1
V
OUT2
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
CLKOUT
MODE_PLLIN
MODE_PLLIN
0 PHASE
FLOAT
180 PHASE
90 PHASE
270 PHASE
V
V
V
OUT1
V
OUT2
OUT1
OUT2
FLOAT
PHASMD
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
MODE_PLLIN
CLKOUT
CLKOUT
MODE_PLLIN
MODE_PLLIN
0 PHASE
SGND
180 PHASE
60 PHASE
SGND
240 PHASE
120 PHASE
FLOAT
300 PHASE
V
OUT1
V
V
V
V
OUT1
V
OUT2
OUT2
OUT1
OUT2
PHASMD
PHASMD
PHASMD
4620A F03
Figure 3. Eꢁaꢂples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD ꢃable
The LTM4620A device is an inherently current mode
controlled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 26 shows an example of parallel operation
and pin connection.
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used when all of the outputs are tied together
to achieve a single high output current design.
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LTM4620A
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Input RMS Ripple Current Cancellation
Frequency Selection and Phase-Lock Loop
(MODE/PLLIN and f Pins)
SEꢃ
Application Note 77 provides a detailed explanation of
multiphaseoperation.TheinputRMSripplecurrentcancel-
lationmathematicalderivationsarepresented,andagraph
isdisplayedrepresentingtheRMSripplecurrentreduction
asafunctionofthenumberofinterleavedphases. Figure4
shows this graph.
TheLTM4620Adeviceisoperatedoverarangeoffrequen-
cies to improve power conversion efficiency. It is recom-
mended to operate the lower output voltages or lower
duty cycle conversions at lower frequencies to improve
efficiency by lowering power MOSFET switching losses.
Higher output voltages or higher duty cycle conversions
can be operated at higher frequencies to limit inductor
ripplecurrent.Theefficiencygraphswillshowanoperating
frequency chosen for that condition. Select frequency in
reference to the highest output voltage.
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
OUT IN
4620A F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
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Miniꢂuꢂ On-ꢃiꢂe
900
800
700
600
500
400
300
200
100
0
Minimum on-time t is the smallest time duration that
ON
theLTM4620AiscapableofturningonthetopMOSFETon
either channel. It is determined by internal timing delays,
and the gate charge required turning on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
VOUT
> tON(MIN)
V •FREQ
IN
0
0.5
1
1.5
2
2.5
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple will increase. The on-time can be
increased by lowering the switching frequency. A good
rule of thumb is to keep on-time longer than 110ns.
f
PIN VOLTAGE (V)
SET
4620A F05
Figure 5. Operating Frequency vs fSEꢃ Pin Voltage
TheLTM4620Aswitchingfrequencycanbesetwithanex-
ternalresistorfromthef pintoSGND.Anaccurate10µA
SET
current source into the resistor will set a voltage that pro-
gramsthefrequencyoraDCvoltagecanbeapplied.Figure5
shows a graph of frequency setting verses programming
voltage. An external clock can be applied to the MODE/
Output Voltage ꢃracking
Output voltage tracking can be programmed externally
using the TRACK pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4620A uses
an accurate 60.4k resistor internally for the top feedback
resistor for each channel. Figure 6 shows an example of
coincident tracking. Equations:
PLLIN pin from 0V to INTV over a frequency range of
CC
400kHz to 780kHz. The clock input high threshold is 1.6V
andtheclockinputlowthresholdis1V.TheLTM4620Ahas
the PLL loop filter components on board. The frequency
setting resistor should always be present to set the initial
switching frequency before locking to an external clock.
Both regulators will operate in continuous mode while
being externally clock.
⎛
⎞
⎟
⎠
60.4k
RTA
The output of the PLL phase detector has a pair of comple-
mentary current sources that charge and discharge the
internal filter network. When the external clock is applied
SLAVE = 1+
• V
TRACK
⎜
⎝
V
TRACK
V
TRACK
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
then the f
frequency resistor is disconnected with
SET
an internal switch, and the current sources control the
frequency adjustment to lock to the incoming external
clock. When no external clock is applied, then the internal
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
switch is on, thus connecting the external f frequency
set resistor for free run operation.
SET
tracking is disabled when V
is more than 0.6V. R
TRACK
TA
in Figure 6 will be equal to the R for coincident tracking.
FB
Figure 7 shows the coincident tracking waveforms.
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INTV
INTV
CC
CC
C10
4.7µF
R2
10k
PGOOD
MASTER
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
7V TO 16V INTERMEDIATE BUS
V
OUT1
V
V
IN
V
IN
OUT1
1.5V AT 13A
C4
22µF
25V
C3
C2
22µF
25V
C1
22µF
25V
C6
100µF
6.3V
C8
470µF
6.3V
R6
100k
R1*
10k
TEMP
V
OUTS1
SW1
22µF
25V
RUN1
RUN2
V
V
FB1
FB2
TRACK1
D1*
5.1V ZENER
LTM4620A
R
FB
TRACK2
40.2k
COMP1
COMP2
60.4k
C
R
R
SS
TA
TB
f
SET
0.1µF
60.4k
60.4k
PHASMD
V
OUTS2
SLAVE
V
OUT2
V
OUT2
SW2
V
OUT1
1.5V
1.2V AT 13A
C5
C7
470µF
6.3V
R4
121k
PGOOD
100µF
6.3V
PGOOD2
DIFFN DIFFOUT
INTV
SGND
GND
DIFFP
CC
R9
10k
RAMP TIME
SOFTSTART
t
= (C /1.3µA) • 0.6
SS
* PULL-UP RESISTOR AND ZENER ARE OPTIONAL
4620A F06
Figure 6. Eꢁaꢂple of Output ꢃracking Application Circuit
MASTER OUTPUT
SLAVE OUTPUT
TIME
4620A F07
Figure 7. Output Coincident ꢃracking Waveforꢂ
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The TRACK pin can be controlled by a capacitor placed on
theregulatorTRACKpintoground.A1.3µAcurrentsource
will charge the TRACK pin up to the reference voltage
rate or coincident tracking, then R is equal to R with
TA FB
V
= V
. Therefore R = 60.4k, and R = 60.4k in
FB
TRACK TB TA
Figure 6.
and then proceed up to INTV . After the 0.6V ramp, the
CC
Inratiometrictracking, adifferentslewratemaybedesired
TRACK pin will no longer be in control, and the internal
voltage reference will control output regulation from the
feedback divider. Foldback current limit is disabled during
this sequence of turn-on during tracking or soft-starting.
The TRACK pins are pulled low when the RUN pin is below
1.2V. The total soft-start time can be calculated as:
for the slave regulator. R can be solved for when SR
TB
is slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
R
TB
= 76.8k. Solve for R to equal to 49.9k.
TA
⎛
⎞
CSS
1.3µA
tSOFT-START
=
• 0.6
⎜
⎟
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
⎝
⎠
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator channels will always start in pulse-skipping
mode up to TRACK = 0.5V. Between TRACK = 0.5V and
0.54V, itwilloperateinforcedcontinuousmodeandrevert
to the selected mode once TRACK > 0.54V. In order to
track with another channel once in steady state operation,
the LTM4620A is forced into continuous mode operation
Power Good
as soon as V is below 0.54V regardless of the setting
FB
on the MODE/PLLIN pin.
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A resistor
can be pulled up to a particular supply voltage no greater
than 6V maximum for monitoring.
Ratiometric tracking can be achieved by a few simple cal-
culations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
Stability Coꢂpensation
The module has already been internally compensated
for all output voltages. Table 5 is provided for most ap-
plication requirements. The Linear Technology µModule
Power Design Tool will be provided for other control loop
optimization.
MR
SR
• 60.4k = RTB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal the 60.4k. R is derived from equation:
TB
Run Enable
TA
TheRUNpinshaveanenablethresholdof1.4Vmaximum,
typically1.25Vwith150mVofhysteresis. Theycontrolthe
0.6V
RTA
=
VTRACK
RTB
V
V
FB
FB
+
−
turnoneachofthechannelsandINTV .Thesepinscanbe
CC
60.4k RFB
pulleduptoV for5Voperation,ora5VZenerdiodecanbe
IN
placedonthepinsanda10kto100kresistorcanbeplaced
up to higher than 5V input for enabling the channels. The
RUN pins can also be used for output voltage sequencing.
In parallel operation the RUN pins can be tie together and
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.6V. Since R is equal to the 60.4k
TRACK
TB
top feedback resistor of the slave regulator in equal slew
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controlled from a single control. See the Typical Applica-
tion circuits in Figure 26.
switched current paths. Usually a series R-C combina-
tion is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usuallyeasiertopredict.Itcombinesthepowerpathboard
inductance in combination with the MOSFET interconnect
bond wire inductance.
INꢃV and EXꢃV
CC
CC
The LTM4620A module has an internal 5V low dropout
regulator that is derived from the input voltage. This regu-
lator is used to power the control circuitry and the power
MOSFET drivers. This regulator can source up to 70mA,
and typically uses ~30mA for powering the device at the
maximum frequency. This internal 5V supply is enabled
by either RUN1 or RUN2.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
EXTV allows an external 5V supply to power the
CC
LTM4620Aandreducepowerdissipationfromtheinternal
low dropout 5V regulator. The power loss savings can be
calculated by:
Z(L) = 2πfL,
(V – 5V) • 30mA = PLOSS
IN
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
itsimpedanceisequaltotheresistorattheringfrequency.
Calculated by: Z(C) = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
EXTV has a threshold of 4.7V for activation, and a maxi-
CC
mum rating of 6V. When using a 5V input, connect this
5V input to EXTV also to maintain a 5V gate drive level.
CC
EXTV must sequence on after V , and EXTV must
CC
IN
CC
sequence off before V . When designing a 5V output,
IN
connect this 5V output to EXTV . Use an external 5V bias
CC
on EXTV to improve efficiency.
CC
Differential Reꢂote Sense Aꢂplifier
ꢃeꢂperature Monitoring
Anaccuratedifferentialremotesenseamplifierisprovided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
Measuring the absolute temperature of a diode is pos-
sible due to the relationship between current, voltage
and temperature described by the classic diode equation:
⎛
⎜
⎝
⎞
⎟
⎠
VD
η• V
I =I • e
D
S
and DIFFOUT is connected to either V
or V
.
OUTS1
OUTS2
T
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
or
one of the V
pins. Review the parallel schematics in
I
OUTS
VD = η• VT •ln D
Figure 29 and review Figure 2. The diffamp can only be
used for output voltage ≤3.3V.
where I is the diode current, V is the diode voltage, η
D
D
is the ideality factor (typically close to 1.0) and I (satura-
SW Pins
S
tion current) is a process dependent parameter. V can
T
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
be broken out to:
k • T
q
VT =
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where T is the diode junction temperature in Kelvin, q is
To obtain a linear voltage proportional to temperature
the electron charge and k is Boltzmann’s constant. V is
we cancel the I variable in the natural logarithm term to
T
S
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
temperature relationship that makes diodes suitable
remove the I dependency from the following equation.
S
This is accomplished by measuring the diode voltage at
two currents I , and I , where I = 10 • I ),
1
2
1
2
temperature sensors. The I term in the equation above
S
Subtracting we get:
is the extrapolated current through a diode junction when
I1
IS
I2
IS
the diode has zero volts across the terminals. The I term
S
ΔVD = T(KELVIN) •KD • ln − T(KELVIN) •KD • ln
varies from process to process, varies with temperature,
and by definition must always be less than I . Combining
D
Combining like terms, then simplifying the natural log
terms yields:
all of the constants into one term:
η • k
q
KD =
ΔVD = T(KELVIN) •KD • ln(10)
and redefining constant
−5
where K = 8.62 , and knowing ln(I /I ) is always posi-
D
D S
K' = K • In(10) = 198µV/K
D
D
tive because I is always greater than I , leaves us with
the equation that:
D
S
yields
I
IS
ΔVD = K'D • T(KELVIN)
VD = T(KELVIN) •KD • ln D
Solving for temperature:
ΔVD
K'D
where V appears to increase with temperature. It is com-
D
T(KELVIN) =
,
mon knowledge that a silicon diode biased with a current
source has an approximately –2mV/°C temperature rela-
tionship (Figure 8), which is at odds with the equation. In
T(KELVIN) = [°C]+ 273.15,
[°C]= T(KELVIN)− 273.15
means that is we take the difference in voltage across the
diode measured at two currents with a ratio of 10, the
resulting voltage is 198µV per Kelvin of the junction with
a zero intercept at 0 Kelvin.
fact, the I term increases with temperature, reducing the
S
ln(I /I )absolutevalueyieldinganapproximately–2mV/°C
D S
composite diode voltage slope.
1.0
I
I
= 100µA
= 10µA
D
D
The diode connected PNP transistor can be pulled up to
V
with a resistor to set the current to 100µA for using
IN
0.8
this diode connected transistor as a general temperature
monitor by monitoring the diode voltage drop with tem-
perature, or a specific temperature monitor can be used
that injects two currents that are at a 10:1 ratio for very
accurate temperature monitoring. See Figure 24 for an
example.
∆V
D
0.6
0.4
–173
–73
27
127
TEMPERATURE (°C)
4620A F08
Figure 8. Diode Voltage VD vs ꢃeꢂperature
ꢃ(°C) for Different Bias Currents
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ꢃherꢂal Considerations and Output Current Derating
1. θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure.Thisenvironmentissometimesreferredtoas“still
air”althoughnaturalconvectioncausestheairtomove.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModulepackagemountedtoahardwaretestboard—also
defined by JESD51-9 (“Test Boards for Area Array Surface
MountPackageThermalMeasurements”).Themotivation
for providing these thermal coefficients in found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical µModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coef-
ficients are quoted or paraphrased below:
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4620A F10
µMODULE DEVICE
Figure 9. Graphical Representation of JESD51-12 ꢃherꢂal Coefficients
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4. θ , the thermal resistance from junction to the printed
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9topredictpowerlossheatflowandtemperature
readingsatdifferentinterfacesthatenablethecalculationof
theJEDEC-definedthermalresistancevalues;(3)themodel
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamberwhileoperatingthedeviceatthesamepowerloss
as that which was simulated. An outcome of this process
and due-diligence yields a set of derating curves provided
in other sections of this data sheet. After these laboratory
test have been performed and correlated to the µModule
model, then the θ and θ are summed together to cor-
JB
circuitboard,isthejunction-to-boardthermalresistance
wherealmostalloftheheatflowsthroughthebottomof
the µModule and into the board, and is really the sum of
the θ
and the thermal resistance of the bottom
JCbottom
of the part through the solder joints and through a por-
tion of the board. The board temperature is measured a
specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 9; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operatingconditionsofaµModule.Forexample,innormal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sivelythroughthetoporexclusivelythroughbottomofthe
µModule—asthestandarddefinesforθ
andθ
,
JCtop
JCbottom
respectively.Inpractice,powerlossisthermallydissipated
inbothdirectionsawayfromthepackage—granted, inthe
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
JB
BA
relatequitewellwiththeµModulemodelwithnoairflowor
heat sinking in a properly define chamber. This θ + θ
JB
BA
valueisshowninthePinConfigurationsectionandshould
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
accurately equal the θ value because approximately
JA
100% of power loss flows from the junction through the
board into ambient with no airflow or top mounted heat
sink. Each system has its own thermal characteristics,
therefore thermal analysis must be performed by the user
in a particular system.
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The LTM4620A module has been designed to effectively
remove heat from both the top and bottom of the pack-
age. The bottom substrate material has very low thermal
resistance to the printed circuit board and the exposed
top metal is thermally connected to the power devices
and the power inductors. An external heat sink can be
applied to the top of the device for excellent heat sinking
with airflow. Basically all power dissipating devices are
mounted directly to the substrate and the top exposed
metal. This provides two low thermal resistance paths to
remove heat.
Figure 10 shows a temperature plot of the LTM4620A
with BGA heat sink and 200LFM airflow with ~5.3W of
internal dissipation.
Figure 10. LꢃM4620A 12V to 1.2V at 26A with 200LFM Air Flow
Figure 11 shows a temperature plot of the LTM4620A with
no heat sink and 200LFM airflow with ~6.5W of internal
dissipation.
These plots equate to a paralleled 1.2V at 26A design, and
a 5V at 25A design operating from a 12V input.
Safety Considerations
The LTM4620A modules do not provide isolation from V
IN
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
tobeprovidedtoprotecteachunitfromcatastrophicfailure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internaltopMOSFETfault. IftheinternaltopMOSFETfails,
then turning it off will not resolve the overvoltage, thus
the internalbottomMOSFET willturnon indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can
be used as a secondary fault protector in this situation.
Figure 11. LꢃM4620A 12V to 5V at 25A with 200LFM Air Flow
Thedevicedoessupportovercurrentprotection.Atempera-
turediodeisprovidedformonitoringinternaltemperature,
and can be used to detect the need for thermal shutdown
that can be done by controlling the RUN pin.
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Power Derating
Figure15,theloadcurrentisderatedto~19Aat~80°Cwith
no air or heat sink and the power loss for the 12V to 1.0V
at 19A output is a ~5.1W loss. The 5.1W loss is calculated
with the ~3.75W room temperature loss from the 12V to
1.0V power loss curve at 19A, and the 1.35 multiplying
factor at 125°C ambient. If the 80°C ambient temperature
is subtracted from the 120°C junction temperature, then
The 1V, 2.5V and 5V power loss curves in Figures 12 to 14
can be used in coordination with the load current derating
curves in Figures 15 to 24 for calculating an approximate
Θ thermalresistancefortheLTM4620Awithvariousheat
JA
sinking and airflow conditions. The power loss curves are
taken at room temperature, and are increased with a 1.35
to 1.4 multiplicative factor at 125°C. These factors come
from thefact thatthe powerlossoftheregulator increases
about 45% from 25°C to 150°C, thus a 45% spread over
125°C delta equates to ~0.35%/°C loss increase. A 125°C
maximumjunctionminus25°Croomtemperatureequates
to a 100°C increase. This 100°C increase multiplied by
0.35%/°C equals a 35% power loss increase at the 125°C
junction, thus the 1.35 multiplier.
the difference of 40°C divided 5.1W equals a 7.8°C/W Θ
JA
thermal resistance. Table 2 specifies a 6.5 to 7°C/W value
whichisprettyclose.Theairflowgraphsaremoreaccurate
duetothefactthattheambienttemperatureenvironmentis
controlled better with airflow. As an example in Figure 16,
the load current is derated to ~22A at ~90°C with 200LFM
of airflow and the power loss for the 12V to 1.0V at 22A
output is a ~5.94W loss.
The 5.94W loss is calculated with the ~4.4W room tem-
perature loss from the 12V to 1.0V power loss curve at
22A, and the 1.35 multiplying factor at 125°C ambient. If
the90°Cambienttemperatureissubtractedfromthe120°C
junction temperature, then the difference of 30°C divided
The derating curves are plotted with CH1 and CH2 in
parallel single output operation starting at 26A of load
with low ambient temperature. The output voltages are
1V, 2.5V and 5V. These are chosen to include the lower
and higher output voltage ranges for correlating the ther-
mal resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis.
5.94W equals a 5.1°C/W Θ thermal resistance. Table 2
JA
specifies a 5.5°C/W value which is pretty close. Tables 2-4
provide equivalent thermal resistances for 1.0V, 2.5V and
5V outputs with and without airflow and heat sinking.
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
ThederivedthermalresistancesinTables2-4forthevarious
conditions can be multiplied by the calculated power loss
asafunctionofambienttemperaturetoderivetemperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the
efficiency curves and adjusted with the above ambient
temperaturemultiplicativefactors.Theprintedcircuitboard
is a 1.6mm thick four layer board with two ounce copper
for the two outer layers and one ounce copper for the two
inner layers. The PCB dimensions are 101mm × 114mm.
The BGA heat sinks are listed below Table 4.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
4620af
24
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
ꢃable 2. 1.0V Output
DERAꢃING CURVE
Figures 15, 16
Figures 15, 16
Figures 15, 16
Figures 17, 18
Figures 17, 18
Figures 17, 18
V
(V)
POWER LOSS CURVE
Figure 12
AIRFLOW (LFM)
HEAꢃ SINK
None
Θ
(°C/W)
JA
IN
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
6.5 to 7
Figure 12
200
400
0
None
5.5
5
Figure 12
None
Figure 12
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
6.5
5
Figure 12
200
400
Figure 12
4
ꢃable 3. 2.5V Output
DERAꢃING CURVE
Figures 19, 20
V
(V)
POWER LOSS CURVE
Figure 13
AIRFLOW (LFM)
HEAꢃ SINK
None
Θ
(°C/W)
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
6.5 to 7
Figures 19, 20
Figure 13
200
400
0
None
5.5 to 6
4.5
Figures 19, 20
Figure 13
None
Figures 21, 22
Figure 13
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
6.5 to 7
4
Figures 21, 22
Figure 13
200
400
Figures 21, 22
Figure 13
3.5
ꢃable 4. 5V Output
DERAꢃING CURVE
Figure 23
V
(V)
POWER LOSS CURVE
Figure 14
AIRFLOW (LFM)
HEAꢃ SINK
None
Θ
(°C/W)
IN
JA
12
0
6.5 to 7
Figure 23
12
12
12
12
12
Figure 14
200
400
0
None
5.5 to 6
4.5
Figure 23
Figure 14
None
Figure 24
Figure 14
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
6.5 to 7
4
Figure 24
Figure 14
200
400
Figure 24
Figure 14
3.5
Connect 5V output to EXTV to increase efficiency.
CC
HEAꢃ SINK MANUFACꢃURER
PARꢃ NUMBER
WEBSIꢃE
Aavid Thermalloy
Cool Innovations
375424B00034G
www.aavid.com
4-050503P
4-050508P
www.coolinnovations.com
4620af
25
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
ꢃable 5. Output Voltage Response vs Coꢂponent Matriꢁ (Refer to Figure 23) 0A to 7A Load Step ꢃypical Measured Values
VENDORS
VALUE
PARꢃ NUMBER
C4532X5R0J107MZ
GRM32ER60J107M
18126D107MAT
2R5TPD470M5
6TPD470M
ESR
~1mΩ
~1mΩ
~1mΩ
9mΩ
TDK, C
Ceramic
100µF 6.3V
100µF 6.3V
100µF 6.3V
470µF 2R5
470µF 6.3V
56µF 25V
OUT1
Murata, C
Ceramic
OUT1
AVX, C
Ceramic
OUT1
Sanyo POSCAP, C
Sanyo POSCAP, C
Bulk
Bulk
OUT2
OUT2
9mΩ
Sanyo, C Bulk
25SVP56M
IN
Sanyo, POSCAP C
Sanyo, POSCAP C
Sanyo, POSCAP C
Bulk
Bulk
Bulk
100µF 6.3V
220µF 2.5V
220µF 6V
67PE100MI
15mΩ to 18mΩ
OUT2
OUT2
OUT2
2R5TPE220M9
6TPF220ML
P-P
DEVIAꢃION RECOVERY LOAD
V
C
C
C
C
C
C
C
V
DROOP Aꢃ 6A LOAD
(ꢂV)
24
ꢃIME
(µs)
SꢃEP
R
FB
OUꢃ
IN
IN
OUꢃ1
OUꢃ2
FF
BOꢃ
COMP
IN
(V) (CERAMIC) (BULK)** (CERAMIC) (BULK)
(pF)
(pF)
(pF)
None
None
None
None
(V)
SꢃEP (ꢂV)
46
(A/µs) (kΩ) FREQ
1
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
56µF
100µF
100µF
470µF × 2 None None
5
30
30
23
23
25
25
40
40
20
20
20
18
20
20
30
20
25
20
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
90.9 400
90.9 400
90.9 400
60.4 500
60.4 500
60.4 500
40.2 550
40.2 550
40.2 500
30.2 600
30.2 600
30.2 600
19.1 650
19.1 650
13.3 700
13.3 700
8.25 750
8.25 750
1
470µF × 2 150
None
None
None
12
12
12
5
24
46
1
100µF × 3
100µF × 3
100µF
470µF
470µF
100
100
33
63
1.2
1.2
1.2
1.5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
3.3
3.3
5
35
70
470µF × 2 150
470µF × 2 150
470µF × 2 220
470µF × 2 220
24
46
100µF
12
5
24
46
100µF
None
26
52
100µF
12
12
12
5
26
52
100µF
220µF
220µF
220µF
None
47
33
64
120
120
120
160
120
120
240
240
382
360
100µF
61
100µF
33
61
100µF × 3
100µF × 3
100µF × 3
100µF
100
150
150
33
12
12
12
12
12
12
12
80
None
None
None
47
47
60
None
60
100µF
118
120
188
180
100µF × 2
100µF
100
47
5
100µF
**Bulk capacitance is optional if V has very low input impedance.
IN
4620af
26
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
12V TO 2.5V POWER LOSS CURVE
5V TO 2.5V POWER LOSS CURVE
12V TO 1V POWER LOSS CURVE
5V TO 1V POWER LOSS CURVE
12V TO 5V POWER LOSS CURVE
2
3
5
6
8
9 10 12 13 15 16 17 19 20 22 23 24 26
LOAD CURRENT (A)
4620A F12
2
3
5
6
8
9 10 12 13 15 16 17 19 20 22 23 24 26
LOAD CURRENT (A)
4620A F13
3
5
6
8
9 10 12 13 15 16 17 19 20 22 23 24 26
LOAD CURRENT (A)
4620A F14
Figure 12. 2.5V Power Loss Curve
Figure 13. 1V Power Loss Curve
Figure 14. 5V Power Loss Curve
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
6
4
2
0
400LFM
200LFM
0LFM
400LFM
4
2
0
200LFM
0LFM
80
0
20
40
60
100
120
80
0
20
40
60
100
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4620A F16
4620A F15
Figure 15. 12V to 1V Derating
Curve, No Heat Sink
Figure 16. 5V to 1V Derating
Curve, No Heat Sink
26
24
22
20
18
16
14
12
10
8
26
24
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
4620A F18
4620A F17
Figure 17. 12V to 1V Derating
Curve, BGA Heat Sink
Figure 18. 5V to 1V Derating
Curve, BGA Heat Sink
4620af
27
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
30
25
20
15
10
30
25
20
15
10
5
5
0
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
0
80
80
0
20
40
60
100 120 140
0
20
40
60
100 120 140
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4620A F19
4620A F20
Figure 19. 12V to 2.5V Derating
Curve, No Heat Sink
Figure 20. 5V to 2.5V Derating
Curve, No Heat Sink
30
25
20
15
10
5
30
25
20
15
10
5
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
0
0
80
AMBIENT TEMPERATURE (°C)
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100 120 140
0
20
40
60
100 120 140
4620A F21
4620A F22
Figure 21. 12V to 2.5V Derating
Curve, with Heat Sink
Figure 22. 5V to 2.5V Derating
Curve, with Heat Sink
30
25
20
15
10
5
30
25
20
15
10
5
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
0
0
80
AMBIENT TEMPERATURE (°C)
80
AMBIENT TEMPERATURE (°C)
0
20
40
60
100
120
0
20
40
60
100
120
4620A F23
4620A F24
Figure 23. 12V to 5V Derating
Curve, No Heat Sink
Figure 24. 12V to 5V Derating
Curve, with Heat Sink
4620af
28
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
Layout Checklist/Eꢁaꢂple
The high integration of LTM4620A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• Use large PCB copper areas for high current paths,
including V , GND, V
and V
. It helps to mini-
IN
OUT1
OUT2
• For parallel modules, tie the V , V , and COMP pins
OUT FB
mize the PCB conduction loss and thermal stress.
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
• Bring out test points on the signal pins for monitoring.
• Place a dedicated power ground layer underneath the
Figure25givesagoodexampleoftherecommendedlayout.
unit.
• To minimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
C
C
IN1
IN2
V
IN
M
L
K
J
GND
GND
H
G
F
SGND
C
C
OUT2
OUT1
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
V
GND
V
OUT2
OUT1
4620A F25
CNTRL
CNTRL
Figure 25. Recoꢂꢂended PCB Layout
4620af
29
For more information www.linear.com/4620A
LTM4620A
applicaTions inForMaTion
4620af
30
For more information www.linear.com/4620A
LTM4620A
Typical applicaTions
4620af
31
For more information www.linear.com/4620A
LTM4620A
Typical applicaTions
4620af
32
For more information www.linear.com/4620A
LTM4620A
Typical applicaTions
INTV
INTV
CC
CC1
C10
4.7µF
R2
5k
CLK1
MODE_PLLIN CLKOUT INTV
PGOOD1
EXTV
PGOOD1
CC
CC
5V TO 16V INTERMEDIATE BUS
V
3.3V
50A
OUT
V
IN
V
IN
V
OUT1
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
C
220pF
OUT1
R6
R1*
10k
TEMP
V
OUTS1
SW1
100µF
6.3V
×2
100k
RUN1
V
FB
V
FB1
FB2
RUN2
V
R5
13.3k
D1*
TRACK1
TRACK2
LTM4620A
5.1V
COMP1
COMP2
ZENER
C20
0.22µF
INTV
COMP
f
CC1
SET
PHASMD
V
OUTS2
V
OUT2
SW2
C
OUT2
100µF
6.3V
×2
PGOOD2
PGOOD1
SGND
GND
DIFFP
DIFFN DIFFOUT
INTV
CC2
C16
4.7µF
5k
CLK1
PGOOD2
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
7V TO 16V INTERMEDIATE BUS
V
V
OUT1
IN
C12
22µF
25V
C15
22µF
25V
C5
22µF
25V
C
OUT3
R9
100k
TEMP
V
OUTS1
SW1
100µF
6.3V
×2
RUN1
RUN2
V
FB
V
FB1
TRACK1
TRACK2
V
FB2
LTM4620A
COMP1
COMP2
INTV
COMP
f
CC2
SET
PHASMD
V
OUTS2
V
OUT2
SW2
4620A F29
C
OUT4
100µF
6.3V
×2
PGOOD2
DIFFN DIFFOUT
PGOOD2
SGND
GND
DIFFP
* PULL-UP RESISTOR AND ZENER ARE OPTIONAL
Figure 29. 4-Phase, 3.3V at 50A, 750kHz
4620af
33
For more information www.linear.com/4620A
LTM4620A
package DescripTion
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCꢃS. REVIEW EACH PACKAGE
LAYOUꢃ CAREFULLY.
LꢃM4620A Coꢂponent LGA Pinout
PIN ID FUNCꢃION
PIN ID
B1
FUNCꢃION
PIN ID
C1
FUNCꢃION PIN ID FUNCꢃION
PIN ID
E1
FUNCꢃION
GND
PIN ID
F1
FUNCꢃION
GND
A1
A2
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
OUT1
V
V
V
V
V
V
V
V
V
D1
D2
GND
GND
GND
GND
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
B2
C2
E2
GND
F2
GND
A3
B3
C3
D3
E3
GND
F3
GND
A4
B4
C4
D4
E4
GND
F4
MODE_PLLIN
RUN1
A5
B5
C5
V
OUT1S
D5
V
E5
TRACK1
COMP1
COMP2
DIFFP
DIFFN
GND
F5
FB1
A6
GND
GND
B6
GND
GND
C6
f
D6
SGND
E6
F6
SGND
SET
A7
B7
C7
SGND
D7
V
E7
F7
SGND
FB2
A8
V
B8
V
C8
V
OUT2S
D8
TRACK2
GND
E8
F8
DIFFOUT
RUN2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
A9
V
V
V
V
B9
V
V
V
V
C9
V
D9
E9
F9
OUT2
OUT2
OUT2
OUT2
A10
A11
A12
B10
B11
B12
C10
C11
C12
V
V
V
D10
D11
D12
GND
E10
E11
E12
F10
F11
F12
GND
GND
GND
GND
GND
GND
GND
PIN ID FUNCꢃION
PIN ID
H1
FUNCꢃION
GND
PIN ID
J1
FUNCꢃION PIN ID FUNCꢃION
PIN ID
L1
FUNCꢃION
PIN ID
M1
FUNCꢃION
G1
G2
GND
SW1
GND
K1
K2
GND
GND
GND
H2
GND
J2
V
V
V
V
V
V
L2
V
V
V
V
V
V
V
V
V
V
M2
V
V
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
G3
GND
H3
GND
J3
K3
L3
M3
G4
PHASEMD
CLKOUT
SGND
H4
GND
J4
K4
L4
M4
G5
H5
GND
J5
GND
K5
GND
GND
GND
GND
L5
M5
G6
H6
GND
J6
TEMP
K6
L6
M6
G7
SGND
H7
GND
J7
EXTV
K7
L7
M7
CC
G8
PGOOD2
PGOOD1
GND
H8
INTV
J8
GND
K8
L8
M8
CC
G9
H9
GND
GND
GND
GND
J9
V
V
V
K9
V
V
V
L9
M9
IN
IN
IN
IN
IN
IN
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
SW2
GND
GND
GND
GND
GND
4620af
34
For more information www.linear.com/4620A
LTM4620A
package DescripTion
Please refer to http://www.linear.coꢂ/designtools/packaging/ for the ꢂost recent package drawings.
LGA Package
144-Lead (15ꢂꢂ × 15ꢂꢂ × 4.41ꢂꢂ)
(Reference LTC DWG # 05-08-1844 Rev B)
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4620af
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
35
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM4620A
package phoTo
relaTeD parTs
PARꢃ NUMBER
DESCRIPꢃION
COMMENꢃS
LTM4628
Dual 8A, Single 16A µModule Regulator
Pin Compatible with LTM4620A; 4.5V ≤ V ≤ 26.5V, 0.6V ≤ V
≤ 5.5V,
IN
OUT
15mm × 15mm × 4.32mm
LTM4627
LTM4611
LTM4620
15A µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V
≤ 5.5V, 15mm × 15mm × 4.32mm
IN
OUT
Ultralow V , 15A µModule Regulator
1.5V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 15mm × 15mm × 4.32mm
IN
IN
OUT
Dual 13A or Single 26A
Lower Output Voltage Range, 0.6V to 2.5V, Pin Compatible
Design resources
SUBJECꢃ
DESCRIPꢃION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Quick Start Guide
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
4620af
LT 0113 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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LINEAR TECHNOLOGY CORPORATION 2013
相关型号：
LTM4622AEV#PBF
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: LGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622AEY#PBF
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622AIV#PBF
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: LGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622AIY
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622AIY#PBF
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622EV#PBF
LTM4622 - Dual Ultrathin 2.5A or Single 5A Step-Down DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622IY
LTM4622 - Dual Ultrathin 2.5A or Single 5A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4622IY#PBF
LTM4622 - Dual Ultrathin 2.5A or Single 5A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4623EV#PBF
LTM4623 - Ultrathin 20VIN, 3A Step-Down DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
LTM4623EY#PBF
LTM4623 - Ultrathin 20VIN, 3A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C
Linear
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