LTM4622AIY#PBF [Linear]
LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C;
| 型号： | LTM4622AIY#PBF |
| 厂家： | 
Linear |
| 描述： | LTM4622A - Dual Ultrathin 2A or Single 4A Step-Down DC/DC µModule Regulator; Package: BGA; Pins: 25; Temperature Range: -40°C to 85°C |
| 文件： | 总30页 (文件大小：1249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4622A
Dual Ultrathin 2A or Single 4A
Step-Down DC/DC µModule Regulator
FEATURES
DESCRIPTION
2
TheLTM®4622Aisacompletedual2Astep-downswitching
modeµModule® (micromodule)regulatorinatinyultrathin
6.25mm×6.25mm×1.82mmLGAand 2.42mmBGApack-
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Complete Solution in <1cm
Wide Input Voltage Range: 3.6V to 20V
1.5V to 12V Output Voltage
Dual 2A (3A Peak) or Single 4A Output Current
1.5ꢀ Maꢁimum Total Output Voltage Regulation
Error Over Load, Line and Temperature
Current Mode Control, Fast Transient Response
External Frequency Synchronization
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ages. Included in the package are the switching controller,
powerFETs, inductorandsupportcomponents. Operating
over an input voltage range of 3.6V to 20V, the LTM4622A
supports an output voltage range of 1.5V to 12V, set by a
single external resistor. Its high efficiency design delivers
dual 2A continuous, 3A peak, output current. Only a few
ceramic input and output capacitors are needed.
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Multiphase Parallelable with Current Sharing
Output Voltage Tracking and Soft-Start Capability
Selectable Burst Mode® Operation
TheLTM4622AsupportsselectableBurstModeoperation
and output voltage tracking for supply rail sequencing. Its
highswitchingfrequencyandcurrentmodecontrolenable
a very fast transient response to line and load changes
without sacrificing stability.
Overvoltage Input and Overtemperature Protection
Power Good Indicators
6.25mm × 6.25mm × 1.82mm LGA and
6.25mm × 6.25mm × 2.42mm BGA Packages
Faultprotectionfeaturesincludeinputovervoltage, output
overcurrent and overtemperature protection.
APPLICATIONS
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General Purpose Point-of-Load Conversion
The LTM4622A is available with SnPb (BGA) or RoHS
compliant terminal finish.
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Telecom, Networking and Industrial Equipment
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Medical Diagnostic Equipment
Test and Debug Systems
Product Selection Guide
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PART NUMBER
LTM4622
V
RANGE
V
RANGE
I
OUT
IN
OUT
All registered trademarks and trademarks are the property of their respective owners.
0.6V to 5.5V
1.5V to 12V
Dual 2.5A or Single 5A
Dual 2A or Single 4A
3.6V to 20V
LTM4622A
TYPICAL APPLICATION
12V Input, 3.3V and 5V Output,
Efficiency vs Load Current
3.3V and 5V Dual Output DC/DC Step-Down µModule Regulator
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For more information www.linear.com/LTM4622A
LTM4622A
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V
OUT
, V ................................................... –0.3V to 22V
Operating Internal Temperature Range
IN1 IN2
V
........................................................... –0.3V to 16V
(Note 2) ............................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature.................260°C
PGOOD1, PGOOD2..................................... –0.3V to 18V
RUN1, RUN2 .................................... –0.3V to V + 0.3V
IN
INTV , TRACK/SS1, TRACK/SS2............ –0.3V to 3.6V
CC
SYNC/MODE, COMP1, COMP2,
FB1, FB2........................................... –0.3V to INTV
CC
PIN CONFIGURATION (See Pin Functions, Pin Configuration Table)
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= 125°C, θ = 17°C/W, θ = 11°C/W,
T
= 125°C, θ = 17°C/W, θ = 11°C/W,
T
JMAX
JMAX
JCtop
JCbottom
JCtop
JCbottom
θ
+ θ = 22°C/W, θ = 22°C/W,
θ
+ θ = 22°C/W, θ = 22°C/W,
JB BA JA
JB
BA
JA
WEIGHT = 0.21g
WEIGHT = 0.25g
http://www.linear.com/product/LTM4622A#orderinfo
ORDER INFORMATION
PART MARKING*
PACKAGE
MSL
TEMPERATURE RANGE
(Note 2)
PART NUMBER
LTM4622AEV#PBF
LTM4622AIV#PBF
LTM4622AEY#PBF
LTM4622AIY#PBF
LTM4622AIY
PAD OR BALL FINISH
Au (RoHS)
DEVICE
FINISH CODE
TYPE
LGA
LGA
BGA
BGA
BGA
RATING
LTM4622AV
LTM4622AV
LTM4622AY
LTM4622AY
LTM4622AY
e4
e4
e1
e1
e0
4
4
4
4
4
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Au (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
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For more information www.linear.com/LTM4622A
LTM4622A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C, VIN1 = VIN2 = 12V, unless otherwise
noted per the typical application shown in Figure 27.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Switching Regulator Section: per Channel
l
l
l
l
V
V
V
V
Input DC Voltage Range
Input DC Voltage Range
Output Voltage Range
3.6
1.5
20
20
V
V
V
V
IN1
3.6V < V < 20V
IN2
IN1
V V = 3.6V to 20V
IN1 = IN2
1.5
12
OUT(RANGE)
OUT(DC)
Output Voltage, Total Variation
with Line and Load
C
= 22µF, C
= 100µF Ceramic, R = 40.2k,
1.477
1.50
1.523
IN
OUT
FB
MODE = INTV ,V
V
= 3.6V to 20V, I
= 0A to 2A
CC IN1 = IN2
OUT
V
RUN
RUN Pin On Threshold
RUN Threshold Rising
RUN Threshold Falling
1.20
0.97
1.27
1.00
1.35
1.03
V
V
I
Input Supply Bias Current
V
V
V
= 12V, V
= 12V, V
= 1.5V, MODE = GND
= 1.5V, MODE = INTV
7
500
45
mA
µA
µA
Q(VIN)
IN1 = IN2
OUT
OUT
V
IN1 = IN2
Shutdown, RUN1 = RUN2 = 0
CC
I
I
Input Supply Current
V
V
V
V
V
= 12V, V
V = 12V, V
IN1 = IN2
= 1.5V, I = 2A
OUT
0.32
A
A
S(VIN)
IN1 = IN2
OUT
OUT
l
l
l
Output Continuous Current Range
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
= 1.5V (Note 3)
= 3.6V to 20V, I = 0A
OUT
0
2
OUT(DC)
ΔV
ΔV
/V
= 1.5V, V
V
0.01
0.2
5
0.1
1.0
%/V
%
OUT(Line) OUT
OUT
OUT
OUT
IN1 = IN2
/V
= 1.5V, I
= 0A to 2A
OUT(Load) OUT
OUT
V
I
= 0A, C
= 1.5V
= 100µF Ceramic, V V
IN1 = IN2
= 12V,
= 12V,
mV
OUT(AC)
OUT
V
OUT
ΔV
Turn-On Overshoot
Turn-On Time
I
= 0A, C
= 1.5V
= 100µF Ceramic, V
V
30
1.25
100
20
mV
ms
mV
µs
OUT(START)
OUTLS
OUT
OUT
OUT
IN1 = IN2
V
t
C
V
= 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
= 12V, V = 1.5V
START
OUT
IN1 = IN2
V
OUT
ΔV
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, C
= 100µF
OUT
= 1.5V
Ceramic, V
V
= 12V, V
IN1 = IN2
OUT
t
I
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load, C
Ceramic, V = 12V, V
= 100µF
SETTLE
OUT
= 1.5V
OUT
V
IN1 = IN2
Output Current Limit
Voltage at FB Pin
Current at FB Pin
V
V
= 12V, V
= 1.5V
3
4
A
V
OUTPK
IN1 = IN2
OUT
l
V
I
= 0A, V = 1.5V
OUT
0.592
0.60
0.608
30
FB
OUT
I
(Note 4)
nA
kΩ
µA
μs
ns
ns
FB
R
Resistor Between V
and FB Pins
60.00 60.40 60.80
1.25
FBHI
OUT
I
t
t
t
Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V
TRACK/SS
SS
Internal Soft-Start Time
Minimum On-Time
Minimum Off-Time
PGOOD Trip Level
10% to 90% Rise Time (Note 4)
400
20
700
(Note 4)
(Note 4)
ON(MIN)
OFF(MIN)
45
V
V
FB
With Respect to Set Output
Ramping Negative
Ramping Positive
PGOOD
V
V
–8
8
–14
14
%
%
FB
FB
R
PGOOD Pull-Down Resistance
1mA Load
20
Ω
V
PGOOD
V
Internal V Voltage
V
V = 3.6V to 20V
IN1 = IN2
3.1
3.3
3.5
INTVCC
CC
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For more information www.linear.com/LTM4622A
LTM4622A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C, VIN1 = VIN2 = 12V, unless otherwise
noted per the typical application shown in Figure 27.
SYMBOL
PARAMETER
CONDITIONS
I = 0mA to 50mA
CC
MIN
TYP
1.3
1
MAX
UNITS
%
V
Load Reg INTV Load Regulation
INTVCC
OSC
CC
f
f
I
Oscillator Frequency
Frequency Sync Range
MODE Input Current
MHz
%
With Respect to Set Frequency
MODE = INTV
30
SYNC
MODE
–1.5
µA
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: See output current derating curves for different V , V
Note 4: 100% tested at wafer level.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
and T .
IN OUT A
Note 2: The LTM4622A is tested under pulsed load conditions such that
T ≈ T . The LTM4622AE is guaranteed to meet performance
J
A
specifications over the 0°C to 125°C internal operating temperature
range. Specifications over the full –40°C to 125°C internal operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTM4622AI is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
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For more information www.linear.com/LTM4622A
LTM4622A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
at 5VIN
Efficiency vs Load Current
at 12VIN
Efficiency vs Load Current
at 16VIN
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4622ꢀ ꢁꢂ2
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂꢃ
Burst Mode Efficiency,
12VIN, 1.5VOUT
1.5V Output Transient Response
3.3V Output Transient Response
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LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
V
OUT
V
OUT
AC-COUPLED
50mV/DIV
AC-COUPLED
50mV/DIV
4622A G05
4622A G06
50µs/DIV
50µs/DIV
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V
= 12V, V
= 1.5V, f = 1MHz
OUT SW
V
= 12V, V
= 3.3V, f = 1MHz
OUT SW
IN
IN
OUTPUT CAPACITOR = 47µF ×1 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
OUTPUT CAPACITOR = 47µF ×1 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
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4622ꢀ ꢁꢂ4
5V Output Transient Response
8V Output Transient Response
12V Output Transient Response
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
V
OUT
V
OUT
V
OUT
AC-COUPLED
100mV/DIV
AC-COUPLED
100mV/DIV
AC-COUPLED
100mV/DIV
4622A G08
4622A G09
4622A G07
50µs/DIV
50µs/DIV
50µs/DIV
V
= 12V, V
= 8V, f = 1.5MHz
OUT SW
V
= 16V, V
= 12V, f = 1.5MHz
OUT SW
V
= 12V, V
= 5V, f = 1MHz
OUT SW
IN
IN
IN
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
OUTPUT CAPACITOR = 47µF ×2 CERAMIC
10pF FEED-FORWARD CAPACITOR
LOAD-STEP = 1A TO 2A (10A/μs)
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LTM4622A
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with No Load
Start-Up with 2A Load
Short-Circuit with No Load
Current Applied
Current Applied
Current Applied
ꢇ
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ꢀꢁꢇꢄꢅꢆꢇ
ꢋꢉꢌ
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ꢜ 4ꢝꢁꢚ ꢗꢊꢒꢘꢇꢗ
Short-Circuit with 2A Load
Current Applied
Recover from Short-Circuit with
No Load Current Applied
Steady-State Output Voltage Ripple
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2ꢆꢃꢄꢅꢆ
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LTM4622A
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
RUN1(D2),RUN2(B2):RunControlInputofEachSwitch-
ing Mode Regulator Channel. Enables chip operation by
tying RUN above 1.27V. Tying this pin below 1V shuts
down the specific regulator channel. Do not float this pin.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
V
IN1
(D3, E2), V (A2, B3): Power Input Pins. Apply
IN2
input voltage between these pins and GND pins. Rec-
ommend placing input decoupling capacitance directly
between BOTH V and V pins and GND pins. Please
PGOOD1 (D4), PGOOD2 (B4): Output Power Good with
Open-Drain Logic of Each Switching Mode Regulator
Channel. PGOOD is pulled to ground when the voltage
on the FB pin is not within 8% (typical) of the internal
0.6V reference.
IN1
IN2
note the module internal control circuity is running off
V
. Channel 2 will not work without a voltage higher that
IN1
3.6V presents at V
.
IN1
TRACK/SS1 (E3), TRACK/SS2 (A3): Output Tracking
and Soft-Start Pin of Each Switching Mode Regulator
Channel. It allows the user to control the rise time of the
output voltage. Putting a voltage below 0.6V on this pin
bypasses the internal reference input to the error ampli-
fier, instead it servos the FB pin to the TRACK voltage.
Above 0.6V, the tracking function stops and the internal
reference resumes control of the error amplifier. There’s
GND (C1 to C2, B5, D5): Power Ground Pins for Both
Input and Output Returns.
INTV (C3): Internal 3.3V Regulator Output. The internal
CC
power drivers and control circuits are powered from this
voltage. This pin is internally decoupled to GND with a
2.2µF low ESR ceramic capacitor. No additional external
decoupling capacitor needed.
an internal 1.4µA pull-up current from INTV on this pin,
CC
SYNC/MODE (C5): Mode Select and External Synchroni-
zation Input. Tie this pin to ground to force continuous
synchronousoperationatalloutputloads.Floatingthispin
so putting a capacitor here provides soft-start function.
A default internal soft-start ramp forces a minimum soft-
start time of 400µs.
or tying it to INTV enables high efficiency Burst Mode
CC
FB1 (E4), FB2 (A4): The Negative Input of the Error
operation at light loads. Drive this pin with a clock to syn-
chronize the LTM4622A switching frequency. An internal
phase-locked loop will force the bottom power NMOS’s
turn on signal to be synchronized with the rising edge
of the clock signal. When this pin is driven with a clock,
forced continuous mode is automatically selected.
Amplifier for Each Switching Mode Regulator Channel.
Internally, this pin is connected to V
with a 60.4k preci-
OUT
sionresistor.Differentoutputvoltagescanbeprogrammed
with an additional resistor between FB and GND pins. In
PolyPhase® operation, tying the FB pins together allows
for parallel operation. See the Applications Information
section for details.
V
OUT1
(D1, E1), V
(A1, B1): Power Output Pins of
OUT2
EachSwitchingModeRegulator.Applyoutputloadbetween
these pins and GND pins. Recommend placing output
decoupling capacitance directly between these pins and
GND pins.
COMP1 (E5), COMP2 (A5): Current Control Threshold
and Error Amplifier Compensation Point of Each Switch-
ing Mode Regulator Channel. The current comparator’s
trip threshold is linearly proportional to this voltage,
whose normal range is from 0.3V to 1.8V. Tie the COMP
pins together for parallel operation. The device is internal
compensated. Do not drive this pin.
FREQ (C4): Frequency is set internally to 1MHz. An
external resistor can be placed from this pin to GND to
increase frequency, or from this pin to INTV to reduce
CC
frequency. See the Applications Information section for
frequency adjustment.
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LTM4622A
BLOCK DIAGRAM
ꢓ
ꢓ
ꢁꢔꢇ2
ꢁꢔꢇꢏ
6ꢋꢌ4ꢍ
6ꢋꢌ4ꢍ
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ꢏꢋꢍ
ꢀꢜꢁꢁꢛꢏ
ꢀꢜꢁꢁꢛ2
ꢉꢊꢏ
ꢒꢆꢇꢓ
ꢒꢆꢇꢓ
ꢅꢅ
ꢏꢝꢌꢝꢍ
ꢉꢊ2
ꢅꢅ
ꢐꢌ2ꢑꢍ
ꢒꢆꢇꢓ
ꢅꢅ
ꢓ
ꢒꢆꢏ
ꢓ
ꢒꢆ
2ꢌ2ꢎꢉ
ꢐꢓ ꢇꢁ 2ꢋꢓ
ꢋꢌ22ꢎꢉ
ꢋꢌꢏꢎꢉ
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4ꢠꢎꢉ
ꢏꢋꢎꢉ
4ꢠꢎꢉ
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2ꢌ2ꢎꢞ
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2ꢕ
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ꢇꢄꢕꢅꢖꢗꢘꢘ2
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2ꢌ2ꢎꢞ
ꢅꢁꢚꢀ
ꢓ
ꢑꢓ
2ꢕ
ꢓ
ꢁꢔꢇ2
ꢁꢔꢇ2
ꢜꢆꢛ
ꢅꢁꢚꢀ2
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ꢅꢁꢚꢀ
ꢝ24ꢍ
4622ꢕ ꢊꢛ
Figure 1. Simplified LTM4622A Block Diagram
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
IN
External Input Capacitor Requirement
I
= 2A
4.7
10
µF
OUT
(V = 3.6V to 20V, V
= 1.5V)
IN
OUT
C
OUT
External Output Capacitor Requirement
(V = 3.6V to 20V, V = 1.5V)
I
= 2A
22
47
µF
OUT
IN
OUT
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LTM4622A
OPERATION
The LTM4622A is a dual output standalone non-isolated
switch mode DC/DC power supply. It can deliver two 2A
DC, 3A peak output current with few external input and
output ceramic capacitors. This module provides dual
precisely regulated output voltage programmable via two
external resistor from 1.5V to 12V over 3.6V to 20V input
voltage range. The typical application schematic is shown
in Figure 27.
a wide range of output capacitors, even with all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast cur-
rent limiting. An internal overvoltage and undervoltage
comparators pull the open-drain PGOOD output low if the
output feedback voltage exits a 8% window around the
regulationpoint.Furthermore,aninputovervoltageprotec-
tion been utilized by shutting down both power MOSFETs
The LTM4622A contains an integrated controlled on-time
valleycurrentmoderegulator,powerMOSFETs,inductors,
and other supporting discrete components. The default
switching frequency is 1MHz. For output voltages above
3.3V, an external resistor is required between FREQ and
SGND pins to set the operating frequency to 1.5MHz to
2MHz to optimize inductor current ripple. For switching
noise-sensitive applications, the switching frequency can
beadjustedbyexternalresistorsandtheμModuleregulator
can be externally synchronized to a clock within 30% of
thesetfrequency.SeetheApplicationsInformationsection.
when V rises above 22.5V to protect internal devices.
IN
Multiphaseoperationcanbeeasilyemployedbyconnecting
SYNC pin to an external oscillator. Up to 6 phases can be
paralleled to run simultaneously a good current sharing
guaranteed by current mode control loop.
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both power MOSFETs and
mostoftheinternalcontrolcircuitry.Atlightloadcurrents,
Burst Mode operation can be enabled to achieve higher
efficiency compared to continuous mode (CCM) by set-
ting MODE pin to INTV . The TRACK/SS pin is used for
CC
With current mode control and internal feedback loop
compensation, the LTM4622A module has sufficient
stability margins and good transient performance with
power supply tracking and soft-start programming. See
the Applications Information section.
APPLICATIONS INFORMATION
where t
is the minimum off-time, 45ns typical for
SW
OFF(MIN)
The typical LTM4622A application circuit is shown in
Figure 27. External component selection is primarily
determined by the input voltage, the output voltage and
the maximum load current. Refer to Table 7 for specific
externalcapacitorrequirementsforaparticularapplication.
LTM4622A,andf istheswitchingfrequency.Conversely
theminimumon-timelimitimposesaminimumdutycycle
of the converter which can be calculated as:
DC
= t
• f
(MIN)
ON(MIN) SW
where t
is the minimum on-time, 20ns typical for
ON(MIN)
V to V
Step-Down Ratios
IN
OUT
LTM4622A. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
There are restrictions in the maximum V and V
step
IN
OUT
down ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of the regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
DC
= 1 – t
• f
OFF(MIN) SW
(MAX)
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LTM4622A
APPLICATIONS INFORMATION
Output Voltage Programming
Output Decoupling Capacitors
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 60.4k 0.5% internal
With an optimized high frequency, high bandwidth design,
only single piece of 47µF low ESR output ceramic capaci-
tor is required for each LTM4622A output to achieve low
output voltage ripple and very good transient response.
Additional output filtering may be required by the system
designer, if further reduction of output ripples or dynamic
transient spikes is required. Table 7 shows a matrix of dif-
ferent output voltages and output capacitors to minimize
the voltage droop and overshoot during a 1A (50%) load
step transient. Multiphase operation will reduce effective
outputrippleasafunctionofthenumberofphases.Applica-
tion Note 77 discusses this noise reduction versus output
ripple current cancellation, but the output capacitance will
be more a function of stability and transient response. The
Linear Technology LTpowerCAD® Design Tool is available
to download online for output ripple, stability and transient
responseanalysisandcalculatingtheoutputripplereduction
asthenumberofphasesimplementedincreasesbyNtimes.
feedback resistor connects V
and FB pins together.
OUT
Adding a resistor R from FB pin to GND programs the
FB
output voltage:
0.6V
R
=
•60.4k
FB
V
– 0.6V
OUT
Table 1. VFB Resistor Table vs Various Output Voltages
(1% Resistor)
V
(V) 1.5
1.8
2.5
3.3
5.0 8.0
10.0 12.0
OUT
R
FB
(k)
40.2 30.1 19.1 13.3 8.25 4.87 3.83 3.16
Pease note that for output above 3.3V, a higher operating
frequency is required to optimize inductor current ripple.
See Operating Frequency section.
For parallel operation of N-channels LTM4622A, the fol-
lowing equation can be used to solve for R :
FB
Burst Mode Operation
0.6V
– 0.6V
60.4k
N
R
=
•
FB
Inapplicationswherehighefficiencyatintermediatecurrent
aremoreimportantthanoutputvoltageripple,BurstMode
operation could be used by connecting SYNC/MODE pin
V
OUT
Input Decoupling Capacitors
to INTV to improve light load efficiency. In Burst Mode
CC
The LTM4622A module should be connected to a low AC-
impedanceDCsource.Foreachregulatorchannel,onepiece
4.7µF input ceramic capacitor is required for RMS ripple
current decoupling. Bulk input capacitor is only needed
whentheinputsourceimpedanceiscompromisedbylong
inductive leads, traces or not enough source capacitance.
Thebulkcapacitorcanbeanelectrolyticaluminumcapaci-
tor and polymer capacitor.
operation, a current reversal comparator (I ) detects
REV
the negative inductor current and shuts off the bottom
power MOSFET, resulting in discontinuous operation and
increased efficiency. Both power MOSFETs will remain
off and the output capacitor will supply the load current
until the COMP voltage rises above the zero current level
to initiate another cycle.
Force Continuous Current Mode (CCM) Operation
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
outputrippleisdesired,forcedcontinuousoperationshould
be used. Forced continuous operation can be enabled by
tying the SYNC/MODE pin to GND. In this mode, induc-
tor current is allowed to reverse during low output loads,
the COMP voltage is in control of the current comparator
threshold throughout, and the top MOSFET always turns
on with each oscillator pulse. During start-up, forced
I
OUT(MAX)
I
=
• D • 1–D
(
)
CIN(RMS)
η%
where is the estimated efficiency of the power module.
4622afa
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LTM4622A
APPLICATIONS INFORMATION
continuous mode is disabled and inductor current is
prevented from reversing until the LTM4622A’s output
voltage is in regulation.
The programmable operating frequency range is from
800kHz to 4MHz.
Frequency Synchronization
Operating Frequency
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of the external clock. The
external clock frequency range must be within 30%
around the set operating frequency. A pulse detection
circuit is used to detect a clock on the SYNC/MODE pin
to turn on the phase-locked loop. The pulse width of the
clock has to be at least 100ns. The clock high level must
be above 2V and clock low level below 0.3V. The presence
of an external clock will place both regulator channels into
forced continuous mode operation. During the start-up of
the regulator, the phase-locked loop function is disabled.
The operating frequency of the LTM4622A is optimized
to achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
The default operating frequency is internally set to 1MHz.
If any operating frequency other than 1MHz is required
by application, the operating frequency can be increased
by adding a resistor, R
, between the FREQ pin and
FSET
SGND, as shown in Figure 29. The operating frequency
can be calculated as:
3.2e11
324k||RFSET Ω
( )
f Hz =
(
)
Multiphase Operation
Pleasenoteaminimumswitchingfrequencyisrequiredfor
given V , V operating conditions to keep a maximum
IN OUT
Foroutputloadsthatdemandmorethan2Aofcurrent,two
outputsintheLTM4622AorevenmultipleLTM4622Ascan
be paralleled to run out of phase to provide more output
currentwithoutincreasinginputandoutputvoltageripples.
peak-to-peak inductor ripple current below 1.2A for the
LTM4622A.
Thepeak-to-peakinductorripplecurrentcanbecalculatedas:
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used when all of the outputs are tied together
to achieve a single high output current design.
⎛
⎞
V
V
1
OUT ⎜
OUT ⎟
ΔI
=
1−
•
P-P
⎜
⎜
⎟
⎟
2.2
V
f
(MHz)
IN
SW
⎝
⎠
The maximum 1.2A peak-to-peak inductor ripple current
is enforced due to the nature of the valley current mode
control to maintain output voltage regulation at no load.
To reduce switching current ripple, 1.5MHz to 2MHz op-
erating frequency is suggested for 5V and above output
with R
to SGND.
FSET
The two switching mode regulator channels inside the
LTM4622A are internally set to operate 180° out of phase.
Multiple LTM4622As could easily operate 90 degrees, 60
degreesor45degreesshiftwhichcorrespondsto4-phase,
6-phase or 8-phase operation by letting SYNC/MODE of
the LTM4622A synchronize to an external multiphase
oscillator like LTC®6902. Figure 2 shows a 4-phase design
example for clock phasing.
V
1.5V to 3.3V
1MHz
5V, 8V
12V
OUT
f
1.5MHz
1.5MHz to 2MHz
SW
The operating frequency can also be decreased by adding
aresistorbetweentheFREQpinandINTV ,calculatedas:
CC
5.67e11
RFSET Ω
( )
f Hz =1MHz –
(
)
4622afa
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LTM4622A
APPLICATIONS INFORMATION
2ꢂꢂꢑ
reductionasafunctionofthenumberofinterleavedphases.
Figure 3 shows this graph.
ꢂꢒ
ꢄ
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ꢃ
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ꢍꢓꢈꢊꢔꢕꢖꢗꢎ
ꢃ
ꢃ
ꢚꢀ
ꢊꢊ
ꢖꢘꢉꢙ
ꢙꢚꢂꢒ
Soft-Start and Output Voltage Tracking
ꢋꢌ
ꢕꢖꢗ
ꢖꢘꢉ2
ꢏꢉꢊ6ꢐꢂ2
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitorontheTRACK/SSpinwillprogramtheramprate
of the output voltage. An internal 1.4µA current source
will charge up the external soft-start capacitor towards
ꢐꢂꢒ
ꢂꢒ
ꢍꢓꢈꢊꢔꢕꢖꢗꢎ
ꢃ
ꢃ
ꢖꢘꢉꢙ
ꢗꢇꢃ
ꢖꢘꢉꢙ
ꢖꢘꢉ2
ꢐꢂꢒ
2ꢜꢂꢒ
ꢛꢈꢗ
ꢖꢘꢉ2
4622ꢀ ꢁꢂ2
Figure 2. Example of Clock Phasing for 4-Phase
Operation with LTC6902
INTV voltage. When the TRACK/SS voltage is below
CC
0.6V, it will take over the internal 0.6V reference voltage
to control the output voltage. The total soft-start time
can be calculated as:
The LTM4622A device is an inherently current mode
controlled device, so parallel modules will have very
good current sharing. This will balance the thermals on
the design. Please tie RUN, TRACK/SS, FB and COMP pin
of each paralleling channel together. Figure 31 shows an
example of parallel operation and pin connection.
C
SS
t
= 0.6 •
SS
1.4µA
whereC isthecapacitanceontheTRACK/SSpin.Current
foldback and force continuous mode are disabled during
the soft-start process.
SS
INPUT RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
The LTM4622A has internal 400μs soft-start time when
TRACK/SS leave floating.
ꢀꢁ6ꢀ
ꢈꢜꢛꢝꢅꢚꢘ
2ꢜꢛꢝꢅꢚꢘ
ꢀꢁꢃꢃ
ꢇꢜꢛꢝꢅꢚꢘ
4ꢜꢛꢝꢅꢚꢘ
6ꢜꢛꢝꢅꢚꢘ
ꢀꢁꢃꢀ
ꢀꢁ4ꢃ
ꢀꢁ4ꢀ
ꢀꢁꢇꢃ
ꢀꢁꢇꢀ
ꢀꢁ2ꢃ
ꢀꢁ2ꢀ
ꢀꢁꢈꢃ
ꢀꢁꢈꢀ
ꢀꢁꢀꢃ
ꢀ
ꢀꢁꢈ ꢀꢁꢈꢃ ꢀꢁ2 ꢀꢁ2ꢃ ꢀꢁꢇ ꢀꢁꢇꢃ ꢀꢁ4 ꢀꢁ4ꢃ ꢀꢁꢃ ꢀꢁꢃꢃ ꢀꢁ6 ꢀꢁ6ꢃ ꢀꢁꢂ ꢀꢁꢂꢃ ꢀꢁꢄ ꢀꢁꢄꢃ ꢀꢁꢉ
ꢊꢋꢌꢍ ꢆꢅꢎꢌꢏꢐ ꢑꢒ ꢓꢒ
ꢖ
ꢏꢋꢌ ꢔꢕ
4622ꢅ ꢆꢀꢇ
Figure 3. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
4622afa
12
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LTM4622A
APPLICATIONS INFORMATION
Outputvoltagetrackingcanalsobeprogrammedexternally
usingtheTRACK/SSpin. Theoutputcanbetrackedupand
down with another regulator. Figure 4 and Figure 5 show
an example waveform and schematic of a Ratiometric
tracking where the slave regulator’s output slew rate is
proportional to the master’s.
The R
TR(BOT)
is the feedback resistor and the R
/
TR(TOP)
FB(SL)
R
is the resistor divider on the TRACK/SS pin of
the slave regulator, as shown in Figure 5.
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in Volts/
Time is determined by:
R
FB(SL)
R
+60.4k
MR
SR
ꢂꢆꢄꢀꢃꢋ ꢈꢉꢀꢊꢉꢀ
ꢄꢅꢆꢇꢃ ꢈꢉꢀꢊꢉꢀ
FB(SL)
R
=
TR(TOP)
R
+R
TR(TOP)
TR(BOT)
Forexample, V
=1.5V, MR=1.5V/msandV
OUT(MA)
OUT(SL)
= 3.3V, SR = 3.3V/ms. From the equation, we could solve
out that R
= 60.4k and R
= 40.2k is a good
TR(TOP)
TR(BOT)
ꢀꢁꢂꢃ
combination for the Ratiometric tracking.
4622ꢆ ꢍꢎ4
Figure 4. Output Ratiometric Tracking Waveform
The TRACK pins will have the 1.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
ꢔꢘꢌꢌꢙꢆ ꢔꢘꢌꢌꢙ2
ꢈ
ꢌꢍꢋꢆ
ꢈ
ꢈ
ꢈ
ꢉꢊꢆ
ꢌꢍꢋꢆ
ꢆꢁꢅ ꢎ 2ꢃ
4ꢏꢇꢄ
6ꢁꢐꢈ
ꢈ
ꢉꢊ
4ꢈ ꢋꢌ 2ꢀꢈ
ꢉꢊ2
ꢆꢀꢇꢄ
2ꢅꢈ
ꢕꢍꢊꢆ
ꢕꢍꢊ2
ꢉꢊꢋꢈ
ꢈ
ꢌꢍꢋ2
ꢈ
ꢌꢍꢋ2
ꢐꢁꢐ ꢎ 2ꢃ
ꢚꢋꢓ4622ꢃ
4ꢏꢇꢄ
6ꢁꢐꢈ
ꢒꢌꢓꢔꢆ
ꢒꢒ
ꢛꢜꢊꢒꢝꢓꢌꢙꢖ
ꢋꢕꢃꢒꢞꢝꢛꢛꢆ
ꢋꢕꢃꢒꢞꢝꢛꢛ2
ꢄꢕꢖꢗ
ꢒꢌꢓꢔ2
ꢄꢑꢆ
6ꢀꢁ4ꢂ
ꢈ
ꢌꢍꢋꢆ
ꢀꢁꢆꢇꢄ
ꢄꢑ2
The Coincident output tracking can be recognized as a
special Ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure 6.
ꢘꢊꢙ
ꢆꢐꢁꢐꢂ
4ꢀꢁ2ꢂ
4622ꢃ ꢄꢀꢅ
4ꢀꢁ2ꢂ
Figure 5. Example Schematic of Ratiometric
Output Voltage Tracking
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a R /R resistor
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
outputvoltageandthemasteroutputvoltageshouldsatisfy
the following equation during the start-up.
ꢂꢄꢅꢀꢃꢆ ꢇꢈꢀꢉꢈꢀ
ꢅꢊꢄꢋꢃ ꢇꢈꢀꢉꢈꢀ
TR(TOP) TR(BOT)
R
FB(SL)
V
•
=
OUT(SL)
ꢀꢁꢂꢃ
R
+60.4k
4622ꢄ ꢍꢎ6
FB(SL)
Figure 6. Output Coincident Tracking Waveform
R
TR(TOP)
V
•
OUT(MA)
R
+R
TR(BOT)
TR(TOP)
4622afa
13
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LTM4622A
APPLICATIONS INFORMATION
From the equation, we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its feedback divider.
TheLTM4622Aaccomplishesthisbyforcingdiscontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
R
R
FB(SL)
TR(BOT)
=
R
+60.4k
R
+R
TR(TOP) TR(BOT)
FB(SL)
Overtemperature Protection
For example, R
= 60.4k and R
= 13.3k is a
TR(TOP)
TR(BOT)
Theinternalovertemperatureprotectionmonitorsthejunc-
tiontemperatureofthemodule.Ifthejunctiontemperature
reachesapproximately160°C,bothpowerswitcheswillbe
turned off until the temperature drops about 15°C cooler.
good combination for coincident tracking for V
OUT(MAX)
= 1.5V and V
= 3.3V application.
OUT(SL)
Power Good
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 8% window around the regulation point. A resistor can
be pulled up to a particular supply voltage for monitoring.
To prevent unwanted PGOOD glitches during transients or
Input Overvoltage Protection
In order to protect the internal power MOSFET devices
againsttransientvoltagespikes,theLTM4622Aconstantly
monitors each V pin for an overvoltage condition. When
IN
V rises above 22.5V, the regulator suspends operation
IN
dynamic V
changes, the LTM4622A’s PGOOD falling
OUT
by shutting off both power MOSFETs on the correspond-
edge includes a blanking delay of approximately 40µs.
ing channel. Once V drops below 21.5V, the regulator
IN
immediately resumes normal operation. The regulator
executes its soft-start function when exiting an overvolt-
age condition.
Stability compensation
The LTM4622A module internal compensation loop is
designed and optimized for low ESR ceramic output
capacitors only application. Table 7 is provided for most
application requirements. The LTpowerCAD Design Tool
is available to down for control loop optimization.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD51-9 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formedonaµModulepackagemountedtoahardwaretest
board—also defined by JESD51-9 (Test Boards for Area
Array Surface Mount Package Thermal Measurements).
The motivation for providing these thermal coefficients in
found in JESD51-12 (Guidelines for Reporting and Using
Electronic Package Thermal Information).
RUN Enable
Pulling the RUN pin to ground forces the LTM4622A into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Trying the RUN pin
voltage above 1.27V will turn on the entire chip.
Pre-Biased Output Start-Up
There may be situations that require the power supply to
start up with a pre-bias on the output capacitors. In this
case, it is desirable to start up without discharging that
output pre-bias. The LTM4622A can safely power up into
a pre-biased output without discharging it.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
4622afa
14
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LTM4622A
APPLICATIONS INFORMATION
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
which does not reflect an actual application or viable
operating condition.
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetop
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below:
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
1. θ , the thermal resistance from junction to ambi-
JA
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as still air although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
4. θ , the thermal resistance from junction to the
JB
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θ
and the thermal re-
JCbottom
sistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
2. θ
, the thermal resistance from junction to
JCbottom
ambient,isthenaturalconvectionjunction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as still air although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 7; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule.
ꢎꢈꢏꢍꢐꢌꢆꢏꢑꢐꢆꢑꢀꢅꢗꢌꢊꢏꢐ ꢐꢘꢊꢖꢅꢀꢉ ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ ꢍꢆꢅꢔꢆꢏꢊꢏꢐꢒ
ꢎꢈꢏꢍꢐꢌꢆꢏꢑꢐꢆꢑꢍꢀꢒꢊ ꢓꢐꢆꢔꢕ
ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
ꢍꢀꢒꢊ ꢓꢐꢆꢔꢕꢑꢐꢆꢑꢀꢅꢗꢌꢊꢏꢐ
ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
ꢎꢈꢏꢍꢐꢌꢆꢏꢑꢐꢆꢑꢗꢆꢀꢖꢇ ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
ꢎꢈꢏꢍꢐꢌꢆꢏ
ꢀꢅꢗꢌꢊꢏꢐ
ꢎꢈꢏꢍꢐꢌꢆꢏꢑꢐꢆꢑꢍꢀꢒꢊ
ꢓꢗꢆꢐꢐꢆꢅꢕ ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
ꢍꢀꢒꢊ ꢓꢗꢆꢐꢐꢆꢅꢕꢑꢐꢆꢑꢗꢆꢀꢖꢇ
ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
ꢗꢆꢀꢖꢇꢑꢐꢆꢑꢀꢅꢗꢌꢊꢏꢐ
ꢖꢊꢒꢌꢒꢐꢀꢏꢍꢊ
4622ꢀ ꢁꢂꢃ
ꢄꢅꢆꢇꢈꢉꢊ ꢇꢊꢋꢌꢍꢊ
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
4622afa
15
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LTM4622A
APPLICATIONS INFORMATION
to correlate quite well with the µModule model with no
airflow or heat sinking in a properly define chamber. This
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op-
erating conditions of a μModule. For example, in normal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sivelythroughthetoporexclusivelythroughbottomofthe
θ
+ θ value is shown in the Pin Configuration section
JB
BA
and should accurately equal the θ value because ap-
JA
proximately 100% of power loss flows from the junction
through the board into ambient with no airflow or top
mounted heat sink.
The 1.5V, 3.3V, 5V, 8V and 12V power loss curves in
Figure 8 to Figure 12 can be used in coordination with the
load current derating curves in Figure 13 to Figure 23 for
µModule—asthestandarddefinesforθ
andθ
,
JCtop
JCbottom
respectively.Inpractice,powerlossisthermallydissipated
in bothdirectionsawayfromthepackage—granted, in the
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
calculating an approximate θ thermal resistance for the
JA
LTM4622A(intwo-phasesingleoutputoperation)withno
heatsinkingandvariousairflowconditions.Thepowerloss
curves are taken at room temperature, and are increased
with multiplicative factors of 1.35 assuming junction
temperature at 120°C. The derating curves are plotted
with the output current starting at 4A and the ambient
temperature at 30°C. These output voltages are chosen
to include the lower and higher output voltage ranges
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in a
controlled temperature chamber along with thermal mod-
eling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
airflow.Thepowerlossincreasewithambienttemperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
currentorpowerwithincreasingambienttemperature.The
decreasedoutputcurrentwilldecreasetheinternalmodule
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operat-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure 16, the load
current is derated to ~3A at ~100°C with 200LFM air but
not heat sink and the power loss for the 5V to 3.3V at 3A
output is about 1.15W. The 1.15W loss is calculated with
the ~0.85W room temperature loss from the 5V to 3.3V
power loss curve at 3A, and the 1.35 multiplying factor.
If the 100°C ambient temperature is subtracted from the
120°C junction temperature, then the difference of 20°C
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the µModule and the specified PCB with all of
thecorrectmaterialcoefficientsalongwithaccuratepower
losssourcedefinitions;(2)thismodelsimulatesasoftware-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the µModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due-diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory test have been performed and correlated to the
divided by 1.15W equals a 17.5°C/W θ thermal resis-
JA
tance. Table 3 specifies a 17°C/W – 18°C/W value which
is very close. Tables 2 to 6 provide equivalent thermal
resistances for 1.5V, 3.3V, 5V, 8V and 12V outputs with
4622afa
µModulemodel,thentheθ andθ aresummedtogether
JB
BA
16
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LTM4622A
APPLICATIONS INFORMATION
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄ6ꢀ
ꢃ ꢄ2ꢀ
ꢃ ꢄꢀ
ꢀ
ꢀ
ꢀ
ꢃ ꢄ6ꢀ
ꢃ ꢄ2ꢀ
ꢃ ꢄꢀ
ꢀ
ꢀ
ꢃ ꢄ6ꢀ
ꢃ ꢄ2ꢀ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢁꢂ
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ꢁꢂ
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ꢀ
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ꢀ
ꢀꢁꢂ
2
2ꢀꢁ
ꢀ
ꢀꢁꢂ
4
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
2
2ꢀꢁ
ꢀ
ꢀꢁꢂ
4
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
2
2ꢀꢁ
ꢀ
ꢀꢁꢂ
4
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂꢃ
Figure 8. 1.5V Output Power Loss
Figure 9. 3.3V Output Power Loss
Figure 10. 5V Output Power Loss
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
4ꢀꢁ
ꢀ
ꢀ
ꢃ ꢄ6ꢀ
ꢁꢂ
ꢁꢂ
ꢀ
ꢃ ꢄ6ꢀ
ꢁꢂ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢃ ꢄ2ꢀ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
2
2ꢀꢁ
ꢀ
ꢀꢁꢂ
4
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
2
2ꢀꢁ
ꢀ
ꢀꢁꢂ
4
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢂꢋ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
4622ꢀ ꢁꢂꢂ
4622ꢀ ꢁꢂ2
4622ꢀ ꢁꢂꢃ
Figure 13. 5V Input to 1.5V Output
Derating Curve, No Heat Sink
Figure 12. 12V Output Power Loss
Figure 11. 8V Output Power Loss
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
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4ꢀꢁ
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ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
4622ꢀ ꢁꢂ4
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂ6
Figure 14. 12V Input to to 1.5V Output
Derating Curve, No Heat Sink
Figure 15. 16V Input to 1.5V Output
Derating Curve, No Heat Sink
Figure 16. 5V Input to 3.3V Output
Derating Curve, No Heat Sink
4622afa
17
For more information www.linear.com/LTM4622A
LTM4622A
APPLICATIONS INFORMATION
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂꢃ
4622ꢀ ꢁꢂꢃ
Figure 17. 12V Input to 3.3V Output
Derating Curve, No Heat Sink
Figure 18. 16V Input to 3.3V Output
Derating Curve, No Heat Sink
Figure 19. 12V Input to 5V Output
Derating Curve, No Heat Sink
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
4ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
4622ꢀ ꢁ2ꢂ
4622ꢀ ꢁ2ꢂ
Figure 20. 16V Input to 5V Output
Derating Curve, No Heat Sink
Figure 21. 12V Input to 8V Output
Derating Curve, No Heat Sink
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
4ꢀꢁ
4ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
2ꢀꢁ
2ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃ
2ꢀꢀꢁꢂꢃ
4ꢀꢀꢁꢂꢃ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁ 4ꢀ ꢀꢁ 6ꢀ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢀꢁ ꢀ2ꢁ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄꢈꢀꢆꢉꢈꢄ ꢊꢋꢌꢍ
4622ꢀ ꢁ22
4622ꢀ ꢁ2ꢂ
Figure 22. 16V Input to 8V Derating
Curve, No Heat Sink
Figure 23. 16V Input to 12V Output
Derating Curve, No Heat Sink
4622afa
18
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LTM4622A
APPLICATIONS INFORMATION
Table 2. 1.5V Output
DERATING CURVE
Figures 13, 14, 15
Figures 13, 14, 15
Figures 13, 14, 15
V
(V)
POWER LOSS CURVE
Figure 8
AIRFLOW (LFM)
HEAT SINK
None
θ
θ
θ
θ
θ
IN
JA(°C/W)
5, 12, 16
5, 12, 16
5, 12, 16
0
19–20
Figure 8
200
400
None
17–18
17–18
Figure 8
None
Table 3. 3.3V Output
DERATING CURVE
Figures 16, 17, 18
Figures 16, 17, 18
Figures 16, 17, 18
V
(V)
POWER LOSS CURVE
Figure 9
AIRFLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
5, 12, 16
5, 12, 16
5, 12, 16
0
19–20
Figure 9
200
400
None
17–18
17–18
Figure 9
None
Table 4. 5V Output
DERATING CURVE
Figures 19, 20
V
(V)
POWER LOSS CURVE
Figure 10
AIRFLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
12, 16
12, 16
12, 16
0
19–20
Figures 19, 20
Figure 10
200
400
None
17–18
17–18
Figures 19, 20
Figure 10
None
Table 5. 8V Output
DERATING CURVE
Figure 21, 22
V
(V)
POWER LOSS CURVE
Figure 11
AIRFLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
5, 12
5, 12
5, 12
0
19–20
Figure 21, 22
Figure 11
200
400
None
17–18
17–18
Figure 21, 22
Figure 11
None
Table 6. 12V Output
DERATING CURVE
Figure 23
V
(V)
POWER LOSS CURVE
Figure 12
AIRFLOW (LFM)
HEAT SINK
None
IN
JA(°C/W)
5, 12
0
19–20
Figure 23
5, 12
5, 12
Figure 12
200
400
None
17–18
17–18
Figure 23
Figure 12
None
4622afa
19
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LTM4622A
APPLICATIONS INFORMATION
Table 7. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure 24)
1.0A Load Step Typical Measured Values
C
C
C
OUT2
IN
OUT1
(CERAMIC)
PART NUMBER
VALUE
(CERAMIC)
PART NUMBER
VALUE
(BULK) PART NUMBER
VALUE
Murata
GRM188R61E475KE11# 4.7µF, 25V, Murata
0603, X5R
GRM21R60J476ME15# 47µF, 6.3V, Panasonic 6TPC150M
0805, X5R
150µF, 6.3V 3.5
× 2.8 × 1.4mm
Murata
GRM188R61E106MA73# 10µF, 25V, Murata
0603, X5R
GRM188R60J226MEA0# 22µF, 6.3V,
0603, X5R
Taiyo Yuden TMK212BJ475KG-T
4.7µF, 25V, Taiyo
0805, X5R Yuden
JMK212BJ476MG-T
47µF, 6.3V,
0805, X5R
C
C
C
OUT2
P-P
DROOP DERIVATION RECOVERY
LOAD STEP
IN
OUT1
V
(CERAMIC)
(μF)
C
(CERAMIC) (BULK)
C
LOAD
TIME (μs) STEP (A)
SLEW RATE
(A/μs)
R
FB
OUT
IN
FF
(V)
1.5
1.5
2.5
2.5
3.3
3.3
5
(BULK)
(μF)
(μF)
(pF)
10
0
V
(V)
(mV)
(mV)
(kΩ)
40.2
40.2
19.1
19.1
13.3
13.3
8.25
8.25
4.87
4.87
3.16
3.16
IN
10
10
10
10
10
10
10
10
10
10
10
10
0
0
0
0
0
0
0
0
0
0
0
0
1 × 47
1 × 4.7
1 × 47
1 × 4.7
1 × 47
1 × 4.7
2 × 47
1 × 4.7
2 × 47
2 × 4.7
3 × 47
3 × 4.7
0
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
12
0
89
10
20
10
25
15
30
25
50
50
70
50
80
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
10
10
10
10
10
10
10
10
10
10
10
10
150
0
0
75
10
0
0
112
92
150
0
0
10
0
0
144
104
157
137
234
149
301
177
150
0
0
10
0
0
5
150
0
12
0
8
10
0
12
0
8
150
0
12
0
12
12
10
0
16
0
150
16
0
4622afa
20
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LTM4622A
APPLICATIONS INFORMATION
Figure 24 and Figure 25 show measured temperature
picture of the LTM4622A with no heat sink from 12V
input down to 3.3V and 5V output with 2A DC current on
each and from 12V down to 5V and 8V output with 2A
DC current on each. Both without heat sink and airflow.
and without airflow. The derived thermal resistances in
Tables 2 to 6 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves in
the Typical Performance Characteristics section and ad-
justed with the above ambient temperature multiplicative
factors. The printed circuit board is a 1.6mm thick four
layer board with two ounce copper for the two outer layers
and one ounce copper for the two inner layers. The PCB
dimensions are 95mm × 76mm.
SAFETY CONSIDERATIONS
The LTM4622A modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection.
4622afa
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LTM4622A
APPLICATIONS INFORMATION
Figure 24. Thermal Image, 12V Input, 3.3V and 5V Output,
2A Each, No Airflow and No Heat Sink
Figure 25. Thermal Image, 12V Input, 5V and 8V Output,
2A Each, No Airflow and No Heat Sink
4622afa
22
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LTM4622A
APPLICATIONS INFORMATION
LAYOUT CHECKLIST/EXAMPLE
•
Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
The high integration of LTM4622A makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout con-
siderations are still necessary.
•
•
Do not put via directly on the pad, unless they are
capped or plated over.
•
Use large PCB copper areas for high current paths,
including V , V , GND, V and V . It helps
Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
IN1 IN2
OUT1
OUT2
to minimize the PCB conduction loss and thermal
stress.
•
Forparallelmodules,tietheV ,V ,andCOMPpins
OUT FB
•
Placehighfrequencyceramicinputandoutputcapaci-
together. Useaninternallayertocloselyconnectthese
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
•
•
Place a dedicated power ground layer underneath
the unit.
•
Bringouttestpointsonthesignalpinsformonitoring.
Figure26givesagoodexampleoftherecommendedlayout.
Thetwodedicatedinputdecouplingcapacitors,onefor
each V , closely placed on each side of the module.
IN
ꢂꢃꢄ
ꢅ
ꢅ
ꢆꢇꢈ2
ꢆꢇꢈꢉ
ꢅ
ꢅ
ꢊꢃ2
ꢊꢃꢉ
4622ꢀ ꢁ26
Figure 26. Recommended PCB Layout
4622afa
23
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LTM4622A
APPLICATIONS INFORMATION
ꢕꢙꢌꢌꢚꢀ ꢕꢙꢌꢌꢚ2
ꢀꢍꢐꢅ
ꢇ
ꢌꢎꢋꢀ
ꢖꢎꢉꢀ
ꢇ
ꢌꢎꢋꢀ
ꢁꢂꢁ ꢏ 2ꢄ
ꢇ
ꢈꢉ
4ꢆꢐꢅ
ꢇ
ꢇ
ꢈꢉꢀ
ꢈꢉ2
ꢖꢎꢉ2
ꢈꢉꢋꢇ
ꢊꢇ ꢋꢌ 2ꢍꢇ
ꢇ
ꢌꢎꢋ2
ꢇ
ꢀꢍꢐꢅ
ꢌꢎꢋ2
ꢑ ꢏ 2ꢄ
ꢛꢋꢔ4622ꢄ
4ꢆꢐꢅ
ꢓꢌꢔꢕꢀ
ꢓꢌꢔꢕ2
ꢅꢒꢀ
ꢓꢓ
ꢜꢝꢉꢓꢞꢔꢌꢚꢗ
ꢋꢖꢄꢓꢟꢞꢜꢜꢀ
ꢋꢖꢄꢓꢟꢞꢜꢜ2
ꢅꢖꢗꢘ
ꢍꢂꢀꢐꢅ
ꢅꢒ2
ꢙꢉꢚ
ꢀꢁꢂꢁꢃ
ꢊꢂ2ꢑꢃ
4622ꢄ ꢅ2ꢆ
ꢍꢂꢀꢐꢅ
Figure 27. 8VIN to 20VIN, 3.3V and 5V Output at 2A Design
ꢔꢘꢇꢇꢚ
ꢔꢘꢇꢇꢚꢐ ꢔꢘꢇꢇꢚ2
ꢐꢏꢍꢄ
ꢆ
ꢇꢈꢉ
ꢆ
ꢇꢈꢉꢐ
ꢕꢈꢙꢐ
ꢊꢀꢊ ꢋ 4ꢃ
4ꢌꢍꢄ
ꢎ2ꢍꢄ
ꢆ
ꢜꢙ
ꢆ
ꢆ
ꢆ
ꢜꢙꢐ
ꢜꢙ2
ꢇꢈꢉ2
4ꢆ ꢉꢇ 2ꢏꢆ
ꢐꢏꢍꢄ
ꢒꢇꢓꢔꢐ
ꢒꢇꢓꢔ2
ꢕꢈꢙ2
ꢜꢙꢉꢆ
ꢛꢉꢓ4622ꢃ
ꢒꢒ
ꢝꢞꢙꢒꢟꢓꢇꢚꢖ
ꢉꢕꢃꢒꢠꢟꢝꢝꢐ
ꢉꢕꢃꢒꢠꢟꢝꢝ2
ꢄꢕꢖꢗ
ꢄꢑꢐ
ꢄꢑ2
ꢏꢀꢐꢍꢄ
6ꢀ6ꢁꢂ
ꢘꢙꢚ
4622ꢃ ꢄ2ꢅ
Figure 28. 4VIN to 20VIN, 3.3V Two Phase in Parallel 4A Design
ꢓꢗꢈꢈꢙꢂ ꢓꢗꢈꢈꢙ2
ꢂꢎꢍꢅ
ꢇ
ꢈꢉꢊꢂ
ꢔꢉꢘꢂ
ꢇ
ꢈꢉꢊꢂ
ꢂ2 ꢋ 2ꢄ
ꢇ
ꢛꢘ
4ꢌꢍꢅ
ꢇ
ꢇ
ꢛꢘꢂ
ꢛꢘ2
ꢔꢉꢘ2
ꢛꢘꢊꢇ
ꢂ6ꢇ ꢊꢈ 2ꢎꢇ
ꢇ
ꢈꢉꢊ2
ꢇ
ꢂꢎꢍꢅ
ꢈꢉꢊ2
ꢏ ꢋ 2ꢄ
ꢚꢊꢒ4622ꢄ
4ꢌꢍꢅ
ꢑꢈꢒꢓꢂ
ꢑꢈꢒꢓ2
ꢅꢐꢂ
ꢑꢑ
ꢜꢝꢘꢑꢞꢒꢈꢙꢕ
ꢊꢔꢄꢑꢟꢞꢜꢜꢂ
ꢊꢔꢄꢑꢟꢞꢜꢜ2
ꢅꢔꢕꢖ
ꢎꢁꢂꢍꢅ
ꢅꢐ2
ꢗꢘꢙ
4ꢁꢏꢌꢃ
ꢀꢁꢂ6ꢃ
ꢀ24ꢃ
ꢎꢁꢂꢍꢅ
4622ꢄ ꢅ2ꢆ
Figure 29. 16VIN to 20VIN, 12V and 8V Output at 2A with 2MHz Switching Frequency
4622afa
24
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LTM4622A
APPLICATIONS INFORMATION
ꢒꢖꢈꢈꢘꢂ ꢒꢖꢈꢈꢘ2
ꢂꢀꢃꢄ
ꢇ
ꢈꢉꢊꢂ
ꢇ
ꢓꢉꢗꢂ
ꢈꢉꢊꢂ
ꢂꢁꢌ ꢍ 2ꢋ
ꢇ
ꢚꢗ
4ꢎꢃꢄ
ꢇ
ꢇ
ꢚꢗꢂ
ꢚꢗ2
ꢓꢉꢗ2
ꢚꢗꢊꢇ
4ꢇ ꢊꢈ 2ꢀꢇ
ꢇ
ꢈꢉꢊ2
ꢇ
ꢈꢉꢊ2
ꢂꢀꢃꢄ
ꢅꢁꢅ ꢍ 2ꢋ
ꢙꢊꢑ4622ꢋ
4ꢎꢃꢄ
ꢐꢈꢑꢒꢂ
ꢐꢈꢑꢒ2
ꢐꢐ
ꢛꢜꢗꢐꢝꢑꢈꢘꢔ
ꢊꢓꢋꢐꢞꢝꢛꢛꢂ
ꢊꢓꢋꢐꢞꢝꢛꢛ2
ꢄꢓꢔꢕ
ꢄꢏꢂ
ꢄꢏ2
6ꢀꢁ4ꢆ
ꢇ
ꢈꢉꢊꢂ
4ꢀꢁ2ꢆ
ꢀꢁꢂꢃꢄ
ꢖꢗꢘ
ꢂꢅꢁꢅꢆ
4622ꢋ ꢄꢅꢀ
ꢂꢅꢁꢅꢆ
Figure 30. 4VIN to 20VIN, 1.5V and 3.3V Output at 2A Design with Output Coincident Tracking
ꢕꢙꢊꢊꢚ
ꢕꢙꢊꢊꢚꢀ ꢕꢙꢊꢊꢚ2
ꢇꢈꢀ
ꢆ
ꢆ
ꢆ
ꢆ
ꢊꢋꢉ
ꢇꢈ
ꢆ
ꢆ
ꢇꢈ2
ꢊꢋꢉꢀ
ꢊꢋꢉ2
ꢀꢌꢍ ꢎ ꢏꢐ
4ꢆ ꢉꢊ 2ꢁꢆ
4ꢑꢃꢄ
ꢅ4
ꢀꢁꢃꢄ
ꢅ4
ꢖꢋꢈꢀ
ꢖꢋꢈ2
ꢇꢈꢉꢆ
ꢜꢝꢈꢓꢞꢔꢊꢚꢗ
ꢉꢖꢐꢓꢟꢞꢜꢜꢀ
ꢉꢖꢐꢓꢟꢞꢜꢜ2
ꢄꢖꢗꢘ
ꢛꢉꢔ4622ꢐ
ꢓꢊꢔꢕꢀ
ꢓꢊꢔꢕ2
ꢓꢊꢔꢕ
ꢓꢓ
2ꢁꢁꢂ
ꢄꢒꢀ
ꢄꢒ2
ꢄꢒ
ꢀꢁꢂ
ꢛꢉꢓ6ꢡꢁ2
ꢙꢈꢚ
ꢢ
ꢇꢈꢉꢆ
ꢆ
ꢜꢗꢉ
ꢓꢓ
ꢀꢃꢄ
ꢚꢇꢆ
ꢔꢊꢚ
ꢙꢈꢚ
ꢕꢣ
ꢕꢙꢊꢊꢚ
ꢊꢋꢉꢀ
ꢊꢋꢉ2
ꢊꢋꢉ4
ꢊꢋꢉꢠ
ꢕꢙꢊꢊꢚꢀ ꢕꢙꢊꢊꢚ2
ꢇꢈꢀ
ꢆ
ꢆ
ꢆ
ꢆ
ꢇꢈ2
ꢊꢋꢉꢀ
ꢊꢋꢉ2
ꢖꢋꢈꢀ
ꢖꢋꢈ2
ꢇꢈꢉꢆ
ꢜꢝꢈꢓꢞꢔꢊꢚꢗ
ꢉꢖꢐꢓꢟꢞꢜꢜꢀ
ꢉꢖꢐꢓꢟꢞꢜꢜ2
ꢄꢖꢗꢘ
ꢛꢉꢔ4622ꢐ
ꢓꢊꢔꢕꢀ
ꢓꢊꢔꢕ2
ꢓꢊꢔꢕ
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4622ꢐ ꢄꢠꢀ
Figure 31. 4 Phase, 1.5V Output at 8A Design with LTC6902
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25
For more information www.linear.com/LTM4622A
LTM4622A
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4622A Component LGA and BGA Pinout
PIN ID
A1
FUNCTION
PIN ID
A2
FUNCTION
PIN ID
A3
FUNCTION
PIN ID
A4
FUNCTION
FB2
PIN ID
A5
FUNCTION
COMP2
GND
V
OUT2
V
OUT2
V
IN2
TRACK/SS2
B1
B2
RUN2
GND
B3
V
B4
PGOOD2
FREQ
B5
IN2
C1
GND
C2
C3
INTV
C4
C5
SYNC/MODE
GND
CC
D1
V
D2
RUN1
D3
V
IN1
D4
PGOOD1
FB1
D5
OUT1
OUT1
E1
V
E2
V
IN1
E3
TRACK/SS1
E4
E5
COMP1
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26
For more information www.linear.com/LTM4622A
LTM4622A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings.
ꢒ
ꢵ ꢵ ꢟ ꢟ ꢟ ꢒ
2 ꢛ ꢜ 4 ꢚ
ꢍ ꢛ 2 ꢝ ꢚ
ꢚ ꢛ ꢗ ꢍ ꢝ ꢜ
ꢚ ꢛ ꢚ ꢚ ꢚ
ꢚ ꢛ ꢗ ꢍ ꢝ
ꢍ ꢛ 2 ꢝ ꢚ
2 ꢛ ꢜ 4 ꢚ
4622afa
27
For more information www.linear.com/LTM4622A
LTM4622A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4622A#packaging for the most recent package drawings.
ꢒ
ꢒ
ꢵ ꢵ ꢨ ꢨ ꢨ ꢒ
2 ꢛ ꢜ 4 ꢚ
ꢍ ꢛ 2 ꢝ ꢚ
ꢚ ꢛ ꢗ ꢍ ꢝ ꢜ
ꢚ ꢛ ꢚ ꢚ ꢚ
ꢚ ꢛ ꢗ ꢍ ꢝ
ꢍ ꢛ 2 ꢝ ꢚ
2 ꢛ ꢜ 4 ꢚ
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28
For more information www.linear.com/LTM4622A
LTM4622A
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
11/17 Corrected Pin Configuration. Swapped V and V
.
IN2
2
IN1
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
29
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.linear.com/LTM4622A
LTM4622A
PACKAGE PHOTOS
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
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COMMENTS
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LTM4624
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4V ≤ V ≤ 14V, 0.6V ≤ V ≤ 5.5V, V
Tracking, PGOOD,
OUT
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IN
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20V , 5A Step-Down µModule Regulator
IN
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LTM4631
LTM4642
LTM4643
LTM4644
LTC6902
Ultrathin, Dual 10A Step-Down µModule Regulator 4.5V ≤ V ≤ 15V, 0.6V ≤ V
≤ 1.8V, 16mm × 16mm × 1.91mm LGA
≤ 5.5V, 9mm × 11.25mm × 4.92mm BGA
IN
OUT
OUT
20V , Dual 4A, Step-Down µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V
IN
IN
Ultrathin, Quad 3A, Step-Down µModule Regulator 4V ≤ V ≤ 20V, 0.6V ≤ V
≤ 3.3V, 9mm × 15mm × 1.82mm LGA
IN
OUT
Quad 4A, Step-Down µModule Regulator
4V ≤ V ≤ 14V, 0.6V to 5.5V, 9mm × 15mm × 5.01mm BGA
IN
Multiphase Oscillator with Spread Spectrum
Frequency Modulation
1-, 3-, or 4-Phase Outputs; to 20MHz Frequency
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LT 1117 REV A • PRINTED IN USA
www.linear.com/LTM4622A
30
ANALOG DEVICES, INC. 2017
相关型号：
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