LTM4627 [Linear]
15A DC/DC μModule Regulator; 15A DC / DC微型模块稳压器
| 型号： | LTM4627 |
| 厂家： | 
Linear |
| 描述： | 15A DC/DC μModule Regulator |
| 文件： | 总28页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4627
15A DC/DC µModule
Regulator
FEATURES
DESCRIPTION
The LTM®4627 is a complete 15A output high efficiency
switch mode DC/DC power supply. Included in the pack-
age are the switching controller, power FETs, inductor and
compensationcomponents.Operatingoveraninputvoltage
range from 4.5V to 20V, the LTM4627 supports an output
voltagerangeof0.6Vto5V,setbyasingleexternalresistor.
Only a few input and output capacitors are needed.
n
Complete 15A Switch Mode Power Supply
n
Wide Input Voltage Range: 4.5V to 20V
n
0.6V to 5V Output Range
n
1.5ꢀ ꢁotal DC Output Error (–40°C to 125°C)
n
Differential Remote Sense Amplifier for Precision
Regulation
n
Current Mode Control/ Fast ꢁransient Response
n
Frequency Synchronization
Current mode operation allows precision current sharing
of up to four LTM4627 regulators to obtain 60A output.
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase/current sharing
operation, BurstModeoperationandoutputvoltagetrack-
ing for supply rail sequencing.
n
Parallel Current Sharing (Up to 60A)
Selectable Pulse-Skipping or Burst Mode® Operation
n
n
Soft-Start/Voltage Tracking
Up to 93% Efficiency (12V , 3.3V
Overcurrent Foldback Protection
Output Overvoltage Protection
Small Surface Mount Footprint, Low Profile
15mm × 15mm × 4.32mm LGA Package
n
)
IN
OUT
n
n
n
The LTM4627 is offered in a thermally enhanced 15mm ×
15mm × 4.32mm LGA package. The LTM4627 is PB-free
and RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and μModule are registered
trademarks of Linear Technology Corporation. PolyPhase is a registered trademark of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589,
6774611, 6677210.
APPLICATIONS
n
Telecom Servers and Networking Equipment
n
ATCA and Storage Cards
n
Industrial Equipment
Medical Systems
n
TYPICAL APPLICATION
1.2V, 15A DC/DC μModule® Regulator
Efficiency vs Load Current
95
90
85
V
IN
4.5V TO 16V
22μF
16V
×3
150pF
10k
V
EXTV
CC
INTV
PGOOD
CC
IN
V
1.2V
15A
OUT
80
75
70
65
60
55
50
0.1μF
COMP
V
OUT
V
OUT_LCL
+
470μF
6.3V
TRACK/SS
RUN
LTM4627
GND
DIFF_OUT
+
100μF*
6.3V
82pF
f
V
V
SET
OSNS
–
100k
MODE_PLLIN
OSNS
V
12V , 1.2V
IN
OUT
FB
SGND
5V , 1.2V
IN OUT
R
**
FB
60.4k
0
2
4
6
8
10 12 14 16
*
SEE TABLE 4
4627 TA01a
LOAD CURRENT (A)
** SEE TABLE 1
4627 TA01b
4627f
1
LTM4627
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V ............................................................. –0.3V to 22V
IN
MODE_PLLIN
CC
INTV , V
(V
≤ 3.3V with
INTV
TRACK/SS COMP
CC OUT OUT
V
IN
1
2
3
4
5
6
7
8
9
10
11
12
DIFF AMP), V
, PGOOD, EXTV ....... –0.3V to 6V
OUT_LCL
CC
A
B
C
D
E
MODE_PLLIN, f , TRACK/SS,
RUN
SET
V
IN
–
+
f
SET
V
, V
FB
, DIFF_OUT...................–0.3V to INTV
OSNS
OSNS CC
COMP, V ................................................ –0.3V to 2.7V
INTV
CC
RUN (Note 5) ............................................... –0.3V to 5V
EXTV
CC
INTV Peak Output Current (Note 6)..................100mA
CC
PGOOD
F
V
FB
Internal Operating Temperature Range
GND
G
H
J
PGOOD
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Reflow (Peak Body) Temperature..........................250°C
SGND
+
V
OSNS
K
L
DIFF_OUT
V
OUT
V
OUT_LCL
–
M
V
OSNS
V
OUT
LGA PACKAGE
133-LEAD (15mm s 15mm s 4.32mm)
T
= 125°C, θ = 13°C/W, θ
= 2.3°C/W, θ
= 11°C/W to 13°C/W,
J(MAX)
JA
JCbottom
JCtop
θ
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.6g
JA
θ VALUES DETERMINED PER JESD51-12
ORDER INFORMATION
LEAD FREE FINISH
LTM4627EV#PBF
LTM4627IV#PBF
ꢁRAY
PARꢁ MARKING*
LTM4627V
PACKAGE DESCRIPꢁION
ꢁEMPERAꢁURE RANGE
–40°C to 125°C
LTM4627EV#PBF
LTM4627IV#PBF
133-Lead (15mm × 15mm × 4.32mm) LGA
133-Lead (15mm × 15mm × 4.32mm) LGA
LTM4627V
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS ꢁhe l denotes the specifications which apply over the full internal operating
temperature range, otherwise specifications are at ꢁA = 25°C (Note 2), VIN = 12V, per the typical application in Figure 18.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
4.5
ꢁYP
MAX
20
UNIꢁS
l
l
V
Input DC Voltage
V
V
IN
V
Output Voltage, Total
Variation with Line and Load
1.477
1.50
1.523
C
C
= 22μF × 3
OUT
OUT(DC)
IN
= 100μF Ceramic, 470μF POSCAP
= 40.2k, MODE_PLLIN = GND
R
FB
IN
V
= 5V to 20V, I
= 0A to 15A (Note 4)
OUT
Input Specifications
V
RUN Pin On Threshold
RUN Pin On Hysteresis
V
Rising
1.1
1.25
130
1.4
V
RUN
RUN
V
mV
RUNHYS
4627f
2
LTM4627
ELECTRICAL CHARACTERISTICS ꢁhe l denotes the specifications which apply over the full internal operating
temperature range, otherwise specifications are at ꢁA = 25°C (Note 2), VIN = 12V, per the typical application in Figure 18.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX
UNIꢁS
I
Input Supply Bias Current
V
V
V
= 12V, V
= 12V, V
= 12V, V
= 1.5V, Burst Mode Operation, I
= 1.5V, Pulse-Skipping Mode, I
= 1.5V, Switching Continuous, I
= 0.1A
= 0.1A
= 0.1A
17
25
54
40
mA
mA
mA
μA
Q(VIN)
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
Shutdown, RUN = 0, V = 12V
IN
I
Input Supply Current
V
V
= 5V, V
= 1.5V, I = 15A
OUT
OUT
5.05
2.13
A
A
S(VIN)
IN
IN
OUT
= 12V, V
= 1.5V, I
= 15A
OUT
Output Specifications
I
Output Continuous Current
Range
V
= 12V, V
= 1.5V (Note 4)
0
15
A
%/V
%
OUT(DC)
IN
OUT
l
l
ΔV
(Line)
OUT
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
Turn-On Overshoot
V
I
= 1.5V, V from 4.5V to 20V
OUT
= 0A
0.02
0.2
15
0.06
0.45
OUT
V
IN
OUT
ΔV
(Load)
OUT
V
= 1.5V, I
= 0A to 15A, V = 12V (Note 4)
OUT IN
OUT
V
OUT
V
I
= 0A, C
= 100μF Ceramic, 470μF POSCAP
= 1.5V
mV
P-P
OUT(AC)
OUT
OUT
OUT
V
= 12V, V
IN
ΔV
C
V
= 100μF Ceramic, 470μF POSCAP,
= 1.5V, I
20
mV
ms
mV
OUT(START)
OUTLS
OUT
OUT
= 0A, V = 12V
IN
OUT
t
Turn-On Time
C
= 100μF Ceramic, 470μF POSCAP,
50
START
OUT
No Load, TRACK/SS = 0.001μF, V = 12V
IN
ΔV
Peak Deviation for Dynamic Load: 0% to 50% to 0% of Full Load
Load
60
C
V
= 100μF Ceramic, 470μF POSCAP,
OUT
= 12V, V
= 1.5V
OUT
IN
t
I
Settling Time for Dynamic
Load Step
Load: 0% to 50% to 0% of Full Load V = 5V,
OUT
20
μs
SETTLE
IN
C
= 100μF Ceramic, 470μF POSCAP
Output Current Limit
V
IN
V
IN
= 12V, V = 1.5V
OUT
25
25
A
A
OUTPK
= 5V, V
= 1.5V
OUT
Control Section
l
l
V
Voltage at V Pin
I
= 0A, V = 1.5V
OUT
0.594
0.60
–12
0.606
–25
V
nA
V
FB
FB
OUT
I
FB
Current at V Pin
(Note 7)
FB
V
Feedback Overvoltage
Lockout
0.65
1.0
0.67
0.69
OVL
I
t
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
(Note 3)
1.2
1.4
μA
TRACK/SS
Minimum On-Time
90
ns
ON(MIN)
R
Resistor Between V
60.05
0
60.40
60.75
4
kΩ
FBHI
OUT_LCL
and V Pins
FB
+
–
V
V
,
Common Mode Input Range
V
IN
= 12V, Run > 1.4V
V
OSNS
OSNS CM RANGE
V
V
A
Maximum DIFF_OUT Voltage
Input Offset Voltage
Differential Gain
I
= 300μA
INTV – 1.4
V
mV
DIFF_OUT(MAX)
DIFF_OUT
+
CC
V
= V
= 1.5V, I = 100μA
DIFF_OUT
2
OS
V
OSNS
DIFF_OUT
1
2
V/V
V/μs
MHz
dB
SR
Slew Rate
GBP
CMRR
Gain Bandwidth Product
Common Mode Rejection
DIFF_OUT Current
3
(Note 7)
Sourcing
60
I
2
mA
DIFF_OUT
4627f
3
LTM4627
ELECTRICAL CHARACTERISTICS ꢁhe l denotes the specifications which apply over the full internal operating
temperature range, otherwise specifications are at ꢁA = 25°C (Note 2), VIN = 12V, per the typical application in Figure 18.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
5V < V < 20V (Note 7)
MIN
ꢁYP
MAX
UNIꢁS
PSRR
Power Supply Rejection
Ratio
100
dB
IN
R
Input Resistance
PGOOD Trip Level
V
V
+ to GND
OSNS
80
kΩ
IN
V
With Respect to Set Output
PGOOD
FB
V
V
–10
10
%
%
Ramping Negative
Ramping Positive
FB
FB
V
PGOOD Voltage Low
I
= 2mA
PGOOD
0.1
0.3
5.2
V
PGL
INꢁV Linear Regulator
CC
V
V
V
Internal V Voltage
6V < V < 20V
4.8
4.5
5
V
%
INTVCC
INTVCC
EXTVCC
CC
IN
Load Reg INTV Load Regulation
I
= 0 to 50mA
CC
0.5
4.7
50
CC
l
External V Switchover
EXTV Ramping Positive
V
CC
CC
VLDO Ext
EXTV Voltage Drop
I
= 25mA, V = 5V
EXTVCC
100
mV
CC
CC
Oscillator and Phase-Locked Loop
f
SYNC Capture Range
Nominal Frequency
250
450
800
550
kHz
kHz
SYNC
Frequency
Nominal
V
= 1.2V
500
fSET
Frequency Low
Frequency High
Lowest Frequency
Highest Frequency
Frequency Set Current
V
V
= 1V
350
700
9
400
770
10
450
850
11
kHz
kHz
μA
fSET
≥ 2.4V
fSET
I
FREQ
R
Mode_PLLIN Input
Resistance
250
kΩ
MODE_PLLIN
V
V
Clock Input Level High
Clock Input Level Low
2.0
V
V
IH_MODE_PLLIN
IL_MODE_PLLIN
0.8
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: The minimum on-time condition is specified for a peak-to-peak
Note 2: The LTM4627 is tested under pulsed load conditions such that
inductor ripple current of ~40% of I
Information section)
Load. (See the Applications
MAX
T ≈ T . The LTM4627E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4627I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
Note 4: See output current derating curves for different V , V
and T .
A
IN OUT
Note 5: Limit current into the RUN pin to less than 2mA.
Note 6: Guaranteed by design.
Note 7: 100% tested at wafer level.
4627f
4
LTM4627
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
with 8VIN
Efficiency vs Load Current
with 12VIN
Efficiency vs Load Current
with 5VIN
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
1V
AT 400kHz
1V
AT 400kHz
AT 400kHz
OUT
OUT
OUT
1V
OUT
AT 400kHz
1.2V
1.5V
2.5V
3.3V
5V
AT 400kHz
AT 400kHz
AT 500kHz
AT 600kHz
1.2V
1.5V
2.5V
3.3V
5V
OUT
OUT
OUT
OUT
1.2V
1.5V
2.5V
3.3V
AT 400kHz
AT 400kHz
AT 400kHz
AT 650kHz
AT 400kHz
AT 650kHz
AT 650kHz
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AT 600kHz
AT 700kHz
OUT
OUT
0
2
4
6
8
10 12 14 16
LOAD CURRENT (A)
0
2
4
6
8
10 12 14 16
LOAD CURRENT (A)
0
2
4
6
8
10 12 14 16
LOAD CURRENT (A)
4627 G01
4627 G02
4627 G03
Burst Mode Efficiency
Pulse-Skipping Mode Efficiency
1.0V ꢁransient Response
1.0
0.9
0.8
0.7
0.6
0.5
0.4
1.0
0.9
0.8
0.7
0.6
0.5
0.4
5V , 2.5V
IN
OUT
5V , 2.5V
Burst Mode OPERATION
PULSE-SKIPPING MODE
IN
OUT
50mV/DIV
12V , 2.5V
Burst Mode OPERATION
IN
OUT
7.5A
LOAD STEP
12V , 2.5V
IN
OUT
4627 G06
PULSE-SKIPPING MODE
100μs/DIV
V
= 12V, V
= 1.0V, C = 82pF, C
= 33pF
COMP
IN
OUT
FF
OUTPUT CAPACITOR = 5 s 100μF CERAMIC X5R
0.1
0.2
0.5
1
1.5
2
0.1
0.2
0.5
1
1.5
2
LOAD CURRENT (A)
LOAD CURRENT (A)
4627 G04
4627 G05
1.2V ꢁransient Response
1.5V ꢁransient Response
1.8V ꢁransient Response
50mV/DIV
50mV/DIV
50mV/DIV
7.5A
LOAD STEP
7.5A
LOAD STEP
7.5A
LOAD STEP
4627 G07
4627 G08
4627 G09
100μs/DIV
100μs/DIV
100μs/DIV
V
= 12V, V
= 1.2V, C = 82pF, C = 33pF
COMP
V
= 12V, V
= 1.5V, C = 82pF, C
= 33pF
V
= 12V, V
= 1.8V, C = 82pF, C
= 33pF
COMP
IN
OUT
FF
IN
OUT
FF
COMP
IN
OUT
FF
OUTPUT CAPACITOR = 5 s 100μF CERAMIC X5R
OUTPUT CAPACITOR = 5 s 100μF CERAMIC X5R
OUTPUT CAPACITOR = 4 s 100μF CERAMIC X5R
4627f
5
LTM4627
TYPICAL PERFORMANCE CHARACTERISTICS
2.5V ꢁransient Response
3.3V ꢁransient Response
5.0V ꢁransient Response
50mV/DIV
50mV/DIV
50mV/DIV
7.5A
LOAD STEP
7.5A
LOAD STEP
7.5A
LOAD STEP
4627 G12
4627 G10
4627 G11
100μs/DIV
100μs/DIV
100μs/DIV
V
= 12V, V
= 5V, C = 82pF, C = 33pF
COMP
V
= 12V, V
= 2.5V, C = 82pF, C = 33pF
COMP
V
= 12V, V
= 3.3V, C = 82pF, C = 33pF
COMP
IN
OUT
FF
IN
OUT
FF
IN
OUT
FF
OUTPUT CAPACITOR = 2 s 100μF CERAMIC X5R
OUTPUT CAPACITOR = 4 s 100μF CERAMIC X5R
OUTPUT CAPACITOR = 2 s 100μF CERAMIC X5R
Start-Up with Soft-Start
Short-Circuit Protection No Load
Short-Circuit Protection 15A Load
V
OUT
V
OUT
V
I
OUT
OUT
500mV/DIV
1A/DIV
500mV/DIV
5A/DIV
500mV/DIV
1A/DIV
I
IN
I
IN
4627 G15
4627 G14
4627 G13
4ms/DIV
4ms/DIV
100μs/DIV
V
= 12V, V
= 1.5V, I
= 15A
OUT
V
= 12V, V
= 1.5V, I
= 0A
OUT
V
= 12V, V
= 1.5V, I
= 15A
OUT
IN
OUT
IN
OUT
IN
OUT
INPUT CAP 150μF SANYO ELECTROLYTIC CAP
AND 22μF s 2 X5R CERAMIC CAP
OUTPUT CAP 1 s 100μF X5R CERAMIC AND 470μF
0.1μF CAP FROM TRACK/SS TO GND
PIN FUNCTIONS
PGOOD(F11,G12):OutputVoltagePowerGoodIndicator.
Open-drain logic output that is pulled to ground when the
output voltage exceeds a 10% regulation window. Both
pins are tied together internally.
V (A1-A6, B1-B6, C1-C6):PowerInputPins. Applyinput
IN
voltage between these pins and GND pins. Recommend
placing input decoupling capacitance directly between V
pins and GND pins.
IN
SGND(G11,H11,H12):SignalGroundPin.Returnground
path for all analog and low power circuitry. Tie a single
connection to the output capacitor GND in the application.
See layout guidelines in Figure 17.
V
(J1-J10, K1-K11, L1-L11, M1-M11): Power Output
OUꢁ
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. Review Table 4.
GND (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,
H1-H9): Power Ground Pins for Both Input and Output
Returns.
4627f
6
LTM4627
PIN FUNCTIONS
RUN:(A10)RunControlPin.Avoltageabove1.4Vwillturn
on the module. A 5.1V Zener diode to ground is internal
to the module for limiting the voltage on the RUN pin to
MODE_PLLIN(A8):ForcedContinuousMode,BurstMode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
5V, and allowing a pull-up resistor to V for enabling the
Connect this pin to INTV to enable pulse-skipping mode
IN
CC
device. Limit current into the RUN pin to ≤ 2mA.
ofoperation.Connecttogroundtoenableforcedcontinuous
modeofoperation.FloatingthispinwillenableBurstMode
operation. A clock on this pin will enable synchronization
with forced continuous operation. See the Applications
Information section.
INꢁV : (A7, D9) Internal 5V LDO for Driving the Control
CC
Circuitry and the Power MOSFET Drivers. Both pins are
internally connected. The 5V LDO has a 100mA current
limit.
f
(B12): A resistor can be applied from this pin to
SEꢁ
EXꢁV (E12): External power input to an internal control
CC
ground to set the operating frequency, or a DC voltage
can be applied to set the frequency. See the Applications
Information section.
switchallowsanexternalsourcegreaterthan4.7V,butless
than6VtosupplyICpowerandbypasstheinternalINTV
LDO. See the Applications Information section.
CC
ꢁRACK/SS (A9): Output Voltage Tracking Pin and Soft-
Start Inputs. The pin has a 1.2μA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. See the Applications
Information section.
V
: (L12) This pin connects to V
through a 1M
OUT
OUꢁ_LCL
resistor, and to V with a 60.4k resistor. The remote sense
FB
amplifier output DIFF_OUT is connected to V
, and
OUT_LCL
drives the 60.4k top feedback resistor in remote sensing
applications. When the remote sense amplifier is used,
DIFF_OUT effectively eliminates the 1MΩ from V
to
OUT
V
. When the remote sense amplifier is not used,
OUT_LCL
then connect V
to V
directly.
OUT_LCL
OUT
+
V
: (J12) (+) Input to the Remote Sense Amplifier.
OSNS
V
(F12): The Negative Input of the Error Amplifier.
FB
This pin connects to the output remote sense point. The
Internally, this pin is connected to V
with a
OUT_LCL
remote sense amplifier is used for V
≤ 3.3V.
OUT
60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between V
–
V
: (M12) (–) Input to the Remote Sense Amplifier.
OSNS
FB
and ground pins. In PolyPhase® operation, tying the
This pin connects to the ground remote sense point. The
remote sense amplifier is used for V ≤ 3.3V.
OUT
V
pins together allows for parallel operation. See the
FB
Applications Information section for details.
DIFF_OUꢁ: (K12) Output of the Remote Sense Amplifier.
This pin connects to the V
applications. Otherwise float when not used.
pin for remote sense
OUT_LCL
COMP(A11):CurrentControlThresholdandErrorAmplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together for parallel operation. The device is internally
compensated.
MꢁP1, MꢁP2, MꢁP3, MꢁP4, MꢁP5, MꢁP6, MꢁP7, MꢁP8
(A12, B11, C10, C11, C12, D10, D11, D12):Extramount-
ing pads used for increased solder integrity strength.
Leave floating.
4627f
7
LTM4627
BLOCK DIAGRAM
INTV
CC
V
OUT_LCL
V
OUT
10k
1M
V
IN
PGOOD
> 1.4V = ON
< 1.1V = OFF
MAX = 5V
R1
R2
V
IN
RUN
V
IN
4.5V TO 20V
+
+
1.5μF
C
IN
5.1V
COMP
60.4k
M1
M2
INTERNAL
COMP
0.4μH
V
OUT
V
OUT
1V
SGND
POWER
CONTROL
15A
10μF
C
OUT
V
FB
f
SET
GND
90.9k
R
fSET
100k
INTERNAL
LOOP
FILTER
INTV
CC
C SOFT-START
TRACK/SS
V
–
MODE_PLLIN
–
OSNS
+
–
DIFF
AMP
250k
V
+
+
OSNS
INTV
EXTV
CC
CC
C
DIFF_OUT
4627 F01
Figure 1. Simplified LꢁM4627 Block Diagram
DECOUPLING REQUIREMENTS ꢁA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
66
ꢁYP
MAX
UNIꢁS
C
External Input Capacitor Requirement
I
= 15A
μF
IN
OUT
(V = 4.5V to 20V, V
= 1.5V)
OUT
IN
C
OUT
External Output Capacitor Requirement
(V = 4.5V to 20V, V = 1.5V)
I
= 15A
200
μF
OUT
IN
OUT
4627f
8
LTM4627
OPERATION
Power Module Description
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
The LTM4627 is a high performance single output stand-
alone nonisolated switching mode DC/DC power supply.
It can provide a 15A output with few external input and
outputcapacitors.Thismoduleprovidespreciselyregulated
output voltages programmable via external resistors from
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for program-
ming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
0.6V to 5V over a 4.5V to 20V input range. The typical
DC
DC
application schematic is shown in Figure 18.
The LTM4627 is internally compensated to be stable over
all operating conditions. Table 4 provides a guideline for
input and output capacitances for several operating con-
ditions. The Linear Technology μModule Power Design
Tool will be provided for transient and stability analysis.
TheLTM4627hasanintegratedconstant-frequencycurrent
moderegulator,powerMOSFETs,0.4μHinductor,andother
supportingdiscretecomponents.Theswitchingfrequency
range is from 400kHz to 800kHz, and the typical operating
frequency is 500kHz. For switching noise-sensitive appli-
cations, it can be externally synchronized from 400kHz to
800kHz.Asingleresistorisusedtoprogramthefrequency.
See the Applications Information section.
The V pin is used to program the output voltage with a
FB
single external resistor to ground.
Aremotesenseamplifierisprovidedforaccuratelysensing
output voltages ≤3.3V at the load point.
With current mode control and internal feedback loop
compensation, the LTM4627 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE_PLLIN
pin. These light load features will accommodate battery
operation. Efficiency graphs are provided for light load
operation in the Typical Performance Characteristics
section.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
4627f
9
LTM4627
APPLICATIONS INFORMATION
The typical LTM4627 application circuit is shown in Fig-
ure 18. External component selection is primarily deter-
mined by the maximum load current and output voltage.
RefertoTable4forspecificexternalcapacitorrequirements
for particular applications.
For parallel operation of N LTM4627s, the following equa-
tion can be used to solve for R :
FB
60.4 /N
RFB=
V
0.6
OUT
–1
Tie the V pins together for each parallel output. The
FB
V to V
Step-Down Ratios
IN
OUꢁ
COMP pins must be tied together also.
There are restrictions in the V to V
step-down ratio
IN
OUT
Input Capacitors
that can be achieved for a given input voltage. The V to
IN
V
OUT
minimum dropout is a function of load current and
The LTM4627 module should be connected to a low
AC-impedance DC source. Additional input capacitors
are needed for the RMS input ripple current rating. The
at very low input voltage and high duty cycle applications
output power may be limited as the internal top power
MOSFET is not rated for 15A operation at higher ambient
temperatures. At very low duty cycles the minimum 90ns
on-time must be maintained. See the Frequency Adjust-
ment section and temperature derating curves.
I
equation which follows can be used to calculate
CIN(RMS)
the input capacitor requirement. Typically 22μF X7R ce-
ramics are a good choice with RMS ripple current ratings
of ~ 2A each. A 47μF to 100μF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long in-
ductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
Output Voltage Programming
The PWM controller has an internal 0.6V 1% reference
voltage. As shown in the Block Diagram, a 60.4k internal
feedback resistor connects the V
and V pins
OUT_LCL
FB
together. When the remote sense amplifier is used, then
DIFF_OUT is connected to the V pin. If the remote
OUT_LCL
For a buck converter, the switching duty cycle can be
estimated as:
sense amplifier is not used, then V
connects to
OUT_LCL
V
. The output voltage will default to 0.6V with no feed-
OUT
back resistor. Adding a resistor R from V to ground
V
OUT
VIN
FB
FB
D=
programs the output voltage:
60.4k +RFB
Without considering the inductor ripple current, for each
V
OUT = 0.6V •
RFB
output, the RMS current of the input capacitor can be
estimated as:
ꢁable 1. VFB Resistor ꢁable vs Various Output Voltages
(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3
Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25
IOUT(MAX)
V
5.0
OUꢁ
ICIN(RMS)
=
• D•(1–D)
η%
R
(k)
FB
Inthepreviousequation,η%istheestimatedefficiencyofthe
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor or a Polymer capacitor.
4627f
10
LTM4627
APPLICATIONS INFORMATION
Output Capacitors
greater than the load requirement. As the COMP voltage
drops below 0.5V, the burst comparator trips, causing
the internal sleep line to go high and turn off both power
MOSFETs.
The LTM4627 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
are
OUT
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP to rise, the internal
sleep line goes low, and the LTM4627 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
ments. C
canbealowESRtantalumcapacitor, lowESR
OUT
Polymercapacitororceramiccapacitors.Thetypicaloutput
capacitancerangeisfrom200μFto800μF.Additionaloutput
filtering may be required by the system designer if further
reduction of output ripple or dynamic transient spikes is
required.Table4showsamatrixofdifferentoutputvoltages
and output capacitors to minimize the voltage droop and
overshoot during a 7A/μs transient. The table optimizes
totalequivalentESRandtotalbulkcapacitancetooptimize
thetransientperformance.Stabilitycriteriaareconsidered
in the Table 4 matrix, and the Linear Technology μModule
Power Design Tool will be provided for stability analysis.
Multiphase operation will reduce effective output ripple
as a function of the number of phases. Application Note
77 discusses this noise reduction versus output ripple
current cancellation, but the output capacitance should be
consideredcarefullyasafunctionofstabilityandtransient
response. The Linear Technology μModule Power Design
Toolcancalculatetheoutputripplereductionasthenumber
of implemented phase’s increases by N times.
Pulse-Skipping Mode Operation
In applications where low output ripple and high effi-
ciencyatintermediatecurrentsaredesired,pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4627 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTV enables pulse-skipping
CC
operation. With pulse-skipping mode at light load, the
internalcurrentcomparatormayremaintrippedforseveral
cycles,thusskippingoperationcycles.Thismodehaslower
ripple than Burst Mode operation and maintains a higher
frequency operation than Burst Mode operation.
Forced Continuous Operation
Burst Mode Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4627’s output
voltage is in regulation.
The LTM4627 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enableBurstModeoperation,simplyfloattheMODE_PLLIN
pin. During Burst Mode operation, the peak current of the
inductorissettoapproximately30%ofthemaximumpeak
current value in normal operation even though the voltage
at the COMP pin indicates a lower value. The voltage at the
COMP pin drops when the inductor’s average current is
4627f
11
LTM4627
APPLICATIONS INFORMATION
Multiphase Operation
The relationship of f voltage to switching frequency is
SET
shown in Figure 3. For low output voltages from 0.8V to
1.5V,400kHzoperationisanoptimalfrequencyforthebest
powerconversionefficiencywhilemaintainingtheinductor
current to about 30% to 40% of maximum load current.
For output voltages from 1.8V to 3.0V, 500kHz to 600kHz
is optimal. For output voltages from 3.0V to 5.0V, 750kHz
operation is optimal, but due to the higher ripple current
at 5V operation the output current is limited to 10A.
For outputs that demand more than 15A of load current,
multiple LTM4627 devices can be paralleled to provide
more output current without increasing input and output
voltage ripple. The MODE_PLLIN pin allows the LTM4627
to be synchronized to an external clock (between 400kHz
to 800kHz) and the internal phase-locked loop allows the
LTM4627 to lock onto input clock phase as well. The f
SET
resistorisselectedfornormalfrequency,thentheincoming
clock can synchronize the device over the specified range.
See Figure 20 for a synchronizing example circuit.
TheLTM4627canbesynchronizedfrom400kHzto800kHz
with an input clock that has a high level above 2V and
a low level below 0.8V. The 400kHz low end operation
limit is put in place to limit inductor ripple current. See the
TypicalApplicationssectionforsynchronizationexamples.
TheLTM4627minimumon-timeislimitedtoapproximately
90ns. Guardband the on-time to 130ns. The on-time can
be calculated as:
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used. See Application Note 77.
⎛
⎜
⎝
⎞
⎟
⎠
VOUT
VIN
1
tON(MIN)
=
•
FREQ
The LTM4627 device is an inherently current mode con-
trolled device, so parallel modules will have good current
sharing. This will balance the thermals in the design. Tie
Output Voltage ꢁracking
Output voltage tracking can be programmed externally
usingtheTRACK/SSpin. Theoutputcanbetrackedupand
downwithanotherregulator.Themasterregulator’soutput
is divided down with an external resistor divider that is the
sameastheslaveregulator’sfeedbackdividertoimplement
coincident tracking. The LTM4627 uses an accurate 60.4k
resistor internally for the top feedback resistor. Figure 4
shows an example of coincident tracking.
the COMP and V pins of each LTM4627 together to
FB
share the current evenly. Figure 20 shows a schematic of
the parallel design.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases
(see Figure 2).
⎛
⎞
⎟
⎠
60.4k
RTA
VOUT(SLAVE) = 1+
• VTRACK
⎜
⎝
V
TRACK
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
TRACK
V
PLL, Frequency Adjustment and Synchronization
TheLTM4627switchingfrequencyissetbyaresistor(R
)
)
fSET
FREQ
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
from the f pin to signal ground. A 10μA current (I
SET
flowingoutofthef pinthroughR
developsavoltage
SET
fSET
on f . R
can be calculated as:
SET fSET
FREQ(kHz)
4.5
RfSET(kΩ)=
+ 2kHz
4627f
12
LTM4627
APPLICATIONS INFORMATION
0.60
1 PHASE
2 PHASE
0.55
3 PHASE
4 PHASE
6 PHASE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
OUT IN
4627 F02
Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six μModule Regulators (Phases)
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
f
PIN VOLTAGE (V)
SET
4627 F03
Figure 3. Relationship Between Switching
Frequency and Voltage at the fSEꢁ Pin
4627f
13
LTM4627
APPLICATIONS INFORMATION
its final value from the slave’s regulation point. Voltage
hasacontrolrangefrom0Vto0.6V.Themaster’sTRACK/SS
pin slew rate is directly equal to the master’s output slew
rate in volts/time. The equation:
tracking is disabled when V
is more than 0.6V. R in
TRACK
TA
Figure 4 will be equal to the R for coincident tracking.
FB
The TRACK/SS pin of the master can be controlled by an
external ramp or the soft-start function of that regulator
canbeusedtodevelopthatmasterramp.TheLTM4627can
be used as a master by setting the ramp rate on its track
pin using a soft-start capacitor. A 1.2μA current source
is used to charge the soft-start capacitor. The following
equation can be used:
MR
SR
•60.4k = RTB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in volts/time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal to 60.4k. R is derived from equation:
TB
TA
CSS
1.2µA
⎛
⎞
0.6V
tSOFT-START = 0.6 •
⎜
⎝
⎟
⎠
RTA =
VTRACK
RTB
VFB
VFB
60.4k RFB
+
–
Ratiometric tracking can be achieved by a few simple
calculationsandtheslewratevalueappliedtothemaster’s
TRACK/SS pin. As mentioned above, the TRACK/SS pin
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.6V. Since R is equal to the 60.4k
TB
TRACK
V
6V
IN
TO 16V
C7
22μF
16V
C10
22μF
16V
150pF
SOFT-START
CAPACITOR
C9
PGOOD
V
EXTV
INTV
CC CC
IN
22μF
16V
V
OUT2
COMP
V
C
OUT
R2
10k
SS
1.5V AT 15A
+
C8
470μF
6.3V
C11
100μF
6.3V
TRACK/SS
RUN
V
OUT_LCL
LTM4627
DIFF_OUT
+
82pF
f
V
V
SET
OSNS
R4
100k
–
MODE_PLLIN
OSNS
V
FB
SGND
GND
R
FB1
40.2k
V
6V
IN
TO 16V
MASTER RAMP
OR OUTPUT
C3
22μF
16V
C2
22μF
16V
150pF
PGOOD
V
EXTV
INTV
CC CC
IN
V
1.2V
15A
C1
22μF
16V
OUT1
R
TB
R
TA
COMP
V
OUT
60.4k
60.4k
R1
10k
+
C4
470μF
6.3V
C6
100μF
6.3V
TRACK/SS
RUN
V
OUT_LCL
LTM4627
DIFF_OUT
+
82pF
f
V
V
SET
OSNS
R3
100k
–
MODE_PLLIN
OSNS
V
FB
SGND
GND
R
FB
60.4k
4627 F04
Figure 4. Dual Outputs (1.5V and 1.2V) with ꢁracking
4627f
14
LTM4627
APPLICATIONS INFORMATION
top feedback resistor of the slave regulator in equal slew
electronic circuit breaker or fuse can be sized to be tripped
or cleared when the bottom MOSFET is turned on to pro-
tect against the overvoltage. Foldback current limiting is
disabled during soft-start or tracking start-up.
rate or coincident tracking, then R is equal to R with
TA
FB
V
= V
. Therefore R = 60.4k, and R = 60.4k in
TRACK TB TA
FB
Figure 4.
Inratiometrictracking, adifferentslewratemaybedesired
Run Enable
for the slave regulator. R can be solved for when SR is
TB
The RUN pin is used to enable the power module or
sequence the power module. The threshold is 1.25V, and
the pin has an internal 5.1V Zener to protect the pin. The
RUN pin can be used as an undervoltage lockout (UVLO)
function by connecting a resistor divider from the input
supply to the RUN pin:
slower than MR. Make sure that the slave supply slew rate
ischosentobefastenoughsothattheslaveoutputvoltage
will reach its final value before the master output.
For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then R
TB
= 75k. Solve for R to equal 51.1k.
TA
For applications that do not require tracking or sequenc-
V
UVLO
= ((R1+R2)/R2) • 1.25V.
ing, simply tie the TRACK/SS pin to INTV to let RUN
CC
See the Block Diagram for the example of use.
control the turn on/off. When the RUN pin is below its
thresholdortheV undervoltagelockout,thenTRACK/SS
IN
INꢁV Regulator
CC
is pulled low.
The LTM4627 has an internal low dropout regulator from
V
IN
called INTV . This regulator output has a 4.7μF
CC
ceramic capacitor internal. This regulator powers the
internal controller and MOSFET drivers. The gate driver
currentis~20mAfor750kHzoperation. Theregulatorloss
can be calculated as:
MASTER OUTPUT
OUTPUT
VOLTAGE
SLAVE OUTPUT
(VIN– 5V)•20mA =PLOSS
EXTV external voltage source ≥ 4.7V can be applied to
CC
4627 F05
this pin to eliminate the internal INTV LDO power loss
TIME
CC
and increase regulator efficiency. A 5V supply can be
applied to run the internal circuitry and power MOSFET
driver. If unused, leave pin floating.
Figure 5. Output Voltage Coincident ꢁracking
Overcurrent and Overvoltage Protection
Stability Compensation
The LTM4627 has overcurrent protection (OCP) in a short
circuit. The internal current comparator threshold folds
back during a short to reduce the output current. An
overvoltage condition (OVP) above 10% of the regulated
output voltage will force the top MOSFET off and the bot-
tom MOSFET on until the condition is cleared. An input
The module has already been internally compensated
for all output voltages. Table 4 is provided for most ap-
plication requirements. The Linear Technology μModule
Power Design Tool will be provided for other control loop
optimization.
4627f
15
LTM4627
APPLICATIONS INFORMATION
ꢁhermal Considerations and Output Current Derating
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
μModulepackagemountedtoahardwaretestboard—also
defined by JESD51-9 (“Test Boards for Area Array Surface
MountPackageThermalMeasurements”).Themotivation
for providing these thermal coefficients in found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
3 θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical μModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the μModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
4 θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
of the μModule and into the board, and is really the
sum of the θ
and the thermal resistance of the
JCbottom
bottomofthepartthroughthesolderjointsandthrough
a portion of the board. The board temperature is mea-
sured a specified distance from the package, using a
two sided, two layer board. This board is described in
JESD 51-9.
A graphical representation of the aforementioned thermal
resistances is given in Figure 6; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the μModule.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coef-
ficients are quoted or paraphrased below:
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operatingconditionsofaμModule.Forexample,innormal
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sivelythroughthetoporexclusivelythroughbottomofthe
1 θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. Thisvalueisdeterminedwiththepartmountedto
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
μModule—asthestandarddefinesforθ
andθ
,
JCtop
JCbottom
respectively.Inpractice,powerlossisthermallydissipated
inbothdirectionsawayfromthepackage—granted, inthe
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
2 θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the package.
In the typical μModule, the bulk of the heat flows out
the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
Within a SIP (system-in-package) module, be aware there
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
4627f
16
LTM4627
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
A
t
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
80421 F05
μMODULE DEVICE
Figure 6. Graphical Representation of JESD 51-12 ꢁhermal Coefficients
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the μModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9topredictpowerlossheatflowandtemperature
readingsatdifferentinterfacesthatenablethecalculationof
theJEDEC-definedthermalresistancevalues;(3)themodel
and FEA software is used to evaluate the μModule with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
process and due-diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory test have been performed and correlated to the
θ + θ value is shown in the Pin Configuration section
JB
BA
and should accurately equal the θ value because ap-
JA
proximately 100% of power loss flows from the junction
through the board into ambient with no airflow or top
mounted heat sink.
The 1.2V and 3.3V power loss curves in Figures 7 and 8
can be used in coordination with the load current derating
curves in Figures 9 to 16 for calculating an approximate
θ thermal resistance for the LTM4627 with various heat
JA
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors according to the ambient tempera-
ture. These approximate factors are: 1 for 40°C; 1.05 for
50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 15A and the ambient temperature at 40°C. The
output voltages are 1.2V, and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derivedfromseveraltemperaturemeasurementsinacon-
trolledtemperaturechamberalongwiththermalmodeling
analysis. The junction temperatures are monitored while
ambienttemperatureisincreasedwithandwithoutairflow.
Thepowerlossincreasewithambienttemperaturechange
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the inter-
μModulemodel,thentheθ andθ aresummedtogether
JB
BA
to correlate quite well with the μModule model with no
airflow or heat sinking in a properly define chamber. This
4627f
17
LTM4627
APPLICATIONS INFORMATION
nal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
Figure 11 the load current is derated to ~12A at ~80°C with
no air or heat sink and the power loss for the 12V to 1.2V
at 12A output is about 2.8W. The 2.8W loss is calculated
with the ~2.35W room temperature loss from the 12V to
1.2V power loss curve at 12A, and the 1.2 multiplying
factor at 80°C ambient. If the 80°C ambient temperature
is subtracted from the 120°C junction temperature, then
the difference of 40°C divided by 2.8W equals a 14°C/W
thermal resistances for 1.2V and 3.3V outputs with and
without airflow and heat sinking. The derived thermal re-
sistances in Tables 2 and 3 for the various conditions can
be multiplied by the calculated power loss as a function
of ambient temperature to derive temperature rise above
ambient, thus maximum junction temperature. Room
temperaturepowerlosscanbederivedfromtheefficiency
curves in the Typical Performance Characteristics section
andadjustedwiththeaboveambienttemperaturemultipli-
cative factors. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sinks
are listed in Table 4.
θ
thermal resistance. Table 2 specifies a 13°C/W value
JA
which is very close. Table 2 and Table 3 provide equivalent
6
3.0
5V TO 1.2V
POWER LOSS
POWER LOSS
OUT
5V TO 3.3V
POWER LOSS
POWER LOSS
OUT
IN
OUT
IN
OUT
12V TO 1.2V
12V TO 3.3V
IN
IN
5
4
2.5
2.0
3
2
1.5
1.0
1
0
0.5
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4627 F08
4627 F07
Figure 7. 1.2VOUꢁ Power Loss
Figure 8. 3.3VOUꢁ Power Loss
16
16
14
12
10
8
14
12
10
8
6
6
4
4
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
2
2
0
0
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F10
40
40 50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F09
Figure 9. 5VIN to 1.2VOUꢁ No Heat Sink
Figure 10. 5VIN to 1.2VOUꢁ with Heat Sink
4627f
18
LTM4627
APPLICATIONS INFORMATION
16
14
12
10
8
16
14
12
10
8
6
6
4
4
0 LFM
200 LFM
400 LFM
0 LFM
2
2
200 LFM
400 LFM
0
0
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F12
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F10
40
40
Figure 11. 12VIN to 1.2VOUꢁ No Heat Sink
Figure 12. 12VIN to 1.2VOUꢁ with Heat Sink
14
12
10
8
14
12
10
8
6
6
4
4
0 LFM
200 LFM
0 LFM
200 LFM
2
2
400 LFM
0
400 LFM
0
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F13
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F14
40
40
Figure 13. 5VIN to 3.3VOUꢁ No Heat Sink
Figure 14. 5VIN to 3.3VOUꢁ with Heat Sink
16
16
14
12
10
8
14
12
10
8
6
6
4
4
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
2
2
0
0
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F15
50 60 70 80 90 100 110 120 130
AMBIENT TEMPERATURE (°C)
4627 F16
40
40
Figure 15. 12VIN to 3.3VOUꢁ No Heat Sink
Figure 16. 12VIN to 3.3VOUꢁ with Heat Sink
4627f
19
LTM4627
APPLICATIONS INFORMATION
ꢁable 2. 1.2V Output
DERAꢁING
CURVE
POWER LOSS
AIRFLOW
(LFM)
V
CURVE
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
HEAꢁ SINK
None
θ
JA
(°C/W)
IN
Figures 9, 11
Figures 9, 11
Figures 9, 11
Figures 10, 12
Figures 10, 12
Figures 10, 12
5V, 12V
5V, 12V
5V, 12V
5V, 12V
5V, 12V
5V, 12V
0
13
11
8
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
12
8
200
400
7
ꢁable 3. 3.3V Output
DERAꢁING
CURVE
POWER LOSS
CURVE
AIRFLOW
(LFM)
V
HEAꢁ SINK
None
θ
JA
(°C/W)
IN
Figures 13, 15
Figures 13, 15
Figures 13, 15
Figures 14, 16
Figures 14, 16
Figures 14, 16
5V, 12V
5V, 12V
5V, 12V
5V, 12V
5V, 12V
5V, 12V
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
Figure 8
0
13
11
8
200
400
0
None
None
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
12
8
200
400
7
4627f
20
LTM4627
APPLICATIONS INFORMATION
ꢁable 4. Output Voltage Response vs Component Matrix (Refer to Figure 18) 0A to 7.5A Load Step
C
AND C
C
AND C
OUꢁ2
C
IN
OUꢁ1
OUꢁ2
OUꢁ1
CERAMIC VENDOR
VALUE
PARꢁ NUMBER
BULK VENDOR
VALUE
PARꢁ NUMBER BULK VENDOR VALUE PARꢁ NUMBER
TDK
22μF 6.3V
22μF 16V
C3216X7SOJ226M
Sanyo POSCAP
1000μF 2.5V 2R5TPD1000M5
Sanyo
56μF 25V
25SVP56M
Murata
GRM31CR61C226KE15L Sanyo POSCAP
470μF 2.5V
470μF 6.3V
2R5TPD470M5
6TPD470M
Sanyo POSCAP
Sanyo POSCAP
TDK
100μF 6.3V C4532X5ROJ107MZ
100μF 6.3V GRM32ER60J107M
Murata
PEAK ꢁO
PEAK
LOAD
V
C
C
C
OUꢁ2
(CERAMIC) AND
C
C
V
DROOP DEVIAꢁION RECOVERY SꢁEP
R
FB
FREQ.
(kHz)
OUꢁ
IN
IN
OUꢁ1
FF
COMP
IN
(V)
(V) (CERAMIC) (BULK)**
C
(CER AND BULK) (pF)
(pF)
150
150
33
(mV)
(mV)
100
100
108
80
ꢁIME(μs)
(A/μs)
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
(kΩ)
90.9
90.9
90.9
60.4
60.4
60.4
60.4
40.2
40.2
40.2
40.2
30.1
30.1
30.1
19.1
19.1
13.3
13.3
8.25
8.25
1
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
56μF
68
82
82
82
82
82
82
82
82
82
82
68
82
82
82
82
82
82
68
47
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
12
50
30
400
400
400
400
400
400
400
400
400
400
400
400
400
400
500
500
600
600
700
700
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
22μF × 3
100μF × 2, 1000μF
1
50
20
100μF × 2, 470μF × 2
100μF × 4
1
52
18
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
3.3
3.3
5
150
150
150
33
40
20
100μF × 2, 1000μF
100μF, 470μF
100μF × 2, 470μF × 2
100μF × 4
60
120
80
20
40
25
50
114
120
130
120
130
130
135
132
164
200
200
200
250
250
20
150
47
60
23
100μF × 2, 1000μF
100μF, 470μF
100μF × 2, 470μF × 2
100μF × 3
67
20
150
33
60
25
65
20
150
150
none
none
150
none
150
none
150
64
25
100μF × 2, 1000μF
100μF, 470μF
100μF × 2
76
22
66
20
88
30
100μF × 2
100μF, 470μF
100μF × 2
100
100
100
125
125
25
30
100μF, 470μF
100μF × 2
30
20
5
470μF
12
25
** Bulk capacitance is optional if V has very low input impedance.
IN
HEAꢁ SINK MANUFACꢁURER
Wakefield Engineering
AAVID Thermalloy
PARꢁ NUMBER
WEBSIꢁE
LTN20069
www.wakefield.com
www.aavidthermalloy.com
375424B00034G
4627f
21
LTM4627
APPLICATIONS INFORMATION
Safety Considerations
• Place a dedicated power ground layer underneath the
unit.
The LTM4627 modules do not provide isolation from V
IN
to V . There is no internal fuse. If required, a slow blow
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
OUT
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic
failure. The device does support overvoltage protection
and overcurrent protection.
• Do not put vias directly on the pad, unless they are
capped or plated over.
Layout Checklist/Example
• Place test points on signal pins for testing.
The high integration of the LTM4627 makes the PCB
board layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout con-
siderations are still necessary.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• For parallel modules, tie the COMP and V pins to-
FB
• Use large PCB copper areas for high current paths,
gether. Use an internal layer to closely connect these
pins together. Figure 17 gives a good example of the
recommended layout.
including V , GND and V . It helps to minimize the
IN
OUT
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
tors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
V
IN
CONTROL
C
C
IN
IN
GND
SIGNAL
GROUND
C
C
OUT
OUT
V
V
OUT
OUT
4627 F17
Figure 17. Recommended PCB Layout
4627f
22
LTM4627
TYPICAL APPLICATIONS
V
IN
4.5V TO 20V
C3
C2
C
COMP
22μF
25V
22μF
25V
150pF
C1
PGOOD
V
EXTV
INTV
CC CC
22μF
25V
IN
C7
V
1.5V
15A
OUT
R1
10k
0.1μF
COMP
V
OUT
V
OUT_LCL
+
C
C
*
OUT1
OUT2
TRACK/SS
RUN
470μF
6.3V
s2
100μF
6.3V
LTM4627
DIFF_OUT
+
C
FF
82pF
f
V
V
SET
OSNS
R3
120k
–
MODE_PLLIN
OSNS
CONTINUOUS
MODE
V
FB
SGND
GND
R
FB
40.2k
4627 TA02
*SEE TABLE 4
Figure 18. 4.5V to 20VIN, 1.5V at 15A Design
4627f
23
LTM4627
TYPICAL APPLICATIONS
4627f
24
LTM4627
TYPICAL APPLICATIONS
V
IN
7V TO 16V
V
OUT
INTV
CC
1.2V AT 60A
C22
22μF
16V
V
EXTV
INTV
CC CC
PGOOD
IN
C28
0.1μF
C20
22μF
16V
R1
10k
COMP
V
OUT
+
C21
470μF
6.3V
C24
100μF
6.3V
TRACK/SS
RUN
V
OUT_LCL
LTM4627
DIFF_OUT
+
270pF
f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
V
100k
100k
100k
100k
FB
SGND
GND
R
FB2
15k
INTV
CC
R2
100k
4-PHASE CLOCK
+
150pF
SET
V
LTC6902
C2
1μF
MOD
DIV
PH
C18
22μF
16V
GND
V
EXTV
INTV
CC
PGOOD
IN
CC
C14
22μF
16V
OUT4
OUT3
OUT1
OUT2
COMP
V
OUT
+
C15
C18
TRACK/SS
RUN
V
OUT_LCL
470μF
6.3V
100μF
6.3V
LTM4627
DIFF_OUT
+
f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
V
INTV
CC
FB
SGND
GND
C9
22μF
16V
V
EXTV
INTV
PGOOD
CC
IN
CC
C7
22μF
16V
COMP
V
OUT
+
C8
C11
100μF
6.3V
TRACK/SS
RUN
V
OUT_LCL
470μF
6.3V
LTM4627
DIFF_OUT
+
f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
V
INTV
CC
FB
SGND
GND
150pF
C1
22μF
16V
V
EXTV
INTV
CC CC
PGOOD
IN
C3
22μF
16V
COMP
V
OUT
+
C4
470μF
6.3V
C6
100μF
6.3V
TRACK/SS
RUN
V
OUT_LCL
LTM4627
DIFF_OUT
+
f
V
V
SET
OSNS
–
MODE_PLLIN
OSNS
V
INTV
CC
FB
SGND
GND
4627 TA04
Figure 20. 1.2V, 60A, Current Sharing with 4-Phase Operation
4627f
25
LTM4627
PACKAGE DESCRIPTION
Pin Assignment ꢁable
(Arranged by Pin Number)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
E1 GND
PIN NAME
F1 GND
A1
A2
A3
A4
A5
A6
V
V
V
V
V
V
B1
B2
B3
B4
B5
B6
V
V
V
V
V
V
C1
C2
C3
C4
C5
C6
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
D1 GND
D2 GND
D3 GND
D4 GND
D5 GND
D6 GND
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
E2 GND
E3 GND
E4 GND
E5 GND
E6 GND
E7 GND
F2 GND
F3 GND
F4 GND
F5 GND
F6 GND
F7 GND
F8 GND
F9 GND
A7 INTV
B7 GND
A8 MODE_PLLIN B8
C7 GND
C8
D7
-
CC
-
-
D8 GND
D9 INTV
E8
-
A9 TRACK/SS
A10 RUN
B9 GND
B10
B11 MTP2
B12
C9 GND
C10 MTP3
C11 MTP4
C12 MTP5
E9 GND
CC
-
D10 MTP6
D11 MTP7
D12 MTP8
E10
E11
-
-
F10
F11 PGOOD
F12
-
A11 COMP
A12 MTP1
f
E12 EXTV
V
FB
SET
CC
PIN NAME
G1 GND
G2 GND
G3 GND
G4 GND
G5 GND
G6 GND
G7 GND
G8 GND
G9 GND
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
H1 GND
H2 GND
H3 GND
H4 GND
H5 GND
H6 GND
H7 GND
H8 GND
H9 GND
J1
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
-
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
V
V
V
V
V
V
V
V
V
V
V
V
M1
M2
M3
M4
M5
M6
M7
M8
M9
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT_LCL
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OSNS
J2
J3
J4
J5
J6
J7
J8
J9
G10
-
H10
-
J10
J11
J12
M10 V
M11 V
M12 V
G11 SGND
H11 SGND
H12 SGND
+
–
G12 PGOOD
V
K12 DIFF_OUT L12
OSNS
PACKAGE PHOTO
4627f
26
LTM4627
PACKAGE DESCRIPTION
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4627f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM4627
TYPICAL APPLICATION
3.3V at 10A Design
5V
C3
C2
22μF
16V
22μF
16V
PGOOD
V
EXTV
INTV
CC CC
IN
V
3.3V
10A
C7
OUT
C1
22μF
16V
0.1μF
COMP
V
OUT
R1
10k
C4
100μF
X5R
C6
TRACK/SS
RUN
V
OUT_LCL
100μF
X5R
6.3V
LTM4627
DIFF_OUT
+
82pF
f
V
V
SET
OSNS
5V
R3
174k
–
MODE_PLLIN
OSNS
V
CONTINUOUS
MODE
FB
SGND
GND
R
C5
47pF
FB
13.3k
4627 TA05
RELATED PARTS
PARꢁ NUMBER
DESCRIPꢁION
COMMENꢁS
Basic 10A DC/DC μModule
LTM4600
10A DC/DC μModule Regulator
LTM4601A
12A DC/DC μModule Regulator with PLL,
Output Tracking/ Margining and Remote Sensing
Synchronizable, PolyPhase Operation to 48A, Pin Compatible with the
LTM4627
LTM4602
LTM4603
6A DC/DC μModule Regulator
Pin Compatible with the LTM4600
6A DC/DC μModule Regulator with PLL and
Output Tracking/Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No
Remote Sensing, Pin Compatible with the LTM4601
LTM4604A
4A Low Voltage DC/DC μModule Regulator
2.375V ≤ V ≤ 5.5V; 0.8V ≤ V
≤ 5V,
OUT
IN
9mm × 15mm × 2.3mm (Ultrathin) LGA Package
LTM4605
LTM4606
LTM4607
LTM4608A
LTM4609
LTM4612
LTM8023
LTM8032
Buck-Boost DC/DC μModule Family
Ultralow Noise 6A DC/DC μModule Regulator
Buck-Boost DC/DC μModule Family
8A Low Voltage DC/DC μModule Regulator
Buck-Boost DC/DC μModule Family
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
OUT
IN
4.5V ≤ V ≤ 28V, 0.6V ≤ V
≤ 5V, 15mm × 15mm × 2.8mm Package
OUT
IN
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
IN
OUT
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V; 9mm × 15mm × 2.8mm LGA Package
IN
OUT
All Pin Compatible; Up to 5A; Up to 36V , 34V
15mm × 15mm × 2.8mm
IN
OUT
Ultralow Noise High V
DC/DC μModule Regulator
5A, 5V ≤ V ≤ 36V, 3.3V ≤ V
≤ 15V, 15mm × 15mm × 2.8mm Package
OUT
IN
OUT
36V, 2A DC/DC μModule Regulator
3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, 9mm × 11.75mm × 2.8mm Package
OUT
IN
Ultralow Noise 36V, 2A DC/DC μModule Regulator
EN55022 Class B Compliant; 0.8V ≤ V
≤ 10V; 3.6V ≤ V ≤ 36V;
OUT IN
9mm × 15mm × 2.8mm
4627f
LT 0810 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTM4628EV#PBF
LTM4628 - Dual 8A or Single 16A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
Linear
LTM4628IV#PBF
LTM4628 - Dual 8A or Single 16A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
Linear
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