LTM4642EY#PBF [Linear]
LTM4642 - 20VIN, Dual 4A or Single 8A DC/DC µModule Regulator; Package: BGA; Pins: 56; Temperature Range: -40°C to 85°C;型号: | LTM4642EY#PBF |
厂家: | Linear |
描述: | LTM4642 - 20VIN, Dual 4A or Single 8A DC/DC µModule Regulator; Package: BGA; Pins: 56; Temperature Range: -40°C to 85°C 开关 输出元件 |
文件: | 总32页 (文件大小:1100K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4642
20V , Dual 4A or Single 8A
IN
DC/DC µModule Regulator
FeaTures
DescripTion
TheLTM®4642isacompletedual4Aorsingle8Astep-down
DC/DCμModule® (micromodule)regulator.Includedinthe
packagearetheswitchingcontroller,powerFETs,inductor,
and all support components. Operating over input voltage
ranges of 4.5V to 20V, (2.375V min with external CPWR
bias), the LTM4642 supports two outputs with voltage
ranges of 0.6V to 5.5V, set by a single external resistor.
Its high efficiency design delivers 4A continuous current
(5A peak) for each output.
n
Small Form Factor Dual 4A Power Supply
n
Wide Input Voltage Range: 4.5V to 20V
(2.375V Min with CPWR Bias)
n
Dual 180° Out-of-Phase Outputs with 4A DC
n
Dual Outputs with 0.6V to 5.5V Range
n
Output Voltage Tracking
n
1.5ꢀ Maꢁimum Total DC Output Voltage Error
n
Up to 95ꢀ Maꢁimum Efficiency
n
Phase-Lockable Fiꢁed Frequency 600kHz to 1.4MHz
n
Constant On-Time, Valley Current Mode Architecture
High switching frequency and a valley current mode
architecture enable a very fast transient response to line
and load changes without sacrificing stability. The two
outputs are interleaved with 180° phase to minimize the
ripple noise and reduce the I/O capacitors.
Selectable Burst Mode® Operation
n
n
Output Overvoltage and Overcurrent Protection
n
9mm × 11.25mm × 4.92mm BGA Package
applicaTions
The power module is offered in a 9mm × 11.25mm ×
4.92mm BGA package. The LTM4642 is RoHS compliant
with Pb-free finish.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule and LTpowerCAD
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066,
6476589, 6774611, 8163643.
n
Telecom and Networking Equipment
n
Servers
n
FPGA Power
Typical applicaTion
Dual 4A 1V and 1.2V DC/DC µModule Regulator
2.2Ω
INTV
CC
V
Efficiency vs Load Current at 12V input
IN
4.75V TO 20V
4.7µF
22µF
2×
133k
V
90
1.2V (650kHz)
V
CPWR
DRV INTV
CC
IN1 IN2
CC
V
RNG1
RUN1
RUN2
85
10k 10k
1V (650kHz)
PGOOD1
PGOOD2
TRACK/SS1
0.1µF
80
V
1V AT 4A LOAD
OUT1
OUT2
V
V
OUT1
OUT2
TRACK/SS2
+
V
1.2V AT 4A LOAD
47µF
100µF
0.1µF
LTM4642
75
70
+
47µF
100µF
FREQ
INTV
MODE/PLLIN
CC
V
OUTS1
–
2.7
LOAD CURRENT (A)
3
0
0.5
1
1.5
2
3.5
4
V
OUTS
61.9k
V
FB2
4642 TA01b
470pF
470pF
V
OUT1
V
OUT2
V
FB1
SGND
GND
90.9k
60.4k
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
4642 TA01a
4642fb
1
For more information www.linear.com/LTM4642
LTM4642
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
1
2
3
4
5
6
7
V
, V , SW1, SW2, CPWR .................... –0.3V to 22V
IN1 IN2
SW2
INTV , DRV , PGOOD1,2, RUN1,2, EXTV ,
A
B
C
D
E
GND
PHASMD
CC
CC
CC
V
RUN2
OUT2
V
, V (Note 4) ....................–0.3V to INTV + 0.3V
FB1 FB2
CC
V
IN2
COMP1, COMP2 (Note 4).......................... –0.3V to 2.7V
V
TRACK/SS2 CPWR
MODE/PLLIN
GND
FB2
MODE/PLLIN, FREQ, PHASMD,
PGOOD2
COMP2 CLKOUT
EXTV
CC
V
V
V
.........................................–0.3V to INTV + 0.3V
CC
RNG1
INTV
SGNDCOMP1 FREQ
–
GND
V
GND DRV
CC
CC
, V
, V
................................... –0.3V to 6V
OUT1 OUT2 OUTS1
OUTS
–
.......................................................0.3V to 2.75V
V
V
PGOOD1
GND
V
OUTS FB1
OUTS1
F
TK/SS1, TK/SS2............................................. 0.3V to 5V
Internal Operating Temperature Range
(Note 2).................................................. –40°C to 125°C
Maximum Reflow Body Temperature.................... 245°C
Storage Temperature Range .................. –55°C to 125°C
V
TRACK/SS1
RUN1
SW1
RNG1
OUT1
V
G
H
IN1
GND
BGA Package
56-Lead (9mm × 11.25mm × 4.92mm)
T
= 125°C, θ = 15°C/W, θ = 4°C/W
JA JP
JMAX
θ
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
JA
WEIGHT = 1.2635g
http://www.linear.com/product/LTM4642#orderinfo
orDer inForMaTion
PART MARKING*
PACKAGE
MSL
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTM4642EY#PBF
LTM4642IY#PBF
LTM4642IY
PAD OR BALL FINISH
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
TYPE
BGA
BGA
BGA
RATING
LTM4642Y
LTM4642Y
LTM4642Y
e1
e1
e0
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
• Consult Marketing for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures: www.linear.com/umodule/pcbassembly
• Terminal Finish Part Marking: www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings: www.linear.com/packaging
elecTrical characTerisTics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.375
0.6
TYP
MAX
20
UNITS
l
l
V
V
V
Input DC Voltage
Output Voltage Range
V
V
C
≤ 4.5V, Connect CPWR to a Bias > 4.5V
= 6V to 20V
V
V
IN(DC)
IN
IN
IN
5.5
OUT1,2(RANGE)
OUT1,2(DC)
Output Voltage, Total Variation
with Line and Load
= 10µF ×2, C
= 47µF Ceramic, 100µF POSCAP,
OUT
R
= 40.2kΩ
IN
SET
V
l
= 12V, V
= 1.5V, I = 4A
OUT
1.4775
1.5 1.5225
0.25
V
OUT
Input Specifications
Input Inrush Current at Start-Up
I
I
= 0A, C = 10µF, C
= 47µF Ceramic and 100µF
INRUSH(VIN)
OUT
IN
OUT
POSCAP, V
= 1.5V
A
OUT
V
= 12V
IN
4642fb
2
For more information www.linear.com/LTM4642
LTM4642
elecTrical characTerisTics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
CPWR Bias Current
Input Supply Bias Current
CPWR = 12V, MODE = Continuous
20
mA
CPWR
Q(VIN)
V
V
V
V
= 12V, V
= 12V, V
= 20V, V
= 20V, V
= 1.5V, Switching Continuous
= 1.5V, Switching Continuous
= 1.5V, Switching Continuous
= 1.5V, Switching Continuous
25
25
22
22
10
mA
mA
mA
mA
µA
IN
IN
IN
IN
OUT1
OUT2
OUT1
OUT2
Shutdown, RUN = 0, V = 12V
IN
I
Input Supply Bias Current
V
IN
V
IN
= 12V, V
= 20V, V
= 1.5V, I
= 1.5V, I
= 4A
= 4A
0.6
0.356
A
A
Q(VIN)
OUT
OUT
OUT
OUT
DRV
Internal V Voltage
6V < V < 20V, No Load
5
5.3
–1.5
200
4.6
5.6
–3
V
%
CC
CC
IN
I
DRV Load Regulation
I
= 0 to 100mA
DRVCC
DRVCC(REG)
CC
EXTV
EXTV
EXTV Switchover Hysteresis
mV
V
CC(HYS)
CC
CC
EXTV Switchover Voltage
EXTV Ramping Positive
4.4
0
4.8
CC
CC
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V = 1.5V (Note 5)
OUT
4
A
OUT1,2(DC)
IN
l
l
ΔV
OUT1(LINE)
= 1.5V, V from 4.5V to 20V,
0.1
0.3
0.2
%
OUT
OUT
IN
I
= 0A For Each Output
V
OUT(NOM)
ΔV
OUT2(LOAD)
Load Regulation Accuracy
Output Ripple Voltage
For Each Output, V
= 1.5V, 0A to 4A (Note 5)
OUT
V
= 12V
0.5
%
IN
V
OUT2(NOM)
V
I
= 0A, C
= 100µF X5R Ceramic
OUT
OUT1,2(AC)
OUT
V
= 12V, V
= 20V, V
= 1.5V
= 1.5V
15
15
mV
mV
IN
IN
OUT
OUT
V
f
Output Ripple Voltage Frequency
Turn-On Overshoot
I
= 2A, V = 12V, V = 1.5V,
OUT
800
kHz
S
OUT
IN
FREQ = 49.9k to Ground
ΔV
C
I
= 100µF and 47µF X5R Ceramic, V
= 0A
= 1.5V,
= 1.5V,
OUT(START)
OUT
OUT
OUT
V
= 12V
= 20V
10
10
mV
mV
IN
IN
V
t
Turn-On Time
C
I
= 100µF X5R and 47µF Ceramic, V
OUT
START
OUT
= 0A Resistive Load, TRACK/SS = 10nF
OUT
V
IN
= 12V
6
ms
mV
µs
ΔV
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
OUT(LS)
C
= 100µF and 47µF X5R Ceramic, V
IN
= 1.5V,
= 1.5V,
OUT
V
OUT
= 12V
50
15
t
I
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
C
SETTLE
= 100µF and 47µF X5R Ceramic, V
IN
OUT
V
OUT
= 12V
Output Current Limit
C
= 100µF and 47µF X5R Ceramic,
OUT(PK)
OUT
V
= 6V, V
= 1.5V
OUT
7
7
A
A
IN
IN
V
= 20V, V
= 1.5V
OUT
Control Section
l
V
Regulated Differential Feedback
Sensed at Load Point with Resistive Divider
0.592
0.592
0.6
0.608
V
OUTS1(REG)
–
V
V
V
V
-V
OUTS1 OUTS
I
I
I
Input Bias Current
(Note 4)
(Note 4)
(Note 4)
5
–25
–5
25
–50
nA
nA
nA
V
VOUTS1
OUTS1
–
–
Input Bias Current
VOUTS
OUTS
Input Bias Current
FB2
50
VFB2
l
V
Voltage at V Pin
I
= 0A, V = 2.5V
OUT
0.6
0.608
FB2
FB2
OUT
4642fb
3
For more information www.linear.com/LTM4642
LTM4642
elecTrical characTerisTics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.0
97
MAX
UNITS
µA
%
I
Soft-Start Charge Current
Maximum Duty Factor
Minimum On-Time
0V < TRACK/SS1,2 < 0.6V
In Dropout (Note 4)
(Note 4)
TRACK/SS1,2
DF
MAX
ON(MIN)
OFF(MIN)
LOW
t
t
f
f
f
30
ns
Minimum Off-Time
(Note 4)
90
ns
Low Frequency
R
R
R
= 61.9k
= 49.9k
= 27.5k
600
730
650
800
700
850
kHz
kHz
kHz
kΩ
V
FREQ
FREQ
FREQ
Nominal Frequency
NOM
Highest Frequency
1250
1400 1500
600
HIGH
R
MODE/PLLIN Input Resistance
MODE/PLLIN Clock In High
MODE/PLLIN Clock In Low
RUN Pin ON/OFF Threshold
RUN1, 2, Threshold Hysteresis
MODE/PLLIN
PLLIN(HIGH)
PLLIN(LOW)
RUN1, 2
V
V
V
V
2
0.5
V
l
RUN Rising
1.1
1.2
200
1.2
5
1.3
V
Delta RUN Rising to RUN Falling
mV
µA
µA
kΩ
RUN1, 2(HYS)
RUN1,2
I
I
RUN Pin Pull-Up Current When Off RUN1,2 at SGND
RUN1,2 Pull-Up Hysteresis
RUN1,2 Resistance to Ground
Undervoltage Lockout
I
= I
– I
(Note 4)
RUN1,2(OFF)
RUN1,2(HYS)
RUN1,2(HYST)
RUN1,2(ON)
RUN1,2 Res
UVLO
100
l
l
INTV Falling (Note 4)
3.3
3.7
4.2
V
V
CC
INTV Rising
4.5
CC
R
, R
FB1 FB2
Resistor Between V
and V
FB
60.1
60.4
60.7
kΩ
OUT
Pins for Each Channel
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Range
V
µA
PGOOD
PGOOD
ΔV
V
V
Ramping Negative
Ramping Positive
–5
5
–7.5
7.5
–10
10
%
%
PGOOD
FB
FB
Ch 2 Phase
Channel 2 Phase (Relative to
Channel 1)
PHASMD = SGND
180
180
240
Deg
Deg
Deg
PHASMD = Floating
PHASMD = INTV
CC
CLKOUT Phase CLKOUT Phase (Relative to
Channel 1)
PHASMD = SGND
60
90
120
Deg
Deg
Deg
PHASMD = Floating
PHASMD = INTV
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 3: The two outputs are tested separately and the same testing
Note 2: The LTM4642E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4642I is guaranteed to meet specifications over the full
internal operating temperature range. Note that the maximum ambient
condition is applied to each output.
Note 4: 100% tested at wafer level only.
Note 5: See Output Current Derating curves for different V , V
Note 6: Consult factory for operation down at 2.375V to 2.5V input.
and T .
A
IN OUT
Operating frequency nominal will be reduced.
4642fb
4
For more information www.linear.com/LTM4642
LTM4642
Typical perForMance characTerisTics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
Efficiency vs Load Current at
3.3VIN, CCM Mode, Eꢁternal 5V
Bias
Efficiency vs Load Current at
5VIN, CCM Mode
Efficiency vs Load Current at
12VIN, CCM Mode
100
98
96
94
92
90
88
86
84
100
95
90
85
80
75
70
100
95
90
85
80
75
70
12V TO 5V (1.2MHz)
12V TO 3.3V (1MHz)
12V TO 2.5V (1MHz)
12V TO 1.8V (800kHz)
12V TO 1.5V (800kHz)
12V TO 1.2V (650kHz)
12V TO 1V (650kHz)
5V TO 3.3V (800kHz)
3.3V TO 2.5V (600kHz)
3.3V TO 1.8V (600kHz)
3.3V TO 1.5V (600kHz)
3.3V TO 1.2V (600kHz)
3.3V TO 1V (600kHz)
5V TO 2.5V (800kHz)
5V TO 1.8V (750kHz)
5V TO 1.5V (650kHz)
5V TO 1.2V (650kHz)
5V TO 1V (650kHz)
2
2.5
2
2.5
2
2.5
0
0.5
1
1.5
3
3.5
4
0
0.5
1
1.5
3
3.5
4
0
0.5
1
1.5
3
3.5
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4642 G01
4642 G02
4642 G02
3.3VIN to 1VOUT Transient
Response
Efficiency vs Load Current at
20VIN, CCM Mode
5VIN to 1VOUT Transient Response
100
95
90
85
80
75
70
65
60
IN
OUT
IN
OUT
20V TO 5V (1.2MHz)
20V TO 3.3V (1MHz)
20V TO 2.5V (1MHz)
1V
1V
OUT
OUT
20mV/DIV
20mV/DIV
I
= 2A/µs
2A/DIV
I
= 2A/µs
2A/DIV
STEP
STEP
4642 G05
4642 G06
20µs/DIV
= 100µF 15mΩ ESR POSCAP,
20µs/DIV
= 100µF 15mΩ ESR POSCAP,
20V TO 1.8V (800kHz)
20V TO 1.5V (800kHz)
20V TO 1.2V (650kHz)
20V TO 1V (650kHz)
C
C
OUT
OUT
47µF CERAMIC
47µF CERAMIC
C
f
= 470pF
= 600kHz
C
f
= 470pF
= 650kHz
FF
FF
SW
SW
2
2.5
0
0.5
1
1.5
3
3.5
4
LOAD CURRENT (A)
4642 G04
12VIN to 1VOUT Transient
Response
3.3VIN to 1.5VOUT Transient
Response
5VIN to 1.5VOUT Transient
Response
IN
OUT
IN
OUT
IN
OUT
1V
1.5V
1.5V
OUT
50mV/DIV
OUT
OUT
20mV/DIV
50mV/DIV
I
=
STEP
I
= 2A/µs
2A/DIV
I
= 2A/µs
2A/DIV
STEP
STEP
2A/µs
2A/DIV
4642 G07
4642 G08
4642 G09
20µs/DIV
= 100µF 15mΩ ESR POSCAP,
20µs/DIV
= 120µF 22mΩ ESR OSCON SVP,
20µs/DIV
= 120µF 22mΩ ESR OSCON SVP,
C
C
C
OUT
OUT
OUT
47µF CERAMIC
47µF CERAMIC
47µF CERAMIC
C
= 470pF
= 650kHz
C
= 470pF
= 600kHz
C
f
= 470pF
= 650kHz
FF
FF
FF
f
f
SW
SW
SW
4642fb
5
For more information www.linear.com/LTM4642
LTM4642
Typical perForMance characTerisTics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
12VIN to 1.5VOUT Transient
Response
3.3VIN to 2.5VOUT Transient
Response
5VIN to 2.5VOUT Transient
Response
IN
OUT
IN
OUT
IN
OUT
1.5V
2.5V
2.5V
OUT
100mV/DIV
OUT
OUT
50mV/DIV
100mV/DIV
I
=
STEP
I
I
I
= 2A/µs
2A/DIV
I
= 2A/µs
2A/DIV
STEP
STEP
2A/µs
2A/DIV
4642 G10
4642 G11
4642 G14
4642 G17
4642 G12
20µs/DIV
= 120µF 22mΩ ESR OSCON SVP,
20µs/DIV
20µs/DIV
C
C
C
SW
= 47µF CERAMIC
C
C
SW
= 47µF CERAMIC
OUT
OUT
OUT
47µF CERAMIC
= 68pF
= 68pF
FF
FF
C
= 470pF
= 800kHz
f
= 600kHz
f
= 800kHz
FF
f
SW
12VIN to 2.5VOUT Transient
Response
5VIN to 3.3VOUT Transient
Response
12VIN to 3.3VOUT Transient
Response
IN
OUT
IN
OUT
IN
OUT
2.5V
100mV/DIV
3.3V
3.3V
OUT
100mV/DIV
OUT
OUT
100mV/DIV
I
=
STEP
= 2A/µs
2A/DIV
I
= 2A/µs
2A/DIV
STEP
STEP
2A/µs
2A/DIV
4642 G13
4642 G15
20µs/DIV
20µs/DIV
20µs/DIV
C
C
SW
= 47µF CERAMIC
= 68pF
= 1MHz
C
C
= 47µF CERAMIC
C
C
SW
= 47µF CERAMIC
OUT
OUT
FF
OUT
= 68pF
= 800kHz
= 68pF
FF
FF
f
f
f
= 1MHz
SW
12VIN to 5VOUT Transient
Response
6VIN to 5VOUT Transient Response
Clock Synchronization
IN
OUT
IN
OUT
EXTCLK
5V/DIV
5V
5V
OUT
100mV/DIV
OUT
V
SW1
100mV/DIV
10V/DIV
V
SW2
I
=
10V/DIV
STEP
= 2A/µs
2A/DIV
STEP
2A/µs
2A/DIV
4642 G16
4642 G18
20µs/DIV
INPUT CAPACITOR 680µF 10V,
20µs/DIV
1µs/DIV
C
C
= 47µF CERAMIC
OUT
LOW IMPEDANCE INPUT CAN USE MUCH LESS
= 68pF
= 1.2MHz
FF
C
C
SW
= 47µF CERAMIC
= 68pF
= 600kHz
f
OUT
FF
SW
f
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For more information www.linear.com/LTM4642
LTM4642
Typical perForMance characTerisTics
(Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.
Output Ripple, 10mV Typical
Shorted Output
PGOOD
5V/DIV
V
SW2
20V/DIV
1.5V
V
OUT
OUT
10mV/DIV
0.5V/DIV
I
SHORT
10A/DIV
4642 G19
4642 G20
2µs/DIV
50µs/DIV
V
V
= 20V
IN
OUT
12V TO 1.5V AT 4A
= 100µF CERAMIC, 47µF CERAMIC
= 1.5V
C
SW
OUT
f
= 800kHz
Load Regulation and Current
Limit (No Airflow)
Start-Up, 20V to 1.5V at 4A
1.8
1.5
1.2
0.9
0.6
0.3
0
RUN2
5V/DIV
V
SW2
20V/DIV
V
OUT2
1V/DIV
DRV
INTV
CC
CC
V
SW
= 1.5V
OUT
5V/DIV
f
= 1MHz
4642 G21
20ms/DIV
MODE = CCM
4.5V
IN
IN
IN
C
C
= 100µF CERAMIC, 47µF CERAMIC
OUT
SS
12V
20V
= 0.1µF
4
5
0
1
2
3
6
7
LOAD CURRENT (A)
4642 G22
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LTM4642
pin FuncTions
PACKAGE ROW AND COLUMN LABELING MAY VARY
COMP1, COMP2 (E3, D3): Current Control Threshold and
ErrorAmplifierCompensationPoint.Themodulehasbeen
internally compensated for all I/O ranges.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A4-A7, C2, D1, D5, E1, E5, E7, F7, H4-H7): Power
FREQ (E4): Frequency Selection Pin. Tie a resistor from
thispintoSGNDtosetthefrequencyofoperationbetween
600kHz to 1.4MHz for the specific output voltages. For
3.3Vinputapplications,650kHzisanoptimizedfrequency.
For 5V to 20V input applications, the optimized operating
frequencyfortheoutputvoltageisasfollows:0.8Vto1.2V
(650kHz), 1.5V to 1.8V (800kHz), 2.0V to 5V (1.2MHz), 5V
from 20V input (1.4MHz). The resistor equation:
ground pins for both input and output returns.
PHASMD (B4): Phase Mode Selection Pin for Program-
ming Clock Out Phase. See Electrical Characteristics and
Applications Information sections.
MODE/PLLIN(C3):ModeSelectionorExternalSynchroni-
zation Pin. Tying this pin to SGND enables discontinuous
mode. Tying this pin to INTV enables forced continuous
CC
41550
operation. A clock on the pin will force the controller into
the continuous mode of operation and synchronize the
internal oscillator. The suitable synchronizable frequency
range is 600kHz to 1400kHz subject to inductor ripple
current limits described in the FREQ/PLLFLTR pin section.
The external clock input high threshold is 2V, while the
input low threshold is 0.5V.
RFREQ kΩ =
–2.2
(
)
FREQ kHz
DRV (E6): This pin is the LDO 5.3V regulator output
CC
used to power the internal control circuits and MOSFET
drivers.Thispinneedsa4.7µFceramicdecouplingcapaci-
tor to GND. For input voltages less than or equal to 5.3V,
connect this pin directly to the input voltage.
CPWR (C7):Thispin is the main inputpowertothe control
IC. This pin normally connects to the input source directly.
This pin can be biased at a voltage greater than 4.5V to
allowtheV andV tooperatedownto2.375Vinputfor
V
(F2): Output Voltage Sense Point for Channel 1
OUTS1
Remote Sensing. This pin has a 49.9Ω resistor connected
to V
. This pin can be connected at the load point for
OUT1
IN1
IN2
accurate remote sensing.
applications that operate at 2.5V or 3.3V input. If the bias
is less than or equal to 5.3V, connect DRV to this pin.
–
CC
V
(F3):RemoteGroundSensePin.Connectatremote
OUTS
ground point.
SGND (D2, E2): Signal Ground Pins. Return ground path
for all analog and low power circuitry. Tie a single connec-
tion to PGND in the application. See the Recommended
Layout section.
V
, V (F4, C4): The negative input of the error
FB1
FB2
amplifier. Internally, this pin is connected to V
with
OUT
a 60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between V
CLKOUT (D4): Clock Out for Synchronizing Other Regula-
tors to the Common Clock. Used for multiphase applica-
tions. See Applications Information section.
FB
and SGND pins. See the Applications Information section
for details.
TRACK/SS1,TRACK/SS2(F5,C5):OutputVoltageTracking
and Soft-Start Pins. Internal soft-start currents of 1.0µA
charge the soft-start capacitors. See the Applications
Information section to use the tracking function.
EXTV (D6): External Power Input to Controller. When
CC
EXTV is higher than 4.7V, the internal 5.3V regulator is
CC
disabledandtheexternalsourcesuppliescurrenttoreduce
the power dissipation in the module. This will improve the
efficiency more at high input voltages.
PGOOD1, PGOOD2 (F6, C6): Output Voltage Power Good
Indicator. Open-drain logic output that is pulled to ground
when the output voltage is not within 7.5% of the regula-
INTV (D7): This pin powers the internal control circuits.
CC
TiethispintoDRV witha2.2Ωresistor. Thispinrequires
CC
tion point. In single output parallel operation when V is
a few milliamps.
FB2
tied to INTV , the PGOOD2 pin is not to be used.
CC
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LTM4642
pin FuncTions
RUN1, RUN2 (G3, B3): Run Control Pins. A source can
be used to enable the RUN pins with an external pull-up
resistor. Forcing either of these pins below 1.2V will shut
down the corresponding outputs. An additional 5µA pull-
up current is added to this pin, once the RUN pin rises
above 1.2V. Also, active control or pull-up resistors can
be used to enable the RUN pin. The maximum voltage is
6V on these pins. There are 100k resistors on RUN1,2
to ground. It is recommended to use an external pull-up
0.6Vto1V, resultinginamaximumsensevoltagebetween
30mV and 50mV. For applications that require less than
7A of the default peak current limit, the V
pin voltage
RNG
can be scaled down to obtain a desired current limit level.
V
(G5, G6, 67), V (B5, B6, B7): Power Input Pins.
IN1
IN2
Apply input voltage between these pins and GND pins.
Recommendplacinginputdecouplingcapacitancedirectly
between V pins and GND pins.
IN
V
(F1, G1, G2, H1, H2), V
(A1, A2, B1, B2, C1):
resistor to V to enable the RUN pin. See the Applications
OUT1
OUT2
IN
Power Output Pins. Apply output load between these pins
and PGND pins. Recommend placing output decoupling
capacitance directly between these pins and PGND pins.
Information section.
V
(G4): Used at Final Test. Tie to INTV in normal
CC
RNG1
operation. This pin can also be used to adjust the current
SW1, SW2 (H3, A3): Switching Test Pins. These pins
are provided externally to check the operation frequency.
limitofchannel1. AnexternalresistivedividerfromINTV
can be used to set the voltage on the V
CC
pin between
RNG
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LTM4642
siMpliFieD block DiagraM
INPUT VOLTAGE SOURCE LESS THAN 5.3V BUT GREATER
THAN 4.5V, CONNECT DRV AND CPWR TO V . INPUT
VOLTAGE LESS THAN 4.5V BUT GREATER THAN 2.375V,
PROVIDE AN EXTERNAL BIAS TO CPWR 5V OR GREATER
CC
IN
PGOOD1
CPWR
PGOOD1
R5
2.2Ω
TRACK1
V
C7
0.1µF
IN1
TRACK1
4.5V TO 20V
V
IN1
SS
CAP
C1
22µF
25V
C7
0.1µF
MTOP1
GND
SW1
OUT1
RUN1*
V
IN1
RUN1 = 100k
((MIN V /1.3) – 1)
R
RUN1
255k
100k
V
IN
OUT1
1.5V/4A
1µH
V
CLKOUT
CLKOUT
INTV
+
+
C3
47µF
MBOT1
2.2µF 49.9Ω
GND
C
MODE/PLLIN
PHASMD
FREQ
OUT1
CC
PHASMD
V
OUTS1
POWER CONTROL
60.4k
R
FREQ
49.9k
V
FB1
V
FB1
SET1
40.2k
+
–
R
–
COMP1
V
OUTS
COMP1
INTERNAL
COMP
SGND
TRACK2
RUN2
TRACK2
PGOOD2
SS
CAP
PGOOD2
V
IN2
V
V
C4
22µF
25V
IN2
IN2
4.5V TO 20V
0.1µF
R
RUN2
255k
MTOP2
GND
SW2
OUT2
100k
INTV
CC
V
RNG1
SW2
V
OUT2
1.2V/4A
DRV
1µH
CC
V
C6
1µF
+
4.7µF
R4
2.2Ω
MBOT2
1µF
C
OUT2
INTV
CC
GND
GND
C2
1µF
60.4k
V
EXTV
FB2
CC
V
FB2
EXTV
CC
R
SET2
60.4k
COMP2
COMP2
INTERNAL
COMP
SGND
SGND
4642 F01
* ABSOLUTE MAXIMUM = 6V
Figure 1. Simplified LTM4642 Block Diagram
TA = 25°C. Use Figure 1 configuration.
CONDITIONS
Decoupling requireMenTs
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
External Input Capacitor Requirement
C
V
= 4.5V to 20V, V
= 1.5V, V
= 1.5V
= 1.5V
I
= 4A, I = 4A
OUT2
22
µF
IN
IN
OUT1
OUT2
OUT1
External Output Capacitor Requirement
= 4.5V to 20V, V = 1.5V, V
C
OUT1
C
OUT2
V
IN
I
I
= 4A
= 4A
150
150
µF
µF
OUT1
OUT2
OUT1
OUT2
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LTM4642
operaTion
The LTM4642 is a dual independent input 4A nonisolated
switching mode DC/DC power supply. It can deliver up to
4A(DCcurrent)foreachoutputwithfewexternalinputand
outputcapacitors.Thismoduleprovidespreciselyregulated
output voltages programmable via external resistors from
0.6V to 5.5V over a 4.5V to 20V input voltage range. The
Typical Application schematic is shown in Figure 27. The
input voltage source can operate down to 2.375V with an
external bias applied to the CPWR pin. The external bias
needs to be 5V or higher. See the Typical Applications
schematics for examples.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit and current foldback in a short-circuit condition. In-
ternal overvoltage and undervoltage comparators pull the
open-drain PGOOD pins output low if the output feedback
voltageexitsa 7.5%windowaroundtheregulationpoint.
The power good pin is disabled during start-up.
Pulling the RUN pins below 1.2V forces the controller
into its shutdown state, by turning off both MOSFETs.
The TRACK/SS pins are used for programming the output
voltage ramp and voltagetracking during start-up. See the
Applications Information section.
The LTM4642 has integrated constant on-time valley cur-
rent mode regulators and built-in power MOSFET devices
with fast switching speed. To reduce switching noise, the
two outputs are interleaved with 180° phase internally and
canbesynchronizedexternallyusingtheMODE/PLLINpin.
The LTM4642 is internally compensated to be stable over
all operating conditions. LTpowerCAD® is available for
transient and stability analysis. The V pins are used to
FB
program the output voltage with a single external resistor
to ground. Multiphase operation can be easily employed
with clock synchronization.
With current mode control and internal feedback loop
compensation, the LTM4642 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectablediscontinuousmodeusingtheMODE/PLLINpin.
Efficiency graphs are provided for light load operations in
the Typical Performance Characteristics section.
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LTM4642
applicaTions inForMaTion
The typical LTM4642 application circuit is shown in
Figure27.Externalcomponentselectionisprimarilydeter-
mined by the maximum load current and output voltage.
For a buck converter, the switching duty-cycle can be
estimated as:
VOUT
D=
V
IN
Output Voltage Programming
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 60.4k internal feedback
resistor R connects V
to the V pin. The output volt-
FB
OUT
FB
age will default to 0.6V with no feedback resistor. Adding
I
ICIN(RMS)
=
OUT(MAX) • D•(1−D)
a resistor R
from the V pin to SGND programs the
SET
FB
η
output voltage:
In the above equation, η is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
aluminumelectrolyticcapacitororapolymercapacitor.One
22µF ceramic input capacitor is typically rated for 2A of
RMS ripple current, so the RMS input current at the worst
case for each output at 4A maximum current is about 2A.
If a low inductance plane is used to power the device, then
two 22µF ceramic capacitors are enough for both outputs
at 4A load and no external input bulk capacitor is required.
60.4k+RSET
V
OUT =0.6V •
RSET
or equivalently:
60.4k
VOUT
RSET
=
⎛
⎜
⎝
⎞
–1
⎟
⎠
0.6V
Table 1. RSET Resistor Table vs Various Output Voltages
(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3
(kΩ) Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25
V
5
Output Capacitors
OUT
R
SET
The LTM4642 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
are
OUT
V
supportsfeedbackvoltagereferredremotesensing,
OUT1
as such the V
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
pin can be tied to V
OUTS
is programmed with a resistor to ground. For
at the load
OUTS1
sense point, and V
OUT1
–
is tied to ground at the load sense
ments. C
can be a low ESR tantalum capacitor, a low
OUT
point. V
OUT2
ESR polymer capacitor or ceramic capacitor. The typical
output capacitance range for each output is from 47µF
to 220µF. Additional output filtering may be required by
the system designer, if further reduction of output ripple
or dynamic transient spikes is required. LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the number
of phases. Application Note 77 discusses this noise re-
duction versus output ripple current cancellation, but the
output capacitance should be considered carefully as a
function of stability and transient response. LTpowerCAD
calculates the output ripple reduction as the number of
implemented phases increased by N times. See Table 6
for output capacitor suggestions.
a 2-phase single 8A output, the V pin can be connected
toINTV todisablethechannel2erroramplifier,andinter-
FB2
CC
nally connect the COMP2 pin to COMP1 pin. The COMP2
pin can be left floating or connected to COMP1 externally.
The TRACK/SS2 and PGOOD2 pins are not functional in
this mode, thus they can be left floating. See the Typical
Applications at the end of the data sheet.
Input Capacitors
The LTM4642 module should be connected to a low AC-
impedance DC source. A 47µF to 100µF surface mount
aluminumelectrolyticcapacitorcanbeusedformoreinput
bulk capacitance. This bulk capacitor is only needed if the
inputsourceimpedanceiscompromisedbylonginductive
leads, traces or not enough source capacitance.
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LTM4642
applicaTions inForMaTion
Mode Selections and Phase-Locked Loop
as well as the CLKOUT signal, as shown in Table 2. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of channel 1. The CLKOUT signal can be used to
synchronize additional power regulator modules. The
system can be configured for up to 12-phase operation
with a multichannel solution. Typical configurations are
shown in Table 3 to interleave the phases of the channels.
The applications will validate a 6 phase multiple regulator
solution with multiple outputs.
The LTM4642 can be enabled to operate in discontinuous
orforcedcontinuousmode.Toselecttheforcedcontinuous
operation, tie the MODE/PLLIN pin to INTV . To select
CC
discontinuous operation, or tie the MODE/PLLIN pin to
ground. This will improve the light load efficiency.
Frequency Selection and Eꢁternal Clock
Synchronization
An internal oscillator (clock generator) provides phase
interleaved internal clock signals for individual channels
to lock on to. The switching frequency and phase of each
switching channel is independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector, and
the time interval of the one-shot timer is adjusted on a
cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
Each of the LTM4642 channels can be paralleled up to 8A
of output, but cannot be paralleled from one module to
the other modules. Twelve phases can be paralleled with
no more than two phases per module.
Table 2
PHASMD
Channel 1
Channel 2
CLKOUT
SGND
0°
FLOAT
0°
INTVCC
0°
180°
60°
180°
90°
240°
120°
Table 3
NUMBER OF
PHASES
NUMBER OF
LTM4642*
PIN CONNECTIONS
[PIN NAME (CHIP NUMBER)]
Thefrequencyoftheinternaloscillatorcanbeprogrammed
from 600kHz to 1.4MHz by connecting a resistor, R
,
FREQ
2
3
1
PHASMD(1) = FLOAT or SGND
fromtheFREQpintosignalground(SGND). Theequation:
2 or
PHASMD(1) = INTV
CC
1 + ½(LTM4642) MODE/PLLIN(2) = CLKOUT(1)
41550
RFREQ kΩ =
–2.2
(
)
4
6
2
PHASMD(1) = FLOAT
FREQ kHz
PHASEMD(2) = FLOAT or SGND
MODE/PLLIN(2) = CLKOUT(1)
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTM4642 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within 30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
3
PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT or SGND
MODE/PLLIN(3) = CLKOUT(2)
*No more than two channels of any one module may be paralleled.
Soft-Start and Tracking
The LTM4642 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
externalsupply.Whenoneparticularchannelisconfigured
to soft-start by itself, a capacitor should be connected to
its TRACK/SS pin. This channel is in the shutdown state
if its RUN pin voltage is below 1.2V. Its TRACK/SS pin is
actively pulled to ground in this shutdown state.
PHASMD Pin Programming
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
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LTM4642
applicaTions inForMaTion
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TRACK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TRACK/SSpin.Thetotalsoft-starttimecanbecalculatedas:
V
isthetrackrampappliedtotheslave’sTRACK/SS2
TRACK
pin. V
has a control range of 0V to 0.6V. When the
TRACK
master’s output is divided down with the same resistor
values used to set the slave’s output, then the slave will
coincident track with the master until it reaches its final
value. The master will continue to its final value from the
slave’s regulation point.
Ratiometric modes of tracking can be achieved by select-
ing different divider resistors values to change the output
tracking ratio. The master output must be greater than the
0.6V •CSS µF
( )
tSOFT-START
=
1µA
MASTER OUTPUT
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The master channel is divided
down with an external resistor divider that is the same
as the slave channel’s feedback divider to implement co-
incident tracking. The LTM4642 uses an accurate 60.4k
resistor internally for the top feedback resistor. Figure 2
shows an example of coincident tracking. Figure 3 shows
the output voltages with coincident tracking.
SLAVE OUTPUT
OUTPUT
VOLTAGE
4642 F03
TIME
⎛
⎞
⎟
⎠
R1
R2
VSLAVE = 1+
•V
TRACK
⎜
Figure 3. Coincident Tracking
⎝
2.2Ω
INTV
V
CC
IN
4.75V TO 20V
4.7µF
C
C
IN2
22µF
IN1
131k
V
RUN1
RUN2
22µF
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
V
10k 10k
PGOOD1
PGOOD2
PGOOD1
PGOOD2
TRACK/SS1
TRACK/SS2
0.1µF
V
V
1.5V AT 4A LOAD
1.0V AT 4A LOAD
+
OUT1
OUT2
V
V
OUT1
OUT2
R1
R2
90.9k
+
C
OUT3
C
OUT4
60.4k
47µF
100µF
LTM4642
C
OUT1
C
OUT2
100µF
V
OUT1
47µF
FREQ
V
INTV
MODE/PLLIN
OUTS1
–
CC
V
OUTS
R
FREQ
V
V
FB2
FB1
61.9k
470pF
470pF
V
OUT1
V
OUT2
SGND
GND
R
R
FB2
90.9k
FB1
40.2k
4642 F02
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 2. Eꢁample of Coincident Tracking
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LTM4642
applicaTions inForMaTion
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistors
values for coincident or ratiometric tracking.
RUN Pin
The RUN pins can be used to enable or sequence the
particular regulator channel. The RUN pins have their own
internal 1.2µA current source to pull up the RUN pins to
1.2V,andthecurrentwillincreaseto5µAabove1.2V.Board
contaminationorresiduecanloaddownthesesmallpull-up
currents, so a 100k resistor is placed from the RUN pins
to ground. This 100k resistor can be used with a resistor
Multiphase Operation
Multiphase operation with the LTM4642 two regulator
channels in parallel will lower the effective input RMS
ripple current as well as the output ripple current due
to the interleaving operation of the regulators. Figure 4
provides a ratio of input RMS ripple current to DC load
current as a function of duty cycle and the number of
paralleled phases. Choose the corresponding duty cycle
and the number of phases to get the correct ripple current
value. For example, the 2-phase parallel for one LTM4642
design provides 8A at 2.5V output from a 12V input. The
duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve
has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25
ratio of RMS ripple current to a DC load current of 8A
equals ~2A of input RMS ripple current for the external
input capacitors. No more than two phases of a module
may be paralleled.
to V to set the turn-on threshold for the RUN pins
IN
The resistor divider needs to be low enough resistance
to swamp out the pull-up current sources to prevent
unintended activation of the device. The RUN pin has a
maximum rated voltage of 6V. See Figure 1 Block Diagram
for set turn on equation.
Power Good
ThePGOODpinisconnectedtotheopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either V pin voltage is not within
FB
7.5% of the 0.6V reference voltage. The PGOOD pin is
alsopulledlowwheneitherRUNpinisbelow1.2Vorwhen
the LTM4642 is in the soft-start or tracking phase. When
The effective output ripple current is lowered with
multiphase operations as well. Figure 5 provides a ratio
of peak-to-peak output ripple current to the normalized
output ripple current as a function of duty cycle and the
number of paralleled phases. Choose the corresponding
duty cycle and the number of phases to get the correct
output ripple current ratio value. If a 2-phase operation is
the V pin voltage is within the 7.5% requirement, the
FB
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
V
pins are within the 7.5% window. However, there is
FB
aninternal17µspowerbadmaskwheneitherV goesout
FB
chosen at 12V to 2.5V
with a duty cycle of 21%, then
IN
OUT
of the 7.5% window. In parallel single output operation,
only use PGOOD1.
0.6 is the ratio of the normalized output ripple current to
inductor ripple DIr at the corresponding duty cycle. This
leads to ~1.3A of the effective output ripple current ΔI
L
CPWR, DRV , INTV and EXTV
CC
CC
CC
if the DIr is at 2.2A. Refer to Application Note 77 for a
detailed explanation of the output ripple current reduction
as a function of paralleled phases.
TheCPWRisthemainpowerinputtotheinternalcontrolIC.
Thispinisnormallyconnectedtotheinputvoltagesource.
This pin can be biased with a 5V supply when operating
The output ripple voltage has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output ripple voltage can be calculated with
the known effective output ripple current. The equation:
at input voltages below 4.5V. When 4.5V < V < 5.3V,
IN
Then tie CPWR to DRV . See the Typical Applications.
CC
The DRV is the internal 5.3V regulator that powers the
CC
LTM4642 internal MOSFET drivers for the internal power
MOSFETs. The DRV requires a 4.7µF ceramic capacitor
CC
ΔV
≈ ΔI /(8 • f • N • C ) + ESR • ΔI
L OUT L
OUT(P-P)
to ground. INTV powers the internal controller circuits
CC
and is connected to DRV through a 2.2Ω resistor. This
wherefisfrequencyandNisthenumberofparallelphases.
CC
INTV bias is ≤20mA.
CC
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0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
*THE LTM4642 CAN ONLY HAVE THE TWO
CHANNELS PER MODULE PARALLELED
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4642 F04
Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Siꢁ Phases*
1.00
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4642 F05
Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L
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where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by: Z = 1/(2πfC). These values are a good
place to start with. Modification to these components
should be made to attenuate the ringing with the least
amount of power loss.
A 5V output on channel 1 or 2 can be used to power the
EXTV pin when the input voltage is at the high end of the
CC
supply range to reduce power dissipation in the module.
For example, the dropout voltage for 20V input would be
20V – 5V = 15V. This 15V headroom then multiplied by
the power MOSFET drive current of ~30mA would equal
~0.45W additional power dissipation. So utilizing a 5V
( )
C
outputontheEXTV wouldimprovedesignefficiencyand
CC
reduce device temperature rise. Otherwise try to operate
CWPR off of a 5V bias when operating at higher supply
voltages. See the Typical Applications section.
Thermal Considerations and Output Current Derating
Indifferentapplications,theLTM4642operatesinavariety
of thermal environments. The maximum output current is
limited by the environmental thermal condition. Sufficient
cooling should be provided to ensure reliable operation.
When the cooling is limited, proper output current derat-
ing is necessary, considering the ambient temperature,
airflow,input/outputconditions,andtheneedforincreased
reliability.
Fault Conditions: Current Limit and Overcurrent
Foldback
The LTM4642 has a current mode controller, which inher-
ently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condi-
tion,theLTM4642providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to one-fourth of
its full current limit value. Foldback current limiting is
disabled during soft-start and tracking up.
The two outputs of the LTM4642 are paralleled to charac-
terize the output current derating curves. The power loss
curves in Figure 8 to Figure 10 can be used in coordination
with load current derating curves in Figure 11 to Figure 24
for calculating an approximate θ for the module with
JA
SW Pins
various cooling methods. Application Note 103 provides
detailedexplanationoftheanalysisforthethermalmodels
and the derating curves. Tables 4 and 5 provide a sum-
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina-
tion is used called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usuallyeasiertopredict.Itcombinesthepowerpathboard
inductance in combination with the MOSFET interconnect
bond wire inductance.
mary of the equivalent θ parameters are correlated to
JA
the measured values, and are improved with airflow.
Thepowerlosscurvesaretakenatroomtemperature, and
are increased with multiplicative factors according to the
ambienttemperature.Theapproximatefactorsare:1.35for
115°C and 1.4 for 120°C. The derating curves are plotted
with CH1 and CH2 paralleled output current starting at 8A
andtheambienttemperaturestartingat50°C. Thederated
output voltages are 1.0V, 2.5V, 3.3V and 5.0V. Tables 4
and 5 specify the approximate θ with airflow conditions
JA
for1Vand5Voutputs. Thesetwoconditionsarechosento
includethelowerandhigheroutputvoltagerangesforcor-
relatingthethermalresistance,butanyderatingcurvepoint
along with power loss curve can be used to calculate the
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
θ .Thermalmodelsarederivedfromseveraltemperature
JA
measurementsinacontrolledtemperaturechamberalong
Z
= 2πfL,
(L)
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Table 4. 1V Output
DERATING CURVE
Figures 11, 13
Figures 11, 13
Figures 11, 13
Figures 12, 14
Figures 12, 14
Figures 12, 14
V
(V)
POWER LOSS CURVE
Figures 8, 9
AIRFLOW (LFM)
HEAT SINK
none
Θ
(°C/W)
13
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
Figures 8, 9
200
400
0
none
10
Figures 8, 9
none
9
Figures 8, 9
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
13
Figures 8, 9
200
400
8
Figures 8, 9
7.5
Table 5. 5V Output
DERATING CURVE
Figures 21, 23
Figures 21, 23
Figures 21, 23
Figures 22, 24
Figures 22, 24
Figures 22, 24
V
(V)
POWER LOSS CURVE
Figures 9, 10
Figures 9, 10
Figures 9, 10
Figures 9, 10
Figures 9, 10
Figures 9, 10
AIRFLOW (LFM)
HEAT SINK
none
Θ
JA
(°C/W)
15
IN
12, 20
0
12, 20
12, 20
12, 20
12, 20
12, 20
200
400
0
none
13
none
12
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
14
200
400
10
10
Table 6. Output Voltage Response vs Component Matriꢁ (Refer to Figure 27) 0A to 2A Load Step Typical Measured Values
CERAMIC CAPACITOR
VENDORS
VALUE
PART NUMBER
BULK VENDORS
Sanyo OSCON SVPC
Panasonic SP
VALUE
PART NUMBER
10SVPC120MV
EEFCTOJ101R
ESR
Murata
C
: 47µF 6.3V, X5R GRM21BR60J476ME15
C
: 120µF 10V
OUT
22mΩ
15mΩ
OUT
Murata
C
: 47µF 10V, X5R
GRM31CR61A476KE15
GRM32ER71C226KEA8
C
OUT
: 100µF 6.3V
OUT
Murata
C : 22µF, X7R, 16V
IN
C
C
C
C
(CER
C
DROOP PEAK TO RECOVERY LOAD STEP
R
FB
FREQ
(kHz)
IN
IN
OUT1
OUT2
FF
V
(V) (CERAMIC) (BULK)** (CERAMIC)
AND BULK)
(pF)
V
(V)
IN
(mV)
PEAK
TIME (µs)
(A/µs)
(kΩ)
90.9
60.4
40.2
30.1
19.1
13.3
8.25
OUT
1
22µF × 2
22µF × 2
22µF × 2
22µF × 2
22µF × 2
22µF × 2
22µF × 2
56µF
56µF
56µF
56µF
56µF
56µF
56µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
100µF or 120µF 470 3.3, 5, 12
100µF or 120µF 470 3.3, 5, 12
100µF or 120µF 470 3.3, 5, 12
100µF or 120µF 470 3.3, 5, 12
31
62
20
20
20
25
20
20
20
2
2
2
2
2
2
2
650
650
1.2
30
63
1.5
1.8
2.5
3.3
5
35
70
700
38
80
750
68
68
68
3.3, 5, 12
5, 12
100
120
185
200
240
390
1000
1000
1200
** Bulk capacitance is optional if V has very low input impedance.
IN
HEAT SINK MANUFACTURER
Cool Innovations
PART NUMBER
3-05040
WEBSITE
www.coolinnovations.com
www.chomerics.com
Chomerics
T411 Interface
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withthermalmodelinganalysis.Thejunctiontemperatures
aremonitoredwhileambienttemperatureisincreasedwith
and without airflow. The power loss increase with ambient
temperature change is factored into the derating curves.
The junctions are maintained at 120°C maximum while
lowering output current or power with increasing ambient
temperature.Thedecreasedoutputcurrentwilldecreasethe
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example
in Figure 14 the load current is derated to ~7A at ~100°C
with no air or heat sink and the power loss for the 12V to
1.0V at 7A output is about 1.2W (power loss at 3.5A load
multiplied by 2). The 1.2W loss is multiplied by the 1.4
multiplying factor at 120°C junction to get 1.68W. If the
100°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 20°C divided
by 1.68W equals a 12°C/W thermal resistance. Table 4
specifies a 13°C/W value which is very close. Table 4 and
Table 5 provide equivalent thermal resistances for 1.0V
and 5V outputs with and without airflow and heat sinking.
The derived thermal resistances in Tables 4 and 5 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sinks
are listed below Table 5.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
1. θ , the thermal resistance from junction to ambi-
JA
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModule,thebulk
of the heat flows out the bottom of the package, but
there is always heat flow out into the ambient environ-
ment. Asaresult, thisthermalresistancevaluemaybe
useful for comparing packages but the test conditions
don’t generally match the user’s application.
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetop
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
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4. θ , the thermal resistance from junction to the
Within the LTM4642, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
the LTM4642 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4642 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. An outcome of this
JB
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the µModule and into the board, and
is really the sum of the θ
and the thermal re-
JCbottom
sistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 6; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4642 F06
µModule DEVICE
Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients
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process and due diligence yields a set of derating curves
to the printed circuit board and the exposed top metal is
thermally connected to the power devices and the power
inductors.Anexternalheatsinkcanbeappliedtothetopof
the device for excellent heat sinking with airflow. Basically
all power dissipating devices are mounted directly to the
substrate and the top exposed metal. This provides two
low thermal resistance paths to remove heat.
provided in other sections of this data sheet. After these
laboratory tests have been performed, then the θ and
JB
θ
are summed together to correlate quite well with the
BA
LTM4642modelwithnoairfloworheatsinkinginaproperly
define chamber. This θ + θ value is shown in the Pin
JB
BA
Configuration section and should accurately equal the θ
JA
value because approximately 100% of power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink. Each system has its own
thermal characteristics, therefore thermal analysis must
be performed by the user in a particular system.
Safety Considerations
The LTM4642 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
The LTM4642 has been designed to effectively remove
heat from both the top and bottom of the package. The
bottomsubstratematerialhasverylowthermalresistance
I
PER
HOT TEMP
PEAK TEMP (°C)
LOAD
V
(V)
V
OUT1
(V)
V
OUT2
(V)
PHASE (A)
f (kHz)
SW
IN
12
2.5
1.5
4
1000
56.6
Figure 7. Thermal Plot for the Specified Operation. The Temperature Rise About 25°C Ambient Is About 30°C Rise
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1.0
0.8
0.6
0.4
0.2
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20V to 5V
20V to 1.5V
20V to 1.2V
20V to 1V
12V to 5V
5V to 3.3V
5V to 2.5V
5V to 1.8V
5V to 1.5V
5V to 1.2V
5V to 1V
20V to 3.3V
20V to 2.5V
20V to 1.8V
12V to 3.3V
12V to 2.5V
12V to 1.8V
12V to 1.5V
12V to 1.2V
12V to 1V
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
CURRENT LOAD (A)
CURRENT LOAD (A)
CURRENT LOAD (A)
4642 F08
4642 F09
4642 F10
Figure 8. 5V Input Power Loss
Figure 9. 12V Input Power Loss
Figure 10. 20V Input Power Loss
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
50
60
70
80
90 100 110 120
(°C)
50
60
70
80
90 100 110 120
(°C)
50
60
70
80
90 100 110 120
(°C)
t
t
t
AMB
AMB
AMB
4642 F11
4642 F12
4642 F13
Figure 11. 5VIN, 1VOUT 650kHz,
No Heat Sink
Figure 12. 5VIN, 1VOUT 650kHz,
with Heat Sink
Figure 13. 12VIN, 1VOUT 650kHz,
No Heat Sink
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
50
60
70
80
t
90 100 110 120
(°C)
50
60
70
80
t
90 100 110 120
(°C)
50
60
70
80
t
90 100 110 120
(°C)
AMB
AMB
AMB
4642 F16
4642 F14
4642 F15
Figure 14. 12VIN, 1VOUT 650kHz,
with Heat Sink
Figure 15. 5VIN, 3.3VOUT 650kHz,
No Heat Sink
Figure 16. 5VIN, 3.3VOUT 650kHz,
with Heat Sink
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9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
50
60
70
80
t
90 100 110 120
(°C)
50
60
70
80
t
90 100 110 120
(°C)
50
60
70
80
90 100 110 120
(°C)
t
AMB
AMB
AMB
4642 F17
4642 F18
4642 F19
Figure 17. 12VIN, 2.5VOUT 1MHz,
No Heat Sink
Figure 18. 12VIN, 2.5VOUT 1MHz,
with Heat Sink
Figure 19. 20VIN, 2.5VOUT 1MHz,
No Heat Sink
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
50
60
70
80
90 100 110 120
(°C)
50
60
70
80
90 100 110 120
(°C)
50
60
70
80
90 100 110 120
(°C)
t
t
t
AMB
AMB
AMB
4642 F20
4642 F21
4642 F22
Figure 20. 20VIN, 2.5VOUT 1MHz,
with Heat Sink
Figure 21. 12VIN, 5VOUT 1.2MHz,
No Heat Sink
Figure 22. 12VIN, 5VOUT 1.2MHz,
with Heat Sink
9
8
7
6
5
4
3
9
8
7
6
5
4
3
2
2
0 LFM
0 LFM
200 LFM
400 LFM
200 LFM
400 LFM
1
0
1
0
50
60
70
80
t
90 100 110 120
50
60
70
80
t
90 100 110 120
(°C)
(°C)
AMB
AMB
4642 F23
4642 F24
Figure 23. 20VIN, 5VOUT 1.2MHz,
No Heat Sink
Figure 24. 20VIN, 5VOUT 1.2MHz,
with Heat Sink
4642fb
23
For more information www.linear.com/LTM4642
LTM4642
applicaTions inForMaTion
Layout Checklist/Eꢁample
The high integration of LTM4642 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnections
between top layer and other power layers.
• Do not put vias directly on the pads.
• Use large PCB copper areas for high current path, in-
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
cluding V , V , PGND, V
and V
. It helps to
IN1 IN2
OUT1
OUT2
minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
• Decouple the input and output grounds to lower the
tors next to the V , PGND and V
pins to minimize
IN
OUT
output ripple noise.
high frequency noise.
Figure25givesagoodexampleoftherecommendedlayout.
• Place a dedicated power ground layer underneath the
unit.
GND
V
OUT2
GND
C
OUT2
1
2
3
4
5
6
7
C
IN2
C
IN4
A
B
C
V
OUT2
V
IN2
D
E
C
INTVCC
GND
GND
F
G
H
V
IN1
C
C
IN3
IN1
V
OUT1
GND
C
OUT2
V
OUT1
GND
4642 F25
Figure 25. Recommended PCB Layout
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24
For more information www.linear.com/LTM4642
LTM4642
Typical applicaTions
2.2Ω
INTV
V
CC
IN
4.5V TO 20V
4.7µF
C
C
IN2
22µF
IN1
131k
V
RUN1
RUN2
22µF
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
V
10k 10k
PGOOD1
PGOOD2
TRACK/SS1
TRACK/SS2
PGOOD1
PGOOD2
0.1µF
0.1µF
V
V
0.9V AT 4A LOAD
OUT1
OUT2
V
V
OUT1
OUT2
+
C
1V AT 4A LOAD
OUT3
C
OUT4
47µF
100µF
+
LTM4642
C
OUT1
C
OUT2
47µF
100µF
FREQ
V
INTV
MODE/PLLIN
OUTS1
–
CC
V
OUTS
R
FREQ
V
V
FB2
FB1
61.9k
V
V
OUT2
OUT1
SGND
GND
R
R
FB2
90.9k
FB1
C
C
FF
FF
121k
470pF
470pF
4642 F26
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 26. 4.5V to 20V Input, 650kHz, 0.9V and 1.2V Outputs at 4A Each
2.2Ω
INTV
V
CC
IN
5V
4.7µF
C
C
IN2
22µF
IN1
131k
V
RUN1
RUN2
22µF
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
V
10k 10k
PGOOD1
PGOOD2
TRACK/SS1
TRACK/SS2
PGOOD1
PGOOD2
0.1µF
0.1µF
V
V
1.8V AT 4A LOAD
2.5V AT 4A LOAD
OUT1
OUT2
V
V
OUT1
OUT2
+
C
C
OUT3
OUT2
120µF
47µF
LTM4642
OSCON SVP
C
OUT1
47µF
FREQ
V
OUTS1
–
INTV
MODE/PLLIN
CC
V
OUTS
R
FREQ
V
V
FB2
FB1
49.9k
470pF
470pF
V
OUT1
V
OUT2
SGND
GND
R
R
FB2
19.1k
FB1
30.2k
4642 F27
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 27. 5V Input, 800kHz, 2.5V and 1.8V Outputs at 4A Each
4642fb
25
For more information www.linear.com/LTM4642
LTM4642
Typical applicaTions
2.2Ω
INTV
V
CC1
IN
4.75V TO 20V
C
C
4.7µF
IN1
IN2
131k
V
RUN1
RUN2
22µF
22µF
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
V
10k 10k
60.4k
60.4k
TRACK/SS1
TRACK/SS2
PGOOD1
PGOOD2
60.4k
1.2V AT 4A LOAD
V
V
OUT1
OUT2
+
C
OUT1
C
OUT2
19.1k
2.5V AT 4A LOAD
C
LTM4642
47µF
100µF
OUT3
47µF
FREQ
V
OUTS1
–
V
OUTS
INTV
MODE/PLLIN
CC1
V
V
FB2
FB1
470pF
68pF
R
FREQ
39.2k
V
OUT1
V
OUT2
SGND
GND
R
R
FB2
FB1
60.4k
19.1k
2.2Ω
INTV
V
CC2
IN
4.75V TO 20V
C
C
4.7µF
IN3
IN4
131k
22µF
22µF
V
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
RUN1
RUN2
V
10k 10k
60.4k
3.3V
TRACK/SS1
PGOOD1
PGOOD2
121k
TRACK/SS2
0.1µF
0.9V AT 4A LOAD
V
V
OUT1
OUT2
+
C
OUT4
C
OUT6
3.3V AT 4A LOAD
C
LTM4642
47µF
100µF
OUT6
47µF
FREQ
V
OUTS1
–
V
INTV
MODE/PLLIN
OUTS
CC2
V
FB2
470pF
68pF
R
FREQ1
39.2k
V
OUT1
V
OUT2
V
FB1
SGND
GND
R
R
FB2
13.3k
FB3
121k
4642 F28
PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 28. 1MHz 4-Phase, Four Outputs (3.3V, 2.5V, 1.2V, 0.9V) with Tracking to the 3.3V Output
4642fb
26
For more information www.linear.com/LTM4642
LTM4642
Typical applicaTions
2.2Ω
INTV
V
CC
IN
4.75V TO 20V
4.7µF
C
C
IN2
22µF
IN1
131k
V
RUN1
RUN2
22µF
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
V
10k
PGOOD1
TRACK/SS1
TRACK/SS2
PGOOD1
PGOOD2
0.1µF
COMP1
COMP2
3.3V AT 8A
V
V
OUT1
LTM4642
C
C
OUT2
47µF
OUT1
47µF
OUT2
FREQ
V
OUTS1
–
V
INTV
MODE/PLLIN
OUTS
CC
INTV
V
CC
FB2
R
39.2k
1MHz
FREQ
68pF
V
FB1
SGND
GND
4642 F29
R
FB1
13.3k
PINS NOT USED: PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 29. Output Paralleled LTM4642 Module for 3.3V at 8A Each
4642fb
27
For more information www.linear.com/LTM4642
LTM4642
Typical applicaTions
5V BIAS
(~30mA)
2.2Ω
INTV
V
CC
IN
3.3V
4.7µF
C
C
IN2
22µF
IN1
100k
V
22µF
3.3V
V
CPWR
DRV INTV
IN1 IN2
CC
CC
RNG1
RUN1
V
10k 10k
PGOOD1
0.1µF
RUN2
PGOOD1
PGOOD2
PGOOD1
PGOOD2
TRACK/SS1
TRACK/SS2
0.1µF
V
V
1V AT 4A LOAD
OUT1
OUT2
V
C
OUT1
OUT2
+
C
OUT1
1.8V AT 4A LOAD
150µF
47µF
V
LTM4642
15mΩ SANYO
POSCAP
OUT2
+
C
OUT3
C
OUT4
47µF
100µF
FREQ
INTV
MODE/PLLIN
CC
V
OUTS1
–
V
OUTS
R
FREQ
66.5k
V
FB2
470pF
470pF
600kHz
V
V
OUT2
V
OUT1
FB1
SGND
GND
R
R
FB2
30.2k
FB1
90.9k
4642 F30
PINS USED: COMP1, COMP2, PHASEMD, CLKOUT, EXTV , SW1, SW2
CC
Figure 30. 3.3V Input to 1V and 1.8V at 4A Each, 1V Sequencing 1.8V Using PGOOD1 to Enable RUN2
4642fb
28
For more information www.linear.com/LTM4642
LTM4642
package DescripTion
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 5. Pin Assignment
PIN ID FUNCTION
PIN ID
B1
FUNCTION
PIN ID
C1
FUNCTION
PIN ID FUNCTION
PIN ID
E1
FUNCTION PIN ID
FUNCTION
A1
A2
A3
A4
A5
A6
A7
V
V
V
V
V
D1
D2
D3
D4
D5
D6
D7
GND
SGND
GND
SGND
COMP1
FREQ
GND
F1
F2
F3
F4
F5
F6
F7
V
OUT1
OUT2
OUT2
OUT2
OUT2
OUT2
B2
C2
GND
E2
V
V
OUTS1
–
SW2
GND
GND
GND
GND
B3
RUN2
C3
MODE/PLLIN
COMP2
CLKOUT
GND
E3
OUTS
B4
PHASMD
C4
V
E4
V
FB1
FB2
B5
V
V
V
C5
TRACK/SS2
PGOOD2
CPWR
E5
TRACK/SS1
PGOOD1
GND
IN2
IN2
IN2
B6
C6
EXTV
E6
DVR
CC
CC
CC
B7
C7
INTV
E7
GND
PIN ID FUNCTION
PIN ID
H1
FUNCTION
G1
G2
G3
G4
G5
G6
G7
V
V
V
OUT1
V
OUT1
OUT1
OUT1
H2
RUN1
H3
SW1
GND
GND
GND
GND
V
RNG1
H4
V
H5
IN1
IN1
IN1
V
H6
V
H7
4642fb
29
For more information www.linear.com/LTM4642
LTM4642
package DescripTion
Please refer to http://www.linear.com/product/LTM4642#packaging for the most recent package drawings.
/ / b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 0 0 0
0 . 3 1 7
1 . 2 7 0
2 . 5 4 0
3 . 8 1 0
4642fb
30
For more information www.linear.com/LTM4642
LTM4642
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/16 Absolute Maximum Rating VFB1, V changed to INTV to 0.3V
2
FB2
CC
B
6/17
Twelve phases can be paralleled with no more than two phases per regulator output
13
4642fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM4642
package phoTograph
Design resources
SUBJECT
DESCRIPTION
Design:
• Selector Guides
µModule Design and Manufacturing Resources
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM4614
LTM4615
LTM4616
LTM4628
Dual, 4A, Low V , DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 15mm × 15mm × 2.82mm LGA
OUT
IN
IN
Triple, Low V , DC/DC µModule Regulator
Two 4A Outputs and One 1.5A, 15mm × 15mm × 2.82mm LGA, 2.375V ≤ V ≤ 5.5V
IN
IN
Dual, 8A, Low V , DC/DC µModule Regulator
2.7V ≤ V ≤ 5.5V, 0.6V ≤ V
≤ 5V, 15mm × 15mm × 2.82mm LGA
IN
IN
OUT
Dual, 8A, 26V, DC/DC µModule Regulator
4.5V ≤ V ≤ 28.5V, 0.6V ≤ V
≤ 5.5V, Remote Sense Amplifier, Internal Temperature
IN
OUT
Sensing Diode Output, 15mm × 15mm × 4.32mm LGA
LTM4620A
Dual, 16V, 13A, 26A, Step-Down µModule
Regulator
4.5V ≤ V ≤ 16V, 0.6V ≤ V ≤ 5.3V, 15mm × 15mm × 4.41mm LGA
IN
OUT
4642fb
LT 0617 Rev B • PRINTED IN USA
www.linear.com/LTM4642
32
LINEAR TECHNOLOGY CORPORATION 2016
相关型号:
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