LTM8050 [Linear]
60VIN, 3A Silent Switcher μModule Regulator;
| 型号： | LTM8050 |
| 厂家： | 
Linear |
| 描述： | 60VIN, 3A Silent Switcher μModule Regulator |
| 文件： | 总26页 (文件大小：1488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM8073
60V , 3A Silent Switcher
IN
µModule Regulator
FeaTures
DescripTion
The LTM®8073 is a 60V , 3A (continuous) or 5A (peak)
n
Complete Step-Down Switch Mode Power Supply
IN
Low Noise Silent Switcher® Architecture
step-down Silent Switcher µModule® (power module)
regulator. Included in the package are the switching con-
troller, power switches, inductor, and all support compo-
nents. Operating over an input voltage range of 3.4V to
60V, the LTM8073 supports an output voltage range of
0.8V to 15V and a switching frequency range of 200kHz
to 3MHz, each set by a single resistor. Only the input and
output filter capacitors are needed to finish the design.
n
n
Wide Input Voltage Range: 3.4V to 60V
n
Wide Output Voltage Range: 0.8V to 15V
n
3A Continuous Output Current, 24V , 5V
,
IN
OUT
T = 85°C
A
n
n
n
n
n
Up to 5A Peak Current
Parallelable for Increased Output Current
Selectable Switching Frequency: 200kHz to 3MHz
Programmable Soft-Start
The low profile package enables utilization of unused
space on the bottom of PC boards for high density point
of load regulation. The LTM8073 is packaged in a thermally
enhanced, compact over-molded ball grid array (BGA)
package suitable for automated assembly by standard sur-
face mount equipment. The LTM8073 is RoHS compliant.
6.25mm × 9mm × 3.32mm BGA Package
applicaTions
n
Power for Portable Products
n
Distributed Supply Regulation
n
Industrial Supplies
Wall Transformer Regulation
L, LT, LTC, LTM, µModule, Burst Mode, Silent Switcher, Linear Technology and the Linear logo
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners.
n
Typical applicaTion
5VOUT from 7VIN to 60VIN Step-Down Converter
Efficiency, VOUT = 5V, BIAS = 5V
95
LTM8073
V
= 24V
V
IN
V
IN
IN
7V TO 60V
BIAS
AUX
RUN
1µF
V
5V
3A
OUT
V
OUT
90
85
80
RT
100µF
32.4k
1.2MHz
47.5k
FB
GND SYNC
8073 TA01a
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
0
1
2
3
LOAD CURRENT (A)
8073 TA01
8073fa
1
For more information www.linear.com/LTM8073
LTM8073
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
V , RUN Voltage ......................................................65V
IN
PG Voltage................................................................42V
RUN BANK 2
V
IN
GND
AUX, V , BIAS Voltage ..........................................19V
OUT
6
5
4
3
2
1
FB, TR/SS Voltage.......................................................4V
SYNC Voltage..............................................................6V
Maximum Internal Temperature (Note 4).............. 125°C
Storage Temperature.............................. –55°C to 125°C
Peak Solder Reflow (Package Body) Temperature..250°C
RT TR/SS
SHARE SYNC
PG
BANK 1
GND
BANK 3
V
OUT
AUX
BIAS
GND FB
A
B
C
D
E
F
G
H
48-LEAD (9mm × 6.25mm × 3.32mm) BGA PACKAGE
= 125°C, θ = 23.6°C/W, θ = 4.4°C/W,
T
JMAX
JA
JCbottom
θ
= 11.3°C/W, θ = 2.8°C/W, WEIGHT = 0.5g
JCtop
JB
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
http://www.linear.com/product/LTM8073#orderinfo
orDer inForMaTion
PART MARKING*
PACKAGE
MSL
TEMPERATURE RANGE
(Note 3)
PART NUMBER
LTM8073EY#PBF
LTM8073IY#PBF
TERMINAL FINISH
DEVICE
FINISH CODE
TYPE
RATING
SAC305 (RoHS)
LTM8073
e1
BGA
3
–40°C to 125°C
• Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended BGA PCB Assembly and Manufacturing Procedures:
www.linear.com/umodule/pcbassembly
• BGA Package and Tray Drawings: www.linear.com/packaging
• Terminal Finish Part Marking: www.linear.com/leadfree
8073fa
2
For more information www.linear.com/LTM8073
LTM8073
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, RUN = 2V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Minimum Input Voltage
Output DC Voltage
V
Rising
3.4
V
IN
R
R
Open
= 14.3kΩ, V = 60V
0.8
15
V
V
FB
FB
IN
Peak Output DC Current
Quiescent Current Into V
V
= 3.3V, f = 1MHz
5
A
OUT
SW
RUN = 0V
3
300
µA
µA
IN
BIAS = 0V, No Load, SYNC = 0V, Not Switching
Quiescent Current Into BIAS
BIAS = 5V, RUN = 0V
1
275
12
µA
µA
mA
BIAS = 5V, No Load, SYNC = 0V, Not Switching
BIAS = 5V, V
= 3.3V, I
= 3A, f = 1MHz
OUT
OUT
SW
Line Regulation
5.5V < V < 36V, I
= 1A
0.5
0.5
10
%
%
IN
OUT
Load Regulation
0.1A < I
< 3A
OUT
Output Voltage Ripple
Switching Frequency
I
= 3A
mV
OUT
R = 232kΩ
200
0.95
3
kHz
MHz
MHz
T
R = 41.2kΩ
T
R = 10.7kΩ
T
l
Voltage at FB
772
0.9
802
817
3.2
1.06
1
mV
V
Minimum BIAS Voltage
RUN Threshold Voltage
RUN Current
(Note 5)
V
µA
µA
Ω
V
TR/SS Current
TR/SS = 0V
2
TR/SS Pull-Down
TR/SS = 0.1V
FB Falling (Note 6)
FB Rising (Note 6)
PG = 42V
200
0.88
0.73
PG Threshold Voltage at FB (Upper)
PG Threshold Voltage at FB (Lower)
PG Leakage Current
PG Sink Current
V
1
µA
µA
V
PG = 0.1V
150
SYNC Threshold Voltage
SYNC Voltage
Synchronization
0.4
2.9
1.5
4.2
35
To Enable Spread Spectrum
SYNC = 0V
V
SYNC Current
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 4: The LTM8073 contains overtemperature protection that is
intended to protect the device during momentary overload conditions. The
internal temperature exceeds the maximum operating junction temperature
when the overtemperature protection is active. Continuous operation
above the specified maximum operating junction temperature may impair
device reliability.
Note 2: Unless otherwise noted, the absolute minimum voltage is zero.
Note 3: The LTM8073E is guaranteed to meet performance specifications
from 0°C to 125°C internal. Specifications over the full –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM8073I is guaranteed to meet specifications over the full –40°C to
125°C internal operating temperature range. Note that the maximum
internal temperature is determined by specific operating conditions in
Note 5. Below this specified voltage, internal circuitry will draw power
from V .
IN
Note 6. PG transitions from low to high.
8073fa
3
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Efficiency, VOUT = 0.8V, BIAS = 5V
Efficiency, VOUT = 1V, BIAS = 5V
Efficiency, VOUT = 1.2V, BIAS = 5V
90
80
70
60
50
90
80
70
60
50
90
80
70
60
50
12V
24V
36V
48V
IN
IN
IN
IN
12V
12V
IN
IN
24V
36V
48V
24V
IN
IN
IN
IN
36V
IN
48V
IN
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G01
8073 G02
8073 G03
Efficiency, VOUT = 1.5V, BIAS = 5V
Efficiency, VOUT = 1.8V, BIAS = 5V
Efficiency, VOUT = 2V, BIAS = 5V
90
80
70
60
50
95
85
75
65
55
95
85
75
65
55
12V
12V
12V
IN
IN
IN
24V
24V
36V
48V
24V
IN
IN
IN
IN
IN
36V
36V
IN
48V
IN
48V
IN
IN
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G04
8073 G06
8073 G05
Efficiency, VOUT = 2.5V, BIAS = 5V
Efficiency, VOUT = 3.3V, BIAS = 5V
Efficiency, VOUT = 5V, BIAS = 5V
95
85
75
65
55
95
85
75
65
55
95
85
75
65
55
12V
12V
12V
IN
IN
IN
24V
24V
36V
48V
24V
IN
IN
IN
IN
IN
36V
36V
IN
48V
IN
48V
IN
IN
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G08
8073 G09
8073 G07
8073fa
4
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Efficiency, VOUT = 8V, BIAS = 5V
Efficiency, VOUT = 12V, BIAS = 5V
Efficiency, VOUT = 15V, BIAS 5V
100
90
80
70
60
100
90
80
70
60
100
90
80
70
60
12V
24V
24V
IN
IN
IN
IN
IN
24V
36V
48V
36V
36V
IN
IN
IN
IN
48V
48V
IN
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G10
8073 G11
8073 G12
Efficiency, VOUT = –8V, BIAS Tied
to LTM8073 GND
Efficiency, VOUT = –3.3V,
BIAS Tied to LTM8073 GND
Efficiency, VOUT = –5V, BIAS Tied
to LTM8073 GND
90
80
70
60
50
90
80
70
60
50
90
80
70
60
50
12V
12V
12V
IN
IN
IN
IN
IN
IN
24V
24V
36V
48V
24V
IN
IN
36V
36V
IN
48V
IN
48V
IN
IN
0
1
2
3
0
1
2
3
4
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G15
8073 G13
8073 G14
Efficiency, VOUT = –12V, BIAS
Tied to LTM8073 GND
Efficiency, VOUT = –15V, BIAS
Tied to LTM8073 GND
Input vs Load Current
VOUT = 0.8V
90
80
70
60
50
90
80
70
60
50
0.75
0.50
0.25
0
12V
24V
36V
48V
IN
IN
IN
IN
12V
12V
24V
36V
IN
IN
IN
IN
IN
IN
IN
24V
36V
48V
0
1
2
3
0
1
2
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G16
8073 G17
8073 G18
8073fa
5
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Input vs Load Current
Input vs Load Current
VOUT = 1V
Input vs Load Current
VOUT = 1.5V
V
OUT = 1.2V
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
12V
12V
12V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
24V
24V
24V
36V
48V
36V
48V
36V
48V
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G19
8073 G21
8073 G20
Input vs Load Current
VOUT = 1.8V
Input vs Load Current
OUT = 2.5V
Input vs Load Current
VOUT = 3.3V
V
1.5
1.0
0.5
0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
12V
24V
36V
48V
12V
24V
36V
48V
IN
IN
IN
IN
IN
IN
IN
IN
12V
24V
36V
48V
IN
IN
IN
IN
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G22
8073 G23
8073 G24
Input vs Load Current
VOUT = 8V
Input vs Load Current
VOUT = 12V
Input vs Load Current
VOUT = 5V
2.5
2.0
1.5
1.0
0.5
0
4.0
3.0
2.0
1.0
0
3
2
1
0
12V
12V
24V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
24V
24V
36V
36V
48V
36V
48V
48V
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G25
8073 G26
8073 G27
8073fa
6
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Input vs Load Current
VOUT = 15V
Input vs Load Current
VOUT = –3.3V
Input vs Load Current
VOUT = –5V
3
2
1
0
1.50
1.00
0.50
0
2.0
1.5
1.0
0.5
0
24V
36V
48V
12V
24V
36V
48V
12V
24V
36V
48V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G28
8073 G29
8073 G30
Input vs Load Current
VOUT = –15V
Input vs Load Current
OUT = –8V
Input vs Load Current
VOUT = –12V
V
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
12V
24V
36V
48V
12V
24V
36V
48V
12V
24V
36V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
1
2
3
0
1
2
3
0
1
2
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
8073 G31
8073 G32
8073 G33
IBIAS vs Switching Frequency
VBIAS = 5V, VIN = 24V
Dropout Voltage vs Load Current
VOUT = 5V, BIAS Open
Input Current vs VIN
VOUT Shorted, DC2389A Eval Board
1500
1000
500
0
2.0
1.5
1.0
0.5
0
20
16
12
8
4
0
0
1
2
3
4
5
0
10
20
30
40
0
1
2
3
LOAD CURRENT (A)
INPUT VOLTAGE (V)
SWITCHING FREQUENCY (MHz)
8073 G35
8073 G36
8073 G34
8073fa
7
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Maximum Load Current vs VIN
BIAS Tied to LTM8073 GND
Maximum Load Current vs VIN
BIAS Tied to LTM8073 GND
Derating, VOUT = 0.8V, BIAS = 5V,
DC2389A Demo Board
5
4
3
2
1
0
3
2
1
0
5
4
3
2
1
0
0 LFM
12V
24V
36V
48V
IN
IN
IN
IN
–12V
–15V
–3.3V
OUT
OUT
OUT
–5V
OUT
–8V
OUT
0
25
50
75
100
125
0
20
40
60
0
20
40
60
o
AMBIENT TEMPERATURE ( C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
8073 G39
8073 G38
8073 G37
Derating, VOUT = 1.2V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 1.5V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 1V, BIAS = 5V,
DC2389A Demo Board
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
0 LFM
0 LFM
0 LFM
12V
24V
36V
48V
12V
24V
36V
48V
12V
24V
36V
48V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8073 G40
8073 G41
8073 G42
Derating, VOUT = 1.8V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 2.5V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 3.3V, BIAS = 5V,
DC2389A Demo Board
5
4
3
2
1
0
5
4
3
2
1
0
5
4
3
2
1
0
0 LFM
0 LFM
0 LFM
12V
24V
36V
48V
12V
24V
36V
48V
12V
24V
36V
48V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8073 G43
8073 G44
8073 G45
8073fa
8
For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Derating, VOUT = 5V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 12V, BIAS = 5V,
DC2389A Demo Board
Derating, VOUT = 8V, BIAS = 5V,
DC2389A Demo Board
5
4
3
2
1
0
4
3
2
1
0
5
4
3
2
1
0
0 LFM
0 LFM
0 LFM
12V
IN
12V
IN
24V
IN
24V
IN
24V
IN
36V
IN
36V
IN
36V
IN
48V
IN
48V
IN
48V
IN
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8073 G46
8073 G48
8073 G47
Derating, VOUT = –3.3V,
BIAS Tied to LTM8073 GND,
DC2389A Demo Board
Derating, VOUT = –5V,
Derating, VOUT = 15V, BIAS = 5V,
DC2389A Demo Board
BIAS Tied to LTM8073 GND,
DC2389A Demo Board
4
3
2
1
0
4
3
2
1
0
3
2
1
0
0 LFM
0 LFM
0 LFM
12V
24V
36V
48V
12V
24V
36V
48V
IN
IN
IN
IN
IN
IN
IN
IN
24V
IN
36V
IN
48V
IN
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8073 G49
8073 G50
8073 G51
Derating, I-Grade VOUT = –8V,
BIAS Tied to LTM8073 GND,
DC2389A Demo Board
Derating, I-Grade VOUT = –12V,
BIAS Tied to LTM8073 GND,
DC2389A Demo Board
Derating, I-Grade VOUT = –15V,
BIAS Tied to LTM8073 GND,
DC2389A Demo Board
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
3
2
1
0
0 LFM
0 LFM
0 LFM
12V
IN
12V
24V
36V
48V
IN
IN
IN
IN
12V
IN
24V
IN
24V
IN
36V
IN
36V
IN
48V
IN
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
8073 G54
8073 G53
8073 G52
8073fa
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For more information www.linear.com/LTM8073
LTM8073
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
CISPR22 Class B Radiated
DC2389A Demo Board, VOUT = 5V
No Filter (FB1 Short, C8, C9 Open)
CISPR22 Class B Radiated
DC2389A Demo Board, VOUT = 5V
No Filter (FB1 Short, C8, C9 Open)
50
40
30
20
10
0
50
40
30
20
10
0
f
= 1.2MHz, V = 28V, I
= 3.5A
f
= 1.2MHz, V = 14V, I
= 3.5A
OUT
SW
IN
OUT
SW
IN
CLASS B LIMIT
HORIZONTAL
VERTICAL
CLASS B LIMIT
HORIZONTAL
VERTICAL
–10
–10
0
200
400
600
800
1000
0
200
400
600
800
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
8073 G55
8073 G56
pin FuncTions
GND (Bank 1, A1, A6, B3): Tie these GND pins to a
local ground plane below the LTM8073 and the circuit
components. In most applications, the bulk of the heat
flow out of the LTM8073 is through these pads, so the
printed circuit design has a large impact on the ther-
mal performance of the part. See the PCB Layout and
Thermal Considerations sections for more details.
PG (Pin A3): The PG pin is the open-collector output
of an internal comparator. PG remains low until the FB
pin voltage is between 0.73V and 0.88V typical. The PG
signal is valid when V is above 3.4V. If V is above
IN
IN
3.4V and RUN is low, PG will drive low. If this function
is not used, leave this pin floating.
SHARE (Pin A4): Tie this to the SHARE pin of another
LTM8073 to load share. Otherwise leave floating. Do not
drive this pin.
VIN (Bank 2): VIN supplies current to the LTM8073’s
internal regulator and to the internal power switch. These
pins must be locally bypassed with an external, low ESR
capacitor; see Table 1 for recommended values.
RT (Pin A5): The RT pin is used to program the switching
frequency of the LTM8073 by connecting a resistor from
this pin to ground. The Applications Information section
of the data sheet includes a table to determine the resis-
tance value based on the desired switching frequency.
Minimize capacitance at this pin. Do not drive this pin.
VOUT (Bank 3): Power Output Pins. Apply the output
filter capacitor and the output load between these pins
and GND pins.
BIAS (Pin A2): The BIAS pin connects to the internal
power bus. Connect to a power source greater than 3.2V.
If VOUT is greater than 3.2V, connect this pin to AUX.
Decouple this pin with at least 1µF if the voltage source
for BIAS is remote.
FB (Pin B1): The LTM8073 regulates its FB pin to 0.8V.
Connect the adjust resistor from this pin to ground. The
value of R is given by the equation R = 199.7/(V
FB
FB
OUT
– 0.8), where R is in kΩ.
FB
8073fa
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LTM8073
pin FuncTions
AUX (Pin B2): Low Current Voltage Source for BIAS.
In many designs, the BIAS pin is simply connected to
pulse-skipping mode with spread spectrum modulation.
4) Synchronization mode. Drive this pin with a clock
source to synchronize to an external frequency. During
synchronization the part will operate in pulse-skipping
mode.
V
. The AUX pin is internally connected to V
and
isOpUlTaced adjacent to the BIAS pin to ease printed cir-
cuit board routing. Also, some applications require a
feed-forward capacitor; it can be connected from AUX
to FB for convenient PCB routing. Although this pin is
OUT
TR/SS (Pin B5): The TR/SS pin is used to provide a
soft-start or tracking function. The internal 2μA pull-up
current in combination with an external capacitor tied
to this pin creates a voltage ramp. If TR/SS is less than
0.8V, the FB voltage tracks to this value. For tracking, tie
a resistor divider to this pin from the tracked output. This
pin is pulled to ground with an internal MOSFET during
shutdown and fault conditions; use a series resistor if
driving from a low impedance output. This pin may be
left floating if the tracking function is not needed.
internally connected to V , it is not intended to deliver
OUT
a high current, so do not draw current from this pin to
the load.
SYNC (Pin B4): External clock synchronization input
and operational mode. This pin programs four different
operating modes: 1) Burst Mode®. Tie this pin to ground
for Burst Mode operation at low output loads—this
will result in low quiescent current. 2) Pulse-skipping
mode. Float this pin for pulse-skipping mode. This mode
offers full frequency operation down to low output loads
before pulse-skipping mode occurs. 3) Spread spectrum
mode. Tie this pin high (between 2.9V and 4.2V) for
RUN (Pin B6): Pull the RUN pin below 0.9V to shut down
the LTM8073. Tie to 1.06V or more for normal opera-
tion. If the shutdown feature is not used, tie this pin to
the V pin.
IN
block DiagraM
BIAS
AUX
V
IN
2.2µH
CURRENT
MODE
CONTROLLER
V
OUT
0.2µF
249k
10pF
0.1µF
GND
RUN
FB
SHARE
TR/SS
SYNC
RT
PG
8073 BD
8073fa
11
For more information www.linear.com/LTM8073
LTM8073
operaTion
The LTM8073 is a standalone nonisolated step-down
switching DC/DC power supply that can deliver up to 5A.
The continuous current is determined by the internal oper-
ating temperature. It provides a precisely regulated output
voltage programmable via one external resistor from 0.8V
to 15V. The input voltage range is 3.4V to 60V. Given that
the LTM8073 is a step-down converter, make sure that the
input voltage is high enough to support the desired output
voltage and load current. A simplified Block Diagram is
given on the previous page.
The oscillator reduces the LTM8073’s operating frequency
when the voltage at the FB pin is low. This frequency fold-
back helps to control the output current during start-up
and overload.
The TR/SS node acts as an auxiliary input to the error
amplifier. The voltage at FB servos to the TR/SS voltage
until TR/SS goes above about 0.8V. Soft-start is imple-
mented by generating a voltage ramp at the TR/SS pin
using an external capacitor which is charged by an internal
constant current. Alternatively, driving the TR/SS pin with
a signal source or resistive network provides a tracking
function. Do not drive the TR/SS pin with a low imped-
ance voltage source. See the Applications Information
section for more details.
The LTM8073 contains a current mode controller, power
switching elements, power inductor and a modest amount
of input and output capacitance. The LTM8073 is a fixed
frequency PWM regulator. The switching frequency is set
by simply connecting the appropriate resistor value from
the RT pin to GND.
The LTM8073 contains a power good comparator which
trips when the FB pin is between 0.73V and 0.88V, typical.
The PG output is an open-drain transistor that is off when
the output is in regulation, allowing an external resistor
An internal regulator provides power to the control cir-
cuitry. This bias regulator normally draws power from the
V
pin, but if the BIAS pin is connected to an external
to pull the PG pin high. The PG signal is valid when V
IN
IN
voltage higher than 3.2V, bias power is drawn from the
external source (typically the regulated output voltage).
This improves efficiency. The RUN pin is used to place
the LTM8073 in shutdown, disconnecting the output and
reducing the input current to a few μA.
is above 3.4V. If V is above 3.4V and RUN is low, PG
IN
will drive low.
The LTM8073 is equipped with a thermal shutdown that
inhibits power switching at high junction temperatures.
The activation threshold of this function is above 125°C to
avoid interfering with normal operation, so prolonged or
repetitive operation under a condition in which the thermal
shutdown activates may damage or impair the reliability
of the device.
To enhance efficiency, the LTM8073 automatically
switches to Burst Mode operation in light or no load
situations. Between bursts, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current.
8073fa
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LTM8073
applicaTions inForMaTion
For most applications, the design process is straight-
forward, summarized as follows:
output current is limited by junction temperature, the
relationship between the input and output voltage mag-
nitude and polarity and other factors. Please refer to the
graphs in the Typical Performance Characteristics section
for guidance.
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
2. Apply the recommended C , C , R and R values.
IN OUT FB
T
The maximum frequency (and attendant RT value) at
which the LTM8073 should be allowed to switch is given
3. Apply the C (from AUX to FB) capacitor as required.
FF
in Table 1 in the Maximum f column, while the recom-
SW
4. Connect BIAS as indicated.
mended frequency (and R value) for optimal efficiency
T
Whilethesecomponentcombinationshavebeentestedfor
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmental conditions. Bear in mind that the maximum
over the given input condition is given in the f column.
SW
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
Table 1. Recommended Component Values and Configuration (TA = 25°C)
(Note 1) (Note 2)
V
V
R
FB
C
C
OUT
C
BIAS
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
f
R
MAX f
MIN R
T
IN
OUT
IN
FF
SW
T
SW
3.4V to 60V
3.4V to 60V
3.4V to 60V
3.4V to 60V
3.4V to 60V
3.4V to 60V
4V to 60V
0.8V
1V
Open
1M
1µF 100V 1206 X7R 2× 100µF 4V 0805 X5R
1µF 100V 1206 X7R 2× 100µF 4V 0805 X5R
1µF 100V 1206 X7R 2× 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
1µF 100V 1206 X7R 100µF 6.3V 1206 X5R
1µF 100V 1206 X7R 47µF 16V 1210 X7R
1µF 100V 1206 X7R 22µF 25V 1210 X5R
1µF 100V 1206 X7R 22µF 25V 1210 X5R
1µF 100V 1206 X7R 100µF 4V 0805 X5R
47pF
47pF
47pF
27pF
10pF
450kHz
450kHz
500kHz
500kHz
500kHz
600kHz
800kHz
850kHz
1.2MHz
1.4MHz
1.4MHz
1.4MHz
95.3k
95.3k
84.5k
84.5k
84.5k
64.8k
51.1k
47.5k
32.4k
26.7k
26.7k
26.7k
47.5k
475kHz
550kHz
650kHz
750kHz
900kHz
950kHz
1.2MHz
1.5MHz
2.2MHz
3MHZ
90.9k
76.8k
63.4k
54.9k
45.6k
42.2k
32.4K
24.3k
16.9k
10k
1.2V
1.5V
1.8V
2V
499k
287k
200k
169k
118k
80.6k
47.5k
28k
2.5V
3.3V
5V
5V to 60V
7V to 60V
11V to 60V
16V to 60V
19.5V to 60V
3.4V to 56V
8V
12V
15V
–3.3V
17.8k
14.3k
80.6k
3MHZ
10k
3MHZ
10k
LTM8073 850kHz
GND
1.5MHz
24.3k
3.4V to 55V
3.4V to 52V
3.4V to 48V
3.4V to 45V
–5V
–8V
47.5k
28k
1µF 100V 1206 X7R 100µF 6.3V 1206 X5R
1µF 100V 1206 X7R 47µF 16V 1210 X7R
1µF 100V 1206 X7R 22µF 25V 1210 X5R
1µF 100V 1206 X7R 22µF 25V 1210 X5R
LTM8073 1.2MHz
GND
32.4k
26.7k
26.7k
26.7k
2.2MHz
3MHZ
3MHZ
3MHZ
16.9k
10k
LTM8073 1.4MHz
GND
–12V
–15V
17.8k
14.3k
LTM8073 1.4MHz
GND
10k
LTM8073 1.4MHz
GND
10k
Note 1: The LTM8073 may be capable of lower input voltages but may skip switching cycles.
Note 2: An input bulk capacitor is required.
8073fa
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LTM8073
applicaTions inForMaTion
Capacitor Selection Considerations
Frequency Selection
The LTM8073 uses a constant frequency PWM architec-
ture that can be programmed to switch from 200kHz to
3MHz by using a resistor tied from the RT pin to ground.
The C and C
capacitor values in Table 1 are the mini-
OUT
mumIrNecommended values for the associated operating
conditions. Applying capacitor values below those indi-
cated in Table 1 is not recommended, and may result in
undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response,
if it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Table 2 provides a list of R resistor values and their resul-
T
tant frequencies.
Table 2. SW Frequency vs RT Value
f
SW
(MHz)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
3.0
R (kΩ)
T
232
150
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable. X5R
and X7R types are stable over temperature and applied
voltage and give dependable service. Other types, includ-
ing Y5V and Z5U have very large temperature and voltage
coefficients of capacitance. In an application circuit they
may have only a small fraction of their nominal capaci-
tance resulting in much higher output voltage ripple than
expected.
110
84.5
64.8
60.4
51.1
40.2
32.4
28.0
23.7
20.5
16.9
15.8
10
Ceramic capacitors are also piezoelectric. In Burst Mode
operation, the LTM8073’s switching frequency depends
on the load current, and can excite a ceramic capacitor
at audio frequencies, generating audible noise. Since the
LTM8073 operates at a lower current limit during Burst
Mode operation, the noise is typically very quiet to a
casual ear.
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal R
T
value given in Table 1 for the input and output oper-
ating condition. System level or other considerations,
however, may necessitate another operating frequency.
While the LTM8073 is flexible enough to accommodate
a wide range of operating frequencies, a haphazardly
chosen one may result in undesirable operation under
certain operating or fault conditions. A frequency that is
too high can reduce efficiency, generate excessive heat
or even damage the LTM8073 if the output is overloaded
or short-circuited. A frequency that is too low can result
in a final design that has too much output ripple or too
large of an output capacitor.
If this audible noise is unacceptable, use a high perfor-
mance electrolytic capacitor at the output. It may also be
a parallel combination of a ceramic capacitor and a low
cost electrolytic capacitor.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8073. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit.
If the LTM8073 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possi-
bly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
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LTM8073
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BIAS Pin Considerations
paralleled LTM8073s together. To ensure that paralleled
modules start up together, the TR/SS pins may be tied
together, as well. If it is inconvenient to tie the TR/SS pins
together, make sure that the same valued soft-start capac-
itors are used for each µModule regulator. An example of
two LTM8073s configured for load sharing is given in the
Typical Applications section.
The BIAS pin is used to provide drive power for the inter-
nal power switching stage and operate other internal cir-
cuitry. For proper operation, it must be powered by at
least 3.2V. If the output voltage is programmed to 3.2V
or higher, BIAS may be simply tied to AUX If V
is less
.
OUT
than 3.2V, BIAS can be tied to V or some other voltage
IN
For closer load sharing, synchronize the LTM8073s to an
external clock source. When load sharing among n units
source. If the BIAS pin voltage is too high, the efficiency
of the LTM8073 may suffer. The optimum BIAS voltage is
dependent upon many factors, such as load current, input
voltage, output voltage and switching frequency. In all
cases, ensure that the maximum voltage at the BIAS pin
is less than 19V. If BIAS power is applied from a remote
or noisy voltage source, it may be necessary to apply a
decoupling capacitor locally to the pin. A 1µF ceramic
capacitor works well. The BIAS pin may also be left open
at the cost of a small degradation in efficiency.
and using a single R resistor, the value of the resistor is:
FB
199.7
RFB =
n V
–0.8
(
)
OUT
where R is in kΩ.
FB
Burst Mode Operation
To enhance efficiency at light loads, the LTM8073 auto-
matically switches to Burst Mode operation which keeps
the output capacitor charged to the proper voltage while
minimizing the input quiescent current. During Burst
Mode operation, the LTM8073 delivers single cycle bursts
of current to the output capacitor followed by sleep peri-
ods where most of the internal circuitry is powered off
and energy is delivered to the load by the output capacitor.
During the sleep time, V and BIAS quiescent currents
are greatly reduced, so,INas the load current decreases
towards a no load condition, the percentage of time that
the LTM8073 operates in sleep mode increases and the
average input current is greatly reduced, resulting in
higher light load efficiency.
If the LTM8073 is configured to provide a negative output,
do not connect BIAS to V
or AUX. Instead, tie to BIAS
OUT
to the LTM8073 GND, which should be the negative output.
Maximum Load
The maximum practical continuous load that the LTM8073
can drive, while rated at 3A, actually depends upon both
the internal current limit and the internal temperature.
The internal current limit is designed to prevent damage
to the LTM8073 in the case of overload or short-circuit.
The internal temperature of the LTM8073 depends upon
operating conditions such as the ambient temperature,
the power delivered, and the heat sinking capability of the
system. For example, if the LTM8073 is configured to reg-
ulate at 1.2V, it may continuously deliver 4.5A from 12VIN
if the ambient temperature is controlled to less than 55°C;
this is more than the 3A continuous rating. Please see the
derating curve for VOUT = 1.2V in the Typical Performance
Characteristics section. Similarly, if the output voltage is
15V and the ambient temperature is 95°C, the LTM8073
Burst Mode operation is enabled by tying SYNC to GND.
Minimum Input Voltage
The LTM8073 is a step-down converter, so a minimum
amount of headroom is required to keep the output in
regulation. Keep the input above 3.4V to ensure proper
operation. Voltage transients or ripple valleys that cause
the input to fall below 3.4V may turn off the LTM8073.
will deliver at most 2A from 24V , which is less than the
IN
3A continuous rating.
Output Voltage Tracking and Soft-Start
Load Sharing
The LTM8073 allows the user to program its output volt-
age ramp rate by means of the TR/SS pin. An internal 2μA
LTM8073s may be paralleled to produce higher currents.
To do this, tie the V , V
and SHARE pins of all the
IN OUT
8073fa
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LTM8073
applicaTions inForMaTion
pulls up the TR/SS pin to about 2.4V. Putting an external
capacitor on TR/SS enables soft starting the output to
reduce current surges on the input supply. During the soft-
start ramp the output voltage will proportionally track the
TR/SS pin voltage. For output tracking applications, TR/SS
can be externally driven by another voltage source. From
0V to 0.8V, the TR/SS voltage will override the internal
0.8V reference input to the error amplifier, thus regulating
the FB pin voltage to that of the TR/SS pin. When TR/SS is
above 0.8V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage. The TR/SS
pin may be left floating if the function is not needed.
pin, the SYNC pin is floated or held high, the frequency
foldback is disabled and the switching frequency will slow
down only during overcurrent conditions.
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below about 0.4V (this can be ground or a logic low
output). To synchronize the LTM8073 oscillator to an
external frequency connect a square wave (with about
20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.4V
and peaks above 1.5V.
An active pull-down circuit is connected to the TR/SS pin
which will discharge the external soft-start capacitor in
the case of fault conditions and restart the ramp when the
faults are cleared. Fault conditions that clear the soft-start
The LTM8073 will not enter Burst Mode operation at low
output loads while synchronized to an external clock, but
instead will pulse skip to maintain regulation. The LTM8073
may be synchronized over a 200kHz to 3MHz range. The RT
resistor should be chosen to set the LTM8073 switching
frequency equal to or below the lowest synchronization
input. For example, if the synchronization signal will be
capacitor are the RUN pin transitioning low, V voltage
IN
falling too low, or thermal shutdown.
Prebiased Output
500kHz and higher, the R should be selected for 500kHz.
T
As discussed in the Output Voltage Tracking and Soft-Start
section, the LTM8073 regulates the output to the FB volt-
age determined by the TR/SS pin whenever TR/SS is less
than 0.8V. If the LTM8073 output is higher than the target
output voltage, the LTM8073 will attempt to regulate the
output to the target voltage by returning a small amount
of energy back to the input supply. If there is nothing load-
ing the input supply, its voltage may rise. Take care that
it does not rise so high that the input voltage exceeds the
absolute maximum rating of the LTM8073.
For some applications it is desirable for the LTM8073 to
operate in pulse-skipping mode, offering two major dif-
ferences from Burst Mode operation. The first is that the
clock stays awake at all times and all switching cycles
are aligned to the clock. Second is that full switching fre-
quency is reached at lower output load than in Burst Mode
operation. These two differences come at the expense
of increased quiescent current. To enable pulse-skipping
mode, the SYNC pin is floated.
The LTM8073 features spread spectrum operation to fur-
ther reduce EMI/EMC emissions. To enable spread spec-
trum operation, apply between 2.9V and 4.2V to the SYNC
pin. In this mode, triangular frequency modulation is used
to vary the switching frequency between the value pro-
Frequency Foldback
The LTM8073 is equipped with frequency foldback which
acts to reduce the thermal and energy stress on the inter-
nal power elements during a short-circuit or output over-
load condition. If the LTM8073 detects that the output
has fallen out of regulation, the switching frequency is
reduced as a function of how far the output is below the
target voltage. This in turn limits the amount of energy
that can be delivered to the load under fault. During the
start-up time, frequency foldback is also active to limit
the energy delivered to the potentially large output capaci-
tance of the load. When a clock is applied to the SYNC
grammed by R to about 20% higher than that value. The
T
modulation frequency is about 3kHz. For example, when
the LTM8073 is programmed to 2MHz, the frequency will
vary from 2MHz to 2.4MHz at a 3kHz rate. When spread
spectrum operation is selected, Burst Mode operation is
disabled, and the part will run in pulse-skipping mode.
The LTM8073 does not operate in forced continuous
mode regardless of SYNC signal.
8073fa
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LTM8073
applicaTions inForMaTion
Negative Output
V
IN
The LTM8073 is capable of generating a negative output
voltage by connected its VOUT to system GND and the
LTM8073 GND to the negative voltage rail. An example
of this is shown in the Typical Applications section. The
most versatile way to generate a negative output is to
use a dedicated regulator that was designed to generate
a negative voltage, but using a buck regulator like the
LTM8073 to generate a negative voltage is a simple and
cost effective solution, as long as certain restrictions are
kept in mind.
V
V
OUT
IN
LTM8073
GND
FAST LOAD
TRANSIENT
OUTPUT
TRANSIENT
RESPONSE
8073 F01b
Figure 1b. Any Output Voltage Transient Appears on
LTM8073 GND
The CIN and COUT capacitors in figure 1c form an AC
Figure 1a shows a typical negative output voltage applica-
divider at the negative output voltage node. If V is hot-
tion. Note that LTM8073 V
is tied to system GND and
IN
OUT
plugged or rises quickly, the resultant V
will be a posi-
input power is applied from V to LTM8073 V . As a
tive transient, which may be unhealthy fOoUrTthe application
load. An antiparallel Schottky diode may be able to pre-
vent this positive transient from damaging the load. The
location of this Schottky diode is important. For example,
in a system where the LTM8073 is far away from the load,
placing the Schottky diode closest to the most sensitive
load component may be the best design choice. Carefully
evaluate whether the negative buck configuration is suit-
able for the application.
IN
OUT
result, the LTM8073 is not behaving as a true buck regu-
lator, and the maximum output current is depends upon
the input voltage. In the example shown in the Typical
Applications section, there is an attending graph that
shows how much current the LTM8073 deliver for given
input voltages.
V
IN
V
IN
V
OUT
FAST V
IN
TRANSIENT
LTM8073
GND
OUTPUT EXPERIENCES
A POSITIVE TRANSIENT
V
IN
NEGATIVE
OUTPUT VOLTAGE
V
IN
V
OUT
8073 F01a
LTM8073
GND
C
IN
C
OUT
Figure 1a. The LTM8073 Can Be Used to Generate a
Negative Voltage
AC DIVIDER
OPTIONAL
SCHOTTKY
Note that this configuration requires that any load current
transient will directly impress the transient voltage onto
the LTM8073 GND, as shown in Figure 1b, so fast load
transients can disrupt the LTM8073’s operation or even
cause damage. Carefully evaluate whether the negative
buck configuration is suitable for the application.
DIODE
8073 F01c
Figure 1c. A Schottky Diode Can Limit the Transient
Caused by a Fast Rising VIN to Safe Levels
If the LTM8073 is configured to provide a negative output,
do not connect BIAS to V
or AUX. Instead, tie to BIAS to
OUT
the LTM8073 GND, which should be the negative output.
8073fa
17
For more information www.linear.com/LTM8073
LTM8073
applicaTions inForMaTion
Shorted Input Protection
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 3
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
Care needs to be taken in systems where the output is
held high when the input to the LTM8073 is absent. This
may occur in battery charging applications or in battery
backup systems where a battery or some other supply is
diode OR-ed with the LTM8073’s output. If the V pin
A few rules to keep in mind are:
IN
is allowed to float and the RUN pin is held high (either
by a logic signal or because it is tied to VIN), then the
LTM8073’s internal circuitry pulls its quiescent current
through its internal power switch. This is fine if your
system can tolerate a few milliamps in this state. If you
ground the RUN pin, the internal current drops to essen-
1. Place CFF, RFB and RT as close as possible to their
respective pins.
2. Place the C capacitor as close as possible to the V
IN
IN
and GND connection of the LTM8073.
3. Place the COUT capacitor as close as possible to the
and GND connection of the LTM8073.
tially zero. However, if the V pin is grounded while the
IN
V
OUT
output is held high, parasitic diodes inside the LTM8073
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent to or underneath
the LTM8073.
can pull large currents from the output through the V
IN
pin. Figure 2 shows a circuit that runs only when the input
voltage is present and that protects against a shorted or
reversed input.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8073.
V
IN
V
IN
LTM8073
RUN
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of
the thermal vias in Figure 3. The LTM8073 can benefit
from the heat-sinking afforded by vias that connect
to internal GND planes at these locations, due to their
proximity to internal power handling components.
The optimum number of thermal vias depends upon
the printed circuit board design. For example, a board
might use very small via holes. It should employ more
thermal vias than a board that uses larger holes.
8073 F02
Figure 2. The Input Diode Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also Protects
the Circuit from a Reversed Input. The LTM8073 Runs Only
When the Input Is Present.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8073. The LTM8073 is neverthe-
less a switching power supply, and care must be taken to
8073fa
18
For more information www.linear.com/LTM8073
LTM8073
applicaTions inForMaTion
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of
the circuit, though it is likely to be the largest component
in the circuit.
V
IN
GND
C
GND
IN
RUN
R
T
RT TR/SS
Thermal Considerations
SYNC
SHARE
PC
The LTM8073 output current may need to be derated if
it is required to operate in a high ambient temperature.
The amount of current derating is dependent upon the
input voltage, output power and ambient temperature.
The derating curves given in the Typical Performance
Characteristics section can be used as a guide. These
curves were generated by the LTM8073 mounted to a
BIAS AUX
FB
R
FB
GND
C
V
OUT
OUT
2
58cm 4-layer FR4 printed circuit board. Boards of other
GND/THERMAL VIAS
8073 F03
sizes and layer count can exhibit different thermal behav-
ior, so it is incumbent upon the user to verify proper oper-
ation over the intended system’s line, load and environ-
mental operating conditions.
Figure 3. Layout Showing Suggested External Components, GND
Plane and Thermal Vias
For increased accuracy and fidelity to the actual applica-
tion, many designers use FEA (finite element analysis) to
predict thermal performance. To that end, Page 2 of the
data sheet typically gives four thermal coefficients:
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8073. However, these capaci
-
θ
JA
– Thermal resistance from junction to ambient
tors can cause problems if the LTM8073 is plugged into
a live supply (see Linear Technology Application Note
88 for a complete discussion). The low loss ceramic
capacitor combined with stray inductance in series with
the power source forms an underdamped tank circuit,
θ
– Thermal resistance from junction to the bot-
JCbottom
tom of the product case
θ
– Thermal resistance from junction to top of the
JCtop
product case
and the voltage at the V pin of the LTM8073 can ring
IN
to more than twice the nominal input voltage, possibly
exceeding the LTM8073’s rating and damaging the part.
If the input supply is poorly controlled or the LTM8073 is
hot-plugged into an energized supply, the input network
should be designed to prevent this overshoot. This can
be accomplished by installing a small resistor in series
θ
– Thermal resistance from junction to the printed cir-
JB
cuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
to V , but the most popular method of controlling input
IN
voltage overshoot is add an electrolytic bulk cap to the
θJA is the natural convection junction-to-ambient air ther-
mal resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as still
V net. This capacitor’s relatively high equivalent series
IN
resistance damps the circuit and eliminates the voltage
8073fa
19
For more information www.linear.com/LTM8073
LTM8073
applicaTions inForMaTion
air although natural convection causes the air to move.
This value is determined with the part mounted to a JESD
51-9 defined test board, which does not reflect an actual
application or viable operating condition.
portion of the board. The board temperature is measured
a specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that
none of these thermal coefficients reflects an actual physi-
cal operating condition of a µModule regulator. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
θ
is the junction-to-board thermal resistance with
JCbottom
all of the component power dissipation flowing through
the bottom of the package. In the typical µModule regula-
tor, the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test condi-
tions don’t generally match the user’s application.
θJCtop is determined with nearly all of the component
power dissipation flowing through the top of the pack-
age. As the electrical connections of the typical µModule
regulator are on the bottom of the package, it is rare for
an application to operate such that most of the heat flows
from the junction to the top of the part. As in the case of
A graphical representation of these thermal resistances
is given in Figure 4. The blue resistances are contained
within the µModule regulator, and the green are outside.
The die temperature of the LTM8073 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8073. The bulk of the heat flow out of the LTM8073 is
through the bottom of the package and the pads into the
printed circuit board. Consequently a poor printed circuit
board design can cause excessive heating, resulting in
impaired performance or reliability. Please refer to the PCB
Layout section for printed circuit board design suggestions.
θ
, this value may be useful for comparing pack-
JCbottom
ages but the test conditions don’t generally match the
user’s application.
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule regulator and into the board, and is often just
the sum of the θ
and the thermal resistance of the
JCbottom
bottom of the part through the solder joints and through a
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
8073 F04
µMODULE REGULATOR
Figure 4: Graphical Representation of the Thermal Resistances Between the Device Junction and Ambient
8073fa
20
For more information www.linear.com/LTM8073
LTM8073
Typical applicaTions
15VOUT from 19.5VIN to 60VIN Step-Down Converter. BIAS Is Tied to AUX
LTM8073
V
IN
V
IN
19.5V TO 60V
BIAS
AUX
RUN
1µF
V
OUT
V
OUT
15V
2.7A
RT
26.7k
1.4MHz
FB
22µF
GND SYNC
14.3k
8073 TA02
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
1.2VOUT from 3.4VIN to 60VIN Step-Down Converter. BIAS Is Tied to an External 3.3V Source
LTM8073
V
IN
V
IN
3.4V TO 60V
RUN
1µF
V
1.2V
3.5A
OUT
V
OUT
AUX
100µF
×2
EXT 3.3V
BIAS
RT
47pf
499k
GND SYNC
FB
84.5k
500kHz
8073 TA03
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
2.5VOUT from 4VIN to 15VIN Step-Down Converter. BIAS Is Tied to VIN
LTM8073
V
V
IN
IN
4V TO 15V
RUN
BIAS
V
2.5V
3.3A
OUT
V
OUT
1µF
100µF
RT
118k
51.1k
800kHz
GND SYNC
FB
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE, AUX
8073 TA04
8073fa
21
For more information www.linear.com/LTM8073
LTM8073
Typical applicaTions
–5VOUT from 3.4VIN to 55VIN Positive to Negative Converter. BIAS Tied to LTM8073 GND
Maximum Load Current vs VIN,
BIAS Tied to LTM8073 GND
INPUT BULK CAP
5
4
3
2
1
0
V
IN
3.4V TO 35V
V
IN
LTM8073
RUN
OPTIONAL
SCHOTTKY
DIODE
V
OUT
1µF
RT
FB
100µF
32.4k
1.2MHz
47.5k
GND SYNC BIAS
V
OUT
–5V
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE, AUX
8073 TA05a
0
20
40
60
INPUT VOLTAGE (V)
8073 TA05b
Use Two LTM8073s Powered from the Same Input Source to Get More Output Current
LTM8073
V
V
IN
IN
7V TO 40V
BIAS
AUX
RUN
1µF
V
OUT
V
OUT
3.3V
6.5A CONTINUOUS
10A PEAK
RT
47.5k
850kHz
FB
TR/SS
GND SYNC SHARE
100µF
OPTIONAL
SYNC
LTM8073
TR/SS
IN
SHARE
V
BIAS
AUX
RUN
1µF
V
OUT
RT
100µF
47.5k
FB
850kHz
GND SYNC
40.2k
OPTIONAL
SYNC
8073 TA06
PIN NOT USED IN THIS CIRCUIT: PG
8073fa
22
For more information www.linear.com/LTM8073
LTM8073
package DescripTion
Table 3. LTM8073 Pinout (Sorted by Pin Number)
PIN
A1
A2
A3
A4
A5
A6
NAME
GND
BIAS
PG
PIN
B1
B2
B3
B4
B5
B6
NAME
FB
PIN
C1
C2
C3
C4
C5
C6
NAME
GND
PIN
D1
D2
D3
D4
D5
D6
NAME
GND
GND
GND
GND
GND
GND
PIN
E1
E2
E3
E4
E5
E6
NAME
GND
GND
GND
GND
GND
GND
PIN
F1
F2
F3
F4
F5
F6
NAME
GND
GND
GND
GND
GND
GND
PIN
G1
G2
G3
G4
G5
G6
NAME
PIN
H1
H2
H3
H4
H5
H6
NAME
V
V
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AUX
GND
GND
SYNC
TR/SS
RUN
V
V
V
V
IN
IN
IN
IN
SHARE
RT
GND
package phoTos
8073fa
23
For more information www.linear.com/LTM8073
LTM8073
package DescripTion
Please refer to http://www.linear.com/product/LTM8073#packaging for the most recent package drawings.
/ / b b b Z
2 . 5
1 . 5
0 . 5
0 . 0 0 0
0 . 5
1 . 5
2 . 5
a a a Z
8073fa
24
For more information www.linear.com/LTM8073
LTM8073
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/17 Changed recomended BIAS pin connection from Open to LTM8073 GND for the negative voltage output application.
Updated derating curves.
5, 8, 9, 13, 22
8, 9
2
Changed minimum storage temperature from –50°C to –55°C.
8073fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
25
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM8073
Typical applicaTion
1VOUT from 3.4VIN to 60VIN Step-Down Converter with Spread Spectrum. BIAS Is Tied to an External 3.3V Source
LTM8073
V
V
IN
IN
3.4V TO 60V
RUN
1µF
V
OUT
V
OUT
1V
3.4A
AUX
FB
100µF
×2
EXT 3.3V
BIAS
SYNC
47pF
GND
RT
8073 TA07
95.3k
450kHz
PINS NOT USED IN THIS CIRCUIT: TR/SS, PG, SHARE
Design resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM8050
LTM8027
LTM8064
LTM8056
LTM8053
LTM8003
58V, 2A Step-Down µModule Regulator
3.6V ≤ V ≤ 58V, 0.8V ≤ V
≤ 24V, 9mm × 15mm × 4.92mm BGA
≤ 24V, 15mm × 15mm × 4.92mm BGA
IN
OUT
60V, 4A Step-Down µModule Regulator
4.5V ≤ V ≤ 60V, 2.5V ≤ V
IN
OUT
58V, 6A CVCC Step-Down µModule Regulator
6V ≤ V ≤ 58V, 1.2V ≤ V
≤ 36V, 11.9mm × 16mm × 4.92mm BGA
≤ 48V, 15mm × 15mm × 4.92mm BGA
IN
OUT
OUT
58V , 48V
Buck-Boost µModule Regulator
5V ≤ V ≤ 58V, 1.2V ≤ V
IN
IN
OUT
40V, 3.5A/6A Step Down Silent Switcher µModule Regulator
3.4V ≤ V ≤ 40V, 0.97V ≤ V
≤ 15V, 6.25mm × 9mm × 3.32mm BGA
≤ 18V, 6.25mm × 9mm × 3.32mm BGA
IN
OUT
OUT
LTM8053 with H-Grade (150°C Operation) and FMAE Compliant 3.4V ≤ V ≤ 40V. 0.97V ≤ V
Pinout
IN
LTM8032
LTM8033
36V, 2A Low EMI Step-Down µModule Regulator
36V, 3A Low EMI Step-Down µModule Regulator
3.6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 10V, EN55022B Compliant
≤ 24V, EN55022B Compliant
IN
OUT
3.6V ≤ V ≤ 36V. 0.8V ≤ V
IN
OUT
8073fa
LT 0817 REV A • PRINTED IN USA
www.linear.com/LTM8073
LINEAR TECHNOLOGY CORPORATION 2017
26
相关型号：
LTM8050EY#PBF
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LTM8050IY#PBF
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LTM8052AMPV#PBF
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