LTM8062_15 [Linear]
32VIN, 2A Module Power Tracking Battery Chargers;
| 型号： | LTM8062_15 |
| 厂家： | 
Linear |
| 描述： | 32VIN, 2A Module Power Tracking Battery Chargers 电池 |
| 文件： | 总24页 (文件大小：708K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM8062/LTM8062A
32V , 2A µModule Power
IN
Tracking Battery Chargers
FeaTures
DescripTion
The LTM®8062/LTM8062A are complete 32V , 2A
n
Complete Battery Charger System
Input Supply Voltage Regulation Loop for Peak
IN
µModule® powertrackingbatterychargers.TheLTM8062/
LTM8062A provide a constant-current/constant-voltage
charge characteristic, a 2A maximum charge current, and
employ a 3.3V float voltage feedback reference, so any
desired battery float voltage up to 14.4V for the LTM8062
and up to 18.8V for the LTM8062A can be programmed
with a resistor divider.
n
Power Tracking in MPPT (Maximum Peak Power
Tracking) Solar Applications
n
Resistor Programmable Float Voltage Up to 14.4V
on the LTM8062 and 18.8V on the LTM8062A
Wide Input Voltage Range: 4.95V to 32V
(40V Abs Max)
2A Charge Current
Accommodates Li-Ion/Polymer, LiFePO , SLA
Integrated Input Reverse Voltage Protection
User Selectable Termination: C/10 or Termination
Timer
0.75% Float Voltage Reference Accuracy
9mm × 15mm × 4.32mm LGA Package
n
n
The LTM8062/LTM8062A employ an input voltage regula-
tion loop, which reduces charge current if the input volt-
age falls below a programmed level, set with a resistor
divider. When the LTM8062/LTM8062A are powered by a
solar panel, this input regulation loop is used to maintain
the panel at peak output power. The LTM8062/LTM8062A
also feature preconditioning trickle charge, bad battery
detection, a choice of termination schemes and automatic
restart.
n
4
n
n
n
n
applicaTions
The LTM8062/LTM8062A are packaged in a thermally en-
hanced, compact (9mm × 15mm × 4.32mm) over-molded
land grid array (LGA) package suitable for automated
assembly by standard surface mount equipment. The
LTM8062/LTM8062A are RoHS compliant.
n
Industrial Handheld Instruments
n
12V to 24V Automotive and Heavy Equipment
n
Desktop Cradle Chargers
Solar Power Battery Charging
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
2A LiFePO4 µModule Battery Charger
Charge Current vs Battery Voltage
2500
LTM8062
V
IN
V
V
V
BAT
BIAS
INA
NORMAL CHARGING
2000
6V TO 32V
IN
CHRG
FAULT
ADJ
INREG
274k
1500
1000
1-CELL
RUN
TMR
NTC
LiFePO
(3.6V)
4
4.7µF
2.87M
GND
500
PRECONDITION
8062 TA01a
TERMINATION
0
0
1
3
4
2
BATTERY VOLTAGE (V)
8062 TA01b
8062fd
1
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V
V
, V ...................................................................40V
INA IN
BIAS ADJ FAULT CHRG GND
, RUN, CHRG, FAULT ......................V + 0.5, 40V
INREG
IN
7
6
5
4
3
2
1
V
BAT
BANK 2
NTC TMR RUN
INREG
TMR, NTC ................................................................2.5V
BAT (LTM8062).........................................................15V
BAT (LTM8062A) ......................................................20V
BIAS..........................................................................10V
ADJ.............................................................................5V
Maximum Internal Operating Temperature
V
BANK 3
BANK 4
INA
BANK 1
GND
V
IN
(Note 2)................................................................. 125°C
Maximum Body Solder Temperature..................... 245°C
A
B
C
D
E
F
G
H
J
K
L
LGA PACKAGE
77-LEAD (15mm × 9mm × 4.32mm)
T
= 125°C, θ = 17.0°C/W, θ = 6.1°C/W,
JMAX
θ
JA
JCbottom
= 16.2°C/W, θ = 11.2°C/W, WEIGHT = 1.7g
JCtop
JB
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
orDer inForMaTion
LEAD FREE FINISH
LTM8062EV#PBF
LTM8062IV#PBF
LTM8062AEV#PBF
LTM8062AIV#PBF
TRAY
PART MARKING*
LTM8062V
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTM8062EV#PBF
LTM8062IV#PBF
LTM8062AEV#PBF
LTM8062AIV#PBF
77-Lead (15mm × 9mm × 4.32mm) LGA
77-Lead (15mm × 9mm × 4.32mm) LGA
77-Lead (15mm × 9mm × 4.32mm) LGA
77-Lead (15mm × 9mm × 4.32mm) LGA
LTM8062V
LTM8062AV
LTM8062AV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
8062fd
2
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
elecTrical characTerisTics The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C. RUN = 2V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
INA
Maximum Operating Voltage
Start Voltage
32
V
V
V
V
V
V
V
V
V
= 4.2V (Note 3)
7.5
32
BAT
OVLO Threshold
OVLO Hysteresis
UVLO Threshold
UVLO Hysteresis
Rising
35
1
40
IN
V
V
Rising
4.6
0.3
0.55
4.95
IN
to V Diode Forward Voltage Drop
Current = 2A
IN
INA
Maximum BAT Float Voltage
LTM8062
LTM8062A
14.7
19.3
V
V
Input Supply Current
Standby Mode
85
18
µA
µA
RUN = 0, V
= 15V
INREG
Maximum BAT Charging Current
ADJ Float Reference Voltage
(Note 4)
1.8
2.1
A
3.275
3.25
3.3
3.325
3.34
V
V
l
ADJ Recharge Threshold Voltage
ADJ Precondition Threshold Voltage
ADJ Precondition Threshold Hysteresis Voltage
ADJ Input Bias Current
Threshold Relative to ADJ Float Reference
ADJ Rising
82.5
2.3
95
mV
V
Relative to ADJ Precondition Threshold
mV
Charging Terminated
CV Operation
65
110
nA
nA
l
V
V
Reference Voltage
Bias Current
ADJ = 3V, I = 1A
2.61
2.7
27
2.83
V
µA
V
INREG
INREG
BAT
V
V
V
= 2.7V
INREG
NTC Range Limit (High) Voltage
NTC Range Limit (Low) Voltage
NTC Disable Impedance
Rising
1.25
0.27
250
45
1.36
0.29
500
1.45
NTC
NTC
Falling
0.315
V
kΩ
µA
%
NTC Bias Current
V
= 0.8V
53
NTC
NTC Threshold Hysteresis
RUN Threshold Voltage
For Both High and Low Range Limits
Rising
20
V
1.15
1.20
120
–10
1.25
V
RUN
RUN Hysteresis Voltage
mV
nA
V
RUN Input Bias Current
CHRG, FAULT Output Low Voltage
TMR Charge/Discharge Current
TMR Disable Threshold Voltage
Operating Frequency
10mA Load
0.4
25
0.25
1
µA
V
0.85
1.15
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: This parameter is valid for programmed output battery float
Note 2: The LTM8062E/LTM8062AE are guaranteed to meet performance
specifications from 0°C to 125°C internal. Specifications over the full
–40°C to 125°C internal operating temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM8062I/LTM8062AI are guaranteed to meet specifications over
the full –40°C to 125°C internal operating temperature range. Note that
voltages ≤ 4.2V. For other float voltages, V Start is 3.3V above the
programmed output battery float voltage. This parameter is guaranteed by
design, characterization, and correlation with statistical process controls.
Note 4: The maximum BAT charging current is reduced by thermal
foldback. See the Typical Performance Characteristics for details.
IN
8062fd
3
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
Efficiency vs IBAT, 4.2V Float
Efficiency vs IBAT, 7.2V Float
Efficiency vs IBAT, 8.4V Float
84
82
80
78
76
74
72
70
87
86
85
84
83
82
81
80
88
87
86
85
84
83
82
81
V
= 12V
INA
V
= 12V
INA
V
= 24V
INA
V
= 24V
INA
V
= 24V
INA
V
= 12V
INA
0
500
1500
2000
0
500
1500
2000
1000
(mA)
1000
I (mA)
BAT
0
500
1500
2000
2500
1000
I
I
(mA)
BAT
BAT
8062 G01
8062 G02
8062 G03
Efficiency vs IBAT, 14.4V Float
Efficiency vs IBAT, 18.8V Float
ADJ Float Voltage vs Temperature
3.280
3.275
3.270
3.265
93
92
91
90
89
88
87
86
90
89
88
87
86
85
84
83
82
V
= 24V
INA
V
= 24V
INA
–50 –25
25
50
75 100 125
0
500
1500
2000
0
0
500
1500
2000
1000
(mA)
1000
(mA)
TEMPERATURE (°C)
I
I
BAT
BAT
8062 G05
8062 G23
8062 G04
IBIAS vs IBAT, 4.2V Float
I
BIAS vs IBAT, 7.2V Float
IBIAS vs IBAT, 8.4V Float
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
V
= 12V
V
= 12V
INA
INA
V
= 12V
INA
V
= 24V
1500
INA
V
= 24V
1500
INA
V
= 24V
INA
0
0
0
0
500
2000
0
500
1500
2000
1000
(mA)
1000
I (mA)
BAT
0
500
2000
1000
(mA)
I
I
BAT
BAT
8062 G06
8062 G08
8062 G07
8062fd
4
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
TA = 25°C, unless otherwise noted.
Typical perForMance characTerisTics
IBIAS vs IBAT, 14.4V Float
IBIAS vs IBAT, 18.8V Float
Input Current vs IBAT, 4.2V Float
50
45
40
35
30
25
20
15
10
5
900
45
40
35
30
25
20
15
10
5
V
= 24V
INA
800
700
V
= 12V
V
= 24V
INA
INA
600
500
400
300
200
100
0
V
INA
= 24V
0
0
0
500
1500
2000
1000
(mA)
0
500
1500
2000
1000
(mA)
0
500
1500
2000
1000
(mA)
I
I
I
BAT
BAT
BAT
8062 G24
8062 G10
8062 G09
Input Current vs IBAT, 7.2V Float
Input Current vs IBAT, 8.4V Float
Input Current vs IBAT, 14.4V Float
1400
1200
1000
800
600
400
200
0
1600
1400
1200
1000
800
600
400
200
0
1400
1200
1000
800
600
400
200
0
V
= 12V
INA
V
= 12V
INA
V
= 24V
INA
V
= 24V
INA
V
= 24V
INA
0
500
1500
2000
0
500
1500
(mA)
2000
2500
1000
(mA)
1000
I
0
500
1500
2000
1000
(mA)
I
I
BAT
BAT
BAT
8062 G11
8062 G12
8062 G13
Maximum IBAT vs ADJ
IQ vs VINA, RUN = 0V, VINREG Open
Input Current vs IBAT, 18.8V Float
2500
2000
1500
1000
500
250
200
150
100
50
1600
1400
1200
1000
800
600
400
200
0
V
= 24V
INA
0
0
1000
(mA)
0
500
1500
2000
0
0.5
1
1.5
ADJ VOLTAGE (V)
3
3.5
0
10
30
40
2
2.5
20
(V)
I
V
BAT
INA
8062 G25
8062 G15
8062 G14
8062fd
5
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
Typical perForMance characTerisTics
Maximum Charge Current
TA = 25°C, unless otherwise noted.
Temperature Rise vs IBAT
4.2V Float Voltage
,
Maximum IBAT vs VINREG
vs Temperature
2000
1600
1200
800
400
0
25
20
15
10
5
2500
2000
1500
1000
500
V
= 24V
INA
V
INA
= 12V
0
0
–40 –20
0
40
80 100 120
0
500
1500
2000
20
60
1000
(mA)
2
3
3.5
2.5
TEMPERATURE (°C)
I
V
(V)
BAT
INREG
8062 G17
8062 G18
8062 G16
Temperature Rise vs IBAT
,
Temperature Rise vs IBAT
,
Temperature Rise vs IBAT
,
7.2V Float Voltage
8.4V Float Voltage
14.4V Float Voltage
40
35
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
V
= 12V
INA
V
V
= 24V
V
INA
V
= 24V
INA
= 24V
= 12V
1500
INA
INA
0
0
0
0
500
1500
2000
0
500
1500
2000
0
500
2000
1000
(mA)
1000
I (mA)
BAT
1000
(mA)
I
I
BAT
BAT
8062 G20
8062 G21
8062 G19
Temperature Rise vs IBAT
,
VIN Standby Mode Current
vs Temperature
18.8V Float Voltage
Minimum VIN vs VBAT 1.7A Load
6
5
4
3
2
1
0
25
20
45
40
35
30
25
20
15
10
5
V
= 24V
INA
15
10
5
V
= 12V
INA
V
= 24V
INA
0
0
0
500
1500
2000
–50
0
100
0
5
15
20
1000
(mA)
50
10
(V)
I
TEMPERATURE (°C)
V
BAT
BAT
8062 G26
8062 G22
8062 G27
8062fd
6
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
pin FuncTions
GND (Bank 1, Pin L7): Power and Signal Ground Return.
ofthetemperaturethresholds.Thetemperaturemonitoring
function remains enabled while thermistor resistance to
ground is less than 250kΩ. If this function is not desired,
leave the NTC pin unconnected.
BAT (Bank 2): Battery Charge Current Output Bus. The
charge function operates to achieve the final float voltage
atthispin.Theauto-restartfeatureinitiatesanewcharging
cycle when the voltage at the ADJ pin falls 2.5% below
the float voltage. Once the charge cycle is terminated, the
input bias current of the BAT pin is reduced to minimize
battery discharge while the charger remains connected.
ADJ (Pin H7): Battery Float Voltage Feedback Input. The
charge function operates to achieve a final float voltage of
3.3Vonthispin.Theoutputbatteryfloatvoltage(V
)
BAT(FLT)
is programmed using a resistor divider. V
can be
BAT(FLT)
programmed up to 14.4V. The auto-restart feature initi-
ates a new charging cycle when the voltage at the ADJ
pin falls 2.5% below the float voltage reference. The ADJ
pin input bias current is 110nA. Using a resistor divider
with an equivalent input resistance at the ADJ pin of 250k
compensatesforinputbiascurrenterror.Requiredresistor
V
(Bank 3): Anode of input reverse protection Schottky
INA
diode. Connect the input power here if input reverse volt-
age protection is desired.
V (Bank 4): Charger Input Supply. Decouple with at least
4.7µF to GND. Connect the input power here if no input
reverse voltage protection is needed.
IN
values to program desired V
follow the equations:
BAT(FLT)
BIAS (Pin G7): The BIAS pin connects to the internal
V
BAT(FLT) • 2.5 •105
power bus. In most cases connect to V . If this is not
BAT
R1=
R2 =
(Ω)
desirable, connect to a power source greater than 2.8V
and less than 10V.
3.3
R1• 2.5 •105
R1−(2.5 •105)
(Ω)
CHRG (Pin K7): Open-Collector Charger Status Output;
typically pulled up through a resistor to a reference
voltage. This status pin can be pulled up to voltages as
R1 is connected from BAT to ADJ, and R2 is connected
from ADJ to ground.
high as V and can sink currents up to 10mA. During
IN
a battery charging cycle, CHRG is pulled low. When the
charge current falls below C/10, the CHRG pin becomes
high impedance. If the internal timer is used for termina-
tion, the pin stays low during the charging cycle until the
charge current drops below a C/10 rate, approximately
200mA, even though the charger will continue to top off
the battery until the end-of-charge timer terminates the
charge cycle. A temperature fault also causes this pin to
be pulled low (see the Applications Information section).
FAULT (Pin J7): Open-Collector Fault Status Output; typi-
cally pulled up through a resistor to a reference voltage.
This status pin can be pulled up to voltages as high as
V and can sink currents up to 10mA. This pin indicates
IN
charge cycle fault conditions during a battery charging
cycle. A temperature fault causes this pin to be pulled
low. If the internal timer is used for termination, a bad bat-
tery fault also causes this pin to be pulled low. If no fault
conditions exist, the FAULT pin remains high impedance
(see the Applications Information section).
NTC (Pin H6): Battery Temperature Monitor Pin. This pin
is the input to the NTC (negative temperature coefficient)
thermistortemperaturemonitoringcircuit.Thisfunctionis
enabled by connecting a 10kΩ, B = 3380 NTC thermistor
from the NTC pin to ground. The pin sources 50μA, and
monitorsthevoltageacrossthe10kΩthermistor.Whenthe
voltageonthispinisabove1.36V(T<0°C)orbelow0.29V
(T > 40°C), charging is disabled and the CHRG and FAULT
pins are both pulled low. If the internal timer termination is
being used, the timer is paused, suspending the charging
cycle. Charging resumes when the voltage on NTC returns
towithinthe0.29Vto1.36Vactiveregion.Thereisapproxi-
mately5°Coftemperaturehysteresisassociatedwitheach
TMR (Pin J6): End-Of-Cycle Timer Programming Pin.
If a timer-based charge termination is desired, connect
a capacitor from this pin to ground. Full charge end-of
cycle time (in hours) is programmed with this capacitor
following the equation:
6
t
= C
• 4.4 • 10
EOC
TIMER
A bad battery fault is generated if the battery does not
reachthepreconditionthresholdvoltagewithinone-eighth
of t , or:
EOC
5
t
= C
• 5.5 • 10
PRE
TIMER
8062fd
7
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
pin FuncTions
A 0.68μF capacitor is often used, which generates a timer
EOC at three hours, and a precondition limit time of 22.5
minutes. If a timer-based termination is not desired, the
timer function can be disabled by connecting the TMR
pin to ground. With the timer function disabled, charging
terminates when the charge current drops below a C/10
rate, approximately 200mA.
the maximum charge current required to maintain the
programmed operational V voltage, through maintain-
IN
ing the voltage on V
at or above 2.7V. If the voltage
INREG
regulation feature is not used, connect the pin to V .
IN
RUN (Pin K6): Precision Threshold Enable Input Pin. The
RUN threshold is 1.25V (rising), with 120mV of input hys-
teresis.Wheninshutdownmode,allchargingfunctionsare
disabled. The precision threshold allows use of the RUN
pin to incorporate UVLO functions. If the RUN pin is pulled
below 0.4V, the IC enters a low current shutdown mode
V
(Pin L6): Input Voltage Regulation Reference. The
INREG
maximumchargecurrentisreducedwhenthispinisbelow
2.7V. There is a 100k resistor to GND. Connecting a resis-
tor from V to this pin sets the minimum operational V
voltage. This is typically used to program the peak power
voltage for a solar panel. The LTM8062/LTM8062A servo
where the V pin current is reduced to 15μA. Typical RUN
IN
IN
IN
pin input bias current is 10nA. If the shutdown function is
not desired, connect the pin to the V pin.
IN
block DiagraM
V
V
IN
INA
SENSE
RESISTOR
BAT
8.2µH
10µF (LTM8062)
2.2µF (LTM8062A)
0.1µF
0.1µF
BIAS
V
INREG
100k
INTERNAL
COMPENSATION
ADJ
RUN
ADJ
TMR
NTC
CURRENT
MODE
BATTERY
MANAGEMENT
CONTROLLER
GND
FAULT
CHRG
8062 BD
8062fd
8
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
operaTion
The LTM8062/LTM8062A are complete monolithic, mid-
power, power tracking battery chargers, addressing
high input voltage applications with solutions that use a
minimum of external components. The products can be
programmed for float voltages between 3.3V and 14.4V
(LTM8062) or between 3.3V and 18.8V (LTM8062A) with
just two external resistors, operating under a 1MHz fixed
frequency,averagecurrentmodestep-downarchitecture.A
2A power Schottky diode is integrated within the μModule
charger for reverse input voltage protection. A wide input
range allows the operation to full charge from an input
voltage up to 32V. A precision threshold on the RUN pin
allows the implementation of a UVLO feature by using a
simple resistor network. The charger can also be put into
a low current shutdown mode, in which the input supply
bias is reduced to only 15μA.
also contain an internal charge cycle control timer, for
timer-based termination. When using the internal timer,
the charge cycle can continue beyond the C/10 level to
top-off the battery. The charge cycle terminates when
the programmed time elapses, about three hours for a
0.68µF timer capacitor. The CHRG status pin continues
to signal charging at a C/10 or greater rate, regardless of
which termination scheme is used. When the timer-based
schemeisused,theLTM8062/LTM8062Aalsosupportbad
battery detection, which triggers a system fault if a battery
stays in precondition mode for more than one-eighth of
the total programmed charge cycle time.
OncechargingterminatesandtheLTM8062/LTM8062Aare
not actively charging, the charger automatically enters a
low current standby mode in which supply bias currents
are reduced to 85μA. If the battery voltage drops 2.5%
fromthefullchargefloatvoltage,theLTM8062/LTM8062A
engage an automatic charge cycle restart. The IC also au-
tomatically restarts a new charge cycle after a bad-battery
fault once the failed battery is removed and replaced with
another battery. The LTM8062/LTM8062A contain a bat-
tery temperature monitoring circuit. This feature, using a
thermistor,monitorsbatterytemperatureandwillnotallow
charging to begin, or will suspend charging, and signal
a fault condition if the battery temperature is outside a
safe charging range. The LTM8062/LTM8062A contain
two digital open-collector outputs, CHRG and FAULT,
which provide charger status and signal fault conditions.
These binary coded pins signal battery charging, standby
or shutdown modes, battery temperature faults and bad
battery faults. For reference, C/10 and TMR based charg-
ing cycles are shown in Figures 1 and 2.
The LTM8062/LTM8062A employ an input voltage regula-
tion loop, which reduces charge current if a monitored
input voltage falls below a programmed level at the V
INREG
pin. There is a 1% 100k resistor to GND at this pin. When
the LTM8062/LTM8062A are powered by a solar panel,
the input regulation loop is used to maintain the panel at
peakoutputpower.TheLTM8062/LTM8062Aautomatically
enter a battery precondition mode if the sensed battery
voltage is very low. In this mode, the charge current is
reduced to 300mA. Once the battery voltage climbs above
the internally set precondition threshold (2.3V at the ADJ
pin), the μModule charger automatically increases the
maximum charge current to the full programmed value.
The LTM8062/LTM8062A can use a charge current based
C/10 termination scheme, which ends a charge cycle
when the battery charge current falls to one-tenth the
programmed charge current. The LTM8062/LTM8062A
8062fd
9
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
operaTion
FLOAT VOLTAGE
RECHARGE THRESHOLD
BATTERY VOLTAGE
PRECONDITION THRESHOLD
MAXIMUM CHARGE CURRENT
BATTERY CHARGE
CURRENT
PRECONDITION CURRENT
C/10
0 AMPS
1
CHRG
FAULT
0
1
0
1
RUN
0
8062 F01
Figure 1. Typical C/10 Terminated Charge Cycle (TMR Grounded, Time Not to Scale)
FLOAT VOLTAGE
RECHARGE THRESHOLD
BATTERY VOLTAGE
PRECONDITION THRESHOLD
MAXIMUM CHARGE CURRENT
BATTERY CHARGE
CURRENT
PRECONDITION CURRENT
C/10 CURRENT
1
CHRG
FAULT
0
1
0
1
RUN
0
< t /8
EOC
t
EOC
AUTOMATIC
RESTART
8062 F02
Figure 2. Typical EOC (Timer-Based) Terminated Charge Cycle
(Capacitor Connected to TMR, Time Not to Scale)
8062fd
10
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LTM8062/LTM8062A
applicaTions inForMaTion
For most applications, the design process is straight
forward, summarized as follows:
V Input Supply
IN
The LTM8062/LTM8062A are biased directly from the
charger input supply through the V pin. This pin pro-
1. Look at Table 1 and find the row that has the desired
input voltage range and battery float voltage.
IN
vides large switched currents, so a high quality low ESR
decoupling capacitor is recommended to minimize volt-
2. Apply the recommended C and R
values.
IN
ADJ
age glitches on V . 4.7μF is typically adequate for most
IN
3. Connect BIAS as indicated.
charger applications.
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction tempera-
ture, therelationshipbetweentheinputandoutputvoltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
Reverse Protection Diode
The LTM8062/LTM8062A integrate a high voltage power
Schottky diode to provide input reverse voltage protec-
tion. The anode of this diode is connected to V , and
INA
the cathode is connected to V . There is a small amount
IN
of capacitance at each end; please see the Block Diagram.
The integrated diode can also be used to block battery
discharge leakage paths. The LTM8062/LTM8062A switch
and drive circuitry are designed to stand off some reverse
Table 1. Recommended Component Values and Configuration
(TA = 25°C)
voltage from BAT to V , but leakage paths exist that can
IN
R
R
ADJ2
BOTTOM
(kΩ)
put a small load on the battery if V falls below BAT.
ADJ1
IN
TOP
Specifically, the RUN pin has a small bias current and
V
RANGE (V)*
6 to 32
V
(V)
C
IN
(kΩ)
IN
BAT
there is a 100k resistor tied to V
to GND. If either
INREG
3.6
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
4.7µF 1206 X7R 50V
274
312
2870
1260
1150
835
464
459
417
412
383
344
340
328
332
328
312
309
301
of these pins is connected to V when it is below BAT,
IN
6 to 32
4.1
4.2
it can present a small but finite discharge current to the
6 to 32
320
battery. This discharge current may be blocked by the
6.25 to 32
9.5 to 32
9.75 to 32
11 to 32
4.7
357
integrated Schottky diode if the RUN and V
circuits
INREG
7.05
7.2
530
are tied to V
.
INA
549
8.2
626
Input Supply Voltage Regulation
11.5 to 32
12.75 to 32
16.5 to 32
17 to 32
8.4
642
The LTM8062/LTM8062A contain a voltage monitor pin
that enables programming a minimum operational volt-
age. There is a 1% 100k resistor from V
Connecting a resistor from V to the V
programming of minimum input supply voltage, typically
used to program the peak power voltage for a solar panel.
Maximum charge current is reduced when the V
is below the regulation threshold of 2.7V.
9.4
715
12.3
12.6
13.5
942
to GND.
pin enables
INREG
965
IN
INREG
18.25 to 32
19 to 32
1020
1090
1110
1240
1270
1420
14.08
14.42
16.4
19.5 to 32
23 to 32
pin
INREG
23.5 to 32
26 to 32
16.8
If the V
function is not used, and if the input supply
INREG
18.8
cannot provide enough power to satisfy the requirements
ofanLTM8062/LTM8062Acharger,theinputsupplyvoltage
*Operating range, V must be 3.3V above V to start. Input bulk
IN
BAT
capacitance is required.
8062fd
11
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LTM8062/LTM8062A
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will collapse. A minimum operating supply voltage can
thus be programmed by monitoring the supply through
a resistor divider, such that the desired minimum voltage
physically located far from the battery and the added line
impedance may interfere with the control loop. Case 2:
the battery ESR is very small or very large; the LTM8062/
LTM8062Acontrollerisdesignedforawiderange,butsome
battery packs have an ESR outside of this range. Case 3:
there is no battery at all. As the charger is designed to
work with the ESR of the battery, the output may oscillate
if no battery is present.
corresponds to 2.7V at the V
pin. The LTM8062/
INREG
LTM8062A servo the maximum output charge current to
maintain the voltage on V at or above 2.7V.
INREG
Programming of the desired minimum voltage is accom-
plished by connecting a resistor as shown in Figure 3.
The optimum ESR is about 100mΩ, but ESR values both
higher and lower will work. Table 2 shows a sample of
parts successfully tested by Linear Technology:
100VIN –270
R =
k
IN
2.7
Table 2
PART NUMBER
If the voltage regulation feature is not used, connect the
V
pin to V .
DESCRIPTION
MANUFACTURER
Sanyo
INREG
IN
16TQC22M
22µF, 16V, POSCAP
18µF, 35V, OS-CON
22µF, 25V Tantalum
22µF, 25V, Tantalum
68µF, 6V, Tantalum
47µF, 6V, Tantalum
68µF, 10V Aluminum
68µF, 25V Aluminum
35SVPD18M
Sanyo
LTM8062
INPUT SUPPLY
V
V
IN
TPSD226M025R0100
T495D226K025AS
TPSC686M006R0150
TPSB476M006R0250
APXE100ARA680ME61G
APS-150ELL680MHB5S
AVX
R
IN
Kemet
INREG
AVX
8062 F03
AVX
Nippon Chemicon
Nippon Chemicon
Figure 3. Resistive Divider Sets Minimum VIN
BIAS Pin Considerations
If system constraints preclude the use of electrolytic ca-
pacitors, aseriesR-Cnetworkmaybeused. Useaceramic
capacitor of at least 22µF and an equivalent resistance of
100mΩ. An example of this is shown in the Typical Ap-
plications section.
The BIAS pin is used to provide drive power for the in-
ternal power switching stage and operate other internal
circuitry. For proper operation, it must be powered by at
least 2.8V and no more than the absolute maximum rat-
ing of 10V. In most applications, connect BIAS to BAT. If
there is no BIAS supply available or the battery voltage is
below 2.8V, the internal switch requires more headroom
MPPT Temperature Compensation
A typical solar panel is comprised of a number of series-
connectedcells,eachcellbeingaforward-biasedp-njunc-
from V for proper operation. Please refer to the Typical
IN
PerformanceCharacteristicscurvesforminimumstartand
running requirements under various battery conditions.
When charging a 2-cell battery using a relatively high
input voltage, the LTM8062/LTM8062A power dissipation
can be reduced by connecting BIAS to a voltage between
2.8V and 3.3V.
tion. As such, the open-circuit voltage (V ) of a solar cell
OC
has a temperature coefficient that is similar to a common
p-ndiode,orabout–2mV/°C.Thepeakpowerpointvoltage
(V ) for a crystalline solar panel can be approximated as
MP
a fixed voltage below V , so the temperature coefficient
OC
for the peak power point is similar to that of V .
OC
Output Capacitance
Panel manufacturers typically specify the 25°C values for
V , V , and the temperature coefficient for V , making
OC MP
OC
In many applications, the internal BAT capacitance of the
LTM8062/LTM8062A is sufficient for proper operation.
There are cases, however, where it may be necessary to
add capacitance or otherwise modify the output imped-
ance of the LTM8062/LTM8062A. Case 1: the µModule is
determination of the temperature coefficient for V of a
MP
typical panel straight forward. The LTM8062/LTM8062A
employs a feedback network to program the V input
IN
regulation voltage. Manipulation of the network makes for
8062fd
12
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LTM8062/LTM8062A
applicaTions inForMaTion
efficientimplementationofvarioustemperaturecompensa-
tionschemesforamaximumpeakpowertracking(MPPT)
application. As the temperature characteristic for a typical
As the temperature coefficient for V is similar to that
MP
of V , the specified temperature coefficient for V
OC
OC
(TC) of –78mV/°C and the specified peak power voltage
solar panel V voltage is highly linear, a simple solution
(V (25°C))of17.6Vcanbeinsertedintotheequationsto
MP
MP
fortrackingthatcharacteristiccanbeimplementedusinga
Linear Technology LM234 3-terminal temperature sensor.
This creates an easily programmable, linear temperature
dependent characteristic.
calculatetheappropriateresistorvaluesforthetemperature
compensation network in Figure 4. Initially, determine the
R
SET
value using the following equation:
1
0.0677
2.7
In the circuit shown in Figure 4,
RSET =100
+
–
–78mV/°C•4405
100VMP 25°C
(
)
–100
17.6
V
INREG
kΩ⇒ 4.12kΩ
R =
kΩ
IN
–78mV /°C•4405•2.7
100000•0.0677
1–
VINREG •RSET
Then, R can be determined using the calculated R
IN
SET
value:
1
0.0677
RSET =100
+
–
TC•4405 V
INREG
100•17.6V
–100
2.7
R =
kΩ⇒1400kΩ
VMP 25°C
(
)
IN
100000•0.0677
kΩ
1–
TC•4405•V
INREG
2.7•4120
where TC = temperature coefficient (in V/°C), and
MP
Battery Voltage Temperature Compensation
V
(25°C) = maximum power voltage at 25°C.
Some battery chemistries have charge voltage require-
ments that vary with temperature. Lead-acid batteries in
particular experience a significant change in charge volt-
age requirements as temperature changes. For example,
manufacturers of large lead-acid batteries recommend
a float charge of 2.25V/cell at 25°C. This battery float
voltage, however, has a temperature coefficient which is
typically specified at –3.3mV/°C per cell.
V
IN
LINEAR
TECHNOLOGY
+
V
V
LM234
R
R
IN
–
V
IN
R
SET
V
INREG
LTM8062
8062 F04
In a manner similar to the MPPT temperature correction
outlinedpreviously,implementationoflinearbatterycharge
voltagetemperaturecompensationcanbeaccomplishedby
incorporating a Linear Technology LM234 into the output
feedback network. For example, a 6-cell lead acid battery
has a float charge voltage that is commonly specified at
2.25V/cellat25°C,or13.5V,anda–3.3mV/°Cpercelltem-
perature coefficient, or –19.8mV/°C. Using the feedback
Figure 4. MPPT Temperature Compensation Network
For example, given a common 36-cell solar panel that has
the following specified characteristics:
Open Circuit Voltage (V ) = 21.7V
OC
Maximum Power Voltage (V ) = 17.6V
MP
Open-Circuit Voltage Temperature Coefficient (V )
OC
= –78mV/°C
8062fd
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LTM8062/LTM8062A
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network shown in Figure 5, with the desired temperature
While the circuit in Figure 5 creates a linear tempera-
ture characteristic that follows a typical –3.3mV/°C per
cell lead-acid specification, the theoretical float charge
voltage characteristic is slightly nonlinear. This nonlinear
characteristic follows the relation:
coefficient (TC) and 25°C float voltage (V
(25°C))
FLOAT
specified, and using a convenient value of 2.4k for R
necessary resistor values follow the relations:
,
SET
R
FB1
= –R • (TC • 4405)
SET
–5
2
–3
V
= 4 • 10 (T ) – 6 • 10 (T) + 2.375
= –2.4k • (–0.0198 • 4405) ⇒ 210kΩ
FLOAT
(with a 2.18V minimum)
RFB1
FLOAT(25°C)+RFB1 •(0.0674/RSET
RFB2
=
where T = temperature in °C. A thermistor-based network
can be used to approximate the nonlinear ideal tempera-
ture characteristic across a reasonable operating range,
as shown in Figure 6.
V
)
-1
V
FB
210k
=
13.5+210k •(0.0674/2.4k)
-1
3.3
BAT
⇒ 43kΩ
+
6-CELL
LEAD-ACID
BATTERY
196k
69k
LTM8062
R
= 250k – R ||R
FB3
FB1 FB2
= 250k – 210k||43k ⇒ 215kΩ
22k
B = 3380
198k
ADJ
(see the Battery Float Voltage Programming section)
69k
8062 F06a
BAT
+
14.8
+
V
V
LINEAR
TECHNOLOGY
LM234
R
FB1
6-CELL
LEAD-ACID
BATTERY
LTM8062
R
14.6
14.4
14.2
210k
–
R
SET
R
FB3
2.4k
215k
ADJ
R
14.0
13.8
13.6
13.4
13.2
FB2
43k
THEORETICAL V
BAT(FLOAT)
FLOAT
8062 F05a
14.3
14.2
14.0
13.8
13.6
13.4
13.2
13.0
12.8
12.6
PROGRAMMED V
13.0
12.8
–19.8mV/°C
–10
0
10
20
30
40
50
60
TEMPERATURE (°C)
8062 F06b
Figure 6. Thermistor-Based Temperature Compensation Network
Programs VFLOAT to Closely Match Ideal Lead-Acid Float Charge
Voltage for 6-Cell Charger
Status Pins
–10
0
10
20
30
40
50
60
TEMPERATURE (°C)
The LTM8062/LTM8062A report charger status through
8062 F05b
two open-collector outputs, the CHRG and FAULT pins.
Figure 5. Lead-Acid 6-Cell Float Charge Voltage vs Temperature
with a –19.8mV/°C Temperature Coefficient Using LM234 with
the Feedback Network
These pins can be pulled up as high as V , and can sink
IN
up to 10mA. The CHRG pin indicates that the charger is
delivering current at greater than a C/10 rate, or one-tenth
8062fd
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of the programmed charge current. The FAULT pin signals
bad-battery and NTC faults. These pins are binary coded,
as shown in Table 3.
TMR pin to ground. The timer cycle time span (t ) is
EOC
determined by C
in the equation:
TIMER
–7
C
TIMER
= t
• 2.27 • 10 (Hours)
EOC
Table 3. Status Pin State
When charging at a 1C rate, t
is commonly set to three
EOC
CHRG FAULT
STATUS
hours, which requires a 0.68μF capacitor.
High
High
Low
Low
High
Low
High
Low
Not Charging—Standby or Shutdown Mode
Bad-Battery Fault (Precondition Timeout/EOC Failure)
Normal Charging at C/10 or Greater
NTC Fault (Pause)
TheCHRGstatuspincontinuestosignalcharging, regard-
less of which termination scheme is used. When timer
termination is used, the CHRG status pin is pulled low
during a charge cycle until the charge current falls below
the C/10 threshold. The charger continues to top off the
battery until timer EOC, when the LTM8062/LTM8062A
terminate the charge cycle and enters standby mode.
If the battery is removed from an LTM8062/LTM8062A
charger that is configured for C/10 termination, a low
amplitude sawtooth waveform appears at the charger
output, due to cycling between termination and recharge
events. This cycling results in pulsing at the CHRG output.
An LED connected to this pin will exhibit a blinking pat-
tern, indicating to the user that a battery is not present.
The frequency of this blinking pattern is dependent on the
output capacitance.
Termination at the end of the timer cycle only occurs if the
charge cycle was successful. A successful charge cycle
occurs when the battery is charged to within 2.5% of the
full-charge float voltage. If a charge cycle is not success-
ful at EOC, the timer cycle resets and charging continues
for another full timer cycle. When V drops 2.5% from
BAT
the full-charge float voltage, whether by battery loading
or replacement of the battery, the charger automatically
resets and starts charging.
C/10 Charge Termination
The LTM8062/LTM8062A support a low current-based
termination scheme, where a battery charge cycle termi-
nates when the charge current falls below one-tenth the
programmed charge current, or approximately 200mA.
ThisterminationmodeisengagedbyshortingtheTMRpin
to ground. When C/10 termination is used, an LTM8062/
LTM8062A charger sources battery charge current as
long as the average current level remains above the C/10
threshold. As the full-charge float voltage is achieved, the
charge current falls until the C/10 threshold is reached,
at which time the charger terminates and the LTM8062/
LTM8062A enter standby mode. The CHRG status pin fol-
lows the charger cycle and is high impedance when the
charger is not actively charging. There is no provision for
bad-battery detection if C/10 termination is used.
Preconditioning and Bad-Battery Fault
TheLTM8062/LTM8062Ahaveapreconditionmode,where
the charge current is limited to 15% of the maximum
charge current, or approximately 300mA. Precondition
mode is engaged if the voltage on the BAT pin is below the
precondition threshold, or approximately 70% of the float
voltage. Once the BAT voltage rises above the precondition
threshold,normalfull-currentchargingcancommence.The
LTM8062/LTM8062Aincorporate90mVhysteresistoavoid
spurious mode transitions.
Bad-battery detection is engaged when the internal timer
is used for termination (capacitor tied to TMR). This fault
detection feature is designed to identify failed cells. A
bad-battery fault is triggered when the voltage on BAT
remains below the precondition threshold for greater
than one-eighth of a full timer cycle (one-eighth EOC). A
bad-battery fault is also triggered if a normally charging
batteryre-enterspreconditionmodeafterone-eighthEOC.
Timer Charge Termination
The LTM8062/LTM8062A support a timer-based termina-
tionscheme, whereabatterychargecycleterminatesafter
a specific amount of time elapses. Timer termination is
engaged when a capacitor (C
) is connected from the
TIMER
8062fd
15
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LTM8062/LTM8062A
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Thermal Foldback
When a bad-battery fault is triggered, the charge cycle
is suspended, and the CHRG status pin becomes high
impedance. The FAULT pin is pulled low to signal that a
fault has been detected.
The LTM8062/LTM8062A contains a thermal fold-
back protection feature that reduces charge current
as the IC junction temperature approaches 125°C. In
most cases, on-chip temperatures servo such that
any overtemperature conditions are relieved with
only slight reductions in maximum charge current. In
some cases, the thermal foldback protection feature
can reduce charge currents below the C/10 threshold.
In applications that use C/10 termination (TMR = 0V),
the LTM8062/LTM8062A will suspend charging and en-
ter standby mode until the overtemperature condition is
relieved.
Cyclingthecharger’spowerorshutdownfunctioninitiates
a new charge cycle, but the LTM8062/LTM8062A chargers
do not require a manual reset. Once a bad-battery fault
is detected, a new timer charge cycle initiates if the BAT
pin exceeds the precondition threshold voltage. During
a bad-battery fault, a small current is sourced from the
charger; removing the failed battery allows the charger
output voltage to rise above the preconditioning threshold
voltage and initiate a charge cycle reset. A new charge
cycle is started by connecting another battery to the
charger output.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
LTM8062/LTM8062Aintegration.TheLTM8062/LTM8062A
isneverthelessaswitchingpowersupply,andcaremustbe
taken to minimize EMI and ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 7 for a suggested layout. Ensure that the grounding
and heat sinking are acceptable.
Battery Temperature Fault: NTC
The LTM8062/LTM8062A can accommodate battery tem-
perature monitoring by using an NTC (negative tempera-
ture coefficient) thermistor close to the battery pack. The
temperaturemonitoringfunctionisenabledbyconnecting
a 10kΩ, β ≈ 3380 NTC thermistor from the NTC pin to
ground. If the NTC function is not desired, leave the pin
open.TheNTCpinsources50μA,andmonitorsthevoltage
dropped across the 10kΩ thermistor. When the voltage
on this pin is above 1.36V (0°C) or below 0.29V (40°C),
the battery temperature is out of range, and the LTM8062/
LTM8062A trigger an NTC fault. The NTC fault condition
remains until the voltage on the NTC pin corresponds to
a temperature within the 0°C to 40°C range. Both hot and
coldthresholdsincorporate20%hysteresis,whichequates
to about 5°C. If higher operational charging temperatures
are desired, the temperature range can be expanded by
adding series resistance to the 10k NTC resistor. Adding
a 909Ω resistor will increase the effective temperature
threshold to 45°C, for example.
ADJ
BAT
GND
(OPTIONAL)
V
RUN
INREG
C
BAT
V
INA
C
GND
IN
During an NTC fault, charging is halted and both status
pins are pulled low. If timer termination is enabled, the
timer count is suspended and held until the fault condi-
tion is cleared.
V
IN
8062 F07
THERMAL VIAS
Figure 7. Suggested Layout and Via Placement
8062fd
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LTM8062/LTM8062A
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1. Place the C capacitor as close as possible to the V
installing a small resistor in series with V , but the most
IN
IN
IN
and GND connection of the LTM8062/LTM8062A.
popular method of controlling input voltage overshoot is
to add an electrolytic bulk capacitor to the V net. This
IN
2. If used, place the C capacitor as close as possible to
BAT
capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter-
ing and can slightly improve the efficiency of the circuit,
though it is physically large.
theBATandGNDconnectionoftheLTM8062/LTM8062A.
3. PlacetheC andC (ifused)capacitorssuchthattheir
IN
BAT
ground current flows directly adjacent or underneath
the LTM8062/LTM8062A.
4. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8062/LTM8062A.
Parallel Operation
If more current is desired, multiple LTM8062/LTM8062As
may be paralleled, as shown in the Typical Applications
section. When doing so, bear in mind the following:
5. For good heat sinking, use vias to connect the GND
copper area to the board’s internal ground planes.
Liberally distribute these GND vias to provide both a
goodgroundconnectionandthermalpathtotheinternal
planes of the printed circuit board. Pay attention to the
location and density of the thermal vias in Figure 5. The
LTM8062/LTM8062A can benefit from the heat-sinking
afforded by vias that connect to internal GND planes at
these locations, due to their proximity to internal power
handlingcomponents.Theoptimumnumberofthermal
vias depends upon the printed circuit board design.
For example, a board might use very small via holes.
It should employ more thermal vias than a board that
uses larger holes.
1. Each LTM8062/LTM8062A ADJ pin requires 250k input
resistanceasdescribedintheADJpinfunctiondescrip-
tion. Table 1 gives the recommended resistor network
for a single LTM8062/LTM8062A. If using more than
one, either apply one network of the appropriate value
to each LTM8062/LTM8062A’s ADJpin orapply a single
network, each resistor value divided by the number of
paralleled LTM8062/LTM8062As and connect all of the
ADJ pins together.
2. Tie the BAT outputs directly together. Apply the same
output capacitance to each LTM8062/LTM8062A as if
it were used as a single device and not paralleled.
3. The individual LTM8062/LTM8062As may not share
current equally as the battery nears the float voltage.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8062/LTM8062A. However, these
capacitorscancauseproblemsiftheLTM8062/LTM8062A
are plugged into a live input supply (see Application Note
88 for a complete discussion). The low loss ceramic
capacitor combined with stray inductance in series with
the power source forms an underdamped tank circuit,
Thermal Considerations
The thermal performance of the LTM8062/LTM8062A is
given in the Typical Performance Characteristics section.
These curves were generated by the LTM8062/LTM8062A
2
mounted to a 58cm 4-layer FR4 printed circuit board.
Boards of other sizes and layer count can exhibit differ-
ent thermal behavior, so it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental operating conditions.
and the voltage at the V pin of the LTM8062/LTM8062A
IN
can ring to more than twice the nominal input voltage,
possibly exceeding the LTM8062/LTM8062A’s rating and
damage the part. If the input supply is poorly controlled
or the user will be plugging the LTM8062/LTM8062A into
anenergizedsupply,theinputnetworkshouldbedesigned
to prevent this overshoot. This can be accomplished by
Forincreasedaccuracyandfidelitytotheactualapplication,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
8062fd
17
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
applicaTions inForMaTion
1. θ : Thermal resistance from junction to ambient.
3. θ
is determined with nearly all of the component
JA
JCtop
power dissipation flowing through the top of the pack-
age.AstheelectricalconnectionsofthetypicalµModule
device are on the bottom of the package, it is rare for an
application to operate such that most of the heat flows
from the junction to the top of the part. As in the case
2. θ
: Thermal resistance from junction to the bot-
JCbottom
tom of the product case.
3. θ : Thermal resistance from junction to top of the
JCtop
product case.
of θ
, this value may be useful for comparing
JCbottom
4. θ : Thermal resistance from junction to the printed
JB
packages but the test conditions don’t generally match
the user’s application.
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
4. θ is the junction-to-board thermal resistance where
JB
almost all of the heat flows through the bottom of the
µModule device and into the board, and is really the
sum of the θ
and the thermal resistance of the
JCbottom
1. θ is the natural convection junction-to-ambient air
JA
bottomofthepartthroughthesolderjointsandthrough
a portion of the board. The board temperature is mea-
sured a specified distance from the package, using a
two sided, two layer board. This board is described in
JESD 51-9.
thermal resistance measured in a one cubic foot sealed
enclosure.Thisenvironmentissometimesreferredtoas
“still air” although natural convection causes the air to
move.Thisvalueisdeterminedwiththepartmountedto
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
The most appropriate way to use the coefficients is when
running a detailed thermal analysis, such as FEA, which
considers all of the thermal resistances simultaneously.
None of them can be individually used to accurately pre-
dict the thermal performance of the product, so it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
given in the Typical Performance Characteristics.
2. θ
is the junction-to-board thermal resistance
JCbottom
with all of the component power dissipation flowing
through the bottom of the package. In the typical
µModule device, the bulk of the heat flows out the bot-
tom of the package, but there is always heat flow out
into the ambient environment. As a result, this thermal
resistancevaluemaybeusefulforcomparingpackages
but the test conditions don’t generally match the user’s
application.
A graphical representation of these thermal resistances
is given in Figure 8.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
80421 F08
µMODULE DEVICE
Figure 8. Thermal Resistances Among µModule Device Printed Circuit Board and Ambient Environment
8062fd
18
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
applicaTions inForMaTion
The blue resistances are contained within the µModule
device, and the green are outside.
flowoutoftheLTM8062/LTM8062Aisthroughthebottom
of the module and the LGA pads into the printed circuit
board. Consequently a poor printed circuit board design
can cause excessive heating, resulting in impaired perfor-
mance or reliability. Please refer to the PCB Layout section
for printed circuit board design suggestions.
The die temperature of the LTM8062/LTM8062A must be
lower than the maximum rating of 125°C, so care should
be taken in the layout of the circuit to ensure good heat
sinking of the LTM8062/LTM8062A. The bulk of the heat
Typical applicaTions
Basic 2A, 2-Cell LiFePO4 Battery Charger with C/10 Termination
LTM8062
V
DC
IN
V
V
V
BAT
BIAS
INA
9.5V TO 32V
(OPTIONAL
IN
+
ELECTROLYTIC
2-CELL
CHRG
FAULT
ADJ
INREG
CAPACITOR)
549k
459k
LiFePO
4
RUN
TMR
NTC
(2× 3.6V)
BATTERY
4.7µF
GND
8062 TA02
Basic 2A, 4-Cell Li-Ion Battery Charger with C/10 Termination
LTM8062A
V
DC
IN
V
V
V
BAT
INA
22V TO 32V
IN
4-CELL
Li-Ion
(4 × 4.1V)
BATTERY
PACK
(OPTIONAL
ELECTROLYTIC
CAPACITOR)
+
4.7µF
CHRG
FAULT
ADJ
INREG
1.24M
312k
RUN
TMR
NTC
BIAS
GND
8062 TA06
EXTERNAL 3.3V
8062fd
19
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
Typical applicaTions
2A Solar Panel Power Manager with 8.4V Lithium Ion Battery Pack and 16V Peak Power Tracking
V
IN
LTM8062
SOLAR
V
V
V
BAT
BIAS
INA
POWER UNIT
IN
CHRG
FAULT
ADJ
INREG
2-CELL
499k
642k
412k
Li-ION
RUN
TMR
NTC
+
(OPTIONAL
ELECTROLYTIC
CAPACITOR)
(2× 4.2V)
BATTERY
NTC
10k
B = 3380
4.7µF
GND
8062 TA03
Three LTM8062s Operating In Parallel to Produce Higher Charge Current
BAT
7.2V, 6A
+
C2
22µF
GND
12V TO 32V
V
INA
V
INA
V
INA
V
V
BAT
V
V
BAT
V
V
BAT
IN
IN
IN
R1
549k
0.1%
R2
549k
0.1%
R3
549k
0.1%
+
+
LTM8062EV
LTM8062EV
LTM8062EV
C1
22µF
C3
22µF
BIAS
ADJ
BIAS
ADJ
BIAS
ADJ
GND
INREG
INREG
INREG
RUN
NTC
RUN
NTC
RUN
NTC
R4
459k
0.1%
R5
459k
0.1%
R6
459k
0.1%
CHRG
FAULT
CHRG
FAULT
CHRG
FAULT
8062 TA05
TMR GND
TMR GND
TMR GND
C5
10µF
35V
C6
10µF
35V
C4
10µF
35V
C4, C5, C6; MURATA, GRM32ER7YA106KA12L
C1, C2, C3; POS-CAP 16TQC22M
8062fd
20
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Z
/ / b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 0 0 0
1 . 2 7 0
2 . 5 4 0
3 . 8 1 0
1 . 5 8 7 5
0 . 9 5 2 5
3 . 4 9 2 5
4 . 1 2 7 5
8062fd
21
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
package DescripTion
Table 3. Pin Assignment Table
(Arranged by Pin Number)
PIN
A1
A2
A3
A4
A5
A6
A7
NAME
GND
GND
GND
GND
GND
BAT
PIN
B1
B2
B3
B4
B5
B6
B7
NAME
GND
GND
GND
GND
GND
BAT
PIN
C1
C2
C3
C4
C5
C6
C7
NAME
GND
GND
GND
GND
GND
BAT
PIN
D1
D2
D3
D4
D5
D6
D7
NAME
GND
GND
GND
GND
GND
BAT
PIN
E1
E2
E3
E4
E5
E6
E7
NAME
GND
GND
GND
GND
GND
BAT
PIN
F1
F2
F3
F4
F5
F6
F7
NAME
GND
GND
GND
GND
GND
BAT
BAT
BAT
BAT
BAT
BAT
BAT
PIN
G1
G2
G3
G4
G5
G6
G7
NAME
GND
GND
GND
GND
GND
GND
BIAS
PIN
H1
H2
H3
H4
H5
H6
H7
NAME
GND
GND
GND
GND
GND
NTC
PIN
J1
J2
J3
J4
J5
J6
J7
NAME
GND
GND
GND
GND
GND
TMR
FAULT
PIN
K1
K2
K3
K4
K5
K6
K7
NAME
PIN
L1
L2
L3
L4
L5
L6
L7
NAME
V
IN
V
IN
V
IN
V
V
V
IN
IN
IN
V
INA
V
INA
V
V
INA
INA
RUN
V
INREG
ADJ
CHRG
GND
package phoTos
8062fd
22
For more information www.linear.com/LTM8062
LTM8062/LTM8062A
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
3/11
Updated Electrical Characteristics section
3
Updated V
(Pin L6) description
7
INREG
Updated Block Diagram
8
8
Updated Operation section
Updated Figures 2, 7
9, 15
Updated Applications Information
Updated/Added Typical Applications
Added LTM8062A parts. Reflected throughout the data sheet
10, 11, 12, 13
18, 22
1-24
B
C
8/11
12/11 Added graph G27
Updated Typical Applications
Correct R and R equations
6
19
13
D
7/13
W
SET
8062fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
re
tion that the interconne tion its cir its a scrib ll no nfrin n existing patent rights.
23
c of cu s de ed he in wi t i ge o
LTM8062/LTM8062A
Typical applicaTion
2A Solar Panel Power Manager for Charging 2-Cell 8.4V Lithium-Ion Battery, Featuring Three Hour
Charge Time and 16V Peak Power Tracking. Battery Powers Two µModule Regulators
V
IN
LTM8062
V
V
SOLAR
V
V
V
BAT
BIAS
LTM8023
LTM8021
OUT
OUT
INA
POWER UNIT
IN
CHRG
FAULT
ADJ
INREG
499k
642k
412k
2-CELL
Li-Ion
(2× 4.2V)
BATTERY
RUN
TMR
NTC
NTC
4.7µF
10k
B = 3380
0.68µF
GND
8062 TA04
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTM4601/
LTM4601A
12A DC/DC µModule Regulator with PLL, Output
Tracking/Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4601-1 Version has no Remote
Sensing
LTM4618
LTM4604A
LTM4608A
LTM8020
6A DC/DC µModule Regulator
4.5V ≤ V ≤ 26.5V, 0.8V ≤ V
≤ 5V, 9mm × 15mm × 4.32mm LGA
≤ 5V, 9mm × 15mm × 2.3mm LGA
OUT
IN
OUT
4A Low V DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
IN
IN
8A Low V DC/DC µModule Regulator
2.7V ≤ V ≤ 5.5V, 0.6V ≤ V
≤ 5V, 9mm × 15mm × 2.8mm LGA
IN
IN
OUT
200mA, 36V DC/DC µModule Regulator
1A, 36V DC/DC µModule Regulator
2A, 36V DC/DC µModule Regulator
EN55022 Class B Compliant, Fixed 450kHz Frequency, 1.25V ≤ V
6.25mm × 6.25mm × 2.32mm LGA
≤ 5V,
OUT
LTM8022
LTM8023
Adjustable Frequency, 0.8V ≤ V
Pin Compatible to the LTM8023
≤ 10V, 9mm × 11.25mm × 2.82mm LGA,
OUT
Adjustable Frequency, 0.8V ≤ V
Pin Compatible to the LTM8022
≤ 10V, 9mm × 11.25mm × 2.82mm LGA,
OUT
LTM8025
LTM8021
3A, 36V DC/DC µModule Regulator
0.8V ≤ V ≤ 24V, 9mm × 15mm × 4.32mm LGA
OUT
500mA, 36V DC/DC µModule Regulator
EN55022 Class B Compliant, Fixed 1.1MHz Frequency, 0.8V ≤ V
6.25mm × 11.25mm × 2.82mm LGA
≤ 5V,
OUT
LTM8042/
LTM8042-1
1A/350mA µModule LED Driver
3V ≤ V ≤ 30V, V
Up to 28V, Buck, Boost or Buck-Boost Operation
LED
IN
9mm × 15mm × 2.82mm LGA
8062fd
LT 0713 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM8062
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LINEAR TECHNOLOGY CORPORATION 2010
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