LTP5902IPC-IPRB1C1#PBF

LTP5901-IPR/LTP5902-IPR

SmartMesh IP Network Manager

2.4GHz 802.15.4e

Wireless Embedded Manager

DescripTion

neTwork FeaTures

n

SmartMesh IP™ wireless sensor networks are self man-

aging, low power internet protocol (IP) networks built

from wireless nodes called motes. The LTP™5901-IPR/

LTP5902-IPR is the IP manager product in the Eterna^®*

family of IEEE 802.15.4e printed circuit board assembly

solutions, featuring a highly integrated, low power radio

design by Dust Networks^®as well as an ARM Cortex-M3

32-bit microprocessor running Dust’s embedded Smart-

Mesh IP networking software.

Complete Radio Transceiver, Embedded Processor,

and Networking Software for Forming a Self-Healing

Mesh Network

SmartMesh^®Networks Incorporate:

n

Time Synchronized Network-Wide Scheduling

n

Per Transmission Frequency Hopping

Redundant Spatially Diverse Topologies

Network-Wide Reliability and Power Optimization

NIST Certified Security

n

SmartMesh Networks Deliver:

Based on the IETF 6LoWPAN and IEEE-802.15.4e stan-

dards, the LTP5901/2-IPR runs SmartMesh IP network

management software to monitor and manage network

performance and provide a data ingress/egress point via

a UART interface. The SmartMesh IP software provided

with the LTP5901/2-IPR is fully tested and validated, and

is readily configured via a software application program-

minginterface.WithDust’stime-synchronizedSmartMesh

IP networks, all motes in the network may route, source

or terminate data, while providing many years of battery

powered operation.

n

>99.999% Network Reliability Achieved in the

Most Challenging RF Environments

Sub 50µA Routing Nodes

n

Compliant to 6LoWPAN Internet Protocol (IP) and

IEEE 802.15.4e Standards

lTp5901/2-ipr FeaTures

n

Manages Networks of Up to 100 Nodes

n

Sub 1mA Average Current Consumption Enables

Battery Powered Network Management

SmartMesh IP motes deliver a highly flexible network

with proven reliability and low power performance in an

easy-to-integrate platform.

L, LT, LTC, LTM, Linear Technology, Dust, Dust Networks, Eterna, SmartMesh and the

Linear logo are registered trademarks and LTP, SmartMesh IP and the Dust Networks logo are

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,

7881239, 7898322, 8222965.

n

RF Modular Certification Include USA, Canada, EU,

Japan, Taiwan, Korea, India, Australia and New

Zealand

n

PCB Assembly with Chip Antenna (LTP5901-IPR) or

with MMCX Antenna Connector (LTP5902-IPR)

* Eterna is Dust Networks’ low power radio SoC architecture.

Typical applicaTion

EXPANDED VIEW

LTP5901-IPR

LTP5901/2-IPM

ANTENNA

+

UART

IN

LTC^®2379-18 SPI

UART

SENSOR

µCONTROLLER

–

IN

HOST

APPLICATION

59012IPR TA01

MOTE

59012iprfa

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LTP5901-IPR/LTP5902-IPR

Table oF conTenTs

Network Features .......................................... 1

LTP5901/2-IPR Features.................................. 1

Typical Application ........................................ 1

Description.................................................. 1

SmartMesh Network Overview........................... 3

Absolute Maximum Ratings.............................. 4

Pin Configuration .......................................... 4

Order Information.......................................... 5

Recommended Operating Conditions................... 5

DC Characteristics......................................... 5

Radio Specifications ...................................... 6

Radio Receiver Characteristics.......................... 6

Radio Transmitter Characteristics....................... 7

Digital I/O Characteristics ................................ 7

Temperature Sensor Characteristics.................... 7

System Characteristics ................................... 8

UART AC Characteristics.................................. 8

Time AC Characteristics .................................. 9

Radio_INHIBIT AC Characteristics .....................10

Flash AC Characteristics.................................10

Flash SPI Slave AC Characteristics ....................10

External Bus AC Characteristics ........................11

Typical Performance Characteristics ..................14

Pin Functions..............................................19

Operation...................................................22

Power Supply..........................................................23

Supply Monitoring and Reset .................................23

Precision Timing.....................................................23

Application Time Synchronization ..........................23

Time References.....................................................23

Radio ......................................................................24

UARTs.....................................................................24

API UART Protocol .................................................24

CLI UART................................................................25

Autonomous MAC...................................................25

Security ..................................................................25

Temperature Sensor ...............................................25

Radio Inhibit ...........................................................25

Software Installation...............................................26

Flash Data Retention...............................................26

Networking .............................................................26

Applications Information ................................29

Regulatory and Standards Compliance...................29

Soldering Information.............................................29

Related Documentation..................................30

Package Description .....................................31

Revision History ..........................................33

Typical Application .......................................34

Related Parts..............................................34

59012iprfa

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LTP5901-IPR/LTP5902-IPR

smarTmesh neTwork overview

ASmartMeshnetworkconsistsofaself-formingmulti-hop,

mesh of nodes, known as motes, which collect and relay

data, and a network manager that monitors and manages

network performance and security, and exchanges data

with a host application.

to the network manager in packets called health reports.

The network manager uses health reports to continually

optimizethenetworktomaintain>99.999%datareliability

even in the most challenging RF environments.

The use of TSCH allows SmartMesh devices to sleep in-

between scheduled communications and draw very little

power in this state. Motes are only active in timeslots

where they are scheduled to transmit or receive, typically

resulting in a duty cycle of < 1%. The optimization soft-

ware in the network manager coordinates this schedule

automatically. When combined with the Eterna low power

radio, every mote in a SmartMesh network—even busy

routing ones—can run on batteries for years. By default,

all motes in a network are capable of routing traffic from

other motes, which simplifies installation by avoiding the

complexity of having distinct routers vs non-routing end

nodes. Motesmaybeconfiguredasnon-routingtofurther

reduce that particular mote’s power consumption and to

support a wide variety of network topologies.

SmartMesh networks communicate using a time slotted

channel hopping (TSCH) link layer, pioneered by Dust

Networks. In a TSCH network, all motes in the network

are synchronized to within less than a millisecond. Time

in the network is organized into timeslots, which enables

collision-free packet exchange and per-transmission

channel-hopping. In a SmartMesh network, every device

has one or more parents (e.g. mote 3 has motes 1 and

2 as parents) that provide redundant paths to overcome

communicationsinterruptionduetointerference,physical

obstruction or multi-path fading. If a packet transmission

fails on one path, the next retransmission may try on a

different path and different RF channel.

A network begins to form when the network manager

instructsitsonboardaccesspoint(AP)radiotobeginsend-

ingadvertisements—packetsthatcontaininformationthat

enablesadevice tosynchronize tothenetworkandrequest

tojoin. Thismessageexchangeispartofthesecurityhand-

shakethatestablishesencryptedcommunicationsbetween

the manager or application, and mote. Once motes have

joined the network, they maintain synchronization through

time corrections when a packet is acknowledged.

ALL NODES ARE ROUTERS.

THEY CAN TRANSMIT AND RECEIVE.

THIS NEW NODE CAN JOIN

ANYWHERE BECAUSE ALL

NODES CAN ROUTE.

HOST

APPLICATION

59012IPR SNO02

At the heart of SmartMesh motes and network managers

is the Eterna IEEE 802.15.4e System-on-Chip (SoC), fea-

turing Dust Networks’ highly integrated, low power radio

design, plus an ARM Cortex-M3 32-bit microprocessor

runningSmartMeshnetworkingsoftware.TheSmartMesh

networking software comes fully compiled yet is configu-

rable via a rich set of application programming interfaces

(APIs) which allows a host application to interact with

the network, e.g. to transfer information to a device, to

configure data publishing rates on one or more motes,

or to monitor network state or performance metrics. Data

publishing can be uniform or different for each device,

with motes being able to publish infrequently or faster

NETWORK MANAGER

AP

Mote

1

Mote

2

Mote

3

59012IPR SNO01

An ongoing discovery process ensures that the network

continually discovers new paths as the RF conditions

change. In addition, each mote in the network tracks per-

formance statistics (e.g. quality of used paths, and lists of

potential paths) and periodically sends that information

than once per second as needed.

59012iprfa

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LTP5901-IPR/LTP5902-IPR

absoluTe maximum raTings

(Notes 1, 2)

Operating Temperature Range

Supply Voltage on VSUPPLY..................................4.20V

Input Voltage on AI_0/1/2/3 Inputs........................1.98V

Voltage on Any Digital I/O Pin .... –0.3V to VSUPPLY + 0.3V

Input RF Level......................................................10dBm

Storage Temperature Range (Note 3)..... –55°C to 105°C

LTP5901I/LPT5902I.............................–40°C to 85°C

CAUTION: This part is sensitive to electrostatic discharge

(ESD). It is very important that proper ESD precautions

be observed when handling the LTP5901/LTP5902-IPR.

pin conFiguraTion

Pin functions shown in italics are currently not supported in software.

1

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

GND

RESERVED

NC

GND

2

NC

3

RADIO_INHIBIT

TIMEn

4

5

6

7

8

9

RESERVED

GND

UART_TX

UART_TX_CTSn

UART_TX_RTSn

UART_RX

UART_RX_CTSn

UART_RX_RTSn

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

RESERVED

NC

VSUPPLY

RESERVED

NC

RESETn

TDI

NC

FLASH_P_ENn / EB_IO_LE1

EB_IO_OEn

EB_IO_WEn

RESERVED / UARTC1_RX

RESERVED / UARTC1_TX

EB_IO_CS0n

EB_DATA_5

EB_DATA_2

EB_DATA_3

GND

TDO

TMS

TCK

GND

RESERVED

EB_DATA_7

EB_DATA_6

EB_DATA_4

EB_DATA_0

NC

EB_ADDR_0

EB_ADDR_1

IPCS_SSn

EB_IO_LE2

GND

31 32 33

34 35 36

PC PACKAGE

66-LEAD PCB

59012iprfa

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LTP5901-IPR/LTP5902-IPR

orDer inFormaTion

LEAD FREE FINISH†

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTP5901IPC-IPMA#PBF

LTP5902IPC-IPMA#PBF

LTP5901IPC-IPMA#PBF

LTP5902IPC-IPMA#PBF

66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna

–40°C to 85°C

66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX

Connector

†This product ships with the flash erased at the time of order. OEMs will need to program devices during development and manufacturing.

For legacy part numbers and ordering information go to: www.linear.com/ltp5901-ipr#orderinfo or www.linear.com/ltp5902-ipr#orderinfo

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

*The temperature grade is identified by a label on the shipping container.

recommenDeD operaTing conDiTions

The l denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER

VSUPPLY Supply Voltage

Supply Noise

CONDITIONS

MIN

TYP

MAX

3.76

250

90

UNITS

V

l

Including Noise and Load Regulation

50Hz to 2MHz

2.1

mV

Operating Relative Humidity

Non-Condensing

10

–8

% RH

l

Temperature Ramp Rate While Operating in

Network

8

°C/min

Dc characTerisTics

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

OPERATION/STATE

CONDITIONS

MIN

TYP

MAX

UNITS

Power-On Reset

During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time from 1V to

1.9V

12

mA

Doze

RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and

State Retained, 32.768kHz Reference Active

1.2

0.8

20

µA

Deep Sleep

RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and

State Retained, 32.768kHz Reference Inactive

In-Circuit Programming

RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz

mA

Peak Operating Current

8dBm

0dBm

System Operating at 14.7MHz, Radio Transmitting, During Flash Write.

Maximum Duration 4.33 ms.

30

26

mA

Active

ARM Cortex-M3, RAM and Flash Operating, Radio and All Other Peripherals

Off. Clock Frequency of CPU and Peripherals Set to 7.3728MHz, VCORE =

1.2V

1.3

mA

Flash Write

Flash Erase

Single Bank Flash Write

3.7

2.5

mA

Single Bank Page or Mass Erase

Radio Tx

0dBm

8dBm

Current with Autonomous MAC Managing Radio Operation, CPU Inactive.

Clock Frequency of CPU and Peripherals Set to 7.3728MHz.

5.4

9.7

mA

Radio Rx

Current with Autonomous MAC Managing Radio Operation, CPU Inactive.

Clock Frequency of CPU and Peripherals Set to 7.3728MHz.

4.5

mA

59012iprfa

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LTP5901-IPR/LTP5902-IPR

raDio speciFicaTions ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Frequency Band

2.4000

2.4835

GHz

Number of Channels

Channel Separation

Channel Center Frequency

Raw Data Rate

15

5

2405 + 5 • (k-11)

250

MHz

kbps

V

Where k = 11 to 25, as Defined by IEEE.802.15.4

Antenna Pin ESD Protection HBM Per JEDEC JESD22-A114F (Note 2)

Range 25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m Above

Ground

6000

Indoor

100

300

1200

m

Outdoor

Free Space

raDio receiver characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

–93

–95

0

MAX

UNITS

dBm

Receiver Sensitivity

Saturation

Packet Error Rate (PER) = 1% (Note 5)

PER = 50%

Maximum Input Level the Receiver Will

Properly Receive Packets

Adjacent Channel Rejection Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

(High Side) Above the Desired Signal, PER = 1% (Note 5)

22

19

40

36

42

–6

dBc

Adjacent Channel Rejection Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

(Low Side) Below the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

(High Side) Above the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

(Low Side)

Below the Desired Signal, PER = 1% (Note 5)

Second Alternate Channel

Rejection

Desired Signal at –82dBm, Second Alternate Modulated Channel

Either 15MHz Above or Below, PER = 1% (Note 5)

Co-Channel Rejection

Desired Signal at –82dBm, Undesired Signal is an 802.15.4

Modulated Signal at the Same Frequency, PER = 1%

LO Feed Through

–55

50

dBm

ppm

Frequency Error Tolerance

(Note 6)

Symbol Error Tolerance

50

ppm

dBm

Received Signal Strength

Indicator (RSSI) Input

Range

–90 to -10

RSSI Accuracy

6

1

dB

RSSI Resolution

59012iprfa

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LTP5901-IPR/LTP5902-IPR

raDio TransmiTTer characTerisTics The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Power

High Calibrated Setting

Low Calibrated Setting

Delivered to a 50Ω Load

8

0

dBm

Spurious Emissions

Conducted Measurement with a 50Ω Single-Ended

Load, 8dBm Output Power. All Measurements Made

with Max Hold.

30MHz to 1000MHz

R

BW

R

BW

R

BW

R

BW

R

BW

= 120kHz, V = 100Hz

< –70

–45

dBm

dBc

BW

1GHz to 12.75GHz

= 1MHz, V = 3MHz

BW

2.4GHz ISM Upper Band Edge (Peak)

2.4GHz ISM Upper Band Edge (Average)

2.4GHz ISM Lower Band Edge

= 1MHz, V = 3MHz

–37

BW

= 1MHz, V = 10Hz

–49

–45

BW

= 100kHz, V = 100kHz

BW

Harmonic Emissions

2nd Harmonic

Conducted Measurement Delivered to a 50Ω Load,

Resolution Bandwidth = 1MHz, Video Bandwidth =

1MHz.

–50

–45

dBm

3rd Harmonic

DigiTal i/o characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

UNITS

l

V

Low Level Input Voltage

High Level Input Voltage

–0.3

0.6

V

IL

(Note 8)

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

IH

l

V

Low Level Output Voltage

High Level Output Voltage

Type 1, I

= 1.2mA

0.4

V

OL

OL(MAX)

OH(MAX)

= –0.8mA

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

OH

l

V

Low Level Output Voltage

High Level Output Voltage

Type 2, Low Drive, I

= 2.2mA

0.4

V

OL

OL(MAX)

OH(MAX)

= –1.6mA

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

OH

l

V

Low Level Output Voltage

High Level Output Voltage

Type 2, High Drive, I

= 4.5mA

0.4

V

OL

OL(MAX)

OH(MAX)

= –3.2mA

VSUPPLY

– 0.3

VSUPPLY

+ 0.3

OH

Input Leakage Current

Input Driven to VSUPPLY or GND

50

nA

Pull-Up/Pull-Down Resistance

kΩ

TemperaTure sensor characTerisTics ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

Offset

CONDITIONS

MIN

TYP

MAX

UNITS

°C

Temperature Offset Error at 25°C

0.25

0.033

Slope Error

°C/°C

59012iprfa

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LTP5901-IPR/LTP5902-IPR

sysTem characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER

Doze to Active State Transmit

CONDITIONS (Note 7)

MIN

TYP

5

MAX

UNITS

µs

Doze to Radio Tx or Rx

1.2

4

ms

Q

Charge to Sample RF Channel RSSI

Charge Consumed Starting from Doze State

and Completing an RSSI Measurement

µC

CCA

l

Largest Atomic Charge Operation

RESETn Pulse Width

Flash Erase, 21ms Max Duration

200

µC

µs

µF

µH

MAX

125

Total Capacitance

Note 12

6

3

Total Inductance

Number of Nodes in Network (Note 12)

Without external SRAM

With external SRAM

32

100

Motes

l

Network Upstream Throughput (Note 12)

Without external SRAM

With external SRAM

24

36

Pkts/s

uarT ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

UNITS

l

Permitted Rx Baud Rate Error

Both Application Programming Interface

(API) and Command Line Interface (CLI)

UARTs

–2

2

%

l

Generated Tx Baud Rate Error

Both API and CLI UARTs

–1

0

1

2

%

t

Assertion of UART_RX_RTSn to Assertion of

UART_RX_CTSn, or Negation of UART_RX_

RTSn to Negation of UART_RX_CTSn

ms

RX_RTS to RX_CTS

l

t

Assertion of UART_RX_CTSn to Start of Byte

0

20

22

ms

RX_CTS to RX

End of Packet (End of the Last Stop Bit) to

Negation of UART_RX_RTSn

EOP to RX_RTS

l

t

Assertion of UART_TX_RTSn to Assertion of

UART_TX_CTSn

0

2

0

22

ms

BEG_TX_RTS to TX_CTS

END_TX_CTS to TX_RTS

TX_CTS to TX

Negation of UART_TX_CTSn to Negation of

UART_TX_RTSn

Bit

Period

l

Assertion of UART_TX_CTSn to Start of Byte

2

1

Bit

Period

End of Packet (End of the Last Stop Bit) to

Negation of UART_TX_RTSn

Bit

Period

EOP to TX_RTS

l

t

Receive Inter-Byte Delay

Receive Inter-Packet Delay

Transmit Inter-Packet Delay

100

ms

RX_INTERBYTE

20

1

RX_INTERPACKET

TX_INTERPACKET

Bit

Period

l

t

Start of Byte to Negation of UART_TX_CTSn

0

µs

TX to TX_CTS

59012iprfa

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LTP5901-IPR/LTP5902-IPR

uarT ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

t

EOP TO RX_RTS

t

RX_INTERPACKET

UART_RX_RTSn

UART_RX_CTSn

UART_RX

t

RX_RTS TO RX_CTS

t

RX_RTS TO RX_CTS

t

RX_CTS TO RX

t

RX_INTERBYTE

BYTE 0

BYTE 1

t

EOP TO TX_RTS

t

TX_INTERPACKET

UART_TX_RTSn

t

END_TX_CTS TO TX_RTS

TX_RTS TO TX_CTS

t

END_TX_RTS TO TX_CTS

t

TX TO TX_CTS

UART_TX_CTSn

UART_TX

t

TX_CTS TO TX

BYTE 0

BYTE 1

59012IPR F01

Figure 1. API UART Timing

Time ac characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

125

0

TYP

MAX

UNITS

µs

l

t

TIMEn Signal Strobe Width

STROBE

Delay from Rising Edge of TIMEn to the Start of

Time Packet on API UART

100

ms

RESPONSE

l

t

Delay from End of Time Packet on API UART to

Falling Edge of Subsequent TIMEn

0

ns

TIME_HOLD

l

Timestamp Resolution (Note 9)

1

5

µs

Network-Wide Time Accuracy (Note 10)

t

STROBE

t

TIME_HOLD

TIMEn

t

RESPONSE

UART_TX

TIME INDICATION PAYLOAD

59012IPR F02

Figure 2. Timestamp Timing

59012iprfa

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LTP5901-IPR/LTP5902-IPR

raDio_inhibiT ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

UNITS

l

t

Delay from Rising Edge of RADIO_

INHIBIT to Radio Disabled

20

ms

RADIO_OFF

t

Maximum RADIO_INHIBIT Strobe Width

2

s

RADIO_INHIBIT_STROBE

t

RADIO_INHIBIT_STROBE

RADIO_INHIBIT

t

RADIO_OFF

RADIO STATE

ACTIVE/OFF

OFF

ACTIVE/OFF

59012IPR F03

Figure 3. RADIO_INHIBIT Timing

Flash ac characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

21

UNITS

ms

l

t

Time to Write a 32-Bit Word (Note 11)

Time to Erase a 2k Byte Page (Note 11)

Time to Erase 256k Byte Flash Bank (Note 11)

Data Retention

WRITE

21

ms

PAGE_ERASE

MASS_ERASE

21

ms

25°C

85°C

105°C

100

20

8

Years

Flash spi slave ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

TYP

MAX

UNITS

l

t

Setup from Assertion of FLASH_P_ENn to

Assertion of RESETn

0

ns

FP_EN_to_RESET

Delay from the Assertion RESETn to the First

Falling Edge of IPCS_SSn

125

10

µs

FP_ENTER

Delay from the Completion of the Last Flash SPI

Slave Transaction to the Negation of RESETn

and FLASH_P_ENn

FP_EXIT

l

t

IPCS_SSn Setup to the Leading Edge of

IPCS_SCK

15

ns

SSS

l

t

IPCS_SSn Hold from Trailing Edge of IPCS_SCK

IPCS_SCK Period

15

300

15

5

ns

SSH

CK

IPCS_MOSI Data Setup

DIS

DIH

DOV

OFF

IPCS_MOSI Data Hold

IPCS_MISO Data Valid

3

IPCS_MISO Data Three-State

0

30

59012iprfa

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Flash spi slave ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

t

FP_EN_TO_RESET

FLASH_P_ENn

RESETn

t

FP_EXIT

FP_ENTER

t

SSH

SSS

IPCS_SSn

IPCS_SCK

t

CK

t

DIS

t

DIH

IPCS_MOSI

59012IPR F04

Figure 4. Flash Programming Interface Timing

exTernal bus ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

EB_IO_LE0, EB_IO_LE1, EB_IO_LE2 Pulse

Width

100

ns

LEPW

t

EB_DATA_[7:0] Address Hold from the

Rising Edge of EB_IO_LE0, EB_IO_LE1, and

EB_IO_LE2

EB_DATA_[7:0] During Address

Phase

90

ns

AH

l

t

EB_ADDR_[1:0] Address Valid Until

EB_DATA_[7:0] Data Latched

AV_to_DL

l

t

EB_CS0n Asserted Until EB_OEn Asserted

EB_CS0n Asserted

150

100

50

ns

CSn_to_OEn

CSn

EB_ADDR_[1:0], EB_IO_WEn Setup to

EB_CSn Asserted

SU_to_CSn

l

t

EB_ADDR_[1:0], EB_IO_WEn Hold from

EB_CSn Negated

50

ns

H_from_CSn

59012iprfa

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exTernal bus ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

t

LEPW

EB_IO_LE0

EB_IO_LE1

t

LEPW

t

LEPW

EB_IO_LE2

EB_DATA_[7:0]

EB_ADDR_[1:0]

t

AH

X

A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]

X

t

AV_to_DL

XX

11

10

01

00

t

CSn_OFF

EB_IO_CS0n

EB_IO_OEn

t

CSn_to_OEn

59012IPR F05

Figure 5. External Bus Read Timing

t

LEPW

EB_IO_LE0

t

LEPW

EB_IO_LE1

t

LEPW

EB_IO_LE2

EB_DATA_[7:0]

EB_ADDR_[1:0]

t

AH

X

A[25:18] A[17:10] A[9:2]

D[31:24]

11

D[23:16]

10

D[7:0]

D[15:8]

01

X

XX

00

t

SU_to_CSn

t

H_from_CSn

EB_IO_WEn

EB_IO_CS0n

t

CSn

t

CSn_OFF

59012IPR F06

Figure 6. External Bus Write Timing

59012iprfa

12

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exTernal bus ac characTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a

frequency tolerance of better than 40ppm.

Note 7: Per pin I/O types are provided in the Pin Functions section.

Note 8: V maximum voltage input must respect the VSUPPLY maximum

IH

Note 2: ESD (electrostatic discharge) sensitive device. ESD protection

devices are used extensively internal to Eterna. However, high electrostatic

discharge can damage or degrade the device. Use proper ESD handling

precautions.

Note 3: Extended storage at high temperature is discouraged, as this

negatively affects the data retention of Eterna’s calibration data. See

FLASH Data Retention section for details.

voltage specification.

Note 9: See the SmartMesh IP Manager API Guide for the time indication

notification definition.

Note 10: Network time accuracy is a statistical measure and varies over

the temperature range, reporting rate and the location of the device relative

to the manager in the network. See Typical Performance Characteristics

section for a more detailed description.

Note 4: Actual RF range is subject to a number of installation-specific

variables including, but not restricted to ambient temperature, relative

humidity, presence of active interference sources, line-of-sight obstacles,

and near-presence of objects (for example, trees, walls, signage, and so

on) that may induce multipath fading. As a result, range varies.

Note 11: Code execution from flash banks being written or erased is

suspended until completion of the flash operation.

Note 12: Guaranteed by design. Not production tested.

Note 5: As specified by IEEE Std. 802.15.4-2006: Wireless Medium

Access Control (MAC) and Physical Layer (PHY) specifications for Low-

Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.

org/findstds/standard/802.15.4-2011.html.

59012iprfa

13

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Typical perFormance characTerisTics

2.0

1.8

1.6

1.4

1.2

1.0

In mesh networks data can propagate from the manager

to the nodes, downstream, or from the motes to the man-

ager, upstream, via a sequence of transmissions from one

device to the next. As shown in Figure 8, data originating

from mote P1 may propagate to the manager directly or

through P2. As mote P1 may directly communicate with

the manager, mote P1 is referred to as a 1-hop mote. Data

originatingfrommoteD1,mustpropagatethroughatleast

one other mote, P2 or P1, and as a result is referred to as

a 2-hop mote. The fewest number of hops from a mote to

the manager determines the hop depth.

0.8

0.6

0.4

0.2

0

30

5

10

15

20

25

PACKET RATE (PACKETS/s)

59012IPR F07a

As described in the Application Time Synchronization

section,Eternaprovidestwomechanismsforapplications

to maintain a time base across a network. The synchro-

nization performance plots that follow were generated

using the more precise TIMEn input. Publishing rate is

the rate a mote application sends upstream data. Syn-

chronization improves as the publishing rate increases.

Baseline synchronization performance is provided for a

network operating with a publishing rate of zero. Actual

performance for applications in network will improve

as publishing rates increase. All synchronization testing

was performed with the 1-hop mote inside a temperature

chamber. Timing errors due to temperature changes and

temperature differences both between the manager and

this mote and between this mote and its descendents

therefore propagated down through the network. The

synchronization of the 3-hop and 5-hop motes to the

manager was thus affected by the temperature ramps

even though they were at room temperature. For 2°C/

minute testing the temperature chamber was cycled

between –40°C and 85°C at this rate for 24 hours. For

8°C/minutetesting,thetemperaturechamberwasrapidly

cycled between 85°C and 45°C for eight hours, followed

by rapid cycling between –5°C and 45°C for eight hours,

and lastly, rapid cycling between –40°C and 15°C for

eight hours.

Figure 7a. Supply Current vs Packet Rate

2.5

2.0

1.5

5 HOPS

4 HOPS

3 HOPS

2 HOPS

1 Hop

1.0

0.5

0

30

5

10

15

20

25

REPORTING INTERVAL (s)

59012IPR F07b

Figure 7b. Packet Latency vs Reporting Interval

MANAGER

P1

P2

1 HOP

P3

2 HOP

D1

3 HOP

D2

5800IPM F08

Figure 8. Example Network Graph

59012iprfa

14

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Typical perFormance characTerisTics

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, Room Temperature

30

60

14

12

10

8

µ = –0.2

σ = 1.7

N = 89699

µ = 0.0

µ = –0.2

σ = 3.6

N = 89698

σ = 0.9

25

20

15

10

N = 89700

50

40

30

20

6

4

5

0

10

0

2

0

–30 –20

0

10 20 30

–40

40

–30 –20

0

10 20 30

–10

–30 –20

0

10 20 30

–40

40

–40

40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G02

59012IPR G01

59012IPR G03

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 2°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 2°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 2°C/Min.

20

15

10

5

14

12

10

8

7

6

5

4

3

2

1

0

µ = 1.5

µ = 0.9

µ = 1.0

σ = 3.3

σ = 3.9

σ = 7.7

N = 93812

N = 93846

N = 93845

6

4

2

0

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

40

–40

40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G04

59012IPR G05

59012IPR G06

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 8°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 8°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 8°C/Min.

12

10

8

14

12

7

6

µ = 3.6

µ = 1.1

µ = 1.0

σ = 5.0

σ = 3.8

σ = 7.4

N = 88144

N = 88179

N = 88178

10

8

5

4

3

6

4

2

0

2

1

0

2

0

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

40

–40

40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G07

59012IPR G08

59012IPR G09

59012iprfa

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Typical perFormance characTerisTics

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, Room Temperature

60

50

40

30

60

50

40

30

50

40

30

20

10

0

µ = 0.0

µ = –0.2

σ = 1.2

µ = –0.2

σ = 1.2

N = 22753

N = 17008

N = 17007

20

10

0

20

10

00

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

40

–40

40

–40

40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G10

59012IPR G11

59012IPR G12

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 2°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 2°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 2°C/Min.

35

30

25

20

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

µ = 0.5

µ = 0.1

σ = 1.9

σ = 1.5

N = 85860

N = 85858

N = 85855

15

10

5

0

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G13

59012IPR G15

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 8°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 8°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 8°C/Min.

60

50

40

30

60

50

40

30

50

40

30

20

10

0

µ = 0.2

µ = 0.0

µ = –1.0

σ = 1.3

N = 33929

σ = 1.4

σ = 1.3

N = 33932

N = 33930

20

10

0

20

10

0

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–30 –20

0

10 20 30

–40

–10

SYNCHRONIZATION ERROR (µs)

59012IPR G16

59012IPR G17

59012IPR G18

59012iprfa

16

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Typical perFormance characTerisTics

As described in the SmartMesh Network Overview sec-

tion, devices in network spend the vast majority of their

time inactive in their lowest power state (Doze). On a

synchronous schedule a mote will wake to communicate

with another mote. Regularly occurring sequences which

wake, perform a significant function and return to sleep

are considered atomic. These operations are considered

atomic as the sequence of events can not be separated

into smaller events while performing a useful function.

For example, transmission of a packet over the radio is an

atomicoperation.Atomicoperationsmaybecharacterized

in either charge or energy. In a time slot where a mote

successfully sends a packet, an atomic transmit includes

setuppriortosendingthemessage,sendingthemessage,

receiving the acknowledgment and the post processing

needed as a result of the message being sent. Similarly

in a time slot when a mote successfully receives a packet,

an atomic receive includes setup prior to listening, listen-

ing until the start of the packet transition, receiving the

packet, sending the acknowledge and the post processing

required due to the arrival of the packet.

To ensure reliability each mote in the network is provided

multiple time slots for each packet it nominally will send

and forward. The time slots are assigned to communicate

upstreamwithatleasttwodifferentmotes.Whencombined

with frequency hopping this provides temporal, spatial

and spectral redundancy. Given this approach a mote will

often listen for a message that it will never receive, since

the time slot is not being used by the transmitting mote.

It has already successfully transmitted the packet. Since

typicallythreetimeslotsarescheduledforeveryonepacket

to be sent or forwarded, motes will perform more of these

atomic idle listens than atomic transmit or atomic receive

sequences. Examples of transmit, receive and idle listen

atomic operations are shown below.

59012iprfa

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Typical perFormance characTerisTics

Atomic Operation—Maximum Length Transmit with Acknowledge, 7.25ms Time Slot (54.5µC Total Charge at 3.6V)

Atomic Operation—Maximum Length Receive with Acknowledge, 7.25ms Time Slot (32.6µC Total Charge at 3.6V)

Atomic Operation—Idle Listen, 7.25ms Time Slot (6.4µC Total Charge at 3.6V)

Figure 9.

59012iprfa

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pin FuncTions ^{Pin functions shown in italics are currently not supported in software.}

The following table organizes the pins by functional

groups. For those I/O with multiple functions the alternate

functions are shown on the second and third line in their

respective row. The No column provides the pin number.

The second column lists the function. The Type column

lists the I/O type. The I/O column lists the direction of the

signal relative to Eterna. The Pull column shows which

signals have a fixed passive pull-up or pull-down. The

Description column provides a brief signal description.

NO POWER SUPPLY

GND

TYPE

Power

I/O

-

PULL DESCRIPTION

1

-

Ground Connection

Power Supply Input to Eterna

11 GND

20 GND

30 GND

34 GND

37 GND

42 GND

56 GND

66 GND

55 VSUPPLY

-

NO RADIO

TYPE

I/O

PULL DESCRIPTION

64 RADIO_INHIBIT

1 (Note 13)

Radio Inhibit

4

5

6

-

GPIO17

GPIO18

GPIO19

ANTENNA

1

I/O

N/A

-

General Purpose Digital I/O

1

General Purpose Digital I/O

N/A

Chip Antenna (LTP5901) or MMCX Connector (LPT5902)

NO ANALOG

TYPE

I/O

PULL DESCRIPTION

7

8

9

AI_2

AI_1

AI_3

Analog

I

-

Analog Input 2

Analog Input 1

Analog Input 3

Analog Input 0

10 AI_0

NO RESET

TYPE

I/O

PULL DESCRIPTION

15 RESETn

1

I

UP

Reset Input, Active Low

NO JTAG

16 TDI

TYPE

I/O

PULL DESCRIPTION

1

I

O

I

UP

-

JTAG Test Data In

17 TDO

18 TMS

19 TCK

JTAG Test Data Out

JTAG Test Mode Select

UP

I

DOWN JTAG Test Clock

59012iprfa

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pin FuncTions ^{Pin functions shown in italics are currently not supported in software.}

NO SPECIAL PURPOSE

TYPE

I/O

PULL DESCRIPTION

63 TIMEn

1 (Note 13)

I

-

Time Capture Request, Active Low

NO CLI AND EXTERNAL MEMORY

25 EB_DATA_7

TYPE

I/O

PULL DESCRIPTION

1

2

-

External Bus Data Bit 7

26 EB_DATA_6

External Bus Data Bit 6

External Bus Data Bit 4

External Bus Data Bit 0

27 EB_DATA_4

28 EB_DATA_0

31 UARTC0_TX

EB_IO_LE0

O

CLI UART 0 Transmit

External Bus I/O Latch Enable 0 for External Address Bits A[25:18]

32 UARTC0_RX

EB_DATA_1

1

I

-

CLI UART 0 Receive

External Bus Data Bit 1

I/O

38 EB_IO_LE2

40 EB_ADDR_1

41 EB_ADDR_0

43 EB_DATA_3

44 EB_DATA_2

45 EB_DATA_5

46 EB_IO_CS0n

47 UARTC1_TX

48 UARTC1_RX

49 EB_IO_WEn

50 EB_IO_OEn

1

2

1

2

1

2

O

-

External Bus I/O Latch Enable 2 for External Address Bits A[9:2]

External Bus Address Bit 1

External Bus Address Bit 0

External Bus Data Bit 3

O

I/O

O

External Bus Data Bit 2

External Bus Data Bit 5

External Bus Chip Select 0

O

CLI UART 1 Transmit

I

CLI UART 1 Receive

O

External Bus Write Enable Strobe

External Bus Output Enable Strobe

O

NO IPCS SPI/FLASH PROGRAMMING (NOTE 14)

33 IPCS_MISO

TYPE

I/O

PULL DESCRIPTION

2

1

O

I

-

SPI Flash Emulation (MISO) Master in Slave Out Port

35 IPCS_MOSI

SPI Flash Emulation (MOSI) Master Out Slave in Port

SPI Flash Emulation (SCK) Serial Clock Port

SPI Flash Emulation Slave Select, Active Low

36 IPCS_SCK

I

39 IPCS_SSn

I

51 FLASH_P_ENn

EB_IO_LE1

I

O

UP Flash Program Enable, Active Low

UP External Bus I/O Latch Enable 1

NO API UART

TYPE

I/O

I

PULL DESCRIPTION

57 UART_RX_RTSn

58 UART_RX_CTSn

59 UART_RX

1 (Note 13)

-

UART Receive (RTS) Request to Send, Active Low

UART Receive (CTS) Clear to Send, Active Low

UART Receive

1

O

I

1 (Note 13)

60 UART_TX_RTSn

61 UART_TX_CTSn

62 UART_TX

1

O

I

UART Transmit (RTS) Request to Send, Active Low

UART Transmit (CTS) Clear to Send, Active Low

UART Transmit

1 (Note 13)

2

O

Note 13: These inputs are always enabled and must be driven or pulled to

a valid state to avoid leakage.

Note 14: Embedded programming over the IPCS SPI bus is only available

when RESETn is asserted.

59012iprfa

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pin FuncTions

VSUPPLY: System and I/O Power Supply. Provides power

to the module. The digital-interface I/O voltages are also

set by this voltage.

latches the network timestamp with sub-microsecond

resolution on the rising edge of the TIMEn signal and

produces a packet on the API serial port containing the

timing information.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the MMCX con-

nectorshouldbe50Ω,single-endedwithrespecttoground.

UARTC0_RX, UARTC0_TX, UARTC1_RX, UARTC1_TX:

The CLI UART provides a mechanism for monitoring,

configuration and control of Eterna during operation. On

the LTP5901/2-IPR CLI UART 0 is used when Eterna is not

configured to support external RAM and CLI UART 1 is

used when Eterna is configured to support external RAM.

For a complete description of the supported commands

see the SmartMesh IP Manager CLI Guide.

RESETn:Theasynchronousresetsignalisinternallypulled

up. Resetting Eterna will result in the ARM Cortex-M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended, except

during power-on and in-circuit programming.

RADIO_INHIBIT: The radio inhibit function is currently

not supported by software. RADIO_INHIBIT provides a

mechanism for an external device to temporarily disable

radiooperation.Failuretoobservethetimingrequirements

defined in the RADIO_INHIBIT AC Characteristics section,

may result in unreliable netowrk operation. In designs

where the RADIO_INHIBIT function is not needed the

input must either be tied, pulled or actively driven low to

avoid excess leakage.

EB_DATA_0 through EB_DATA_7, EB_ADDR_0, EB_

ADDR_1, EB_IO_LE1 through EB_IO_LE2, EB_IO_CS0n,

EB_IO_WEn, EB_IO_ENn: The external bus provides a

multiplexed address data bus enabling the Cortex-M3

direct access of external byte wide RAM. The additional

RAM is used by network management software enabling

thesupportofalargernetworkofmoteswithhigherpacket

throughput. To support the addressing needed, each

latch signal, EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 will

strobe to latch 8-bits of address from the EB_DATA[7:0]

bus.EB_IO_LE0,EB_IO_LE1,andEB_IO_LE2correspond

to addres bits [25:18], [17:10] and [9:2] respectively.

EB_ADDR_0 and EB_ADDR_1 correspond to the lower

two bits of address. For systems with 256k bytes or less

EB_IO_LE2canbeignored.EB_IO_CS0n,EB_IO_WEnand

EB_IO_OEn provide chip select, write enable and output

enable control of the external RAM.

TMS, TCK, TDI, TDO: JTAG port supporting software

debug and boundary scan.

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

UART_RX,UART_RX_RTSn,UART_RX_CTSn,UART_TX,

UART_TX_RTSn,UART_TX_CTSn:TheAPIUARTinterface

includes bi-directional wake up and flow control. Unused

inputsignalsmustbedrivenorpulledtotheirinactivestate.

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The In-circuit programming control system

(IPCS)busenablesin-circuitprogrammingofEterna’sflash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

TIMEn:StrobingtheTIMEninputisthemostaccuratemeth-

odtoacquirethenetworktimemaintainedbyEterna.Eterna

59012iprfa

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operaTion

TheLTP5901/LTP5902istheworld’smostenergy-efficient

IEEE 802.15.4 compliant platform, enabling battery and

energyharvestedapplications.Withapowerful32-bitARM

Cortex-M3, best-in-class radio, flash, RAM and purpose-

built peripherals, Eterna provides a flexible, scalable and

robust networking solution for applications demanding

minimal energy consumption and data reliability in even

the most challenging RF environments.

Shown in Figure 10, Eterna integrates purpose-built pe-

ripheralsthatexcelinbothlowoperating-energyconsump-

tion and the ability to rapidly and precisely cycle between

operating and low power states. Items in the gray shaded

region labeled analog core correspond to the analog/RF

components.

32kHz

DIGITAL CORE

ANALOG CORE

32kHz, 20MHz

TIMERS

SCHED

VOLTAGE REFERENCE

PRIMARY

CORE REGULATOR

CLOCK REGULATOR

ANALOG REGULATOR

DC/DC

SRAM

72kB

CONVERTER

PMU/

RELAXATION

OSCILLATOR

FLASH

512kB

CLOCK

CONTROL

PA

DC/DC

CONVERTER

PoR

20MHz

FLASH

CONTROLLER

802.15.4

MOD

LPF

DAC

AES

PA

CODE

802.15.4

FRAMING

DMA

PLL

AUTO

MAC

SYSTEM

802.15.4

DEMOD

BPF

PPF

LNA

ADC

LIMITER

AGC

RSSI

BAT

LOAD

IPCS

SPI

SLAVE

CLI

UART

(2 PIN)

API

ADC

CTRL

10-BIT

ADC

UART

(6 PIN)

VGA

PTAT

4-BIT

DAC

59012IPR F10

Figure 10. Eterna Block Diagram

59012iprfa

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LTP5901-IPR/LTP5902-IPR

operaTion

POWER SUPPLY

with other wireless products. In addition, precise timing

enablesnetworkstoreducespectraldeadtime, increasing

total network throughput.

Eterna is powered from a single pin, VSUPPLY, which

powers the I/O cells and is also used to generate internal

supplies.Eterna’stwoon-chipDC/DCconvertersminimize

Eterna’senergyconsumptionwhilethedeviceisawake.To

conserve power the DC/DC converters are disabled when

the device is in low power state. Eterna’s integrated power

supply conditioning architecture, including the two inte-

gratedDC/DCconvertersandthreeintegratedlowdropout

regulators, provides excellent rejection of supply noise.

Eterna’s operating supply voltage range is high enough

to support direct connection to lithium-thionyl chloride,

Li-SOCl2, sources and wide enough to support battery

operation over a broad temperature range.

APPLICATION TIME SYNCHRONIꢀATION

In addition to coordinating time slots across the network,

which is transparent to the user, Eterna’s timing manage-

mentisusedtosupporttwomechanismstosharenetwork

time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to

be performed in a synchronized fashion across a network.

Eterna will send a time packet through its serial interface

when one of the following occurs:

• Eterna receives an API request to read time

• The TIMEn signal is asserted

SUPPLY MONITORING AND RESET

TheuseofTIMEnhastheadvantageofbeingmoreaccurate.

The value of the timestamp is captured in hardware relative

to the rising edge of TIMEn. If an API request is used, due

to packet processing, the value of the timestamp may be

capturedseveralmillisecondsafterreceiptofthepacketdue

topacketprocessing.SeesectionTIMEnACCharacteristics,

for the time function’s definition and specifications.

Eterna integrates a power-on reset (PoR) circuit. As the

RESETn input pin is nominally configured with an internal

pull-up resistor, no connection is required. For a graceful

shutdown, the software and the networking layers should

be cleanly halted via API commands prior to assertion of

theRESETnpin.SeetheSmartMeshIPManagerAPIGuide

for details on the disconnect and reset commands. Eterna

includes a soft brown-out monitor that fully protects the

flash from corruption in the event that power is removed

while writing to flash. Integrated flash supervisory func-

tionality, in conjunction with a fault tolerant file system,

yields a robust non-volatile storage solution.

TIME REFERENCES

Eterna includes three clock sources: an internal relaxation

oscillator, a low power oscillator designed for a 32.768kHz

crystal, and the radio reference oscillator designed for a

20MHz crystal.

PRECISION TIMING

Relaxation Oscillator

A major feature of Eterna over competing 802.15.4 prod-

uct offerings is its low power dedicated timing hardware

and timing algorithms. This functionality provides timing

precision two to three orders of magnitude better than

any other low power solution available at the time of

publication. Improved timing accuracy allows motes to

minimize the amount of radio listening time required to

ensure packet reception thereby lowering even further

the power consumed by SmartMesh networks. Eterna’s

patented timing hardware and timing algorithms provide

superior performance over rapid temperature changes,

further differentiating Eterna’s reliability when compared

The relaxation oscillator is the primary clock source for

Eterna, providing the clock for the CPU, memory subsys-

tems, and all peripherals. The internal relaxation oscillator

is dynamically calibrated to 7.3728MHz. The internal re-

laxation oscillator typically starts up in a few μs, providing

anexpedient, lowenergymethodfordutycyclingbetween

active and low power states. Quick start-up from the doze

state,definedintheStateDiagramsection,allowsEternato

wakeupandreceivedataovertheUARTandSPIinterfaces

by simply detecting activity on the appropriate signals.

59012iprfa

23

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32.768kHz Crystal

API UART PROTOCOL

Once Eterna is powered up and the 32.768kHz crystal

source has begun oscillating, the 32.768kHz crystal re-

mains operational while in the active state, and is used as

the timing basis when in doze state. See the State Diagram

section, for a description of Eterna’s operational states.

The API UART protocol was created with the goal of sup-

portingawiderangeofcompanionmultipointcontrolunits

(MCUs)whilereducingpowerconsumptionofthesystem.

The receive half of the API UART protocol includes two ad-

ditional signals in addition to UART_RX: UART_RX_RTSn

and UART_RX_CTSn. The transmit half of the API UART

protocol includes two additional signals in addition to

UART_TX: UART_TX_RTSn and UART_TX_CTSn. The

API UART protocol is referred to as Mode 4.

20MHz Crystal

The 20MHz crystal source provides a frequency reference

for the radio, and is automatically enabled and disabled

by Eterna as needed.

In the figures accompanying the protocol descriptions,

signals driven by the companion processor are drawn

in black and signals driven by Eterna are drawn in blue.

RADIO

Eterna includes the lowest power commercially available

2.4GHz IEEE 802.15.4e radio by a substantial margin.

(Please refer to section Radio Specifications, for power

consumption numbers). Eterna’s integrated power ampli-

fier is calibrated and temperature-compensated to con-

sistently provide power at a limit suitable for worldwide

radio certifications. Additionally, Eterna uniquely includes

a hardware-based autonomous MAC that handles precise

sequencing of peripherals, including the transmitter, the

receiver, and advanced encryption standard (AES) periph-

erals. The hardware-based autonomous media access

controller (MAC) minimizes CPU activity, thereby further

decreasing power consumption.

UART Mode 4

UART Mode 4 incorporates level-sensitive flow control

on the TX channel and requires no flow control on the

RX channel, supporting 115200 baud. The use of level-

sensitive flow control signals enables higher data rates

with the option of using a reduced set of the flow control

signals; however, Mode 4 has specific limitations. First,

the use of the RX flow control signals (UART_RX_RTSn

and UART_RX_CTSn) for Mode 4 are optional provided

the use is limited to the industrial temperature range

(–40°Cto85°C);otherwise, theflowcontrolismandatory.

If RX flow control signals are not used, UART_RX_RTSn

shouldbetiedtoVSUPPLY(inactive)andUART_RX_CTSn

should be left unconnected. Second, unless the com-

panion processor is always ready to receive a packet,

the companion processor must negate UART_TX_CTSn

prior to the end of the current packet. Failure to negate

UART_TX_CTSn prior to the end of a packet may result

in back to back packets. Third, the companion processor

UARTS

The principal network interface is through the applica-

tion programming interface (API) UART. A command-line

interface (CLI) is also provided for support of test and

debug functions. Both UARTs sense activity continuously,

consumingvirtuallynopoweruntildataistransferredover

the port and then automatically returning to their lowest

power state after the conclusion of a transfer. The defini-

tion for packet encoding on the API UART interface can

be found in the SmartMesh IP Manager API Guide and the

CLI command definitions can be found in the SmartMesh

IP Manager CLI Guide.

must wait at least t

between transmitting

RX_INTERPACKET

packets on UART_RX. See the UART AC Characteristics

section for complete timing specifications. Packets are

HDLCencodedwithonestopbitandnoparitybit. Theflow

control signals for the TX channel are shown in Figure 11.

TransfersareinitiatedbyEternaassertingUART_TX_RTSn.

59012iprfa

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The UART_TX_CTSn signal may be actively driven by the

companion processor when ready to receive a packet or

UART_TX_CTSn may be tied low if the companion pro-

cessor is always ready to receive a packet. After detecting

a logic ‘0’ on UART_TX_CTSn Eterna sends the entire

packet. Following the transmission of the final byte in

the packet Eterna negates UART_TX_RTSn and waits for

to remain inactive during the majority of the radio activity.

The autonomous MAC, provides software-independent

timing control of the radio and radio-related functions,

resultinginsuperiorreliabilityandexceptionallylowpower.

SECURITY

Network security is an often overlooked component of a

complete network solution. Proper implementation of se-

curity protocols is significant in terms of both engineering

effort and market value in an OEM product. Eterna system

solutionsprovideaFIPS-197validatedencryptionscheme

that includes authentication and encryption at the MAC

and network layers with separate keys for each mote.

This not only yields end-to-end security, but if a mote is

somehowcompromised,communicationfromothermotes

is still secure. A mechanism for secure key exchange al-

lows keys to be kept fresh. To prevent physical attacks,

Eternaincludeshardwaresupportforelectronicallylocking

devices, thereby preventing access to Eterna’s flash and

RAM memory and thus the keys and code stored therein.

t

, defined in the UART AC Characteristics

TX_INTERPACKET

section, before asserting UART_TX_RTSn again.

For details on the timing of the UART protocol, see the

UART AC Characteristics section.

UART_TX_RTSn

UART_TX_CTSn

UART_TX

BYTE 0

BYTE 1

59012IPR F11

Figure 11. UART Mode 4 Transmit Flow Control

CLI UART

The command line interface (CLI) UART port is a two

wire protocol (TX and RX) that operates at a fixed 9600

baud rate with one stop bit and no parity. The CLI UART

interfaceisintendedtosupportcommandlineinstructions

and response activity.

TEMPERATURE SENSOR

Eterna includes a calibrated temperature sensor on chip.

The temperature readings are available locally through

Eterna’s serial API, in addition to being available via the

network manager. The performance characteristics of

the temperature sensor can be found in the Temperature

Sensor Characteristics section.

AUTONOMOUS MAC

Eterna was designed as a system solution to provide a

reliable, ultralow power, and secure network. A reliable

network capable of dynamically optimizing operation

over changing environments requires solutions that are

far too complex to completely support through hardware

acceleration alone. As described in the Precision Timing

section,propertimemanagementisessentialforoptimizing

a solution that is both low power and reliable. To address

theserequirementsEternaincludestheautonomousMAC,

which incorporates a coprocessor for controlling all of

the time-critical radio operations. The autonomous MAC

provides two benefits: first, preventing variable software

latency from affecting network timing and second, greatly

reducing system power consumption by allowing the CPU

RADIO INHIBIT

The RADIO_INHIBIT input enables an external control-

ler to temporarily disable the radio software drivers (for

example, to take a sensor reading that is susceptible to

radio interference). When RADIO_INHIBIT is asserted

the software radio drivers will disallow radio operations

including clear channel assessment, packet transmits, or

packet receipts. If the radio is active in the current time

slot when RADIO_INHIBIT is asserted the radio will be

disabledafterthepresentoperationcompletes. Fordetails

on the timing associated with RADIO_INHIBIT, see the

RADIO_INHIBIT AC Characteristics section.

59012iprfa

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LTP5901-IPR/LTP5902-IPR

operaTion

SOFTWARE INSTALLATION

Where:

Devices are supplied with the flash erased, requiring pro-

gramming as part of the OEMs manufacturing procedure.

The US Department of Commerce places restrictions on

export of systems and software supporting encryption.

All of Linear/Dust product software produced to date

contains encryption and is subject to export regulations

and may be provided only via MyLinear, https://www.

linear.com/mylinear. Customers purchasing SmartMesh

products will receive a certificate containing a registration

key and registration instructions with their order. After

registering with the key, customers will be able to

download SmartMesh software images from MyLinear.

Once registered, customers will receive automated e-mail

notifications as software updates are made avaialbe.

AF = acceleration factor

Ea = activation energy = 0.6eV

–5

k = 8.625 • 10 eV/°K

T

= is the specified temperature retention in °C

USE

= actual storage temperature in °C

STRESS

Example: Calculate the effect on retention when storing

at a temperature of 105°C.

T

= 105°C

STRESS

= 85°C

USE

AF = 2.8

So the overall retention of the flash would be degraded

by a factor of 2.8, reducing data retention from 20 years

at 85°C to 7.1 years at 105°C.

Linear Technology offers the DC9010, in circuit program-

mer for the Eterna based products. While the DC9010, is

provided as a finished product, the design documents are

provided as a reference for customers.

NETWORKING

Oncesoftwarehasbeenloaded,devicescanbeconfigured

via either the CLI or API ports. Configuration commands

and settings are defined in SmartMesh IP Manager API

Guide and SmartMesh IP Manager CLI Guide.

The LTP5901-IPR/LTP5902-IPR network manager pro-

vides the ingress/egress point for at the wired to wireless

mesh network boundary, via the API UART interface. The

complexity of the mesh network management is handled

entirely within the embedded software, which provides

dynamic network optimization, deterministic power man-

agement, intelligent routing, and configurable bandwidth

allocation while achieving carrier class data reliability and

low power operation.

FLASH DATA RETENTION

Eterna contains internal flash (non-volatile memory) to

store calibration results, unique ID, configuration settings

and software images. Flash retention is specified over the

operatingtemperaturerange.SeeElectricalCharacteristics

and Absolute Maximum Ratings sections.

Dynamic Network Optimization

Non destructive storage above the operating temperature

range of –40°C to 85°C is possible; although, this may

result in a degradation of retention characteristics.

Dynamic network optimization allows Eterna to address

the changing RF requirements in harsh industrial en-

vironments resulting in a network that is continuously

self-monitoringandself-adjusting.Themanagerperforms

dynamicnetworkoptimizationbaseduponperiodicreports

on network health and link quality that it receives from

the network motes. The manager uses this information

to provide performance statistics to the application layer

and proactively solve problems in the network. Dynamic

The degradation in flash retention for temperatures >85°C

can be approximated by calculating the dimensionless

acceleration factor using the following equation.



























Ea

k

1



•

−





AF = e^

T

+273

T

+273

USE

STRESS

59012iprfa

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LTP5901-IPR/LTP5902-IPR

operaTion

requirements, such as request/response, fast file trans-

fer, and alerting. Relevant configuration parameters are

described in the SmartMesh IP Users Guide. The design

trade-offs between network performance and current

consumption are supported via the SmartMesh Power

and Performance Estimator.

network optimization not only maintains network health,

but also allows Eterna to deliver deterministic power

management. One of the key advantages of SmartMesh

networking solutions is the network manager is aware of

and tracking the success or failure of every packet trans-

action, so not only can the network be optimized, but the

solution can be rigorously tested to produce a system

solution with better than 99.999% reliability.

IP Manager Options

The IP Manager can operate with or without external

SRAM, as described in the LTP5901 and LTP5902 Inte-

gration Guide. When used without external SRAM, the IP

manager is limited to managing networks of 32 motes

or fewer and is limited to a maximum packet throughput

of 24 packets per second. With external SRAM, the IP

Managersupportsmanagingnetworksofupto100motes

and the packet throughput of the IP Manager increases

from 24 packets per second to 36 packets per second.

Deterministic Power Management

Deterministic power management balances traffic in the

network by diverting traffic around heavily loaded motes

(for example, motes with high reporting rates). In do-

ing so, it reduces power consumption for these motes

and balances power consumption across the network.

Deterministic power management provides predictable

maintenance schedules to prevent down time and lower

the cost of network ownership. When combined with field

devices using Eterna’s industry-leading low power radio

technology,deterministicpowermanagementenablesover

a decade of battery life for network motes.

State Diagram

In order to provide capabilities and flexibility in addition

to ultra low power, Eterna operates in various states, as

shown in Figure 12 Eterna State Diagram and described

in this section. State transitions shown in red are not

recommended.

Intelligent Routing

Intelligent routing provides each packet with an optimal

path through the network. The shortest distance between

two points is a straight line, but in RF the quickest path is

notalwaystheonewiththefewesthops.Intelligentrouting

finds optimal paths by considering the link quality (one

path may lose more packets than another) and the retry

schedule, in addition to the number of hops. The result

is reduced network power consumption, elimination of

in-network collisions, and unmatched network scalability

and reliability.

Start-Up

Start-up occurs asa resultofeithercrossing the power-on

reset threshold or asserting RESETn. After the comple-

tion of power-on reset or the falling edge of an internally

synchronized RESETn, Eterna loads its fuse table which,

as described in the previous section, includes setting

I/O direction. In this state, Eterna checks the state of

the FLASH_P_ENn and RESETn and enters the serial

flash emulation mode if both signals are asserted. If the

FLASH_P_ENnpinisnotassertedbutRESETnisasserted,

Eterna automatically reduces its energy consumption to

a minimum until RESETn is released. Once RESETn is

de-asserted, Eterna goes through a boot sequence, and

then enters the active state.

Configurable Bandwidth Allocation

SmartMesh networks provide configurations that enable

users to make bandwidth and latency versus power trade-

offs both network-wide and on a per device basis. This

flexibly enables solutions that tailored to the application

59012iprfa

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operaTion

Serial Flash Emulation

Operation

When both RESETn and FLASH_P_ENn are asserted,

Eterna disables normal operation and enters a mode to

emulate the operation of a serial flash. In this mode, its

flash can be programmed.

Once Eterna has completed start-up, Eterna transitions to

the operational group of states (active/CPU active, active/

CPU inactive, and Doze). There, Eterna cycles between the

various states, automatically selecting the lowest pos-

sible power state while fulfilling the demands of network

operation.

POWER-ON

RESET

VSUPPLY > PoR

RESETn LOW AND

FLASH_P_ENn LOW

LOAD FUSE

SETTINGS

SET RESETn HIGH AND

FLASH_P_ENn HIGH

FOR 125µs, THEN

SERIAL FLASH

EMULATION

SET RESETn LOW

RESETn LOW AND

FLASH_P_ENn HIGH

RESETn HIGH

AND

FLASH_P_ENn

HIGH

RESET

DEASSERT

RESETn

BOOT

START-UP

ASSERT RESETn ASSERT RESETn

ASSERT RESETn

CPU AND

PERIPHERALS

INACTIVE

CPU

ACTIVE

DEEP SLEEP

DOZE

CPU

INACTIVE

LOW POWER SLEEP

COMMAND

HW OR PMU EVENT

OPERATION

INACTIVE

59012IPR F12

Figure 12. Eterna State Diagram

59012iprfa

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operaTion

Active State

Doze State

In the active state, Eterna’s relaxation oscillator is running

and peripherals are enabled as needed. The ARM Cortex-

M3cyclesbetweenCPU-activeandCPU-inactive(referred

to in the ARM Cortex-M3 literature as sleep now mode).

Eterna’s extensive use of DMA and intelligent peripherals

that independently move Eterna between active state and

doze state minimizes the time the CPU is active, signifi-

cantly reducing Eterna’s energy consumption.

The doze state consumes orders of magnitude less cur-

rent than the active state and is entered when all of the

peripherals and the CPU are inactive. In the Doze state

Eterna’s full state is retained, timing is maintained, and

Eterna is configured to detect, wake, and rapidly respond

to activity on I/Os (such as UART signals and the TIMEn

pin). In the doze state the 32.768kHz oscillator and as-

sociated timers are active.

applicaTions inFormaTion

REGULATORY AND STANDARDS COMPLIANCE

The RoHS-compliant design features include:

• RoHS-compliant solder for solder joints

• RoHS-compliant base metal alloys

Radio Certification

The LTP5901 and LTP5902 have been certified under a

single modular certification, with the module name of

ETERNA2.Followingtheregulatoryrequirementsprovided

in the ETERNA2 Users Guide can enable customers to

ship products in the supported geographies, by simply

completing an unintentional radiator scan of the finished

product(s). The ETERNA2 Users Guide also provides the

technical information needed to enable customers to fur-

ther certify either the modules or products based upon the

modules in geographies that have not or do not support

modular certification.

• RoHS-compliant precious metal plating

• RoHS-compliant cable assemblies and connector

choices

• Halogen-free mold compound

• RoHS-compliant and 245°C re-flow compatible

Note: Customers may elect to use certain types of lead-

free solder alloys in accordance with the European Com-

munity directive 2011/65/EU. Depending on the type of

solder paste chosen, a corresponding process change to

optimize reflow temperatures may be required.

Compliance to Restriction of Hazardous Substances

(RoHS)

SOLDERING INFORMATION

Restriction of hazardous substances 2(RoHS 2) is a

directive that places maximum concentration limits on

the use of certain hazardous substances in electrical and

electronic equipment. Linear Technology is committed to

meeting the requirements of the European Community

directive 2011/65/EU.

The LTP5901 and LTP5902 are suitable for both eutectic

PbSn and RoHS-6 reflow. The maximum reflow solder-

ing temperature is 260°C. A more detailed description of

layoutrecommendations,assemblyproceduresanddesign

considerations is included in the LTP5901 and LTP5902

Hardware Integration Guide.

This product has been specifically designed to utilize

RoHS-compliant materials and to eliminate or reduce the

use of restricted materials to comply with 2011/65/EU.

59012iprfa

29

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LTP5901-IPR/LTP5902-IPR


型号：	LTP5902IPC-IPRB1C1#PBF
厂家：	Linear
描述：	LTP5902-IPM - SmartMesh IP Wireless 802.15.4e PCBA Module with Antenna Connector; Pins: 66; Temperature Range: -40°C to 85°C PC 无线
文件：	总34页 (文件大小：1129K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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