SD210DE-TO-72-4L [Linear]
Transistor,;
| 型号： | SD210DE-TO-72-4L |
| 厂家： | 
Linear |
| 描述： | Transistor, |
| 文件： | 总3页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SD210DE/214DE
N-CHANNEL LATERAL
DMOS SWITCH
PRODUCT SUMMARY
PART NUMBER
V(BR)DS Min (V)
V(GS)th Max (V)
rDS(on) Max (Ω)
Crss Max (pF)
tON Max (ns)
SD210DE
SD214DE
30
1.5
1.5
45 @ VGS=10V
45 @ VGS=10V
0.5
0.5
2
2
20
Features
Benefits
Applications
• Fast Analog Switch
• Fast Sample-and-Holds
• Pixel-Rate Switching
• DAC Deglitchers
• Ultra-High Speed Switching—tON: 1ns
• Ultra-Low Reverse Capacitance: 0.2pF
• Low Guaranteed rDS @5V
• High-Speed System Performance
• Low Insertion Loss at High Frequencies
• Low Transfer Signal Loss
• Low Turn-On Threshold Voltage
• N-Channel Enhancement Mode
• Simple Driver Requirement
• Single Supply Operation
• High-Speed Driver
Description
The SD210DE/214DE are enhancement-mode MOSFETs designed
results in lower gate leakage and ± voltage capability from gate to
for high speed low-glitch switching in audio, video and high-frequency substrate. A poly-silicon gate is featured for manufacturing
applications. The SD214DE is normally used for a ±10-V analog
switching. These MOSFETs utilize lateral construction to
achieve low capacitance and ultra-fast switching speeds. These
MOSFETs do not have a gate protection Zener diode which
reliability.
For similar products see: quad array—SD5000/5400 series, and
Zener protected—SD211DE/SST211 series.
TO-206AF
(TO-72)
Linear Integrated Systems
•
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201114 06/19/2013 Rev#A7 ECN# SD210DE_214DE
Absolute Maximum Ratings (TA = 25°C unless otherwise noted)
Gate-Drain, Gate-Source Voltage
Gate-Substrate Voltage
Drain-Source Voltage
. . . . . . . . . . . . . . . . . . . . . . . . ± 40V
. . . . . . . . . . . . . . . . . . . . .± 30V
(SD210DE) . . . . . . . . . . . . . . . 30V
(SD214DE) . . . . . . . . . . . . . . . 20V
(SD210DE) . . . . . . . . . . . . . . . 10V
(SD214DE) . . . . . . . . . . . . . . . 20V
(SD210DE) . . . . . . . . . . . . . . . 30V
(SD214DE) . . . . . . . . . . . . . . . 25V
Source-Substrate Voltage
(SD210DE) . . . . . . . . . . . . . . . 15V
(SD210DE) . . . . . . . . . . . . . . . 25V
. . . . . . . . . . . . . . . . . . . . . . . .50mA
. . . . . . . . . . . . . . . . . . . . . . . 300°C
. . . . . . . . . . . . . . . . . -65 to 150°C
. . . . . . . . . . . . . . . . . -55 to 125°C
. . . . . . . . . . . . . . . . . . . . . . .300mW
Drain Current
Lead Temperature (1/16” from ease for 10 seconds)
Storage Temperature
Operating Junction Temperature
Power Dissipation*
Source-Drain Voltage
Drain-Substrate Voltage
Note:
* Derate 3mW/
°
C above 25°C
Specificationsa
LIMITS
SD210DE SD214DE
PARAMETER
Static
SYMBOLb
TEST CONDITIONSb
TYPc
UNIT
Min Max Min Max
VGS = VBS = 0V, ID = 10 µA
VGS = VBS = -5V, ID = 10 nA
35
30
30
10
Drain - Source
Breakdown Voltage
V(BR)DS
V(BR)SD
V(BR)DBO
20
20
Source - Drain
Breakdown Voltage
VGD = VBD = -5V, IS = 10 nA
22
35
35
10
V
Drain - Substrate
Breakdown Voltage
VGB = 0V, ID= 10 nA
Source Open
VGB = 0V, Is = 10 µA
Drain Open
15
15
25
25
Source - Substrate
Breakdown Voltage
V(BR)SBO
IDS(off)
ISD(off)
IGBS
VDS = 10V
0.4
0.9
0.5
0.8
10
10
Drain – Source
Leakage
VGS = VBS = -5V
VGD = VBD = -5V
VDS = 20V
VSD = 10V
VSD = 20V
10
Source - Drain
Leakage
nA
V
10
Gate Leakage
VDB = VSB = 0V, VGB = ±4 0V
0.001
0.1
0.1
VDS = VGS, ID = 1 µA ,
VSB = 0V
Threshold Voltage
VGS(th)
0.8
0.5 1.5 0.1 1.5
VGS = 5V
58
38
70
45
70
45
VGS = 10V
Drain – Source
On-Resistance
VSB = 0V
ID = 1mA
VGS = 15V
30
26
24
rDS(on)
Ω
VGS = 20V
VGS = 25V
Linear Integrated Systems
•
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201114 06/19/2013 Rev#A7 ECN# SD210DE_214DE
Specificationsa
LIMITS
SD210DE SD214DE
SYMBOLb
TEST CONDITIONSb
TYPc
UNIT
PARAMETER
Min Max Min Max
Dynamic
gfs
gos
11
0.9
10
10
Forward
Transconductance
VDS = 10V, VSB = 0V,
ID = 20mA, f = 1kHz
mS
Gate Node
Capacitance
Drain Node
Capacitance
Source Node
Capacitance
Reverse Transfer
Capacitance
C(GS+GD+GB)
C(GD+DB)
C(GS+SB)
Crss
2.5
1.1
3.7
0.2
3.5
1.5
5.5
0.5
3.5
1.5
5.5
0.5
VDS = 10V, f = 1MHz
pF
ns
VGS
= VBS = -15V
Switching
tD(on)
tr
tD (off)
tf
0.5
0.6
2
1
1
1
1
Turn-On Time
VSB = 0V, VIN0 to 5V, RG = 25Ω
VDD = 5V, RL = 680Ω
Turn-Off Time
6
Notes:
a. TA= 25°C unless otherwise noted.
b. B is the body (substrate) and V(BR) is breakdown voltage.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing
high-quality discrete components. Expertise brought to LIS is based on processes and products developed
at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall,
a protégé of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide,
co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems.
Linear Integrated Systems
•
4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261
Doc 201114 06/19/2013 Rev#A7 ECN# SD210DE_214DE
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