TCA62746FG [MARKTECH]

Interface Circuit;
TCA62746FG
型号: TCA62746FG
厂家: MARKTECH CORPORATE    MARKTECH CORPORATE
描述:

Interface Circuit

驱动 光电二极管 接口集成电路
文件: 总15页 (文件大小:338K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
TOSHIBA CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC  
TCA62746FG/FNAG  
16-ch constant current LED driver  
TCA62746 FG  
TCA62746FNAG  
The TCA62746FG/FNAG are the LED driver who has constant  
current output by the sink type and is the most suitable for the LED  
module and the LED display to light up.  
This driver is composed of 16-bit constant current outputs, 16-bit  
shift register, 16-bit latch and 16-bit AND logic gates.  
All output becomes the same value except for the error when the  
current value of 16-bit outputs and set a resistor outside.  
And, the LED of the output load is broken ( open ) and has the  
function that the lighting-up bad condition can be detected.  
SSOP24-P-300-1.00B  
SSOP24-P-150-0.64  
FEATURE  
16 output built-in  
Output open detection (OOD)  
Output a detection result in the transfer from SOUT by the detection mode.  
Output short detection (OSD) <--- Consideration in built-in.  
Output a detection result in the transfer from SOUT by the detection mode.  
Output current capability  
2 ~ 80 mA × 16-bit constant current output  
Constant current accuracy  
± 1 % of output to output  
<--- this is the target spec.  
<--- this is the target spec.  
± 3 % of device to device  
Control data form  
1 I/O ( Serial in, serial out )  
High-speed switching output  
tr/tf = 15 ns (typ.) @ IOUT = 20 mA  
<--- this is the target spec.  
CMOS input level ( schumit trigger input )  
Data transfer frequency  
Power-supply voltage  
Operating temperature  
Supply voltage for the LED  
fMAX = 25 MHz  
VDD = 3.0 ~ 5.5 V  
Topr = -40 ~ 85  
VOUT = 17 V ( min. )  
The output propagation-delay-time to have been well-balanced  
tpLH tpHL @ OE-OUTn - - - target spec..  
Output delay circuit built-in for noise margine  
Power on reset circuit (POR) built-in - - - This is idea  
Upper compatible of the series of the TB62706B and TB62726A series  
Package  
FG type :  
SSOP24-P-300-1.00B  
FNAG type : SSOP24-P-150-0.64 (Manufactured by Malaysia factory.)  
Company Headquarters  
California Sales Office:  
950 South Coast Drive, Suite 225  
Costa Mesa, California 92626  
Toll Free: 800.984.5337  
3 Northway Lane North  
Latham, New York 12110  
Toll Free: 800.984.5337  
Fax: 518.785.4725  
Web: www.marktechopto.com | Email: info@marktechopto.com  
Fax: 714.850.9314  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
PACKAGE AND PIN PAYOUT ( TOP VIEW )  
< FG-type >  
< FNAG-type >  
GND  
SIN  
V
OUT14  
OUT15  
OUT13  
OUT12  
OUT11  
OUT10  
OUT9  
OUT8  
OUT7  
OUT6  
OUT5  
OUT4  
OUT3  
OUT2  
DD  
R
EXT  
CLK  
SOUT  
EN  
ENABLE  
SERIAL-OUT  
R-EXT  
LAT  
OUT 0  
OUT 1  
OUT 2  
OUT 3  
OUT 4  
OUT 5  
OUT 6  
OUT 7  
OUT 15  
OUT 14  
OUT 13  
OUT 12  
OUT 11  
OUT 10  
OUT 9  
VDD  
GND  
SERIAL-IN  
CLOCK  
LATCH  
OUT0  
OUT 8  
OUT1  
WARNING :  
Short-circuiting an output terminal to GND or to the power supply terminal may broken the device.  
Please take care when wiring the output terminals, the power supply terminal and the GND terminals.  
BLOCK DIAGRAM  
Exp. this is one of the ideas of control circuit for OOD and OSD.  
OUT0 OUT1  
OUT15  
2.7V  
16  
0.05V  
16  
OUT0 OUT1  
OUT15  
Constant current outputs with  
V
DD  
delay for total rush current  
B.G  
POR  
Delay  
Delay  
GND  
OE  
R
EXT  
OE  
Q0 Q1 ---  
Q15  
OOD/OSD  
Controller  
16bit D-latch  
D0 D1 ---  
R
SLAT  
G
D15  
ST-OUT  
SIN  
D0  
Q0 Q1 ---  
Q15  
Q15  
R
SOUT  
Presetable 16bit Shift Register  
ST D0~D15  
SCK  
S
OSD  
16bit  
MUX  
OOD  
DO  
16  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
TIMING DIAGRAM  
n=0 1 2 3 4 5 6 7 8 9 101112131415  
3.3v/5v  
0V  
CLK  
3.3v/5v  
0V  
SIN  
3.3v/5v  
0V  
LAT  
3.3v/5v  
0V  
EN  
On  
Off  
OUT0  
OUT1  
OUT3  
On  
Off  
On  
Off  
On  
Off  
OUT15  
SOUT  
3.3v/5v  
0V  
<-- SOUT has half clock delayed.  
WARNING :  
Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.  
NOTE1 :  
The latches circuit holds data by pulling the LAT terminal Low. And, when LAT terminal is a High-level,  
latch circuit doesn’t hold data, and it passes from theInput to the output.  
When EN terminal is Low-level, output terminal OUT0~OUT15 respond to the data, and on & off does.  
And, when EN terminal is a High-level, it offs with the output terminal regardless of the data.  
TRUTH TABLE  
CLK  
LAT  
EN  
SIN  
OUT0 --- OUT7 --- OUT15  
SOUT  
Positive edge  
Positive edge  
Positive edge  
Negative edge  
Negative edge  
H
L
H
X
X
L
L
L
L
H
Dn  
Dn --- Dn-7 --- Dn-15  
No Change  
Dn+2 --- Dn-5 --- Dn-13  
Dn+2 --- Dn-5 --- Dn-13  
Off  
Dn-15  
Dn-14  
Dn-13  
Dn-13  
Dn-13  
Dn+1  
Dn+2  
Dn+3  
Dn+3  
NOTE2:  
OUT0~OUT15=ON when Dn=Hi, OUT0~OUT15=OFF when Dn=Lo.  
In order to ensure that the level of the power supply voltage is correct, an external resistor have to  
connected between R-EXT and GND.  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
TERMINAL DESCRIPTION  
Pin No.  
Pin Name  
Function  
1
2
3
GND  
GND terminal for control logic  
SIN  
Input terminal for serial data for data shift register  
Input terminal for clock for data shift on rising edge  
CLK  
Input terminal for data strobe When the LAT = ”Hi”, data is no latched.  
When ithe LAT = ”Lo”, data is latched.  
4
LAT  
5 ~ 20  
OUT0 ~ OUT15 Constant-current output terminals  
Input terminal for output enable.  
21  
EN  
All outputs (OUT0 ~ OUT15) are turned off, when the EN = ”Hi”.  
And are turned on, when the EN = ”Lo”.  
22  
23  
24  
SOUT  
REXT  
Output terminal for serial data input on SIN terminal  
Input terminal used to connect an external resistor.  
This regulated the output current.  
VDD  
3.3V - 5V supply voltage terminal.  
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUT  
2. LAT Terminal  
1. EN Terminal  
R(UP)  
V
V
DD  
DD  
LAT  
EN  
GND  
GND  
R(DOWN)  
4. SERIAL-OUT Terminal  
3. CLOCK,SERIAL-IN Terminal  
V
V
DD  
DD  
CLK,  
SIN  
SOUT  
Internal data  
GND  
GND  
5. OUT0 ~ OUT15 Terminal  
OUT 0 ~ OUT15  
Parasitic Diode  
GND  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
ABSOLUTE MAXIMUM RATINGS  
Characteristics  
Supply Voltage  
Input Voltage  
Symbol  
Rating  
Unit  
V
VDD  
+6  
-0.2 ~ VDD+0.2  
VIN  
Output Current  
Output Voltage  
IOUT  
90  
mA/ch  
V
VOUT  
Pd1  
-0.2 ~ 6.5  
FNAG type : 0.625(Free air)  
FG type : 0.83(Free air), 1.00(On PCB)  
FNAG type : 200(Free air)  
FG type : 140(Free air), 120(On PCB)  
-40 to 85  
Power Dissipation  
W
°C/W  
°C  
Pd2  
Rth(j-a)  
Rth(j-a)  
Topr  
1
Thermal Resistance  
2
Operating Temperature  
Storage Temperature  
Tstg  
-55 to 150  
NOTE3:  
With devide monuted on glass-epoxy PCB of less than 40% Cu and of dimensions  
50mm x 50 mm x 1.6mm.  
RECOMMENDED OPERATING CONDITION  
(Topr = -40 ~ 85 °C, unless otherwise noted. )  
Characteristics  
Supply voltage  
Output voltage  
Symbol  
Condition  
Min  
Typ  
Max  
Unit  
V
VDD  
-
3
-
5.5  
VOUT(on)  
IOUT  
-
-
0.7  
4
V
Each DC 1 Circuit  
2
-
-
-
-
-
-
80  
mA/ch  
Output current  
IOH  
-1  
SOUT  
-
mA  
V
IOL  
-
1
VDD+0.15  
0.4  
VIH  
2.5  
-0.15  
Input voltage  
Input current  
VIL  
IIH  
The terminal which  
doesn't have pull  
-1  
uA  
IIL  
1
up/pull down resistance  
Clock frequency  
Latch pulse width  
Clock pulse width  
fCLK  
-
-
-
-
25  
-
MHz  
ns  
tw LAT  
tw CLK  
Cascade connected  
IOUT= 2 ~ 80 mA  
50  
20  
-
ns  
Enable pulse width  
**** Note 4  
tw EN  
200  
10  
5
-
-
-
-
-
-
ns  
ns  
ns  
ns  
Setup time  
for clock terminal  
t SETUP  
t HOLD  
t SETUP  
1
Hold time  
for clock terminal  
Setup time  
for latch terminal  
2
5
NOTE4:  
When the pulse of the “Lo” level is inputted to the EN terminal held in the “Hi” level.  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
ELECTRICAL CHARACTERISTICS  
( VDD = 3 V ~ 5.5 V, Topr = 25 °C unless otherwise noted.)  
Characteristics  
Symbol  
Condition  
Min  
Typ  
Max  
5.5  
Unit  
V
Supply voltage  
VDD  
Normal operation  
3.0  
-
IOUT  
IOUT  
IOUT  
IOUT  
1
2
3
4
VOUT=0.4V,VDD=3.3V  
REXT  
910 ohm  
REXT  
=
20  
20  
75  
75  
VOUT=0.4V,VDD=5V  
VOUT=0.7V,VDD=3.3V  
VOUT=0.7V,VDD=5V  
VOUT=0.4V,  
Output current  
mA  
=
250 ohm  
dIOUT  
1
Output current  
REXT=*** ohm  
%
mA  
V
All output on  
-
-
+/-1  
+/-3  
1
error between bits  
VOUT=0.4V,  
dIOUT  
IOZ  
2
REXT=*** ohm  
Output leakage  
Current Input voltage  
VOUT= 6.5V  
-
IOL = +1 mA, VDD = 3.3V  
IOL = +1 mA, VDD = 5V  
IOH = - 1 mA, VDD = 3.3V  
IOH = +1 mA,VDD = 5V  
-
-
-
-
-
0.3  
0.3  
-
VOL  
VOH  
SOUT terminal  
Voltage  
-
VDD -0.4  
VDD -0.4  
-
Output current  
%/V  
%/VDD  
When VDD is changed 3V upto 5.5V  
-
-1  
-5  
supply voltage  
regulation  
Pull up resistor  
R(UP)  
ENABLE terminal  
LATCH terminal  
.
200  
Pull down resistor  
R(DOWN)  
IDD(OFF)  
1
REXT=Open, VOUT=15V  
-
0.1  
3.5  
6
0.5  
5
IDD(OFF)  
2
3
REXT=910 Ω  
REXT=250 Ω  
All output off,  
VOUT=15V  
.1  
.4  
IDD(OFF)  
9
All output on,  
VOUT=0.7V  
REXT=910 Ω  
-
-
-
-
-
-
-
-
TBD  
TBD  
TBD  
TBD  
mA  
IDD(ON)  
1
Supply current  
Topr = -40 °C,  
Same as the avobe.  
All output ON,  
VOUT=0.7V  
Topr = -40 °C,  
Same as the avobe.  
REXT=250Ω  
IDD(ON)  
2
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
SWITCHING CHARACTERISTICS  
(Topr = 25 °C, unless otherwise noted )  
Characteristics  
Symbol  
Condition  
CLK-OUT0, LAT = ”Hi”, EN = ”Lo”  
LAT-OUT0, EN = ”Lo”  
EN-OUT0, LAT= ”Hi”  
Min  
Typ  
50  
50  
50  
-
Max  
100  
100  
100  
-
Unit  
tpLH  
tpLH  
tpLH  
1
2
3
-
-
-
tpLH  
CLK-SOUT  
5
-
Propagation delay  
tpHL  
tpHL  
tpHL  
1
CLK-OUT0, LAT = “Hi”, EN = ”Lo”  
LAT-OUT0, EN = ”Lo”  
EN-OUT0, LAT = ”Hi”  
CLK-SOUT  
50  
50  
50  
-
100  
100  
100  
-
ns  
2
3
-
-
tpLH  
tor  
5
40  
40  
-
Output rise time  
Output fall time  
Voltage waveform 10%~90%  
Voltage waveform 90%~10%  
85  
70  
-
150  
150  
1
tof  
Slow CLK rise time  
Slow CLKfall time  
tr range 10%~90%  
Cascade connected  
us  
ns  
ns  
tf range 90%~10%  
-
-
1
tDLY(on)1  
tDLY(off)1  
tDLY(on)2  
tDLY(off)2  
15  
15  
225  
225  
OUT0 ~ OUT1  
OUT0 ~ OUT15  
Output skew  
by delay circuit  
100  
100  
500  
500  
Condition : (Refer to test circuit)  
Topr = 25 degree, VDD=VIH=3.3V and 5V, VOUT= 0.7 V, VIL= 0 V,REXT= 910 ohm,  
VL = 3 V, RL= 120 ohms,CL = 10.5 pF  
NOTE5 :  
If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to  
achieve the timing required for data transfer. Please consider the timings carefully.  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
OUTPUT DELAY CIRCUIT  
The connection of the delay to decrease switching noise : Delay circuit for OUT0 ~ OUT15  
EN  
OUT0  
x 1  
OUT01  
Delay  
x15  
OUT15  
Delay  
Delay  
The total current waveform and each voltage waveform  
EN  
The total current  
of Out0 ~ Out15.  
01  
Out 00  
07  
15  
Out 00 01  
07  
15  
50%  
50%  
a delay time  
Total delay of waveform when turn on.  
Total delay of waveform when turn off.  
The delay circuit is put on the output, and the level of the noise will be decreaced.  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
TEST CIRCUIT  
IDD  
VDD  
VIH,VIL  
RL  
ENABLE  
CLOCK  
OUT0  
Function  
Generator  
CL  
LATCH  
IOL  
OUT15  
SERIAL-IN  
R-EXT  
SERIAL-OUT  
VL  
GND  
Logic input waveform  
Iref  
CL  
V
=V =3.3V  
IH  
DD  
V =0V  
IL  
tr = tf = 10ns  
(10% to 90%)  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
TIMING WAVEFORM  
1. CLK ,SIN, SOUT  
twCLK  
CLK  
SIN  
50%  
50%  
t SETUP  
1
50%  
50%  
t HOLD  
SOUT  
50%  
tpLH / tpHL  
2. CLK, SIN , LAT, EN, OUTn  
CLK  
SIN  
50%  
t SETUP  
2
50%  
3
50%  
50%  
LAT  
tw LAT  
tw EN  
tSETUP  
50%  
EN  
OUTn  
50%  
tpLH1 / tpHL  
1
tpLH2 / tpHL  
2
tpLH3 / tpHL  
3
3. OUTn  
90%  
90%  
OUTn (current waveform)  
10%  
10%  
tof  
tor  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
OUTPUT CURRENT vs DUTY (Turn on Rate)  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
NOTE6 :  
Operating is likely to become unstable due to the electromagnetic inductive load of wiring and so on.  
Recommend that adjoins and arranged so far as device and LED are possible.  
Damage by the over-voltage is likely to be suffered in LED and the output by over voltage's occurring  
due to the inductance between LEDs from the output terminal.  
There is only one GND terminal in this device.  
When the inductance of the GND line resistance and so on are big.  
It is likely to operate faultily by the GND noise when output switchings by the circuit board pattern  
and wiring.  
And, it is necessary for the REXT terminal to connect it in the GND line which became stable through  
the resistor.  
Vibration is likely to occur for the output wave form when GND was unstable and capacity  
(beyond 50pF) was added.  
Therefore, be fully careful of the circuit board pattern layout and wiring from the controller.  
This application circuit is a reference example, and it doesn't assure operating in all the conditions.  
Be sure to carry out operating confirmation.  
This device doesn't build in the protection circuit of over-voltage, over-current and over-temperature.  
Carry it out on the control side when protection is necessary.  
Device is likely to destroy it when it short-circuits between the output terminals to each power supply.  
Be fully careful of output terminal, each power supply (VDD, VLED) and the design of the GND line.  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
PACKAGE DIMMENSION : SSOP24-P-300-1.00B  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
PACKAGE DIMMENSION : SSOP24-150-0.635  
UNIT : Inch  
TENTATIVE  
24  
13  
1
12  
0.0325 REF  
0.008 ~ 0.012  
0.025  
0.337  
~0.344  
2005-05-19 (Ver.03)  
TOSHIBA  
TCA62746FG/FNAG  
TENTATIVE  
About solderability, following conditions were confirmed  
Solderability  
(1) Use of Sn-63Pb solder Bath  
solder bath temperature 230°C  
dipping time 5 seconds  
the number of times once  
use of R-type flux  
(2) Use of Sn-3.0Ag-0.5Cu solder Bath  
solder bath temperature 245°C  
dipping time 5 seconds  
the number of times once  
use of R-type flux  
000707EBA  
RESTRICTIONS ON PRODUCT USE  
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor  
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical  
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety  
in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such  
TOSHIBA products could cause loss of human life, bodily injury or damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as  
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and  
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability  
Handbook” etc..  
The TOSHIBA products listed in this document are intended for usage in general electronics applications  
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,  
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires  
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or  
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or  
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,  
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this  
document shall be made at the customer’s own risk.  
The products described in this document are subject to the foreign exchange and foreign trade laws.  
The information contained herein is presented only as a guide for the applications of our products. No  
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other  
rights of the third parties which may result from its use. No license is granted by implication or otherwise under any  
intellectual property or other rights of TOSHIBA CORPORATION or others.  
The information contained herein is subject to change without notice.  
2005-05-19 (Ver.03)  

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