TCA6408A-Q1 [TI]
具有中断输出、复位和配置寄存器的汽车类 8 位转换 I2C 和 SMBus I/O 扩展器;
| 型号： | TCA6408A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有中断输出、复位和配置寄存器的汽车类 8 位转换 I2C 和 SMBus I/O 扩展器 |
| 文件： | 总41页 (文件大小：1518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCA6408A-Q1
ZHCSFH3A –SEPTEMBER 2016 –REVISED FEBRUARY 2023
TCA6408A-Q1 具有中断输出的低电压8 位I2C 和SMBus I/O 扩展器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准
• 汽车信息娱乐系统
• 高级驾驶员辅助系统(ADAS)
• 汽车车身电子设备
• HEV、EV 和动力总成
• 工业、工厂和楼宇自动化
• 测试与测量
– 温度等级1：–40°C 至+125°C，TA
• 功能安全型
– 可提供用于功能安全系统设计的文档
• I2C 至并行端口扩展器
• 工作电源电压范围为1.65 V 至3.6 V
• 支持1.8V、2.5V、3.3V I2C 总线和P 端口之间进
行双向电平转换和GPIO 扩展
• 低待机电流消耗
• 400kHz 快速I2C 总线
• 硬件地址引脚，允许在同一I2C/SMBus 总线上支持
两个TCA6408A-Q1 器件
• EPOS
3 说明
TCA6408A-Q1 是一款 16 引脚器件，可为两线双向
I2C 总线（或 SMBus）协议提供 8 位通用并行输入/输
出 (I/O) 扩展。在器件运行过程中，I2C 总线侧 (VCCI
)
和 P 端口侧 (VCCP) 均可由电压介于 1.65V 至 3.6V 之
间的电源供电。这使得 TCA6408A-Q1 能够在
SDA/SCL 侧（电源电平在此逐渐降低以节省功率）与
下一代微处理器和微控制器相连。与微处理器和微控制
器的降压电源相比，部分 PCB 组件（例如 LED）仍由
高电压电源供电。
• 低电平有效复位(RESET) 输入
• 开漏低电平有效中断(INT) 输出
• 输入和输出配置寄存器
• 极性反转寄存器
• 内部上电复位
• 加电时所有通道均被配置为输入
• 加电时无干扰
• SCL 和SDA 输入端装有噪声滤波器
• 具有最大高电流驱动能力的锁存输出，适用于直接
驱动LED
该器件支持 100kHz（标准模式）和 400kHz（快速模
式）时钟频率。当开关、传感器、按钮、LED、风扇等
设备需要额外使用I/O 时，I/O 扩展器（如TCA6408A-
Q1）可提供简易解决方案。
• 锁断性能达100mA，符合AEC Q100-004
• 施密特触发操作支持在SCL 和SDA 输入端实现缓
慢输入转换并提升开关噪声抗扰度
• ESD 保护
封装信息
封装(1)
封装尺寸（标称值）
器件型号
TCA6408A-Q1
TSSOP (16)
5.00mm × 4.40mm
– 2000V 人体放电模型(Q100-002)
– 1000V 带电器件模型(Q100-011)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VCCI
VCCP
Peripheral
Devices
SDA
SCL
P0
P1
P2
P3
I2C or SMBus Controller
ꢀꢁRESET, EN or
INT
(e.g. Processor)
RESET
Control Inputs
ꢀꢁINT or status
outputs
ꢀꢁLEDs
ꢀꢁKeypad
TCA6408A-Q1
P4
P5
P6
P7
ADDR
GND
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS234
TCA6408A-Q1
ZHCSFH3A –SEPTEMBER 2016 –REVISED FEBRUARY 2023
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Table of Contents
8.2 Functional Block Diagrams....................................... 17
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
8.5 Programming............................................................ 20
8.6 Register Map.............................................................24
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Application.................................................... 27
9.3 Power Supply Recommendations.............................30
9.4 Layout....................................................................... 31
10 Device and Documentation Support..........................33
10.1 Receiving Notification of Documentation Updates..33
10.2 商标.........................................................................33
10.3 静电放电警告.......................................................... 33
10.4 术语表..................................................................... 33
11 支持资源........................................................................ 33
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 Reset Timing Requirements........................................7
6.8 Switching Characteristics............................................8
6.9 Typical Characteristics................................................9
7 Parameter Measurement Information..........................12
8 Detailed Description......................................................16
8.1 Overview...................................................................16
Information.................................................................... 33
4 Revision History
Changes from Revision * (September 2016) to Revision A (February 2023)
Page
• 将提到I2C 的旧术语实例通篇更改为控制器和目标.............................................................................................1
• 添加了特性：符合面向汽车应用的AEC-Q100 标准........................................................................................... 1
• Added the HBM and CDM ESD classification levels.......................................................................................... 4
• Added paragraph: "Ramping up the device VCCP" to Power-On Reset Requirements ....................................30
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5 Pin Configuration and Functions
V
ꢀ
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
ꢀ
CCI
CCP
ADDR
RESET
P0
SDA
SCL
INT
P7
P1
P2
P6
P3
P5
GND
P4
Not to scale
图5-1. PW Package, 16-Pin TSSOP
(Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
ADDR
NO.
2
I
Address input. Connect directly to VCCP or ground
Ground
GND
INT
8
—
13
O
Interrupt output. Connect to VCCI through a pull-up resistor
P-port input-output (push-pull design structure).
At power on, P0 is configured as an input
P0
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
P-port input-output (push-pull design structure).
At power on, P1 is configured as an input
P1
P-port input-output (push-pull design structure).
At power on, P2 is configured as an input
P2
6
P-port input-output (push-pull design structure).
At power on, P3 is configured as an input
P3
7
P-port input-output (push-pull design structure).
At power on, P4 is configured as an input
P4
9
P-port input-output (push-pull design structure).
At power on, P5 is configured as an input
P5
10
11
12
3
P-port input-output (push-pull design structure).
At power on, P6 is configured as an input
P6
P-port input-output (push-pull design structure).
At power on, P7 is configured as an input
P7
Active-low reset input. Connect to VCCI through a pull-up resistor, if no active
connection is used
RESET
SCL
SDA
14
15
I
Serial clock bus. Connect to VCCI through a pull-up resistor
Serial data bus. Connect to VCCI through a pull-up resistor
I/O
Supply voltage of I2C bus. Connect directly to the VCC of the external I2C
controller. Provides voltage level translation
VCCI
1
—
—
VCCP
16
Supply voltage of TCA6408A-Q1 for P-ports
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (see (1)
)
MIN
MAX
UNIT
V
VCCI
VCCP
VI
Supply voltage for I2C pins
Supply voltage for P-ports
Input voltage(2)
3.6
3.6
3.6
3.6
±20
±20
±20
±20
50
–0.5
–0.5
–0.5
–0.5
V
V
VO
Output voltage(2)
V
IIK
Input clamp current
Output clamp current
ADDR, RESET, SCL
VI < 0
mA
mA
IOK
INT
VO < 0
P-port
SDA
VO < 0 or VO > VCCP
VO < 0 or VO > VCCI
VO = 0 to VCCP
VO = 0 to VCCI
VO = 0 to VCCP
IIOK
Input/output clamp current
mA
Continuous output low current
Continuous output low current
Continuous output high current
Continuous current through GND
Continuous current through VCCP
Continuous current through VCCI
Maximum junction temperature
Storage temperature
P-port
SDA, INT
P-port
IOL
IOH
mA
mA
25
50
200
160
10
ICC
mA
Tj(MAX)
Tstg
135
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 1C
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
CDM ESD classification level C6
±1000
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
(1)
VCCI
Supply voltage for I2C pins
Supply voltage for P-ports
SCL, SDA, INT
P-ports, ADDR, RESET
SCL, SDA
1.65
1.65
3.6
3.6
V
V
VCCP
0.7 × VCCI
0.7 × VCCI
0.7 × VCCP
VCCI
RESET
3.6
VIH
High-level input voltage
V
3.6
ADDR, P7–P0
SCL, SDA, RESET
0.3 × VCCI
0.3 × VCCP
10
–0.5
–0.5
VIL
IOH
Low-level input voltage
High-level output current
V
ADDR, P7–P0
P00-P07
mA
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Tj = 65°C
Tj = 85°C
Tj = 105°C
Tj = 125°C
Tj = 135°C
Tj = 85°C
Tj = 105°C
Tj = 125°C
Tj = 135°C
25
18
9
P00-P07
4.5
(2)
IOL
Low-level output current
3.5
6
mA
3
INT, SDA
1.8
1.5
125
Operating free-air temperature
TA
°C
–40
(1) For voltages applied above VCCI, and increase in ICC will result.
(2) The values shown apply to specific junction temperature. See the 节9.2.1.1 section on how to calculate the junction temperature.
6.4 Thermal Information
TCA6408A-Q1
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
122
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
56.4
67.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
10.8
66.5
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range, VCCI = 1.65 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
1.65 V to 3.6 V
1.65 V to 3.6 V
1.65 V to 3.6 V
1.65 V
MIN TYP(1)
MAX UNIT
VIK
Input diode clamp voltage
V
II = –18 mA
–1.2
VPORR
VPORF
Power-on reset voltage, VCCP rising(2)
Power-on reset voltage, VCCP falling(2)
VI = VCCP or GND, IO = 0
VI = VCCP or GND, IO = 0
1.2
1.5
V
V
0.6
1.2
1.8
2.6
3.3
1.0
1.7
2.5
3.2
1
2.3 V
IOH = –8 mA
3 V
3.6 V
VOH
P-port high-level output voltage
V
1.65 V
2.3 V
IOH = –10 mA
3 V
3.6 V
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6.5 Electrical Characteristics (continued)
over recommended operating free-air temperature range, VCCI = 1.65 V to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCP
1.65 V
2.3 V
3 V
MIN TYP(1)
MAX UNIT
0.45
0.25
IOL = 8 mA
0.25
3.6 V
1.65 V
2.3 V
3 V
0.23
V
VOL
P-port low-level output voltage
0.6
0.3
0.25
0.23
IOL = 10 mA
VOL = 0.4 V
3.6 V
SDA
3
IOL
1.65 V to 3.6 V
1.65 V to 3.6 V
mA
INT
3
15
SCL, SDA, RESET
ADDR
VI = VCCI or GND
VI = VCCP or GND
VI = VCCP
±0.1
μA
II
±0.1
IIH
IIL
P-port
1.65 V to 3.6 V
1.65 V to 3.6 V
2.3 V to 3.6 V
1
1
μA
μA
P-port
VI = GND
SDA,
9
5
36
VI = VCC or GND, I/O =
inputs,
fSCL = 400 kHz, No load
P-port,
Operating mode
ADDR,
1.65 V to 2.3 V
2.3 V to 3.6 V
1.65 V to 2.3 V
33
10
7
RESET
ICC
(ICCI + ICCP
μA
μA
)
SCL, SDA,
1.2
0.6
VI = VCC or GND, I/O =
inputs,
fSCL = 0 kHz, No load
P-port,
ADDR,
Standby mode
RESET
One input at VCCI –0.6 V,
Other inputs at VCCI or GND
SCL, SDA
6
6
6
10
55
80
1.65 V to 3.6 V
ΔICCI
Additional current
RESET
RESET at VCCI –0.6 V,
Other inputs at VCCI or GND
in standby mode
One input at VCCP –0.6 V,
Other inputs at VCCP or GND
P-port, ADDR
1.65 V to 3.6 V
1.65 V to 3.6 V
ΔICCP
μA
Ci
SCL
VI = VCCI or GND
VIO = VCCI or GND
VIO = VCCP or GND
7
8
7
9
10.5
8
pF
SDA
P-port
Cio
1.65 V to 3.6 V
pF
(1) All typical values are at nominal supply voltage (1.8-V, 2.5-V, or 3.3-V VCC) and TA = 25°C.
(2) When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A-Q1 in a reset condition until VCCP has
reached VPORR. At that time, the reset condition is released, and the TCA6408A-Q1 registers and I2C/SMBus state machine initialize to
their default states. After that, VCCP must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle.
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
MIN
MAX
UNIT
I2C BUS—STANDARD MODE
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
0
4
100
50
kHz
μs
μs
ns
4.7
0
tsds
tsdh
ticr
I2C serial data setup time
I2C serial data hold time
I2C input rise time
250
0
ns
ns
1000
ns
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6.6 I2C Interface Timing Requirements (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
MIN
MAX
UNIT
ns
ticf
I2C input fall time
300
300
tocf
I2C output fall time, 10-pF to 400-pF bus
I2C bus free time between Stop and Start
I2C Start or repeater Start condition setup time
I2C Start or repeater Start condition hold time
I2C Stop condition setup time
ns
tbuf
4.7
4.7
4
μs
μs
μs
μs
μs
μs
tsts
tsth
tsps
4
tvd(data)
tvd(ack)
I2C BUS—FAST MODE
Valid data time, SCL low to SDA output valid
1
1
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
fscl
tsch
tscl
tsp
I2C clock frequency
0
0.6
1.3
0
400
50
kHz
μs
μs
ns
I2C clock high time
I2C clock low time
I2C spike time
tsds
tsdh
ticr
I2C serial data setup time
I2C serial data hold time
I2C input rise time
100
0
ns
ns
20
300
300
ns
20 x (Vcc/
5.5 V)
ticf
I2C input fall time
ns
ns
20 x (Vcc/
5.5 V)
tocf
I2C output fall time, 10-pF to 400-pF bus
300
tbuf
I2C bus free time between Stop and Start
1.3
0.6
0.6
0.6
μs
μs
μs
μs
μs
μs
tsts
I2C Start or repeater Start condition setup time
I2C Start or repeater Start condition hold time
I2C Stop condition setup time
tsth
tsps
tvd(data)
tvd(ack)
Valid data time, SCL low to SDA output valid
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
1
1
6.7 Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-4)
MIN
MAX
UNIT
I2C BUS—STANDARD and FAST MODE
tW
Reset pulse duration
Reset recovery time
Time to reset
40
0
ns
ns
ns
tREC
tRESET
600
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6.8 Switching Characteristics
over recommended operating free-air temperature range, CL ≤100 pF (unless otherwise noted) (see 图7-1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
I2C BUS—STANDARD and FAST MODE
tiv
Interrupt valid time
Interrupt reset delay time
Output data valid
P-Port
SCL
INT
INT
4
4
μs
μs
ns
tir
tpv
tps
tph
SCL
400
P7–P0
SCL
Input data setup time
Input data hold time
P-Port
P-Port
0
ns
SCL
300
ns
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6.9 Typical Characteristics
TA = 25°C (unless otherwise noted)
12
2
1.8
1.6
1.4
1.2
1
1.65 V
1.8 V
2.5 V
3.3 V
3.6 V
1.65 V
1.8 V
2.5 V
3.3 V
3.6 V
10
8
6
0.8
0.6
0.4
4
2
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature, TA (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature, TA (°C)
D001
D002
图6-1. Supply Current vs Temperature
图6-2. Standby Supply Current vs Temperature
10
8
16
1.8 V (-40èC)
1.8 V (125èC)
2.5 V (-40èC)
2.5 V (125èC)
3.3 V (-40èC)
3.3 V (125èC)
tr = 3 ns
tr = 150 ns
tr = 300 ns
14
12
10
8
6
6
4
4
2
2
0
30
60
90 120 150 180 210 240 270 300
tr - Rise and fall time (ns)
1.6 1.8
2
2.2 2.4 2.6 2.8
VCCP - Supply Voltage(V)
3
3.2 3.4 3.6
D003
D004
图6-3. Supply Current vs Rise and Fall Times (tr)
图6-4. Supply Current vs Supply Voltage
25
25
20
15
10
5
-40èC
25èC
-40èC
25èC
85èC
125èC
85èC
20
125èC
15
10
5
VCCP = 1.65 V
VCCP = 1.8 V
0
0
0
0.1
0.2
VOL - Output Low Voltage (V)
0.3
0.4
0.5
0.6
0
0.1
0.2
VOL - Output Low Voltage (V)
0.3
0.4
0.5
0.6
D005
D006
图6-5. I/O Sink Current vs Output Low Voltage (VCCP = 1.65 V)
图6-6. I/O Sink Current vs Output Low Voltage (VCCP = 1.8 V)
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6.9 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
25
25
20
15
10
5
-40èC
25èC
-40èC
25èC
85èC
125èC
85èC
20
125èC
15
10
5
VCCP = 2.5 V
VCCP = 3.3 V
0
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
VOL - Output Low Voltage (V)
0
0.05
0.1
0.15
0.2
0.25
VOL - Output Low Voltage (V)
0.3
0.35
0.4
D007
D008
图6-7. I/O Sink Current vs Output Low Voltage (VCCP = 2.5 V)
图6-8. I/O Sink Current vs Output Low Voltage (VCCP = 3.3 V)
25
0.3
-40èC
25èC
VCC = 1.8 V, IOL = 1 mA VCC = 1.8 V, IOL = 10 mA
VCC = 5 V, IOL = 10 mA
VCC = 5 V, IOL = 1 mA
0.25
0.2
85èC
20
125èC
15
10
5
VCCP = 3.6 V
0.15
0.1
0.05
0
0
0
0.05
0.1
0.15
0.2
0.25
VOL - Output Low Voltage (V)
0.3
0.35
0.4
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA - Temperature (èC)
D009
D010
图6-9. I/O Sink Current vs Temperature (VCCP = 3.6 V)
图6-10. I/O Low Voltage vs Temperature
18
21
18
15
12
9
-40èC
-40èC
25èC
85èC
125èC
16
25èC
85èC
125èC
14
12
VCCP = 1.65 V
10
VCCP = 1.8 V
8
6
4
2
0
6
3
0
0
0.1
0.2
Output High Voltage VCCP - VOH (V)
0.3
0.4
0.5
0.6
0
0.1
0.2
Output High Voltage VCCP - VOH (V)
0.3
0.4
0.5
0.6
D011
D012
图6-11. I/O Source Current vs Output High Voltage (VCCP = 1.65
图6-12. I/O Source Current vs Output High Voltage (VCCP = 1.8
V)
V)
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6.9 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
35
50
45
40
35
30
25
20
15
10
5
-40èC
-40èC
25èC
85èC
125èC
25èC
30
85èC
125èC
25
VCCP = 2.5 V
VCCP = 3.3 V
20
15
10
5
0
0
0
0.1
0.2
Output High Voltage VCCP - VOH (V)
0.3
0.4
0.5
0.6
0
0.1
0.2
Output High Voltage VCCP - VOH (V)
0.3
0.4
0.5
0.6
D013
D014
图6-13. I/O Source Current vs Output High Voltage (VCCP = 2.5
图6-14. I/O Source Current vs Output High Voltage (VCCP = 3.3
V)
V)
50
40
-40èC
VCCP = 1.8 V
VCCP = 5 V
45
25èC
35
85èC
125èC
40
ISOURCE = -10 mA
35
30
30
VCCP = 3.6 V
25
20
15
10
5
25
20
15
10
0
0
0.1
0.2
0.3
0.4
Output High Voltage VCCP - VOH (V)
0.5
0.6
-40 -25 -10
5
20 35 50 65 80 95 110 125
TA - Temperature (°C)
D015
D015
图6-15. I/O Source Current vs Output High Voltage (VCCP = 3.6
图6-16. I/O High Voltage vs Temperature
V)
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7 Parameter Measurement Information
V
CCI
R
= 1 kW
L
SDA
DUT
C
= 50 pF
L
(see Note A)
SDA LOAD CONFIGURATION
Two Bytes for READ Input Port Register
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
R/W
Bit 0
(LSB)
ACK
(A)
Address
Bit 1
t
t
sch
scl
0.7 ´ V
CCI
SCL
SDA
0.3 ´ V
CCI
t
t
icr
vd
t
t
sts
sp
t
t
icf
t
buf
vd
t
t
sps
ocf
0.7 ´ V
CCI
0.3 ´ V
CCI
t
t
vd(ack)
icr
t
sdh
t
t
icf
sds
t
sth
Repeat Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
I2C address
1
2
Input register port data
A. CL includes probe and jig capacitance. tocf is measured with CL of 10 pF or 400 pF.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr/tf ≤30 ns.
图7-1. I2C Interface Load Circuit and Voltage Waveforms
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V
CCI
R
= 4.7 kW
L
INT
DUT
C
= 100 pF
L
(see Note A)
INTERRUPT LOAD CONFIGURATION
ACK
From Target
ACK
From Target
Start
Condition
8 Bits
(One Data Byte)
From Port
R/W
1
Target Address
Data From Port
Data 2
AD
DR
Data 1
A
1
P
S
0
1
0
3
0
4
0
0
6
A
A
1
2
5
7
8
A
t
B
B
ir
t
ir
INT
A
t
t
iv
sps
A
Data
Into
Port
Address
Data 1
Data 2
0.7 ´ V
0.3 ´ V
CCI
CCI
0.5 ´ V
SCL
INT
Pn
CCI
R/W
A
t
t
iv
ir
0.5 ´ V
INT
0.5 ´ V
CCI
CCP
View A−A
A. CL includes probe and jig capacitance.
View B−B
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr/tf ≤30 ns.
图7-2. Interrupt Load Circuit and Voltage Waveforms
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Pn
500 W
DUT
2 ´ V
CCP
C
= 50 pF
L
500 W
(see Note A)
P-PORT LOAD CONFIGURATION
0.7 ´ V
0.3 ´ V
CCP
CCI
SCL
P0
A
P3
Target
ACK
SDA
Pn
t
pv
(see Note B)
Last Stable Bit
Unstable
Data
WRITE MODE (R/W = 0)
0.7 ´ V
0.3 ´ V
CCI
CCI
SCL
P0
A
P3
t
ph
t
ps
Pn
0.5 ´ V
CCP
READ MODE (R/W = 1)
A. CL includes probe and jig capacitance.
B. tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr/tf ≤30 ns.
D. The outputs are measured one at a time, with one transition per measurement.
图7-3. P-Port Load Circuit and Timing Waveforms
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V
CCI
R
= 1 kW
L
Pn
500 W
SDA
DUT
2 ´ V
CCP
DUT
C = 50 pF
L
(see Note A)
C
= 50 pF
500 W
L
(see Note A)
SDA LOAD CONFIGURATION
P-PORT LOAD CONFIGURATION
Start
SCL
ACK or Read Cycle
SDA
0.3 ´ V
CCI
t
RESET
V
/2
/2
RESET
CCP
t
t
REC
REC
t
W
V
Pn
CCP
t
RESET
A. CL includes probe and jig capacitance.
B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr/tf ≤30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. I/Os are configured as inputs.
图7-4. Reset Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The bidirectional voltage-level translation in the TCA6408A-Q1 is provided through VCCI. VCCI must be
connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the
TCA6408A-Q1. The voltage level on the P-port of the TCA6408A-Q1 is determined by VCCP
.
The TCA6408A-Q1 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity
Inversion (active high) Register. At power on, the I/Os are configured as inputs. However, the system controller
can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or
output is kept in the corresponding Input or Output Register. The polarity of the Input Port Register can be
inverted with the Polarity Inversion Register. All registers can be read by the system controller.
The system controller can reset the TCA6408A-Q1 in the event of a timeout or other improper operation by
asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the
I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the
part.
The TCA6408A-Q1 open-drain interrupt ( INT) output is activated when any input state differs from its
corresponding Input Port Register state and is used to indicate to the system controller that an input state has
changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via
the I2C bus. Thus, the TCA6408A-Q1 can remain a simple target device.
The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low
device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices
to share the same I2C bus or SMBus.
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8.2 Functional Block Diagrams
Interrupt
Logic
13
INT
LP Filter
2
ADDR
14
15
SCL
SDA
Input
Filter
I2C Bus
Control
Shift
P7œP0
8 Bits
I/O Port
Register
1
VCCI
Write Pulse
Read Pulse
16
3
VCCP
Power-On
Reset
RESET
8
GND
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All pin numbers shown are for the PW package.
All I/Os are set to inputs at reset.
图8-1. Logic Diagram (Positive Logic)
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Data From
Shift Register
Configuration
Output Port
Register Data
Register
VCCP
Data From
D
Q
Q1
Shift Register
FF
CK
Write Configuration
Pulse
D
Q
Q
Q
FF
CK
P0 to P7
Write Pulse
Q2
ESD Protection Diode
Output
Port
Input
Port
Register
GND
Register
Input Port
D
Q
Q
Register Data
FF
CK
Read Pulse
To INT
Data From
Polarity
D
Q
Q
Shift Register
Register Data
FF
CK
Write Polarity Pulse
Polarity
Inversion
Register
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On power up or reset, all registers return to default values.
图8-2. Simplified Schematic of P0 to P7
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8.3 Feature Description
8.3.1 Voltage Translation
表 8-1 shows some common supply voltage options for voltage translation between the I2C bus and the P-ports
of the TCA6408A-Q1.
表8-1. Voltage Translation
VCCI
VCCP
(P-PORT)
(SCL AND SDA OF I2C
CONTROLLER)
(V)
(V)
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
8.3.2 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 3.6 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin must not exceed the recommended levels for proper operation.
8.3.3 Interrupt Output ( INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to VCCP or VCCI, depending on the
application. INT must be connected to the voltage source of the device that requires the interrupt information.
8.3.4 Reset Input ( RESET)
The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6408A-Q1 registers and I2C/
SMBus state machine are changed to their default state when RESET is low (0). When RESET is high (1), the
I/O levels at the P-port can be changed externally or through the controller. This input requires a pull-up resistor
to VCCI, if no active connection is used. It is not recommended to assert the RESET pin during communication
with the TCA6408A-Q1. Assertion of RESET during communication can result in data corruption.
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8.4 Device Functional Modes
8.4.1 Power-On Reset (POR)
When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6408A-Q1 in a reset
condition until VCCP has reached VPORR. At that time, the reset condition is released, and the TCA6408A-Q1
registers and I2C/SMBus state machine initialize to their default states. After that, VCCP must be lowered to
below VPORF and back up to the operating voltage for a power-reset cycle.
8.4.2 Powered-Up
When power has been applied to both VCCP and VCCI and a POR has taken place, the device is in a functioning
mode. The device is always ready to receive new requests via the I2C bus.
8.5 Programming
8.5.1 I2C Interface
The TCA6408A-Q1 has a standard bidirectional I2C interface that is controlled by a controller device in order to
be configured or read the status of this device. Each target on the I2C bus has a specific device address to
differentiate between other target devices that are on the same I2C bus. Many target devices require
configuration upon startup to set the behavior of the device. This is typically done when the controller accesses
internal register maps of the target, which have unique register addresses. A device can have one or multiple
registers where data is stored, written, or read.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I2C lines. (For further details, see the application report, I2C Pull-up Resistor Calculation
(SLVA689)). Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and
SCL lines are high after a STOP condition. See 图8-3 and 图8-4.
The following is the general procedure for a controller to access a target device:
1. If a controller wants to send data to a target:
• Controller-transmitter sends a START condition and addresses the target-receiver.
• Controller-transmitter sends data to target-receiver.
• Controller-transmitter terminates the transfer with a STOP condition.
2. If a controller wants to receive or read data from a target:
• Controller-receiver sends a START condition and addresses the target-transmitter.
• Controller-receiver sends the requested register to read to target-transmitter.
• Controller-receiver receives data from the target-transmitter.
• Controller-receiver terminates the transfer with a STOP condition.
SCL
SDA
Data Transfer
START
Condition
STOP
Condition
图8-3. Definition of Start and Stop Conditions
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SDA line stable while SCL line is high
SCL
1
0
1
1
1
ACK
0
0
0
SDA
MSB
Bit
Bit
Bit
Bit
Bit
Bit
LSB
ACK
Byte: 1010 1010 ( 0xAAh )
图8-4. Bit Transfer
表8-2 shows the interface definition for the TCA6408A-Q1 device.
表8-2. Interface Definition
BIT
BYTE
7 (MSB)
6
H
5
L
4
L
3
L
2
L
1
0 (LSB)
I2C target address
I/O data bus
L
ADDR
P1
R/ W
P0
P7
P6
P5
P4
P3
P2
8.5.2 Bus Transactions
Data must be sent to and received from the target devices, and this is accomplished by reading from or writing to
registers in the target device.
Registers are locations in the memory of the target which contain information, whether it be the configuration
information or some sampled data to send back to the controller. The controller must write information to these
registers in order to instruct the target device to perform a task.
While it is common to have registers in I2C targets, note that not all target devices will have registers. Some
devices are simple and contain only 1 register, which may be written to directly by sending the register data
immediately after the target address, instead of addressing a register. An example of a single-register device is
an 8-bit I2C switch, which is controlled via I2C commands. Since it has 1 bit to enable or disable a channel, there
is only 1 register needed, and the controller merely writes the register data after the target address, skipping the
register number.
8.5.2.1 Writes
To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well
as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the
controller then sends the register address of the register to which it wishes to write. The target will acknowledge
again, letting the controller know it is ready. After this, the controller starts sending the register data to the target
until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller
terminates the transmission with a STOP condition.
图8-5 and 图8-6 show an example of writing a single byte to a target register.
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Controller controls SDA line
Target controls SDA line
Write to one register in a device
Register Address N (8 bits)
Data Byte to Register N (8 bits)
Device (Target) Address (7 bits)
AD
DR
S
0
1
0
0
0
0
0
A
B7 B6 B5 B4 B3 B2 B1 B0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
START
R/W=0 ACK
ACK
ACK STOP
图8-5. Write to Register
<br/>
Controller controls SDA line
Target controls SDA line
Register Address 0x02 (8 bits)
Data Byte to Register 0x02 (8 bits)
Device (Target) Address (7 bits)
AD
DR
S
0
1
0
0
0
0
0
A
0
0
0
0
0
0
1
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
START
R/W=0 ACK
ACK
ACK STOP
图8-6. Write to the Polarity Inversion Register
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8.5.2.2 Reads
Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target,
the controller must first instruct the target which register it wishes to read from. This is done by the controller
starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0
(signifying a write), followed by the register address it wishes to read from. When the target acknowledges this
register address, the controller sends a START condition again, followed by the target address with the R/ W bit
set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases the
SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller
becomes the controller-receiver, and the target becomes the target-transmitter.
The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit
data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it is
ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK,
signaling to the target to halt communications and release the bus. The controller follows this up with a STOP
condition.
Read transactions that are performed without writing to the address of the device and simply supply the
command byte will result in a NACK.
图8-7 and 图8-8 show an example of reading a single byte from a target register.
Controller controls SDA line
Target controls SDA line
Read from one register in a device
Device (Target) Address (7 bits)
Register Address N (8 bits)
Device (Target) Address (7 bits)
Data Byte from Register N (8 bits)
D7 D6 D5 D4 D3 D2 D1 D0 NA
AD
AD
S
0
1
0
0
0
0
0
A
B7 B6 B5 B4
B2 B1 B0
A
Sr
0
1
0
0
0
0
1
A
P
B3
DR
DR
R/W=1
START
ACK
ACK Repeated START
ACK
NACK STOP
R/W=0
图8-7. Read from Register
1
2
3
4
5
6
7
R
1
9
SCL
SDA
Data From Port
Data 1
Target Address
Data From Port
Data 4
AD
DR
S
0
1
0
0
0
A
A
NA P
0
Start
Condition
NACK From
Controller
ACK From
Target
ACK From
Controller
Stop
Condition
R/W
Read From
Port
Data Into
Port
Data 2
Data 3
Data 4
Data 5
t
t
ps
ph
INT is cleared
by Read from Port
INT
t
Stop not needed
to clear INT
t
iv
ir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is
valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port Register).
B. This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual
data transfer from P-port (see 图8-7).
图8-8. Read from Input Port Register
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8.6 Register Map
8.6.1 Device Address
The address of the TCA6408A-Q1 is shown in 图8-9.
Target Address
AD
0
1
0
0
0
0
DR
R/W
Fixed
Programmable
图8-9. TCA6408A-Q1 Address
表8-3 shows the TCA6408A-Q1 address reference.
表8-3. Address Reference
I2C BUS TARGET ADDRESS
32 (decimal), 20 (hexadecimal)
33 (decimal), 21 (hexadecimal)
ADDR
L
H
The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte (see 表
8-4), which is stored in the Control Register in the TCA6408A-Q1. Two bits of this data byte state both the
operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that is
affected. This register can be written or read through the I2C bus. The command byte is sent only during a write
transmission. See 图8-10.
B7 B6
B5 B4 B3 B2 B1 B0
图8-10. Control Register Bits
表8-4. Command Byte
CONTROL REGISTER BITS
COMMAND BYTE
POWER-UP
DEFAULT
REGISTER
PROTOCOL
(HEX)
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
00
01
02
03
Input Port
Output Port
Read byte
xxxx xxxx
1111 1111
0000 0000
1111 1111
0
0
0
0
0
0
0
1
Read/write byte
Read/write byte
Read/write byte
0
0
0
0
0
0
1
0
Polarity Inversion
Configuration
0
0
0
0
0
0
1
1
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8.6.3 Register Descriptions
The Input Port Register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration Register. They act only on read operation. Writes to this
register have no effect. The default value (X) is determined by the externally applied logic level. Before a read
operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port
Register will be accessed next. See 表8-5.
表8-5. Register 0 (Input Port Register)
BIT
I-7
I-6
I-5
I-4
I-3
I-2
I-1
I-0
DEFAULT
X
X
X
X
X
X
X
X
The Output Port Register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration Register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See 表
8-6.
表8-6. Register 1 (Output Port Register)
BIT
O-7
O-6
O-5
O-4
O-3
O-2
O-1
O-0
DEFAULT
1
1
1
1
1
1
1
1
The Polarity Inversion Register (register 2) allows polarity inversion of pins defined as inputs by the
Configuration Register. If a bit in this register is set (written with 1), the polarity of the corresponding port pin is
inverted. If a bit in this register is cleared (written with a 0), the original polarity of the corresponding port pin is
retained. See 表8-7.
表8-7. Register 2 (Polarity Inversion Register)
BIT
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N-0
DEFAULT
0
0
0
0
0
0
0
0
The Configuration Register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See 表8-8.
表8-8. Register 3 (Configuration Register)
BIT
C-7
C-6
C-5
C-4
C-3
C-2
C-1
C-0
DEFAULT
1
1
1
1
1
1
1
1
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA6408A-Q1 has this device connected as a target to an I2C controller (processor), and the
I2C bus may contain any number of other target devices. The TCA6408A-Q1 is in a remote location from the
controller, placed close to the GPIOs to which the controller needs to monitor or control.
A typical application of the TCA6408A-Q1 operates with a lower voltage on the controller side (VCCI), and a
higher voltage on the P-port side (VCCP). The P-ports can be configured as outputs connected to inputs of
devices such as enable, reset, power select, the gate of a switch, and LEDs. The P-ports can also be configured
as inputs to receive data from interrupts, alarms, status outputs, or push buttons.
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9.2 Typical Application
图9-1 shows an application in which the TCA6408A-Q1 can be used.
VCCI
VCCP
(1.8 V)
(3.3 V)
Subsystem 1
(e.g., Alarm)
10 k
(x 4)
100 k
(x 3)
VCC
VCCI
VCCP
ALARM
(see Note D)
SCL
P0
SCL
SDA
INT
Controller
SDA
INT
RESET
RESET
GND
P1
ENABLE
TCA6408A-Q1
P2
P3
P4
P5
P6
Keypad
ADDR
GND
P7
A. Device address configured as 0100000 for this example.
B. P0 and P2–P4 are configured as inputs.
C. P1 and P5–P7 are configured as outputs.
D. Resistors are required for inputs (on P-port) that may float. If a driver to an input will never let the input float, a resistor is not needed.
Outputs (in the P-port) do not need pull-up resistors.
图9-1. Typical Application Schematic
9.2.1 Design Requirements
9.2.1.1 Calculating Junction Temperature and Power Dissipation
When designing with the TCA6408A-Q1, it is important that the 节6.3 not be violated. Many of the parameters of
this device are rated based on junction temperature. So junction temperature must be calculated in order to
verify that safe operation of the device is met. The basic equation for junction temperature is shown in 方程式1.
Tj = TA + q ´ P
(
)
JA
d
(1)
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θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in 节6.4 table.
Pd is the total power dissipation of the device, and the approximation is shown in 方程式2.
P » ICC_STATIC ´ VCC
(
+
Pd_PORT _L
+
Pd_PORT _H
)
d
å
å
(2)
方程式 2 is the approximation of power dissipation in the device. The equation is the static power plus the
summation of power dissipated by each port (with a different equation based on if the port is outputting high, or
outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by
the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these
transients to be small. They can easily be included in the power dissipation calculation by using 方程式 3 to
calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power
dissipation.
Pd_PORT _L = I ´ VOL
(
OL
)
(3)
方程式 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the
port is the VOL of the port multiplied by the current it is sinking.
Pd_PORT _H = I
(
´ V - VOH
(
CC
)
)
OH
(4)
方程式 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the
port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC
and the output voltage).
9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in 图
9-1. The LED acts as a diode, so when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC
parameter in the 节 6.5 table shows how ICC increases as VIN becomes lower than VCC. Designs that must
minimize current consumption, such as battery power applications, must consider maintaining the I/O pins
greater than or equal to VCC when the LED is off.
图 9-2 shows a high-value resistor in parallel with the LED. 图 9-3 shows VCC less than the LED supply voltage
by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VCC and prevent additional supply
current consumption when the LED is off.
VCC
LED
100 kΩ
VCC
Px
图9-2. High-Value Resistor in Parallel With LED
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3.3 V
5 V
LED
VCC
Px
图9-3. Device Supplied by a Low Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all targets on the I2C bus. The minimum pull-up resistance is a function of
V
CC, VOL,(max), and IOL as shown in 方程式5.
VCC - VOL(max)
Rp(min)
=
IOL
(5)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb as shown in 方程式6.
tr
Rp(max)
=
0.8473´C
(6)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the TCA6408A-Q1, Ci for
SCL or CIO for SDA, the capacitance of wires, connections, traces, and the capacitance of additional targets on
the bus.
9.2.3 Application Curves
25
20
15
10
5
1.8
1.6
1.4
1.2
1
Standard-mode
Fast-mode
0.8
0.6
0.4
0.2
0
VCC > 2V
VCC <= 2
0
0
0.5
1
1.5
2
2.5 3
VCC (V)
3.5
4
4.5
5
5.5
0
50
100 150 200 250 300 350 400 450
Cb (pF)
D009
D008
Standard-mode: fSCL= 100 kHz, tr = 1 µs
Fast-mode: fSCL= 400 kHz, tr= 300 nsb
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤2 V
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V
图9-4. Maximum Pull-Up Resistance (Rp(max)) vs
图9-5. Minimum Pull-Up Resistance (Rp(min)) vs
Pull-Up Reference Voltage (VCCI
Bus Capacitance (C)
)
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9.3 Power Supply Recommendations
9.3.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA6408A-Q1 can be reset to its default conditions by using the
power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.
This reset also happens when the device is powered on for the first time in an application.
Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW.
The two types of power-on reset are shown in 图9-6 and 图9-7.
VCCP
Ramp-Up
Ramp-Down
Re-Ramp-Up
tRR_GND
Time
Time to Re-Ramp
tRT
tFT
tRT
图9-6. VCCP is Lowered Below 0.2 V and then Ramped Up to VCCP
VCCP
Ramp-Down
Ramp-Up
tRR_POR50
VIN drops below POR levels
Time
Time to Re-Ramp
tFT
tRT
图9-7. VCCP is Lowered Below the POR Threshold, then Ramped Back Up to VCCP
表 9-1 specifies the performance of the power-on reset feature for TCA6408A-Q1 for both types of power-on
reset.
表9-1. Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1)
PARAMETER
MIN TYP
MAX UNIT
tFT
Fall rate
0.1
0.1
1
2000
2000
ms
ms
μs
μs
See 图9-6
See 图9-6
See 图9-6
See 图9-7
tRT
Rise rate
tRR_GND
tRR_POR50
Time to re-ramp (when VCCP drops to GND)
1
Time to re-ramp (when VCCP drops to VPOR_MIN –50 mV)
Level that VCCP can glitch down from VCCP, but not cause a
functional disruption when tVCCP_GW = 1 μs
VCCP_GH
VCCP_MV
tVCCP_GW
1.2
V
V
See 图9-8
See 图9-8
See 图9-8
The minimum voltage that VCC can glitch down to without
causing a reset (VCC_GH must not be violated)
1.5
Glitch width that does not cause a functional disruption when
tVCCP_GH = 0.5 × VCCx
10
μs
VPORF
VPORR
Voltage trip point of POR on falling VCCP
Voltage trip point of POR on rising VCCP
0.6
1
V
V
1.2
1.5
(1) Not tested. Specified by design.
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(tVCCP_GW) and height (VCCP_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. 图 9-8 and 表 9-1 provide more
information on how to measure these specifications.
VCCP
VCCP_GH
V
CCP_MV
Time
tVCCP_GW
图9-8. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPORR / VPORF is the voltage level at which the reset condition is released/
asserted and all the registers and the I2C/SMBus state machine are initialized to the default states (upon a
release of a reset condition). The voltage that the device has a reset condition asserted or released differs based
on whether VCCP is being lowered to or from 0. 图9-9 and 表9-1 provide more details on this specification.
VCCP
VPORR
VPORF
Time
POR
Time
图9-9. Power On Reset
9.4 Layout
9.4.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA6408A-Q1, common PCB layout practices must be followed, but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCCI and VCCP pins, using a larger capacitor to provide
additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency
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ripple. These capacitors must be placed as close to the TCA6408A-Q1 as possible. These best practices are
shown in 节9.4.2.
For the layout example provided in 节 9.4.2, it is possible to fabricate a PCB with only 2 layers by using the top
layer for signal routing and the bottom layer as a split plane for power (VCCI and VCCP) and ground (GND).
However, a 4-layer board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is
common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and
dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and
ground, vias are placed directly next to the surface mount component pad which needs to attach to VCCI, VCCP
,
or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also
used when a signal trace needs to be routed to the opposite side of the board, but this technique is not
demonstrated in 节9.4.2.
9.4.2 Layout Example
= Via to GND Plane
To CPU/MCU
V
V
CCP
CCI
ADDR
RST
P0
SDA
SCL
INT
P7
TCA6408A-Q1
P1
P2
P6
P3
P5
GND
P4
图9-10. Example Layout (PW Package)
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.3 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA6408AQPWRQ1
ACTIVE
TSSOP
PW
16
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
6408AQ
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCA6408A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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19-Jan-2023
Catalog : TCA6408A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA6408AQPWRQ1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
TCA6408AQPWRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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