TCA6408PW_技术文档

TCA6408

LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

FEATURES

•

Operating Power-Supply Voltage Range of

1.65 V to 5.5 V

•

5-V Tolerant I/O Ports

Active-Low Reset Input (RESET)

Open-Drain Active-Low Interrupt Output (INT)

400-kHz Fast I²C Bus

•

Allows Bidirectional Voltage-Level Translation

and GPIO Expansion Between

–

1.8-V SCL/SDA and 1.8-V, 2.5-V,

3.3-V, or 5-V P Port

Input/Output Configuration Register

Polarity Inversion Register

2.5-V SCL/SDA and 1.8-V, 2.5-V,

3.3-V, or 5-V P Port

Internal Power-On Reset

Power-Up With All Channels Configured as

Inputs

3.3-V SCL/SDA and 1.8-V, 2.5-V,

3.3-V, or 5-V P Port

•

No Glitch On Power-Up

5-V SCL/SDA and 1.8-V, 2.5-V,

3.3-V, or 5-V P Port

Noise Filter on SCL/SDA Inputs

I²C to Parallel Port Expander

Latched Outputs With High-Current Drive

Maximum Capability for Directly Driving LEDs

•

Low Standby Current Consumption of 1 µA

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Schmitt-Trigger Action Allows Slow Input

Transition and Better Switching Noise

Immunity at the SCL and SDA Inputs

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

–

V_hys= 0.18 V Typ at 1.8 V

V_hys= 0.25 V Typ at 2.5 V

V_hys= 0.33 V Typ at 3.3 V

V_hys= 0.5 V Typ at 5 V

1000-V Charged-Device Model (C101)

RGT PACKAGE

(TOP VIEW)

PW PACKAGE

(TOP VIEW)

ZXY PACKAGE

(TOP VIEW)

V_CCI

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

V_CCP

SDA

SCL

ADDR

1

5

2

3

4

16 15 14 13

RESET

SCL

INT

P7

RESET

P0

1

2

3

4

12

11

10

9

A

B

C

D

P0

P1

P2

INT

P7

P1

P6

P2

5

6

7

8

P3

P5

P4

GND

DESCRIPTION/ORDERING INFORMATION

This 8-bit I/O expander for the two-line bidirectional bus (I²C) is designed to provide general-purpose remote I/O

expansion for most microcontroller families via the I²C interface [serial clock (SCL) and serial data (SDA)].

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TCA6408

LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TCA6408RGTR

TOP-SIDE MARKING

QFN – RGT

Reel of 3000

Reel of 2500

Tube of 70

ZWP

BGA – ZXY (Pb-free)

TCA6408ZXYR

PH408

–40°C to 85°C

TCA6408PW

TSSOP – PW

PH408

Reel of 2000

TCA6408PWR

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

The major benefit of this device is its wide V_CCrange. It can operate from 1.65-V to 5.5-V on the P port side and

on the SDA/SCL side. This allows the TCA6408 to interface with next-generation microprocessors and

microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to

the dropping power supplies of microprocessors and microcontrollers, some PCB components such as LEDs

remain at a 5-V power supply.

The bidirectional voltage level translation in the TCA6408 is provided through V_CCI. V_CCIshould be connected to

the V_CCof the external SCL/SDA lines. This indicates the V_CClevel of the I²C bus to the TCA6408. The voltage

level on the P port of the TCA6408 is determined by V_CCP

.

The TCA6408 consists of one 8-bit configuration (input or output selection), input, output, and polarity inversion

(active high) register. At power on, the I/Os are configured as inputs. However, the system master can enable

the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is

kept in the corresponding input or output register. The polarity of the input port register can be inverted with the

polarity inversion register. All registers can be read by the system master.

The system master can reset the TCA6408 in the event of a timeout or other improper operation by asserting a

low in the RESET input. The power-on reset puts the registers in their default state and initializes the I²C/SMBus

state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6408 open-drain interrupt (INT) output is activated when any input state differs from its corresponding

input port register state and is used to indicate to the system master that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the

remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via

the I²C bus. Thus, the TCA6408 can remain a simple slave device.

The device P port outputs have high-current sink capabilities for directly driving LEDs while consuming low

device current.

One hardware pin (ADDR) can be used to program and vary the fixed I²C address and allow up to two devices

to share the same I²C bus or SMBus.

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TCA6408

LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

ZXY Terminal Assignments

1

P3

2

3

4

5

A

B

C

D

P2

P1

P0

INT

P7

RESET

N.C.⁽¹⁾

SCL

ADDR

V_CCI

GND

P4

N.C.⁽¹⁾

P6

V_CCP

SDA

P5

(1) N.C. – No internal connection

TERMINAL FUNCTIONS

PIN NUMBER

NAME

DESCRIPTION

TSSOP

(PW)

QFN

(RGT)

BGA

(ZXY)

Supply voltage of I²C bus. Connect directly to the V_CCof the external I²C master.

Provides voltage level translation.

1

2

3

15

16

1

B5

A5

A4

V_CCI

ADDR

RESET

Address input. Connect directly to V_CCPor ground.

Active-low reset input. Connect to V_CCPthrough a pullup resistor, if no active

connection is used.

P port input/output (push-pull design structure). At power on, P0 is configured as

an input.

4

5

6

2

3

4

B3

A3

A2

P0

P1

P2

P port input/output (push-pull design structure). At power on, P1 is configured as

an input.

P port input/output (push-pull design structure). At power on, P2 is configured as

an input.

P port input/output (push-pull design structure). At power on, P3 is configured as

an input.

7

8

9

5

6

7

A1

B1

C1

P3

GND

P4

Ground

P port input/output (push-pull design structure). At power on, P4 is configured as

an input.

P port input/output (push-pull design structure). At power on, P5 is configured as

an input.

10

11

12

8

9

D1

D2

D3

P5

P6

P7

P port input/output (push-pull design structure). At power on, P6 is configured as

an input.

P port input/output (push-pull design structure). At power on, P7 is configured as

an input.

10

13

14

15

16

11

12

13

14

C3

D4

D5

C5

INT

SCL

SDA

V_CCP

Interrupt output. Connect to V_CCIthrough a pullup resistor.

Serial clock bus. Connect to V_CCIthrough a pullup resistor.

Serial data bus. Connect to V_CCIthrough a pullup resistor.

Supply voltage of TCA6408 for P port.

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TCA6408

LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

Voltage Translation

Table 1 shows how to set up V_CClevels for the necessary voltage translation between the I²C bus and the

TCA6408.

Table 1. Voltage Translation

V_CCI

V_CCP

(P Port)

(V)

(SCL and SDA of I²C master)

(V)

1.8

2.5

3.3

5

1.8

2.5

3.3

5

1.8

2.5

3.3

5

1.8

2.5

3.3

5

1.8

2.5

3.3

5

4

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TCA6408

LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

LOGIC DIAGRAM (POSITIVE LOGIC)

Interrupt

Logic

13

INT

LP Filter

2

ADDR

14

15

SCL

SDA

Input

Filter

I²C Bus

Control

Shift

Register

P7–P0

8 Bits

I/O Port

1

V_CCI

Write Pulse

Read Pulse

16

3

V_CCP

Power-On

Reset

RESET

8

GND

A. All pin numbers shown are for the PW package.

B. All I/Os are set to inputs at reset.

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SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

Simplified Schematic of P0 to P7

Data From

Shift Register

Configuration

Output Port

Register Data

Register

V_CCP

Data From

Shift Register

D

Q

Q1

FF

C_K

Write Configuration

Pulse

D

Q

FF

C_K

P0 to P7

Write Pulse

Q2

ESD Protection Diode

Output

Port

Register

Input

Port

Register

GND

Input Port

D

Q

Register Data

FF

Read Pulse

C_K

To INT

Data From

Shift Register

Polarity

D

Q

Register Data

FF

C_K

Write Polarity Pulse

Polarity

Inversion

Register

A. On power up or reset, all registers return to default values.

I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The

input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In

this case, there are low impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin should not exceed the recommended levels for proper operation.

I²C Interface

The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be

connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

I²C communication with this device is initiated by a master sending a start condition, a high-to-low transition on

the SDA input/output, while the SCL input is high (see Figure 1). After the start condition, the device address

byte is sent, MSB first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address input (ADDR) of the slave device must

not be changed between the start and the stop conditions.

On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 2).

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WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

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SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop

conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before

the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK

clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see

Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,

the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold

times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)

after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line

high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.

SDA

SCL

S

P

Stop Condition

Start Condition

Figure 1. Definition of Start and Stop Conditions

SDA

SCL

Data Line

Change

Figure 2. Bit Transfer

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

1

2

8

9

S

Clock Pulse for

Acknowledgment

Start

Condition

Figure 3. Acknowledgment on the I²C Bus

7

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LOW-VOLTAGE 8-BIT I²C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

www.ti.com

SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

Interface Definition

BIT

BYTE

7 (MSB)

6

H

5

L

4

L

3

L

2

L

1

0 (LSB)

R/W

I²C slave address

I/O data bus

L

ADDR

P1

P7

P6

P5

P4

P3

P2

P0

Device Address

The address of the TCA6408 is shown in Figure 4.

Slave Address

AD

0

1

0

DR

R/W

Fixed

Programmable

Figure 4. TCA6408 Address

Address Reference

ADDR

I²C BUS SLAVE ADDRESS

32 (decimal), 20 (hexadecimal)

33 (decimal), 21 (hexadecimal)

L

H

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Control Register and Command Byte

Following the successful acknowledgement of the address byte, the bus master sends a command byte, which

is stored in the control register in the TCA6408. Two bits of this data byte state the operation (read or write) and

the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be

written or read through the I²C bus. The command byte is sent only during a write transmission.

B7 B6

B5 B4 B3 B2 B1 B0

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND

BYTE

POWER-UP

DEFAULT

REGISTER

PROTOCOL

B7

B6

B5

B4

B3

B2

B1

B0

(HEX)

0

1

0

1

0

1

00

Input Port

Read byte

xxxx xxxx⁽¹⁾

1111 1111

0000 0000

1111 1111

01

Output Port

Read/write byte

02

Polarity Inversion Read/write byte

Configuration Read/write byte

03

(1) Undefined

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Register Descriptions

The input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the configuration register. They act only on read operation. Writes to this

register have no effect. The default value (X) is determined by the externally applied logic level. Before a read

operation, a write transmission is sent with the command byte to indicate to the I²C device that the input port

register will be accessed next.

Register 0 (Input Port Register)

BIT

I-7

X

I-6

X

I-5

X

I-4

X

I-3

X

I-2

X

I-1

X

I-0

X

DEFAULT

The output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.

Register 1 (Output Port Register)

BIT

O-7

1

O-6

1

O-5

1

O-4

1

O-3

1

O-2

1

O-1

1

O-0

1

DEFAULT

The polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the configuration

register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in

this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Register 2 (Polarity Inversion Register)

BIT

N-7

0

N-6

0

N-5

0

N-4

0

N-3

0

N-2

0

N-1

0

N-0

0

DEFAULT

The configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output.

Register 3 (Configuration Register)

BIT

C-7

1

C-6

1

C-5

1

C-4

1

C-3

1

C-2

1

C-1

1

C-0

1

DEFAULT

Power-On Reset

When power (from 0 V) is applied to V_CCP, an internal power-on reset holds the TCA6408 in a reset condition

until V_CCPhas reached V_POR. At that time, the reset condition is released, and the TCA6408 registers and

I²C/SMBus state machine initialize to their default states. After that, V_CCPmust be lowered to below 0.2 V and

back up to the operating voltage for a power-reset cycle.

Reset Input (RESET)

The RESET input can be asserted to intialize the system while keeping V_CCPat its operating level. A reset can

be accomplished by holding the RESET pin low for a minimum of t_W. The TCA6408 registers and I²C/SMBus

state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels

at the P port can be changed externally or through the master. This input requires a pullup resistor to V_CCP, if no

active connection is used.

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SCPS151C–FEBRUARY 2007–REVISED JUNE 2007

Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t_iv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read

mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a

stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock

pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the

I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the

state of the pin does not match the contents of the input port register.

The INT output has an open-drain structure and requires a pullup resistor to V_CCPor V_CCIdepending on the

application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6408,

then the INT pin has to be connected to V_CCI. If not, the INT pin can be connected to V_CCP

.

Bus Transactions

Data is exchanged between the master and TCA6408 through write and read commands.

Writes

Data is transmitted to the TCA6408 by sending the device address and setting the least-significant bit to a logic

0 (see Figure 4 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one

write transmission.

SCL

1

2

3

4

5

6

7

8

9

Slave Address

Command Byte

Data to Port

Data 1

AD

DR

SDA

S

0

1

0

A

0

1

A

P

Start Condition

R/W ACK From Slave

ACK From Slave

Write to Port

Data Out

Data 1 Valid

From Port

t_pv

Figure 6. Write to Output Port Register

<br/>

SCL

1

2

3

4

5

6

7

8

0

9

Slave Address

Command Byte

Data to Register

Data

AD

DR

1

SDA

S

0

1

0

A

0

1/0

A

P

Start Condition

R/W ACK From Slave

ACK From Slave

Figure 7. Write to Configuration or Polarity Inversion Registers

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Reads

The bus master first must send the TCA6408 address with the least-significant bit set to a logic 0 (see Figure 4

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the TCA6408 (see Figure 8 and Figure 9).

Data is clocked into the register on the rising edge of the ACK clock pulse.

ACK From

Master

ACK From

Slave

ACK From

Slave

ACK From

Slave

Data from Register

Slave Address

AD

DR

AD

DR

Command Byte

S

0

1

0

A

S

0

1

0

1

A

Data

A

First byte

R/W

At this moment, master-transmitter

becomes master-receiver, and

slave-receiver becomes

slave-transmitter

NACK From

Data from Register

Master

Data

P

NA

Last Byte

Figure 8. Read From Register

<br/>

1

2

3

4

5

6

7

8

0

9

SCL

SDA

Data From Port

Data 1

Slave Address

Data From Port

Data 4

AD

DR

S

0

1

0

A

NA

P

Start

Condition

NACK From

Master

ACK From

Slave

ACK From

Master

Stop

R/W

Condition

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

t_ph

t_ps

INT

t_iv

t_ir

A. Transfer of data can be stopped at any time by a stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read

input port register).

B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from P port (see Figure 8).

Figure 9. Read Input Port Register

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Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

6.5

UNIT

V_CCI

V_CCP

V_I

Supply voltage range

Input voltage range⁽²⁾

Output voltage range⁽²⁾

Input clamp current

V

6.5

±20

50

V

V_O

V

I_IK

ADDR, RESET, SCL

V_I< 0

mA

I_OK

Output clamp current

INT

V_O< 0

P Port

SDA

V_O< 0 or V_O> V_CCP

V_O< 0 or V_O> V_CCI

V_O= 0 to V_CCP

V_O= 0 to V_CCI

V_O= 0 to V_CCP

I_IOK

Input/output clamp current

Continuous output low current

Continuous output high current

Continuous current through GND

Continuous current through V_CCP

Continuous current through V_CCI

P Port

SDA, INT

P Port

I_OL

I_OH

25

50

200

160

10

I_CC

PW package

RGT package

ZXY package

108

53

θ_JA

Package thermal impedance⁽³⁾

°C/W

°C

193

150

T_stg

Storage temperature range

–65

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions

MIN

1.65

MAX

5.5

UNIT

V_CCI

Supply voltage

V

V_CCP

1.65

5.5

SCL, SDA

0.7 × V_CCI

0.7 × V_CCP

–0.5

5.5

V_IH

V_IL

High-level input voltage

Low-level input voltage

V

ADDR, P7–P0, RESET

SCL, SDA

5.5

0.3 × V_CCI

ADDR, P7–P0, RESET

P7–P0

–0.5 0.3 × V_CCP

I_OH

I_OL

T_A

High-level output current

Low-level output current

Operating free-air temperature

10

25

mA

°C

P7–P0

–40

85

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Electrical Characteristics

over recommended operating free-air temperature range, V_CCI= 1.65 V to 5.5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CCP

1.65 V to 5.5 V

1.65 V

MIN

TYP⁽¹⁾

MAX

UNIT

V

V_IK

Input diode clamp voltage I_I= –18 mA

Power-on reset voltage⁽²⁾V_I= V_CCPor GND, I_O= 0

–1.2

V_POR

1

1.4

V

1.2

1.8

2.6

4.1

1.1

1.7

2.5

4.0

2.3 V

I_OH= –8 mA

3 V

4.5 V

P port high-level output

voltage

V_OH

V

1.65 V

2.3 V

I_OH= –10 mA

3 V

4.5 V

1.65 V

0.45

0.25

0.2

2.3 V

I_OL= 8 mA

3 V

4.5 V

P port low-level output

voltage

V_OL

V

1.65 V

0.6

2.3 V

0.3

I_OL= 10 mA

3 V

0.25

0.2

4.5 V

SDA

V_OL= 0.4 V

1.65 V to 5.5 V

3

I_OL

mA

INT

V_OL= 0.4 V

15

SCL, SDA

ADDR, RESET

P port

V_I= V_CCIor GND

V_I= V_CCPor GND

V_I= V_CCP

±0.1

1

I_I

1.65 V to 5.5 V

µA

I_IH

I_IL

µA

P port

V_I= GND

1

V_Ion SDA = V_CCIor GND,

V_Ion P port, ADDR and

RESET = V_CCPor GND,

I_O= 0, I/O = inputs,

3.6 V to 5.5 V

2.3 V to 3.6 V

10

20

15

SDA,

6.5

Operating

mode

P Port,

ADDR,

RESET

1.65 V to 2.3 V

4

9

f_SCL= 400 kHz

V_Ion SDA = V_CCIor GND,

V_Ion P port, ADDR and

RESET = V_CCPor GND,

I_O= 0, I/O = inputs,

3.6 V to 5.5 V

2.3 V to 3.6 V

2.5

1.6

5

SDA,

3.8

Operating

mode

P Port,

ADDR,

RESET

I_CC

(I_CCI+ I_CCP

µA

)

1.65 V to 2.3 V

1

2.3

f_SCL= 100 kHz

V_Ion SCL and SDA = V_CCIor

SCL, SDA, GND,

3.6 V to 5.5 V

2.3 V to 3.6 V

0.2

0.1

1

0.6

Standby

mode

P Port,

ADDR,

RESET

V_Ion P Port, ADDR and

RESET = V_CCPor GND,

I_O= 0, I/O = inputs,

f_SCL= 0

1.65 V to 2.3 V

1.65 V to 5.5 V

0.1

0.4

25

60

One input at V_CCI– 0.6 V,

Other inputs at V_CCIor GND

∆I_CCI

SCL, SDA

µA

Additional

current in

Standby

mode

P Port,

ADDR,

RESET

One input at V_CCP– 0.6 V,

Other inputs at V_CCPor GND

∆ I_CCP

C_i

SCL

V_I= V_CCIor GND

V_IO= V_CCIor GND

V_IO= V_CCPor GND

1.65 V to 5.5 V

6

7

8

pF

SDA

C_io

P Port

7.5

8.5

(1) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V V_CC) and T_A= 25°C.

(2) When power (from 0 V) is applied to V_CCP, an internal power-on reset holds the TCA6408 in a reset condition until V_CCPhas reached

V_POR. At that time, the reset condition is released, and the TCA6408 registers and I²C/SMBus state machine initialize to their default

states. After that, V_CCPmust be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.

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I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

MIN

0

UNIT

kHz

MIN

0

MAX

400

f_scl

I²C clock frequency

100

t_sch

t_scl

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

I²C input rise time

I²C input fall time

I²C output fall time; 10 pF to 400 pF bus

I²C bus free time between Stop and Start

I²C Start or repeater Start condition setup time

I²C Start or repeater Start condition hold time

I²C Stop condition setup time

Valid data time; SCL low to SDA output valid

4

0.6

µs

ns

µs

4.7

0

1.3

t_sp

50

0

50

t_sds

t_sdh

t_icr

250

0

100

0

(1)

1000

300

20 + 0.1C_b

300

(1)

t_icf

20 + 0.1C_b

t_ocf

t_buf

t_sts

300

4.7

4

1.3

0.6

t_sth

t_sps

t_vd(data)

4

1

Valid data time of ACK condition; ACK signal from SCL low to

SDA (out) low

t_vd(ack)

µs

(1) C_b= total capacitance of one bus line in pF

Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

UNIT

MIN

4

MAX

MIN

4

MAX

t_W

Reset pulse duration

Reset recovery time

Time to reset⁽¹⁾

ns

t_REC

t_RESET

0

600

(1) Minimum time for SDA to become high or minimum time to wait before doing a START

Switching Characteristics

over recommended operating free-air temperature range, C_L≤ 100 pF (unless otherwise noted) (see Figure 10)

STANDARD

FAST MODE

MODE

I²C BUS

PARAMETER

FROM

TO

UNIT

MIN

MAX

4

MIN

MAX

4

t_iv

Interrupt valid time

Interrupt reset delay time

Output data valid

P Port

SCL

INT

µs

ns

t_ir

4

t_pv

t_ps

t_ph

SCL

P7–P0

SCL

400

Input data setup time

Input data hold time

P Port

0

SCL

300

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TYPICAL CHARACTERISTICS

T_A= 25°C (unless otherwise noted)

SUPPLY CURRENT

vs

TEMPERATURE

STANDBY SUPPLY CURRENT

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

vs

TEMPERATURE

18

16

14

12

10

8

120

100

80

60

40

20

0

18

16

14

12

10

8

f_SCL= 400 kHz

SCL = V_CC

All I/Os unloaded

V_CC= 5.0 V

V_CC= 3.3 V

6

4

V_CC= 2.5 V

V_CC= 1.8 V

V_CC= 3.3 V

2

6

0

4

V_CC= 2.5 V

V_CC= 1.8 V

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Supply Voltage, V_CC(V)

2

0

–40 –15

10

35

60

85

–40 –15

10

35

60

85

Temperature,T_A(°C)

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

30

25

20

15

10

5

60

50

40

30

20

10

70

V_CC= 1.8 V

V_CC= 3.3 V

V_CC= 2.5 V

T_A= –40°C

60

50

40

30

20

10

0

T_A= –40°C

T_A= 25°C

T_A= 85°C

T_A= 25°C

T_A= 85°C

0

0.0 0.1 0.2 0.3 0.4 0.5 0.6

Output Low Voltage, V_OL(V)

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.1 0.2

0.3

0.4

0.5

0.6

Output Low Voltage, V_OL(V)

I/O SINK CURRENT

vs

OUTPUT LOW VOLTAGE

I/O LOW VOLTAGE

vs

TEMPERATURE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

90

80

70

60

50

40

30

20

10

0

30

300

250

200

150

100

50

V_CC= 5.0 V

V_CC= 1.8 V

25

20

15

10

5

V_CC= 1.8 V, I_SOURCE= 10 mA

T_A= –40°C

T_A= 25°C

V_CC= 5.0 V, I_SOURCE= 10 mA

T_A= 85°C

V_CC= 1.8 V, I_SOURCE= 1 mA

V_CC= 5 V, I_SOURCE= 1 mA

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.1

0.2

0.3

0.4

0.5

0.6

V_CCP– V_OH(V)

Output Low Voltage, V_OL(V)

0

–40 –15

10

35

60

85

Temperature,T_A(°C)

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TYPICAL CHARACTERISTICS (continued)

T_A= 25°C (unless otherwise noted)

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs

OUTPUT HIGH VOLTAGE

50

45

40

35

30

25

20

15

10

5

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

V_CC= 3.3 V

V_CC= 2.5 V

V_CC= 5.0 V

T_A= –40°C

T_A= 25°C

T_A= 85°C

0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.0

0.1

0.2 0.3

V_CCP– V_OH(V)

0.4

0.5

0.6

0.1

0.2

0.3

0.4

0.5

0.6

V_CCP– V_OH(V)

I/O HIGH VOLTAGE

vs

TEMPERATURE

300

250

200

150

100

50

V_CC= 1.8 V, I_SOURCE= 10 mA

V_CC= 5.0 V, I_SOURCE= 10 mA

0

–40 –15

10

35

60

85

Temperature,T_A(°C)

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PARAMETER MEASUREMENT INFORMATION

V

CCI

R

= 1 kW

L

SDA

DUT

C

= 50 pF

L

(see Note A)

SDA LOAD CONFIGURATION

Two Bytes for READ Input Port Register

(see Figure 9)

Stop

Start

Address

Bit 7

(MSB)

Data

Bit 7

(MSB)

Data

Bit 0

(LSB)

Stop

Condition

(P)

R/W

Bit 0

(LSB)

ACK

(A)

Address

Bit 1

Condition Condition

(P) (S)

t

sch

scl

0.7 ´ V

CCI

SCL

SDA

0.3 ´ V

CCI

t

icr

vd

t

sts

sp

t

icf

t

buf

vd

t

sps

ocf

0.7 ´ V

0.3 ´ V

CCI

t

vd(ack)

icr

t

sdh

t

icf

sds

t

sth

Repeat Start

Condition

Stop

Condition

VOLTAGE WAVEFORMS

BYTE

DESCRIPTION

I²C address

1

2

Input register port data

A. C_Lincludes probe and jig capacitance. tocf is measured with C_Lof 10 pF or 400 pF.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 10. I²C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CCI

R

= 4.7 kW

L

INT

DUT

C

= 100 pF

L

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

Start

8 Bits

From Slave

Condition

R/W

1

(One Data Byte)

From Port

Slave Address

Data From Port

Data 2

AD

DR

Data 1

A

1

P

S

0

1

0

3

0

4

0

6

A

1

2

5

7

8

A

t

B

ir

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 ´ V

CCI

0.5 ´ V

SCL

INT

CCI

R/W

A

0.3 ´ V

t

iv

t

ir

0.5 ´ V

INT

CCI

Pn

0.5 ´ V

CCP

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 11. Interrupt Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Pn

500 W

DUT

2 ´ V

CCP

C

= 50 pF

L

(see Note A)

500 W

P PORT LOAD CONFIGURATION

0.7 ´ V

0.3 ´ V

CCP

CCI

SCL

P0

A

P3

Slave

ACK

SDA

Pn

t

pv

(see Note B)

Last Stable Bit

Unstable

Data

WRITE MODE (R/W = 0)

0.7 ´ V

0.3 ´ V

CCI

SCL

Pn

P0

A

P3

CCI

t

ph

t

ps

0.5 ´ V

CCP

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 12. P Port Load Circuit and Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

V

CCI

R

= 1 kW

L

Pn

500 W

SDA

DUT

2 ´ V

CCP

DUT

C = 50 pF

L

(see Note A)

C

= 50 pF

500 W

L

(see Note A)

SDA LOAD CONFIGURATION

P PORT LOAD CONFIGURATION

Start

SCL

ACK or Read Cycle

SDA

0.3 ´ V

CCI

t

RESET

V

/2

RESET

CCP

t

REC

t

W

V

/2

Pn

CCP

t

RESET

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

Figure 13. Reset Load Circuits and Voltage Waveforms

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APPLICATION INFORMATION

Figure 14 shows an application in which the TCA6408 can be used.

V

CCI

CCP

16

V

CCI

(1.8 V)

1

10 kW

(x 4)

V

CC

100 kW (x 3)

V

CCP

CCI

14

15

SCL

ALARM

(see note D)

Master

Controller

4

P0

SDA

INT

SDA

Subsystem 1

(e.g., Alarm)

13

3

INT

GND

RESET

A

5

P1

TCA6408

ENABLE

B

6

P2

P3

P4

P5

P6

P7

2

ADDR

7

9

Keypad

10

11

12

GND

8

A. Device address configured as 0100000 for this example.

B. P0 and P2–P4 are configured as inputs.

C. P1 and P5-P7 are configured as outputs.

D. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a

resistor is not needed. Outputs (in the P port) do not need pullup resistors.

Figure 14. Typical Application

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APPLICATION INFORMATION (continued)

Minimizing I_CCWhen the I/O is Used to Control LEDs

When the I/Os are used to control LEDs, normally they are connected to V_CCthrough a resistor as shown in

Figure 14. The LED acts as a diode so when the LED is off the I/O V_INis about 1.2 V less than V_CC. The ∆I_CC

parameter in "Electrical Characteristics" shows how I_CCincreases as V_INbecomes lower than V_CC. Designs

needing to minimize current consumption, such as battery power applications, should consider maintaining the

I/O pins greater than or equal to V_CCwhen the LED is off.

Figure 15 shows a high-value resistor in parallel with the LED. Figure 16 shows V_CCless than the LED supply

voltage by at least 1.2 V. Both of these methods maintain the I/O V_INat or above V_CCand prevent additional

supply current consumption when the LED is off.

V_CC

LED

100 kΩ

V_CC

Px

Figure 15. High-Value Resistor in Parallel With the LED

3.3 V

5 V

LED

V_CC

Px

Figure 16. Device Supplied by a Low Voltage

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PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2007

PACKAGING INFORMATION

Orderable Device

TCA6408PW

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TSSOP

PW

16

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TCA6408PWG4

TCA6408PWR

TSSOP

QFN

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TCA6408PWRG4

TCA6408RGTR

TCA6408RGTRG4

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

RGT

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Sep-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

12

TCA6408PWR

TCA6408RGTR

PW

16

SITE 41

7.0

3.3

5.6

3.3

1.6

1.1

8

12

Q1

Q2

RGT

330

12

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Sep-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TCA6408PWR

TCA6408RGTR

PW

16

SITE 41

346.0

0.0

RGT

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCA6408PW
厂家：	TEXAS INSTRUMENTS
描述：	LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS 低压8位I2C和SMBus I / O扩展器，带有中断输出，复位和配置寄存器并行IO端口微控制器和处理器外围集成电路光电二极管输出元件 PC
文件：	总30页 (文件大小：842K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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