DS1350ABP-70+ [MAXIM]
4096k Nonvolatile SRAM with Battery Monitor;
| 型号： | DS1350ABP-70+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4096k Nonvolatile SRAM with Battery Monitor 电池 静态存储器 |
| 文件： | 总10页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5585; Rev 10/10
DS1350Y/AB
4096k Nonvolatile SRAM
with Battery Monitor
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
. 10 years minimum data retention in the
absence of external power
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A18
A17
A14
1
2
3
4
5
6
7
8
9
BW
.
Data is automatically protected during power
loss
A15
A16
RST
VCC
A13
A12
A11
A10
A9
. Power supply monitor resets processor when
CC power loss occurs and holds processor in
WE
OE
V
CE
A8
DQ7
reset during VCC ramp-up
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
13
14
15
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
. Battery monitor checks remaining capacity
daily
GND VBAT
. Read and write access times of 70ns
. Unlimited write cycle endurance
. Typical standby current 50µA
. Upgrade for 512k x 8 SRAM, EEPROM, or
Flash
16
17
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
. Lithium battery is electrically disconnected to
retain freshness until power is applied for the
first time
. Full ±10% VCC operating range (DS1350Y)
or optional ±5% VCC operating range
(DS1350AB)
. Optional industrial temperature range of
-40°C to +85°C, designated IND
. PowerCap Module (PCM) package
PIN DESCRIPTION
A0 – A18
DQ0 – DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Reset Output
- Battery Warning
- Power (+5V)
- Ground
WE
OE
RST
BW
VCC
GND
-
-
Directly surface-mountable module
Replaceable snap-on PowerCap provides
lithium backup battery
-
-
Standardized pinout for all nonvolatile
(NV) SRAM products
Detachment feature on PowerCap allows
easy removal using a regular screwdriver
DESCRIPTION
The DS1350 4096k NV SRAMs are 4,194,304 bit, fully static, NV SRAMs organized as 524,288 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the status of
VCC and the status of the internal lithium battery. DS1350 devices in the PowerCap Module package are
directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete NV
SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or Flash components.
1 of 10
DS1350Y/AB
READ MODE
The DS1350 devices execute a read cycle whenever
(Write Enable) is inactive (high) and
(Chip
CE
WE
Enable) and
(Output Enable) are active (low). The unique address specified by the 19 address inputs
OE
(A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that
and
(Output Enable) access times are also satisfied. If
and
access times are not
CE
CE
OE
OE
satisfied, then data access must be measured from the later-occurring signal (
or
) and the limiting
OE
CE
parameter is either tCO for
or tOE for
rather than address access.
OE
CE
WRITE MODE
The DS1350 devices execute a write cycle whenever the
and
signals are in the active (low) state
CE
WE
after address inputs are stable. The later-occurring falling edge of
or
will determine the start of
CE
WE
the write cycle. The write cycle is terminated by the earlier rising edge of
must be kept valid throughout the write cycle.
or
. All address inputs
WE
CE
must return to the high state for a minimum recovery
WE
time (tWR) before another cycle can be initiated. The
control signal should be kept inactive (high)
OE
during write cycles to avoid bus contention. However, if the output drivers are enabled ( and
CE
OE
active) then
will disable the outputs in tODW from its falling edge.
WE
DATA RETENTION MODE
The DS1350AB provides full functional capability for VCC greater than 4.75V and write protects by 4.5V.
The DS1350Y provides full functional capability for VCC greater than 4.5V and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The NV SRAMs
constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below
approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit connects
external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.75V for the DS1350AB and 4.5V for the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting
. On power-up,
is held active for 200ms nominal to prevent system
RST
RST
operation during power-on transients and to allow tREC to elapse.
has an open drain output driver.
RST
BATTERY MONITORING
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MΩ test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output
is asserted. Once asserted,
remains active until the module is replaced.
BW
BW
The battery is still retested after each VCC power-up, however, even if
is active. If the battery voltage
BW
is found to be higher than 2.6V during such testing,
is de-asserted and regular 24-hour testing
BW
resumes.
has an open drain output driver.
BW
2 of 10
DS1350Y/AB
PACKAGES
The 34-pin PowerCap module integrates SRAM memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC PowerCap. The PowerCap module package design
allows a DS1350 PCM device to be surface mounted without subjecting its lithium backup battery to
destructive high-temperature reflow soldering. After a DS1350 PCM is reflow soldered, a DS9034PC is
snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to
prevent improper attachment. DS1350 PowerCap modules and DS9034PC PowerCaps are ordered
separately and shipped in separate containers. See the DS9034PC data sheet for further information.
3 of 10
DS1350Y/AB
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
-0.3V to +6.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
+260°C
Industrial:
Storage Temperature Range
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1350AB Power Supply Voltage
DS1350Y Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0.0
V
V
V
V
5.0
VCC
0.8
Logic 0
DC E L E C TR IC A L C HAR AC TE R IS TIC S
(VCC = 5V ± 5% for DS1350AB)
(TA: See Note 10) (VCC = 5V ± 10% for DS1350Y)
PARAMETER
SYMBOL MIN
TYP
MAX
+1.0
UNITS NOTES
Input Leakage Current
IIL
IIO
-1.0
-1.0
-1.0
2.0
µA
µA
+1.0
I/O Leakage Current
≥ VIH ≤ VCC
CE
Output Current @ 2.4V
Output Current @ 0.4V
IOH
mA
mA
µA
µA
mA
V
14
14
IOL
ICCS1
ICCS2
ICCO1
VTP
VTP
200
50
600
150
85
Standby Current
Standby Current
=2.2V
CE
CE
=V -0.5V
CC
Operating Current
Write Protection Voltage (DS1350AB)
Write Protection Voltage (DS1350Y)
4.50
4.25
4.62
4.37
4.75
4.5
V
CAPACITANCE
PARAMETER
(TA = +25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
10
Input Capacitance
CIN
5
5
pF
pF
Input/Output Capacitance
CI/O
10
4 of 10
DS1350Y/AB
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 5% for DS1350AB)
(TA: See Note 10) (VCC = 5V ± 10% for DS1350Y)
DS1350AB-70
DS1350Y-70
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
Access Time
tRC
tACC
tOE
70
ns
ns
ns
ns
ns
ns
70
35
70
to Output Valid
OE
CE
OE
tCO
to Output Valid
or to Output Active
tCOE
tOD
5
5
5
5
CE
Output High Z from Deselection
25
Output Hold from Address
Change
tOH
ns
Write Cycle Time
Write Pulse Width
Address Setup Time
tWC
tWP
tAW
70
55
0
ns
ns
ns
3
tWR1
tWR2
5
12
12
13
Write Recovery Time
ns
tODW
tOEW
tDS
25
ns
ns
ns
5
5
4
Output High Z from
Output Active from
Data Setup Time
WE
WE
5
30
tDH1
tDH2
0
7
12
13
Data Hold Time
ns
READ CYCLE
SEE NOTE 1
5 of 10
DS1350Y/AB
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
6 of 10
DS1350Y/AB
POWER-DOWN/POWER-UP CONDITION
BATTERY WARNING DETECTION
SEE NOTE 14
7 of 10
DS1350Y/AB
(TA: See Note 10)
UNITS NOTES
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL MIN
tPD
tF
tRPD
tR
TYP
MAX
1.5
11
µs
µs
µs
µs
ms
ms
ms
s
VCC Fail Detect to
and
Inactive
WE
CE
VCC slew from VTP to 0V
VCC Fail Detect to Active
150
150
15
14
RST
VCC slew from 0V to VTP
VCC Valid to and
tPU
2
Inactive
WE
CE
VCC Valid to End of Write Protection
tREC
tRPU
tBPU
125
350
1
150
200
14
14
VCC Valid to
VCC Valid to
Inactive
Valid
RST
BW
BATTERY WARNING TIMING
PARAMETER
(TA: See Note 10)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Battery Test Cycle
tBTC
tBTPW
tBW
24
hr
s
Battery Test Pulse Width
1
1
s
Battery Test to
Active
BW
(TA = +25°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
TYP
MAX
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
is high for a Read Cycle.
WE
2.
= VIH or VIL. If
= VIH during write cycle, the output buffers remain in a high-impedance state.
OE
OE
3. tWP is specified as the logical AND of
and
. t is measured from the latter of
or
CE WE
CE
WE
WP
going low to the earlier of
or
going high.
WE
CE
4. tDS are measured from the earlier of
or
going high.
WE
CE
5. These parameters are sampled with a 5pF load and are not 100% tested.
6. If the low transition occurs simultaneously with or latter than the
low transition, the output
high transition, the output
WE
CE
WE
buffers remain in a high-impedance state during this period.
7. If the high transition occurs prior to or simultaneously with the
CE
buffers remain in high-impedance state during this period.
8. If is low or the low transition occurs prior to or simultaneously with the low transition,
CE
WE
WE
the output buffers remain in a high-impedance state during this period.
8 of 10
DS1350Y/AB
9. Each DS1350 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from
13. tWR2 and tDH2 are measured from
going high.
going high.
WE
CE
14.
and
are open drain outputs and cannot source current. External pull-up resistors should be
BW
RST
connected to these pins for proper operation. Both pins will sink 10mA.
15. DS1350 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 – 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
SUPPLY
TOLERANCE
PART
TEMP RANGE
PIN-PACKAGE
DS1350ABP-70+
DS1350ABP-70IND+
DS1350YP-70+
DS1350YP-70IND+
+Denotes a lead(Pb)-free/RoHS-compliant package.
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
34 PCAP*
34 PCAP*
34 PCAP*
34 PCAP*
5V ± 5%
5V ± 5%
5V ± 10%
5V ± 10%
* DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
LAND
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0246
PATTERN NO.
34 PCAP
PC2+5
—
9 of 10
DS1350Y/AB
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Updated the soldering and storage information in the Absolute
Maximum Ratings section, removed the unused AC timing specs in
the AC Electrical Characteristics table, updated the Ordering
Information table, replaced the package outline drawing with the
Package Information table
10/10
1, 4, 5, 9
10 of 10
相关型号：
DS1350ABP-70IND+
Non-Volatile SRAM Module, 512KX8, 70ns, CMOS, ROHS COMPLIANT, POWERCAP MODULE-34
MAXIM
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