DS2430AP+T [MAXIM]
256-Bit 1-Wire EEPROM; 256位的1-Wire EEPROM
| 型号： | DS2430AP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 256-Bit 1-Wire EEPROM |
| 文件： | 总19页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5236; Rev 2/12
DS2430A
256-Bit 1-Wire EEPROM
FEATURES
PIN ASSIGNMENT
. 256-bit Electrically Erasable Programmable
Read Only Memory (EEPROM) plus 64-bit
one-time programmable application register
. Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-bit
serial number + 8-bit CRC tester) assures
absolute identity because no two parts are alike
. Built-in multidrop controller ensures
compatibility with other MicroLAN products
. EEPROM organized as one page of 32 bytes
for random access
TO-92
TSOC PACKAGE
DALLAS
DS2430A
1
3
5
4
OP VIEW
.7mm x 4.0mm x 1.5mm
SIDE VIEW
. Reduces control, address, data, and power to a
single data pin
1
3
. Directly connects to a single port pin of a
microprocessor and communicates at up to
15.3kbits per second
. 8-bit family code specifies DS2430A
communication requirements to reader
. Presence detector acknowledges when reade
first applies voltage
1 2 3
BOTTOM VIEW
. Low cost TO-92 or 6-pin TSOC and UCS
surface mount package
. Reads and writes over a wide voage range of
2.8V to 5.25V from -40°C to 85°C
NOTE: The leads of TO-92 packages on tape and reel are formed
to approximately 100-mil (2.54mm) spacing. For details see the
Package Information.
PIN DESCRIPTION
ORDERING INFORMTION
TO-92
Ground
Data
TSOC
Ground
Data
NC
PART
DS2430A+
TERANGE PIN-PACKAGE
-40+85°C 3 TO-92
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
DS2430A+T&R
DS2430AP+
-40°C to +85°C 3 TO-92 (2k pcs)
-40°C to +85°C 6 TSOC
NC
––––
––––
––––
NC
NC
NC
DS2430AP+TR
-40°C to +85°C 6 TSOC (4k pcs)
+Denotes a d(Pb)-free/RoHS-compliant package.
T&R = Tape nd reel.
1 of 19
DS2430A
DESCRIPTION
The DS2430A 256-bit 1-Wire® EEPROM identifies and stores relevant information about the product to
which it is associated. This lot or product specific information can be accessed with minimal interface, for
example a single port pin of a microcontroller. The DS2430A consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (14h) plus
256 bits of user-programmable EEPROM and a 64-bit one-time programmable application register. The
power to read and write the DS2430A is derived entirely from the 1-Wire communication line. Data is
transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.
The 48-bit serial number that is factory-lasered into each DS2430A provides a guaranteed unique identity
that allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that
allows standard assembly equipment to handle the device easily for attachment to printed circuit boards
or wiring. Typical applications include storage of calibration constants, board identificatio, and product
revision status.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control nd memory sections of
the DS2430A. The DS2430A has four main data components: 1) 64-bt lasered ROM, 2) 256-bit
EEPROM data memory with scratchpad, 3) 64-bit one-time programmble application register with
scratchpad and 4) 8-bit status memory. The hierarchical structure of te 1-Wire protocol is shown in
Figure 2. The bus master must first provide one of the four ROM Fnction Commands: 1) Read ROM, 2)
Match ROM, 3) Search ROM, 4) Skip ROM. The protocol requirefor these ROM Function Commands
is described in Figure 8. After a ROM Function Commas successfully executed, the memory
functions become accessible and the master can provide ay one of the four memory function commands.
The protocol for these memory function commands is descibed in Figure 6. All data is read and written
least significant bit first.
64-BIT LASERED ROM
Each DS2430A contains a unique ROM codt is 64 bits long. The first 8 bits are a 1-Wire family code
(14h). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure
3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR
gates as shown in Figure 4. The plynomial is X8 + X5 + X4 + 1. Additional information about the
1-Wire CRC is available in Appliation Note 27. The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the
family code has been enteredthen the serial number is entered. After the 48th bit of the serial number has
been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the
shift register to all 0s.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
2 of 19
DS2430A
DS2430A BLOCK DIAGRAM Figure 1
3 of 19
DS2430A
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2
64-BIT LASERED ROM Figure 3
8-Bit CRC Ce
48-Bit Serial Number
8-Bit Family Code (14H)
LSB MSB LSB
MSB
LSB MSB
1-WIRE RC GENERATOR Figure 4
Polynomial = X8 + X5 + X4 + 1
4 of 19
DS2430A
MEMORY
The memory of the DS2430A consists of three separate sections, called data memory, application
register, and status register (Figure 5). The data memory and the application register each have its own
intermediate storage area called scratchpad that acts as a buffer when writing to the device. The data
memory can be read and written as often as desired. The application register, however, is one-time
programmable only. Once the application register is programmed, it is automatically write protected. The
status register indicates whether the application register is already locked or whether it is still available
for storing data. As long as the application register is unprogrammed, the status register reads FFh.
Copying data from the register scratchpad to the application register clears the 2 least significant bits of
the status register, yielding an FCh the next time one reads the status register.
DS2430A MEMORY MAP Figure 5
MEMORY FUNCTION COMMANDS
The Memory Function Flow Char(Figure 6) describes the protocols necessary for accessing the different
memory sections of the DS2430A. An example is shown later in this document.
WRITE SCRATCHPAD [0Fh]
After issuing the Writratchpad command, the master must first provide a 1-byte address, followed by
the data to be wrien to the scratchpad for the data memory. The DS2430A automatically increments the
address after every byte it receives. After having received a data byte for address 1Fh, the address counter
wraps around t00h for the next byte and writing continues until the master sends a Reset Pulse.
READ SCRATCHPAD [AAh]
This command is used to verify data previously written to the scratchpad before it is copied into the final
age EEPROM memory. After issuing the Read Scratchpad command, the master must provide the 1-
be starting address from where data is to be read. The DS2430A automatically increments the address
after every byte read by the master. After the data at address 1Fh has been read, the address counter wraps
around to 00h for the next byte and reading continues until the master sends a Reset Pulse.
5 of 19
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6
COPY SCRATCHPAD [55h]
After the data stored in the scratchpad has been verified the master may send the Copy Scratchpad
command followed by a validation key of A5h to transfer data from the scratchpad to the EEPROM
memory. This command always opies the data of the entire scratchpad. Therefore, if one desires to
change only a few bytes of te EEPROM data, the scratchpad should contain a copy of the latest
EEPROM data before the Write Scratchpad and Copy Scratchpad commands are issued. After this
command and the validation key are issued, the data line must be held above VPUPmin for at least tPROG
.
READ MEMORY [F0h]
The Read Memory command is used to read a portion or all of the EEPROM data memory and to copy
the entire data memory into the scratchpad to prepare for changing a few bytes. To copy data from the
data memy to the scratchpad and to read it, the master must issue the read memory command followed
by the 1-byte starting address of the data to be read from the scratchpad. The DS2430A automatically
increments the address after every byte read by the master. After the data of address 1Fh has been read,
address counter wraps around to 00h for the next byte and reading continues until the master sends a
Ret Pulse. If one intends to copy the entire data memory to the scratchpad without reading data, a
starting address is not required; the master may send a Reset Pulse immediately following the command
code.
6 of 19
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6 (continued)
WRITE APPLICATION REGISTER [99h]
This command is essentially the same as the Writcratchpad command, but it addresses the 64-bit
register scratchpad. After issuing the command ode, the master must provide a 1-byte address, followed
by the data to be written. The DS2430A autotically increments the address after every byte it receives.
After receiving the data byte for address 07hhe address counter wraps around to 00h for the next byte
and writing continues until the master snda Reset Pulse. The Write Application Register command can
be used as long as the application register has not yet been locked. If issued for a device with the
application register locked, the daa witten to the register scratchpad will be lost.
READ STATUS REGITER [66h]
The status register is a means for the master to find out whether the application register has been
programmed and locAfter issuing the read status register command, the master must provide the
validation key 00h before receiving status information. The two least significant bits of the 8-bit status
register are 0 if te application register was programmed and locked; all other bits always read 1. The
master may fiish the read status command by sending a Reset Pulse at any time.
7 of 19
DS2430A
MEMORY FUNCTION FLOW CHART Figure 6 (continued)
READ APPLICATION REGISTR [C3h]
This command is used to read the application register or the register scratchpad. As long as the
application register is not yet locked, the DS2430A transmits data from the register scratchpad. After the
application register is locked the DS2430A transmits data from the application register, making the
register scratchpad inaccessile for reading. The contents of the status register indicate where the data
received with this command came from. After issuing the Read Application Register command, the
master must provide 1-byte starting address from where data is to be read. The DS2430A
automatically increments the address after every byte read by the master. After the data at address 07h
has been read, the address counter wraps around to 00h for the next byte and reading continues until the
master sends a eset Pulse.
COPY & LOCK APPLICATION REGISTER [5Ah]
After he data stored in the register scratchpad has been verified the master may send the Copy & Lock
lication Register command followed by a validation key of A5h to transfer the contents of the entire
rister scratchpad to the application register and to simultaneously write-protect it. The master may
cancel this command by sending a Reset Pulse instead of the validation key. After the validation key is
transmitted, the data line must be held above VPUPmin for at least tPROG. Once tPROG has expired, the
application register will contain the data of the register scratchpad. Further write accesses to the
application register will be denied. The Copy & Lock Application Register command can only be
executed once.
8 of 19
DS2430A
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the
DS2430A is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal type and timing). The 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open
drain connection or three-state outputs. The 1-Wire port of the DS2430A is open drain with an internal
circuit equivalent to that shown in Figure 7. A multidrop bus consists of a 1-Wire bus ith multiple
slaves attached. The DS2430A communicates at regular 1-Wire speed, 15.3kbits per se, and requires
a pullup resistor as shown in Figure 7. The idle state for the 1-Wire bus is high. If for any reason a
transaction needs to be suspended, the bus MUST be left in the idle state if the transction is to resume. If
this does not occur and the bus is left low for more than 120µs, one or more of the evices on the bus may
be reset.
HARDWARE CONFIGURATION Figure 7
RPU
IL
RPU
Nte: Depending on the 1-Wire communication speed and the bus characteristics, the optimal pullup
resistor value will be in the 0.3kΩ to 2.2kΩ range. To write to a single device, a RPUPmax resistor and
VPUP of at least 4.0V is sufficient. For writing multiple DS2430As simultaneously or operation at low
VPUP, the resistor should be bypassed by a low-impedance pullup to VPUP while the device copies the
scratchpad to EEPROM.
9 of 19
DS2430A
ROM FUNCTIONS FLOW CHART Figure 8
10 of 19
DS2430A
Transaction Sequence
The sequence for accessing the DS2430A via the 1-Wire port is as follows:
. Initialization
. ROM Function Command
. Memory Function Command
. Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initializaion sequence
consists of a Reset Pulse transmitted by the bus master followed by a Presence Pulse(s) tnsmitted by the
slave(s).
The Presence Pulse lets the bus master know that the DS2430A is on the bus and s ready to operate. For
more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence pulse, it can issue one f the four ROM function commands.
All ROM function commands are 8 bits long. A list of these comands follows (refer to flowchart in
Figure 8):
Read ROM [33h]
This command allows the bus master to read the DS0A’s 8-bit family code, 48-bit serial number, and
8-bit CRC. This command can be used only if there a single DS2430A on the bus. If more than one
slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time
(open drain produces a wired-AND result). resultant family code and 48-bit serial number usually
result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, follwed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2430A on a multidrop bus. Only the DS2430A that exactly matches the 64-bit ROM sequence
will respond to the subsequet memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a Reset Pulse. This command can be used with a single or multiple devices on the
bus.
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the
memory fctions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns produces a wired-AND result).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The Search ROM process
is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM.
11 of 19
DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a search ROM, including an actual example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-0, Write-1 and Read
Data. All these signals (except Presence Pulse) are initiated by the bus master.
To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL.
To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time t takes
for the voltage to make this rise is seen in Figure 9 as ε, and its duration depends on the ullup resistor
(RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX elevant for the
DS2430A when determining a logical level, not triggering any events.
Figure 9 shows the initialization sequence required to begin any communicatiowith the DS2430A. A
Reset Pulse followed by a Presence Pulse indicates the DS2430A is ready to receive data, given the
correct ROM and memory function command. If the bus master uses sew-rate control on the falling
edge, it must pull down the line for tRSTL + tF to compensate for the edge.
After the bus master has released the line it goes into Receive mde. Now the 1-Wire bus is pulled to
VPUP through the pullup resistor. When the threshold VTH is cd, the DS2340A waits for tPDH and then
transmits a Presence Pulse by pulling the line low for tP. To detect a Presence Pulse, the master must
test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX
,
tPDLMAX, and tRECMIN. Immediately after tRSTH is expirthe DS2430A is ready for data communication.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
MASTER TX “RESET PULSEMASTER RX “PRESENCE PULSE”
tMSP
ε
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
tRSTL
tPDL
tRSTH
tPDH
tREC
RESISTOR
MASTER
DS2430A
Read/Write Time Slots
Data communication with the DS2430A takes place in time slots, which carry a single bit each. Write
slots transport data from bus master to slave. Read time slots transfer data from slave to master.
Figure 10 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold VTL, the DS2430A starts its internal timing generator that determines when the
data line is sampled during a write time slot and how long data is valid during a read time slot.
12 of 19
DS2430A
Master-to-Slave
For a Write-1 time slot, the voltage on the data line must have crossed the VTH threshold before the
Write-1 low time tW1LMAX is expired. For a Write-0 time slot, the voltage on the data line must stay below
the VTH threshold until the Write-0 low time tW0LMIN is expired. For the most reliable communication, the
voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH
threshold has been crossed, the DS2430A needs a recovery time tREC before it is ready for the next time
slot.
READ/WRITE TIMING DIAGRAM Figure 10
Write-1 Time Slot
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ε
tSLOT
RESISTOR
MASTER
Write-0 Time Slot
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tF
ε
tREC
tSLOT
RESISTOR
MASTER
Read-data Time Slot
tMSR
tRL
VPUP
VIHMASTER
VTH
Master
Sampling
Window
V
VILMAX
0V
tF
tREC
δ
tSLOT
RESISTOR
MASTER
DS2430A
13 of 19
DS2430A
Slave-to-Master
A Read-data time slot begins like a Write-1 time slot. The voltage on the data line must remain below
VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the
DS2430A starts pulling the data line low; its internal timing generator determines when this pulldown
ends and the voltage starts rising again. When responding with a 1, the DS2430A does not hold the data
line low at all, and the voltage starts rising as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS2430A on the other
side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a ead
from the data line. For the most reliable communication, tRL should be as short as permissible, and the
master should read close to but no later than tMSRMAX. After reading from the data line, the master must
wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2430A tget ready for
the next time slot. Note that tREC specified herein applies only to a single DS2430A atted to a 1-Wire
line. For multidevice configurations, tREC must be extended to accommodate the addition1-Wire device
input capacitance. Alternatively, an interface that performs active pullup during the -Wire recovery time
such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transiets controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are susceptible to noisof various origins. Depending on the
physical size and topology of the network, reflections from end pnts and branch points can add up, or
cancel each other to some extent. Such reflections are visas glitches or ringing on the 1-Wire
communication line. Noise coupled onto the 1-Wire line rom external sources can also result in signal
glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization
with the master and, consequently, result in a SearcOM command coming to a dead end or cause a
device-specific function command to abort. For tter performance in network applications, the
DS2430A uses a new 1-Wire front end, which maes it less sensitive to noise.
The 1-Wire front end of the DS2430A differm traditional slave devices in three characteristics.
1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity o high-frequency noise.
2) There is a hysteresis at the low-o-high switching threshold VTH. If a negative glitch crosses VTH but
does not go below VTH - VHY, t will not be recognized (Figure 11, Case A)..
3) There is a time window spcified by the rising edge hold-off time tREH during which glitches are
ignored, even if they extend below VTH - VHY threshold (Figure 11, Case B, tGL < tREH). Deep voltage
droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH
window cannot be red out and are taken as the beginning of a new time slot (Figure 11, Case C,
tGL ≥ tREH).
Devices that have the parameters VHY, and tREH specified in their electrical characteristics use the
improved 1-We front end.
NOISE SUPPRESSION SCHEME Figure 11
tREH
tREH
VPUP
VTH
VHY
Case A
Case B
Case C
tGL
0V
tGL
14 of 19
DS2430A
MEMORY FUNCTION EXAMPLE
Example: Write 2 data bytes to data memory locations 0006h and 0007h. Read entire data memory.
MASTER MODE DATA (LSB FIRST)
COMMENTS
Reset pulse (480µs to 960µs)
Presence pulse
Issue “Skip ROM” command
Issue “Write Scratchpad” command
Start address = 06h
Write 2 bytes of data to scratchpad
Reset pulse
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX
TX
RX
TX
TX
TX
TX
TX
RX
TX
TX
TX
RX
TX
RX
Reset
Presence
CCh
0Fh
06h
<2 Data Bytes>
Reset
Presence
CCh
AAh
Presence pulse
Issue “Skip ROM” command
Issue “Read Scratchpad” command
Start address = 06h
Read scratchpad data and vify
Reset pulse
06h
<2 Data Bytes>
Reset
Presence
CCh
Presence pulse
Issue “Skip ROMommand
Issue “Copy Scratchpad” command
Validation k
Data line must be above VPUPmin for tPROG
Reset pulse
55h
A5h
<Data Line High>
Reset
.
Presence
CCh
Pree pulse
Issue “Skip ROM” command
Isue “Read Memory” command
Start address = 00h
Read EEPROM data page
Reset pulse
F0h
00h
<32 Bytes
Rest
Prsene
Presence pulse
15 of 19
DS2430A
-0.5V to +6.0V
ABSOLUTE MAXIMUM RATINGS
Voltage Range on DATA to Ground
DATA Sink Current
20mA
Operating Temperature Range
Junction Temperature
-40°C to +85°C
+150°C
Storage Temperature Range
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
TSOC
-55°C to +125°C
+300°C
+260°C
+250°C
TO-92
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and funtional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. xpoure to the
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYMAX UNITS
DATA PIN GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
VPUP
RPUP
CIO
IL
(Notes 2)
(Notes 2, 3)
(Notes 4, 5)
DATA pin at VPUP
2.8
0.
5.25
2.2
1000
15
V
kΩ
pF
µA
0.05
0.46
VPUP
1.8V
0.5
-
VTL
VIL
(Notes 5, 6, 7)
(Notes 2, 8)
V
V
V
VPUP
1.1V
1.70
0.4
-
VTH
(Notes 5, 6, 9)
1.0
Switching Hysteresis
Output Low Voltage
Recovery Time
VHY
VOL
tREC
(Notes 5, 6, 10)
0.21
V
V
µs
At 4mA (Note 11)
RPUP = 2.2kΩ Notes 2,12)
(Notes 5,
5
Rising-Edge Hold-off
Time
tREH
0.5
65
5.0
µs
µs
Timeslot Duration
tSLOT
(Notes 14)
DATA PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE
Reset Low Time
Presence Detect High
Time
tRSTL
Noe 2)
480
15
960
60
µs
µs
tPD
Presence Detect Low
Time
Presence Detect Sample
Time
DL
tMSP
60
60
240
75
µs
µs
(Notes 2, 15)
DATA PIN, 1-Wire WRITE
(Notes 2, 16)
(Notes 2, 16)
Write-0 Low Time
tW0L
60
1
µs
µs
120 - ε
15 - ε
Write-1 Low Tie
tW1L
DATA P, 1-Wire READ
(Notes 2, 17)
(Notes 2, 17)
1
Read Low Time
tRL
µs
µs
15 - δ
15
Read Sample Time
tMSR
tRL + δ
EPROM
gramming Current
Programming Time
Write/Erase Cycles
(Endurance)
(Notes 20, 21)
Data Retention (Notes 22,
23, 24)
IPROG
tPROG
(Notes 5, 18)
(Note 19)
At 25°C
0.5
10
mA
ms
200k
50k
NCY
tDR
At 85°C (worst case)
At 85°C (worst case)
40
years
16 of 19
DS2430A
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature
range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not
guaranteed.
Note 1:
System requirement.
Note 2:
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire
recovery times. The specified value here applies to systems with only one device and with the minimum tREC. For
more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 my
be required. If longer tREC is used, higher RPUP values may be able to be tolerated.
Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resior used
to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal
communications.
Note 4:
Guaranteed by design, characterization and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPRPUP, 1-Wire
timing, and capacitive loading on DATA. Lower VPUP, higher RPUP, shorter tREC, and heaier capacitive loading
Note 5:
Note 6:
all lead to lower values of VTL, VTH, and VHY
.
Voltage below which, during a falling edge on DATA, a logic 0 is detected.
The voltage on DATA needs to be less or equal to VIL(MAX) at all times the mastr is driving DATA to a logic-0
level.
Note 7:
Note 8:
Voltage above which, during a rising edge on DATA, a logic 1 is detected.
After VTH is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least VHY to be
detected as logic '0'.
Note 9:
Note 10:
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tEH after VTH has been reached on the preceding rising
edge.
Note 11:
Note 12:
Note 13:
Defines maximum possible bit rate. Equal to 1/(tW0L) + tREC(min)).
Interval after tRSTL during which a bus master is gued to sample a logic-0 on DATA if there is a DS2430A
Note 14:
Note 15:
present. Minimum limit is tPDH(max); maximum limit itPDH(min) + tPDL(min)
.
Note 16:
Note 17:
ε in Figure 10 represents the time required for te pullup circuitry to pull the voltage on DATA up from VIL to
VTH. The actual maximum duration for thster to pull the line low is tW1Lmax + tF and tW0Lmax + tF respectively.
δ in Figure 10 represents the time requred r the pullup circuitry to pull the voltage on DATA up from VIL to the
input high threshold of the bus mas. Te actual maximum duration for the master to pull the line low is
tRLmax + tF.
Current drawn from DATA durithe EEPROM programming interval. The pullup circuit on DATA during the
programming interval shoulbe such that the voltage at DATA is greater than or equal to VPUPMIN. If VPUP in the
system is close to VPUPMINa w-impedance bypass of RPUP, which can be activated during programming, may
need to be added.
Interval begins tREHax ter the trailing rising edge on DATA for the last timeslot of the validation key for a valid
copy sequence. erval ends once the device's self-timed EEPROM programming cycle is complete and the
current drawn e device has returned from IPROG to IL.
Note 18:
Note 19:
Write-cye endurance is degraded as TA increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Datretention is degraded as TA increases.
araneed by 100% production test at elevated temperature for a shorter time; equivalence of this production
t to data sheet limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
17 of 19
DS2430A
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
3 TO-92 (Bulk)
3 TO-92 (T&R)
6 TSOC
PACKAGE CODE
OUTLINE NO.
21-0248
LAND PATTERN NO.
Q3+1
Q3+4
D6+1
—
—
21-0250
21-0382
90-0321
18 of 19
DS2430A
REVISION HISTORY
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
4/3/95
8/26/96
3/26/97
Initial release
—
Changed “C-lead” package to “TSOC” package. Deleted VIHmax specification
value. Note “Under certain low voltage conditions VILMAX may have to be
reduced to as much as 0.5V to always guarantee a presence pulse.” added to
VIL specification, changed VCC to VPUP in Note 6.
Various
Variou
Changed “Touch Memory” to “iButton”.
Programming time changed from 100ms to 10ms, change VDD to VPUP, revised
note below Figure 7, programming current changed from 600µA to 500µA, QOP
removed from EC table, deleted from Note 5 “and will remain valid for 14µs
minimum (15µs total from falling edge on 1-wire bus).” Endurance added to EC
table with note “The Copy Scratchpad takes 10 ms maximum, during which th
voltage on the 1-Wire bus must not fall below 2.8V.”
12/8/98
Various
1/20/99
5/20/99
Chip scale package added to ordering information
1
Deleted duplicate tPDL and contradicting tPROG spec from EC table
15
Template conversion, style changes (capitalization of command nmes, “Write-
one” to “Write-1”, “Write-zero” to “Write-0”)
10/21/99
All
Part number corrections, style corrections, note below figure revised explain-
ing the appropriate RPUP range, corrections in the Memory Functions Example
(removed Read Memory section at the beginning), chad solder spec from
260°C to JEDEC reference, added notes 11, 12, 13 to Etable, changed
tRSTLmax from 5000µs to 960µs, revised text of EC note 8.
2/2/02
Various
11/1/05
1/16/07
NRFND watermark added
All
Lead free part numbers added; added flip chip gaphic with bump electrical
assignment, orientation mark and markiAdded flip chip 56-level drawing
number, changed "Chip Scale" name to p Chip"; replaced references to the
Book of iButton Standards with the orresponding application notes.
Note on formed leads for TO-92 RL nd URL to 56-G0006-003 added, ILmin
and ILmax spec values added to able. Data retention added to EC table.
Ordering information for stanard and flip chip versions deleted, pin assignment
for flip chip version deleteddata rate changed from 16.3kbps to 15.3 kbps.
Style corrections and inor text updates for clarification.
Various
8/8/07
4/10
1, 15
1
Various
12-14, 16-17
18
New 1-Wire front ed, iproved EEPROM and related EC table with notes.
Package informiosection added.
Reformatted e Ordering Information, deleted the reference to the UCSP
package.
Revised EC able notes 1 and 18; added the Land Pattern No. to the Package
Informsection.
1
2/12
17, 18
19 of 19
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reserves the right to change the circuitry and specifications without notice at any time.
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