DS28E80Q+T [MAXIM]
Memory Circuit,;
| 型号： | DS28E80Q+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Memory Circuit, 内存集成电路 |
| 文件： | 总28页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
DS28E80
Gamma Radiation Resistant 1-Wire Memory
General Description
Features and Benefits
● High Gamma Resistance Allows User-Programmable
Manufacturing or Calibration Data Before Medical
Sterilization
The DS28E80 is a user-programmable nonvolatile mem-
ory chip. In contrast to the floating-gate storage cells,
the DS28E80 employs a storage cell technology that is
resistant to gamma radiation. The DS28E80 has 248
bytes of user memory that are organized in blocks of
8 bytes. Individual blocks can be write-protected. Each
memory block can be written 8 times. The DS28E80
communicates over the single-contact 1-Wire® bus at
standard speed or overdrive speed. Each device has its
own guaranteed unique 64-bit registration number that is
factory programmed into the chip. The communication fol-
lows the 1-Wire protocol with a 64-bit registration number
acting as node address in the case of a multiple-device
1-Wire network.
• Resistant Up to 75kGy (kiloGray) of Gamma Radiation
• Reprogrammable 248 Bytes of User Memory
● Lower Block Size Provides Greater Flexibility in
Programming User Memory
• Memory is Organized as 8-Byte Blocks
• Each Block Can Be Written 8 Times
• User-Programmable Write Protection for Individual
Memory Blocks
● Advanced 1-Wire Protocol Minimizes Interface to
Just Single Contact
● Compact Package and Single IO Interface Reduces
Board Space and Enhances Reliability
• Unique Factory-Programmed, 64-Bit Identification
Number
Applications
● Identification of Medical Consumables
● Identification and Calibration Medical Tools/Accessories
• Communicates at 1-Wire Standard Speed
(15.3kbps max) and Overdrive Speed (76kbps max)
• Operating Range: 3.3V ±10%, -40°C to + 85°C
Reading, 0°C to +50°C Writing
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
• ±8kV HBM ESD Protection (typ) for IO Pin
• 6-Pin TDFN Package
Ordering Information appears at end of data sheet.
Typical Application Circuit
V
CC
10kΩ
R
PUP
V
CC
PIOX
PIOY
BSS84
DS28E80
µC
IO
GND
GND
19-7120; Rev 0; 9/14
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Absolute Maximum Ratings
IO Voltage Range to GND....................................-0.5V to +4.0V
IO Sink Current.................................................................±20mA
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
TDFN...........................................................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TDFN
Junction-to-Ambient Thermal Resistance (θ ) ..........60°C/W
JA
Junction-to-Case Thermal Resistance (θ )...............11°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 3)
= 3.3V ±10% (Note 4)
2.97
300
3.63
750
V
PUP
R
V
Ω
PUP
PUP
C
(Notes 5, 6)
IO pin at V
6.5
5
nF
µA
IO
Input Load Current
I
22
L
PUP
High-to-Low Switching
Threshold
0.65 x
V
(Notes 6, 7, 8)
(Notes 3, 9)
V
V
V
TL
V
PUP
Input Low Voltage
V
0.3
IL
Low-to-High Switching
Threshold
0.75 x
V
(Notes 6, 7, 10)
(Notes 6, 7, 11)
TH
V
PUP
Switching Hysteresis
Output Low Voltage
Recovery Time
V
V
0.3
V
V
HY
I
= 4mA (Note 12)
OL
0.4
OL
t
R
= 750Ω (Notes 3, 13)
10
65
13
µs
REC
PUP
Standard speed
Time Slot Duration
(Notes 3, 14)
t
µs
SLOT
Overdrive speed
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
480
48
480
48
60
8
640
80
Reset Low Time (Note 3)
Reset High Time (Note 15)
t
µs
µs
µs
RSTL
t
RSTH
72
Presence Detect Sample Time
(Notes 3, 16)
t
MSP
10
IO PIN: 1-Wire WRITE
Standard speed
60
8
120
16
Write-Zero Low Time
(Notes 3, 17)
t
µs
W0L
Overdrive speed
Maxim Integrated
│ 2
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Electrical Characteristics (continued)
(T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
Standard speed
MIN
1
TYP
MAX
15
UNITS
Write-One Low Time
(Notes 3, 17)
t
µs
W1L
Overdrive speed
1
2
IO PIN: 1-Wire READ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
Read Low Time
(Notes 3, 18)
15 - d
2 - d
15
t
µs
µs
RL
1
Read Sample Time
(Notes 3, 18)
t
t
+ d
RL
RL
t
MSR
2
+ d
MEMORY
Programming Current
I
t
V
= 3.63V (Notes 6, 19, 20)
12
20
mA
ms
PROG
PROG
PUP
Programming Time for a
Memory Block
(Notes 20, 21)
= +85°C (Note 22)
Data Retention
t
T
10
Years
DR
A
Note 2: Limits are 100% production tested at T = +25°C or T = +85°C. Limits over the operating temperature range and relevant
A
A
supply voltage range are guaranteed by design and characterization. Typical values are at T = +25°C.
A
Note 3: System requirement.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5: Typical value represents the internal parasite capacitance when V
is first applied. Once the parasite capacitance is
PUP
charged, it does not affect normal communication.
Note 6: Guaranteed by design and/or characterization only. Not production tested.
Note 7: V , V , and V are functions of the internal supply voltage, which is a function of V , R , 1-Wire timing, and
PUP PUP
TL TH
HY
capacitive loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values
PUP
PUP
REC
of V , V , and V
.
TL TH
HY
Note 8: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.
ILMAX
Note 10: Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V
to be detected as logic-zero.
HY
TH
Note 12: The I-V characteristic is linear for voltages less than 1V.
Note 13: Applies to a single device attached to a 1-Wire line.
Note 14: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 15: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 16: Interval after t during which a bus master can read a logic-zero on IO if there is a DS28E80 present. The power-up
RSTL
presence detect pulse can be outside this interval, but it is completed within 2ms after power-up. 1-Wire communication
should be considered invalid until 2ms after power-up. Send a 1-Wire reset after POR for presence detect.
Note 17: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V . The actual
IL
TH
maximum duration for the master to pull the line low is t
+ t - ε and t
+ t - ε, respectively.
W1LMAX
F
W0LMAX F
Note 18: δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high
IL
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
+ t .
RLMAX
F
Note 19: Current drawn from IO during the programming interval. The pullup circuits on IO during the programming interval should
be such that the voltage at IO is greater than or equal to V
. A low-impedance bypass of R
, which can be acti-
PUPMIN
PUP
vated during programming, may need to be added.
Note 20: T = 0°C to +50°C.
A
Note 21: The t
interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte (FFh) for
PROG
a valid Write Block sequence. The interval ends once the device’s self-timed programming cycle is complete and the cur-
rent drawn by the device has returned from I to I .
PROG
L
Note 22: Data retention is tested in compliance with JESD47G. No elevated gamma radiation level.
Maxim Integrated
│ 3
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Pin Configuration
TOP VIEW
DS28E80
+
N.C.
IO
1
2
3
6
4
5
N.C.
N.C.
N.C.
GND
EP*
TDFN-EP
3mm x 3mm
*EP = EXPOSED PAD
Pin Description
PIN
1, 4–6
2
NAME
N.C.
IO
FUNCTION
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
3
GND
Ground Reference
Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
—
EP
and operate independently of each other. The main appli-
cation of the DS28E80 is identification and monitoring of
consumables for medical applications.
Detailed Description
The DS28E80 combines 1984 bits of 8-times program-
mable radiation hard nonvolatile user memory, adminis-
tration memory, protection memory, and a 64-bit ROM ID
in a single chip. A data buffer assists when writing to the
memory. Data is transferred serially through the 1-Wire
protocol that requires only a single data lead and a
ground return. The user memory can be write protected
to prevent overwriting the memory data. The protection
applies to individual memory blocks. To protect against
adverse effects caused by bit errors, the communication
relies on 16-bit CRCs that the DS28E80 generates at
various places in the protocol. The master verifies the
CRC and, when found correct, transmits a release byte
(any value from 00h to FFh) to approve EEPROM pro-
gramming cycle. In case of a CRC error, the master can
abort the communication and start over.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E80. The device has five main data components:
user memory (31 blocks of 8 bytes), administration mem-
ory, protection memory, 64-bit ROM ID, and a 64-bit data
buffer. Figure 2 shows the hierarchical structure of the
1-Wire protocol. The bus master must first provide one of
the seven ROM function commands: Read ROM, Match
ROM, Search ROM, Skip ROM, Resume Communication,
Overdrive-Skip ROM and Overdrive-Match ROM. The
protocol required for these ROM function commands is
described in Figure 8. After a ROM function command
is successfully executed, the memory functions become
accessible and the master can provide any one of the
5 available memory function commands. The function
protocols are described in Figure 6. All data is read and
written least-significant bit first.
The device’s 64-bit ROM ID can be used to electronically
identify the object in which the DS28E80 is used. The
ROM ID guarantees unique identification and functions as
logical address in a multidrop 1-Wire network environment
where multiple devices reside on a common 1-Wire bus
Maxim Integrated
│ 4
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
PARASITE POWER
1-Wire BUS
1-Wire
64-BIT
FUNCTION CONTROL
ROM ID
MEMORY
FUNCTION CONTROL
ADMINISTRATION
MEMORY
DS28E80
CRC-16
GENERATOR
PROTECTION
MEMORY
USER
MEMORY
WRITE BUFFER
Figure 1. DS28E80 Block Diagram
DS28E80
COMMAND
LEVEL:
AVAILABLE
COMMANDS:
DATA FIELD
AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
1-Wire ROM
FUNCTION COMMANDS
RESUME
RC-FLAG
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
RC-FLAG, OD-FLAG
64-BIT ROM ID, RC-FLAG, OD-FLAG
WRITE BLOCK
USER MEMORY, ADMINISTRATION
MEMORY, PROTECTION
MEMORY, WRITE BUFFER
USER MEMORY
DS28E80-SPECIFIC
MEMORY FUNCTION
COMMANDS
READ MEMORY
WRITE PROTECT BLOCK
READ BLOCK PROTECTION
READ REMAINING CYCLES
PROTECTION MEMORY
PROTECTION MEMORY
ADMINISTRATION MEMORY
Figure 2. Hierarchical Structure for 1-Wire Protocol
Maxim Integrated
│ 5
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
®
Using Cyclic Redundancy Checks with Maxim iButton
Products.
64-Bit ROM ID
Each DS28E80 contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code: 4Ah. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The CRC is generated using a
polynomial generator consisting of a shift register and
The shift register bits are initialized to 0. Then, starting
with the least-significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. Then the fixed
data is entered. After the last bit of the serial data has
been entered, the shift register contains the CRC value.
Shifting in the 8 bits of the CRC returns the shift register
to all 0s.
8
XOR gates as shown in Figure 4. The polynomial is X +
5
4
X + X + 1. Additional information about the 1-Wire CRC
is available in Application Note 27: Understanding and
MSb
LSb
8-BIT
CRC CODE
8-BIT FAMILY CODE
48-BIT SERIAL NUMBER
(4Ah)
MSb
LSb MSb
LSb MSb
LSb
Figure 3. 64-Bit ROM ID
8
5
4
POLYNOMIAL = X + X + X + 1
MSb
LSb
8TH
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
5TH
STAGE
6TH
STAGE
7TH
STAGE
STAGE
0
1
2
3
4
5
6
7
8
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 4. 8-Bit CRC Generator
Maxim Integrated
│ 6
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Memory Resources
Memory Function Commands
The memory of the DS28E80 consists of user memory,
administration memory, protection memory, a write buffer,
and a ROM ID. Table 1 shows the size, access mode, and
purpose of the various memory areas. Brackets around
an access mode indicate possible restrictions, such as
write protection.
Figure 6 describes the protocols to access the memory of
the DS28E80. Common to all functions is one parameter
byte that is to be transmitted after the command code. If
the parameter byte is valid, the master receives a 16-bit
CRC as confirmation. All subsequent communication
depends on the command issued. The user memory is
written in blocks of 8 bytes. The write buffer serves as
intermediate storage space when writing a memory block.
Each block can be programmed 8 times. The Write Protect
Block command is implemented to set the block protec-
tion. The Read Block Protection command allows reading
the block protection settings. The Read Remaining Cycles
command reports how many more write accesses are left
for each block. The data transmission sequence is least-
significant byte and least-significant bit first. The CRC-16
is always communicated in its inverted form.
The user memory (Figure 5) is organized as 31 blocks
of 8 bytes each, totaling of 248 bytes. Write protection is
activated through the Write Protect Block command. Once
a protection is activated, it cannot be reversed. The cur-
rently valid protection settings are read accessible through
the Read Block Protection command. See the Memory
Function Commands section for command flow details.
Table 1. Memory Resources
NAME
User Memory
SIZE (BYTES)
ACCESS MODE
PURPOSE
248
Read, (write)
Application-specific data storage
Read, internal read,
and write
Administration Memory
Protection Memory
32
Block erase/rewrite control
Read, internal read,
and write
4
Block write protection settings
Write Buffer (SRAM)
ROM ID
8
8
Write, internal read
Read
Intermediate data storage when writing to the memory
1-Wire network device address
BLOCK NUMBER (HEX)
BLOCK NUMBER (DECIMAL)
COMMENT
First block of user memory
Second block of user memory
00h
01h
0
1
02h to 1Ch
1Dh
2 to 28
29
User memory (continued)
1Eh
30
Highest block number of user memory
Figure 5. User Memory Map
Maxim Integrated
│ 7
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Write Block
The Write Block command writes an entire 8-byte memory block. This command affects the remaining cycles counter.
The data provided with the command is temporarily stored in the write buffer. The protocol allows writing multiple adjacent
blocks, up to the end of the memory in a single write block command flow. To detect transmission errors when issuing this
command, the DS28E80 generates and transmits a CRC after the parameter byte as well as after having received the
new block data. In case of an invalid CRC, the master aborts the command by issuing a 1-Wire reset. To start the transfer
to user memory, the master must transmit a release byte. After the programming time is over, the DS28E80 transmits a
CS byte. In case of an error (CS byte ≠ xAh) the master should end the command by issuing a reset.
WRITE BLOCK
Command Code
Parameter Byte
55h
Starting block number (Table 2)
•ꢀ The memory block must not be write-protected.
•ꢀ There must still be at least one write access left for the block.
Restrictions
•ꢀ Write one block.
•ꢀ Write multiple consecutive blocks.
Protocol Variations
•ꢀ Invalid parameter byte
•ꢀ The block is write protected.
•ꢀ Write accesses are exhausted.
•ꢀ Internal programming error
Error Conditions
CS Byte
xAh = Success; the upper nibble reports the number of remaining write accesses.
55h = The command failed because the block is write protected.
33h = The command failed because of write accesses exhausted.
EEh = The command failed because of an internal programming error.
First occurrence: Shifting (least-significant bit first) the command code and then the parameter byte into the
cleared CRC-16 generator.
CRCS
Computation
Subsequent occurrences: Shifting the new block data (8 bytes) into the cleared CRC-16 generator. The new
data is shifted into the CRC-16 generator in the same byte and bit sequence as sent by the master.
Table 2. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the location where the writing begins. Valid block numbers are 00000b
(start of memory) to 11110b (last block of user memory).
Maxim Integrated
│ 8
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Memory
The Read Memory command is used to read the user memory. The protocol allows reading multiple blocks up to the end
of the memory in a single read memory command flow. After the last byte of a block is read, the DS28E80 transmits a
CRC of the block data for the master to verify the data integrity. If the master continues reading, the DS28E80 transmits
data from the next block, and so on. After the last memory block is read and the master continues reading beyond the
CRC, the resulting data is FFh. The master can end the Read Memory command at any time by issuing a reset pulse.
READ MEMORY
Command Code
Parameter Byte
Restrictions
F0h
Starting block number (Table 3)
None. The command can be issued at any time.
•ꢀ Read one block.
•ꢀ Read multiple consecutive blocks.
Protocol Variations
Error Conditions
CS Byte
•ꢀ Invalid parameter byte
N/A
First occurrence: Shifting (lease-significant bit first) the command code and then the parameter byte
into the cleared CRC-16 generator.
Subsequent occurrences: Shifting the block data into the cleared CRC-16 generator. The shifting takes
place in the same bit and byte sequence as transmitted by the DS28E80.
CRCS Computation
Table 3. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the location where the reading begins. Valid block numbers are
00000b (start of memory) to 11110b (last block of user memory).
Maxim Integrated
│ 9
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Write Protect Block
The Write Protect Block command is used to protect a user memory block from changes. Once set, the protection cannot
be reset. To detect transmission errors when issuing this command, the DS28E80 generates and transmits a CRC after
the parameter byte. In case of an invalid CRC, the master aborts the command by issuing a 1-Wire reset. To activate the
protection the master must transmit a release byte. After the programming time is over, the DS28E80 transmits a CS byte.
WRITE PROTECT BLOCK
Command Code
Parameter Byte
Restrictions
C3h
Block to be write protected (Table 4)
None. The command can be issued at any time.
None
Protocol Variations
•ꢀ Invalid parameter byte
Error Conditions
•ꢀ The block is already write protected.
•ꢀ Internal programming error
AAh = Success
CS Byte
55h = The command failed because the block is already write protected.
EEh = The command failed because of an internal programming error.
Shifting (least-significant bit first) the command code and then the parameter byte PB into the cleared
CRC-16 generator.
CRCS Computation
Table 4. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the memory block to be write protected. Valid block
numbers are 00000b (start of memory) to 11110b (last block of user memory).
Maxim Integrated
│ 10
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Block Protection
The Read Block Protection command is used to read the protection status of a memory block. To detect transmission
errors when issuing this command, the DS28E80 generates and transmits a CRC after the parameter byte. After the
CRC, the master receives the protection status byte. If the block is unprotected, the code is 0Fh; the code for a protected
block is F0h. If the master continues reading, the DS28E80 transmits the protection status byte of the next block, and
so on. After the status byte of the last memory block is read and the master continues reading, it reads FFh bytes. The
master can end the Read Block Protection command at any time by issuing a reset pulse.
READ BLOCK PROTECTION
Command Code
Parameter Byte
Restrictions
AAh
Starting block number (Table 5)
None. The command can be issued at any time.
Protocol Variations
Error Conditions
CS Byte
None
•ꢀ Invalid parameter byte
N/A
Shifting (least-significant bit first) the command code and then the parameter byte into the cleared
CRC-16 generator.
CRCS Computation
Table 5. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the first memory block for which to read the protection.
Valid block numbers are 00000b (start of memory) to 11110b (last block of user memory).
Maxim Integrated
│ 11
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Remaining Cycles
The Read Remaining Cycles command is used to read how many more times the Write Block command can be executed
for a given memory block. The value for an unprogrammed memory block is 08h. The value 00h indicates that the write
cycles for the block are exhausted. To detect transmission errors when issuing this command, the DS28E80 generates
and transmits a CRC after the parameter byte. After the CRC, the master receives the remaining write cycles number for
the specific block. If the master continues reading, the DS28E80 transmits the remaining write cycles number of the next
block, and so on. After the remaining write cycles number of the last memory block is read and the master continues read-
ing, it reads FFh bytes. The master can end the Read Remaining Cycles command at any time by issuing a reset pulse.
READ REMAINING CYCLES
Command Code
Parameter Byte
Restrictions
A5h
Starting block number (Table 6)
None. The command can be issued at any time.
Protocol Variations
Error conditions
CS Byte
None
•ꢀ Invalid parameter byte
N/A
Shifting (least-significant bit first) the command code and then the parameter byte into the cleared
CRC-16 generator.
CRCS computation
Table 6. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the first memory block for which to read the remaining
cycles. Valid block numbers are 00000b (start of memory) to 11110b (last block of user memory).
Maxim Integrated
│ 12
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
55h
WRITE
BLOCK?
N
TO FIGURE 6b
MASTER Tx MEMORY
FUNCTION COMMAND
Y
FROM ROM
FUNCTIONS FLOW
CHART
MASTER Tx PARAMETER BYTE
N
P.- BYTE
VALID?
Y
MASTER Rx CRC-16 OF COMMAND,
PARAMETER BYTE
DS28E80 SETS BYTE COUNTER = 0,
SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Tx DATA BYTE
DS28E80 INCREMENTS
BYTE COUNTER
N
BYTE
COUNT = 7?
Y
DS28E80 INCREMENTS
BLOCK NUMBER, SETS
BYTE COUNTER = 0
MASTER Rx CRC-16
OF DATA BYTES
N
MASTER Tx
RELEASE?
Y
MASTER WAITS 1 X tPROG
MASTER Rx CS BYTE
Y
N
N
N
MASTER
Tx RESET?
BLOCK #
= 1Eh
Y
MASTER
Tx RESET?
MASTER Rx 1s
FROM FIGURE 6b
Y
TO ROM FUNCTIONS
FLOW CHART
Figure 6a. Memory Functions Flow Chart
Maxim Integrated
│ 13
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
FROM FIGURE 6a
TO FIGURE 6c
F0h
READ
N
MEMORY?
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BYTE COUNTER = 0, SETS
BLOCK NUMBER FROM PARAMETER BYTE
DS28E80
INCREMENTS
BYTE COUNTER
DS28E80 INCREMENTS
BLOCK NUMBER, SETS
BYTE COUNTER = 0
MASTER Rx
DATA BYTE
N
BYTE
COUNT = 7?
Y
MASTER Rx CRC – 16
OF DATA
N
END OF
MEMORY?
Y
N
MASTER
Tx RESET?
MASTER Rx 1s
TO FIGURE 6a
FROM FIGURE 6c
Y
Figure 6b. Memory Functions Flow Chart
Maxim Integrated
│ 14
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
C3h
FROM FIGURE 6b
TO FIGURE 6d
N
WRITE PROTECT
BLOCK?
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
N
Y
MASTER
Tx RELEASE?
MASTER WAITS
1 x tPROG
MASTER Rx
CS BYTE
N
MASTER
Tx RESET?
MASTER Rx 1s
Y
TO FIGURE 6b
FROM FIGURE 6d
Figure 6c. Memory Functions Flow Chart
Maxim Integrated
│ 15
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
AAh
READ BLOCK
FROM FIGURE 6c
TO FIGURE 6e
N
PROTECTION?
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Rx BLOCK
PROTECTION STATUS
DS28E80 INCREMENTS
BLOCK NUMBER
N
BLOCK #
= 1Eh?
Y
N
MASTER
Tx RESET?
MASTER Rx 1s
Y
FROM FIGURE 6e
TO FIGURE 6c
Figure 6d. Memory Functions Flow Chart
Maxim Integrated
│ 16
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
FROM FIGURE 6d
A5h
N
READ REMAIN.
CYCLES?
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Rx REMAINING
CYCLES COUNT
DS28E80 INCREMENTS
BLOCK NUMBER
N
BLOCK #
= 1Eh?
Y
N
MASTER
Tx RESET?
MASTER Rx 1s
Y
TO FIGURE 6d
Figure 6e. Memory Functions Flow Chart
Maxim Integrated
│ 17
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
The idle state for the 1-Wire bus is high. If for any reason
a transaction must be suspended, the bus must be left in
the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 16µs (over-
drive speed) or more than 120µs (standard speed), one or
more devices on the bus could be reset.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E80 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Transaction Sequence
The protocol for accessing the DS28E80 through the
1-Wire port is as follows:
•
•
•
•
Initialization
Hardware Configuration
ROM Function Command
Memory Function Command
Transaction Data
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or three-
state outputs. The 1-Wire port of the DS28E80 is open
drain with an internal circuit equivalent to that shown in
Figure 7.
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E80 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling section.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E80 supports both standard
and overdrive communication speed of 15.3kbps (max)
and 76kbps (max), respectively. The value of the pullup
resistor primarily depends on the 1-Wire pullup voltage,
network size, and load conditions. The DS28E80 requires
a pullup resistor of maximum 750Ω.
V
PUP
BUS MASTER
DS28E80 1-Wire PORT
R
PUP
DATA
Rx
Tx
Rx
I
Tx
L
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
100Ω MOSFET
Figure 7. Hardware Configuration
Maxim Integrated
│ 18
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion including an example.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E80 supports. All ROM function commands are 8
bits long. A list of these commands follows (Figure 8).
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64-bit ROM ID. If more
than one slave is present on the bus and, for example,
a read command is issued following the Skip ROM com-
mand, data collision occurs on the bus as multiple slaves
transmit simultaneously (open-drain pulldowns produce a
wired-AND result).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E80’s ROM ID (8-bit family code, unique 48-bit
serial number, and 8-bit CRC). This command can only
be used if there is a single slave on the bus. If more than
one slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The family code and
48-bit serial number as read by the master are unlikely to
match the CRC.
Resume Command [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the memory functions, similar to a
Skip ROM command. The only way to set the RC bit is
through successfully executing the Match ROM or Search
ROM command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume command.
Accessing another device on the bus clears the RC bit,
preventing two or more devices from simultaneously
responding to the Resume command.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM ID,
allows the bus master to address a specific DS28E80 on
a multidrop bus. Only the DS28E80 that exactly matches
the 64-bit ROM ID responds to the following memory or
SHA function command. All other slaves wait for a reset
pulse. This command can be used with a single or mul-
tiple devices on the bus.
Overdrive-Skip ROM [3Ch]
Search ROM [F0h]
On a single-drop bus this command can save time by
allowing the bus master to access the memory functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM sets the
DS28E80 in the overdrive mode (OD = 1). All communi-
cation following this command must occur at overdrive
speed until a reset pulse of minimum 480µs duration
resets all devices on the bus to standard speed (OD = 0).
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit of the ID number, starting with the least-
significant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To sub-
sequently address a specific overdrive-supporting device,
a reset pulse at overdrive speed must be issued followed
by a Match ROM or Search ROM command sequence.
This speeds up the time for the search process. If more
than one slave that supports overdrive is present on the
bus and the Overdrive-Skip ROM command is followed
by a read command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain pull-
downs produce a wired-AND result).
Maxim Integrated
│ 19
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
BUS MASTER Tx
RESET PULSE
FROM FIGURE 8b
FROM MEMORY FUNCTIONS
FLOW CHART (FIGURE 6)
OD
N
OD = 0
RESET PULSE?
Y
BUS MASTER Tx ROM
DS28E80 Tx
FUNCTION COMMAND
PRESENCE PULSE
TO FIGURE 8b
N
33h
READ ROM
COMMAND?
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
CCh
SKIP ROM
COMMAND?
N
N
N
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
DS28E80 Tx BIT 0
DS28E80 Tx BIT 0
MASTER Tx BIT 0
DS28E80 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
BIT 0
MATCH?
BIT 0
MATCH?
N
N
N
N
N
N
Y
Y
DS28E80 Tx BIT 1
DS28E80 Tx BIT 1
MASTER Tx BIT 1
DS28E80 Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
BIT 1
MATCH?
BIT 1
MATCH?
Y
Y
DS28E80 Tx BIT 63
DS28E80 Tx BIT 63
MASTER Tx BIT 63
DS28E80 Tx
CRC BYTE
MASTER Tx BIT 63
BIT 63
BIT 63
MATCH?
MATCH?
Y
Y
RC = 1
RC = 1
TO FIGURE 8b
FROM FIGURE 8b
TO MEMORY FUNCTIONS
FLOW CHART (FIGURE 6)
Figure 8a. ROM Functions Flow Chart
Maxim Integrated
│ 20
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
TO FIGURE 8a
A5h
RESUME
COMMAND?
3Ch
OVERDRIVE-SKIP
ROM ?
69h
OVERDRIVE-MATCH
ROM ?
FROM FIGURE 8a
N
N
N
Y
Y
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
Y
Y
MASTER Tx
RESET?
MASTER Tx BIT 0
N
(SEE NOTE)
OD = 0
Y
N
BIT 0
MATCH?
MASTER Tx
RESET?
N
Y
MASTER Tx BIT 1
(SEE NOTE)
OD = 0
BIT 1
MATCH?
N
Y
MASTER Tx BIT 63
(SEE NOTE)
OD = 0
BIT 63
MATCH?
N
Y
RC = 1
FROM FIGURE 8a
TO FIGURE 8a
NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE
SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
Figure 8b. ROM Functions Flow Chart (continued)
Maxim Integrated
│ 21
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
V
is relevant for the DS28E80 when determining a
Overdrive-Match ROM [69h]
ILMAX
logical level, not triggering any events.
The Overdrive-Match ROM command followed by a
64-bit ROM ID transmitted at overdrive speed allows the
bus master to address a specific DS28E80 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E80 that exactly matches the 64-bit ROM
ID responds to the subsequent memory function com-
mand. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480µs duration. The Overdrive-Match
ROM command can be used with a single or multiple
devices on the bus.
Figure 9 shows the initialization sequence required to
begin any communication with the DS28E80. A reset
pulse followed by a presence pulse indicates that the
DS28E80 is ready to receive data, given the correct ROM
and memory/control function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for t
+ t to compensate for the edge.
RSTL
F
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to V
PUP
through the pullup resistor. When the threshold V
is
TH
crossed, the DS28E80 waits and then transmits a pres-
ence pulse by pulling the line low. To detect a presence
pulse, the master must test the logical state of the 1-Wire
1-Wire Signaling
line at t
.
MSP
The DS28E80 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and pres-
ence pulse, write-zero, write-one, and read-data. Except
for the presence pulse, the bus master initiates all falling
edges. The DS28E80 communicates at overdrive speed
only.
Read/Write Time Slots
Data communication with the DS28E80 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 10 illustrates
the definitions of the write and read time slots.
To get from idle to active, the voltage on the 1-Wire line
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
needs to fall from V
below the threshold V . To get
PUP
TL
from active to idle, the voltage needs to rise from V
the threshold V , the DS28E80 starts its internal timing
ILMAX
TL
past the threshold V . The time it takes for the voltage
to make this rise is seen in Figure 9 as ε, and its dura-
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
TH
tion depends on the pullup resistor (R
) used and the
PUP
capacitance of the 1-Wire network attached. The voltage
MASTER Tx RESET PULSE
MASTER Rx PRESENCE PULSE
ε
t
MSP
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
REC
t
RSTL
t
F
t
RSTH
RESISTOR
MASTER
DS28E80
Figure 9. Reset/Presence pulse
Maxim Integrated
│ 22
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Master to Slave
Slave to Master
For a write-one time slot, the voltage on the data line must
A read-data time slot begins like a write-one time slot. The
have crossed the V
threshold before the write-one low
voltage on the data line must remain below V until the
TH
TL
time t
expires. For a write-zero time slot, the volt-
read low time t is expired. During the t window, when
RL RL
W1LMAX
age on the data line must stay below the V
threshold
responding with a 0, the DS28E80 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E80 does not hold the data
TH
until the write-zero low time t
expires. For the
W0LMIN
most reliable communication, the voltage on the data line
should not exceed V during the entire t or t
W1L
ILMAX
W0L
window. After the V
DS28E80 needs a recovery time t
threshold has been crossed, the
line low at all, and the voltage starts rising as soon as t
is over.
TH
RL
before it is ready
REC
for the next time slot.
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
F
t
SLOT
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
ε
t
t
REC
F
t
SLOT
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER
SAMPLING
WINDOW
V
TL
V
ILMAX
0V
δ
t
t
REC
F
t
SLOT
RESISTOR
MASTER
DS28E80
Figure 10. Read/Write Timing Diagram
Maxim Integrated
│
23
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
The sum of t + δ (rise time) on one side and the internal
timing generator of the DS28E80 on the other side define
Such reflections are visible as glitches or ringing on the
1-Wire communication line. Noise coupled onto the 1-Wire
RL
the master sampling window (t
which the master must perform a read from the data line.
For the most reliable communication, t should be as
to t
), in
line from external sources can also result in signal glitch-
ing. A glitch during the rising edge of a time slot can cause
a slave device to lose synchronization with the master and,
consequently, result in a Search ROM command coming to
a dead end or cause a device-specific function command
to abort. The DS28E80 uses a 1-Wire front-end with built-in
MSRMIN
MSRMAX
RL
short as permissible, and the master should read close
to but no later than t . After reading from the data
MSRMAX
line, the master must wait until t
is expired. This
SLOT
guarantees sufficient recovery time t
for the DS28E80
hysteresis at the low-to-high switching threshold V . If a
REC
TH
to get ready for the next time slot. Note that t
speci-
negative glitch crosses V
but does not go below V , it
TH TL
REC
fied herein applies only to a single DS28E80 attached to a
1-Wire line. For multidevice configurations, t must be
extended to accommodate the additional 1-Wire device
is not recognized (Figure 11).
REC
CRC Generation
input capacitance.
The 1-Wire port of the DS28E80 uses two different types
of CRCs. One CRC is an 8-bit type that is computed at
the factory and is stored in the most-significant byte of
the 64-bit ROM ID. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM ID and com-
pare it to the value read from the DS28E80 to determine
whether the ID number has been received error-free. The
equivalent polynomial function of this CRC is X + X + X
+ 1. This 8-bit CRC is received in the true (noninverted)
form.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire driv-
er). 1-Wire networks, therefore, are susceptible to noise of
various origins. Depending on the physical size and topol-
ogy of the network, reflections from end points and branch
points can add up or cancel each other to some extent.
8
5
4
V
PUP
V
TH
V
HY
V
TL
0V
Figure 11. Noise Suppression Scheme
16
15
2
POLYNOMIAL = X + X + X + 1
1ST
2ND
3RD
4TH
5TH
6TH
7TH
8TH
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
STAGE
0
1
2
3
4
5
6
7
X
X
X
X
X
X
X
X
9TH
STAGE
10TH
STAGE
11TH
STAGE
12TH
STAGE
13TH
STAGE
14TH
STAGE
15TH
STAGE
16TH
STAGE
8
9
10
11
12
13
14
15
16
CRC OUTPUT
X
X
X
X
X
X
X
X
X
INPUT DATA
Figure 12. CRC-16 Generator
Maxim Integrated
│ 24
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
16
15
2
The other CRC is a 16-bit type, generated according to the standardized CRC-16 polynomial function X + X + X +
1. This CRC is used for error detection with all memory function commands. In contrast to the 8-bit CRC, the 16-bit CRC
is always communicated in the inverted form. A CRC generator inside the DS28E80 chip (Figure 12) calculates a new
16-bit CRC, as shown in the memory function flowchart (Figure 6). The bus master compares the CRC value read from
the device to the one it calculates from the data and decides whether to continue with an operation or to start over again.
1-Wire Communication Examples
See Table 7 and Table 8 for the 1-Wire Communication legend and the data direction color codes.
Table 7. 1-Wire Communication—Legend
SYMBOL
WB
DESCRIPTION
Command “Write Block”, 55h
RM
Command “Read Memory”, F0h
Command “Write Protect Block”, C3h
Command “Read Block Protection”, AAh
WPB
RBP
RRC
RST
PD
Command “Read Remaining Cycles”, A5h
Reset pulse
Presence detect pulse
Select
PB
Any communication that satisfies the network functions
Parameter byte, always follows the command code
Slave-generated CRC-16, always transmitted inverted, LS-bit first
Command Success indicator
CRCS
CS
Byte sent by the master to start a write activity in the slave. Byte can be any value from 00h
to FFh.
Release
<n bytes>
Transfer of n bytes
FF loop
Indefinite loop where the bus master reads FF bytes
Table 8. Data Direction Color Codes
MASTER TO SLAVE
SLAVE TO MASTER
MASTER WAITS (1-Wire IDLE HIGH)
1-Wire Communication Examples
WRITE BLOCK
SUCCESSFUL WRITING
RST
PD
SELECT
WB
PB
CRCS
CRCS
<8 bytes>
<8 bytes>
CRCS
RELEASE
WAIT tPROG
CS = xAh
RST
RST
REPEAT FOR ADDITIONAL BLOCKS
WRITING FAILS WITH ERROR
WB
CRCS
RST
PD
SELECT
PB
RELEASE
WAIT tPROG
CS ≠ xAh
FAILURE (INVALID PARAMETER BYTE)
RST PD SELECT WB PB = 1Fh
FF LOOP
Maxim Integrated
│ 25
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
READ MEMORY
STARTING AT BLOCK NUMBER 05h, READING 3 BYTES
RST PD SELECT RM PB = 05h CRCS
<3 bytes>
<8 bytes>
RST
STARTING AT BLOCK NUMBER 12h, READING 2 BLOCKS
RST
PD
SELECT
RM
PB = 12h
CRCS
CRCS
<8 bytes>
CRCS
RST
REPEAT FOR ADDITIONAL BLOCKS
FAILURE (INVALID PARAMETER BYTE)
RST PD SELECT RM PB = 1Fh
FF LOOP
WRITE PROTECT BLOCK
SUCCESSFUL WRITE-PROTECTING MEMORY BLOCK 10
RST PD SELECT WPB PB = 10h CRCS
h
CS = AAh
RST
RELEASE
WAIT tPROG
WRITING FAILS BECAUSE THE BLOCK IS ALREADY WRITE PROTECTED.
RST PD SELECT WPB PB CRCS RELEASE WAIT tPROG
CS = 55h
RST
FAILURE (INVALID PARAMETER BYTE)
RST PD SELECT WPB PB = 1Fh
FF LOOP
READ BLOCK PROTECTION
READ THE PROTECTION OF MEMORY BLOCKS 10h TO 12h
RST
PD
SELECT
RBP
PB = 10h
CRCS
<3 bytes>
RST
FAILURE (INVALID PARAMETER BYTE
)
RST PD SELECT RBP PB = 1Fh
FF LOOP
READ REMAINING CYCLES
READ THE REMAINING CYCLES OF MEMORY BLOCKS 10
h
TO 15
h
PD
SELECT
RRC
PB = 10h
CRCS
<6 bytes>
RST
RST
FAILURE (INVALID PARAMETER BYTE)
RST PD SELECT RRC PB = 1Fh
FF LOOP
Maxim Integrated
│ 26
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
6 TDFN
6 TDFN (2.5k pcs)
DS28E80Q+U
DS28E80Q+T
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 TDFN
T633MK+1
21-0137
90-0058
Maxim Integrated
│ 27
www.maximintegrated.com
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
9/14
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 28
相关型号：
©2020 ICPDF网 联系我们和版权申明