MAX1087ETA+ [MAXIM]
ADC, Successive Approximation, 10-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, PDSO8, 3 X 3 MM, 0.8 MM HEIGHT, LEAD FREE, MO-229WEEC, TDFN-8;
| 型号： | MAX1087ETA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, PDSO8, 3 X 3 MM, 0.8 MM HEIGHT, LEAD FREE, MO-229WEEC, TDFN-8 |
| 文件： | 总15页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2036; Rev 0; 5/01
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
General Description
Features
The MAX1086–MAX1089 are low-cost, micropower, ser-
ial output 10-bit analog-to-digital converters (ADCs)
available in a tiny 8-pin SOT23. The MAX1086/MAX1088
operate with a single +5V supply. The MAX1087/MAX1089
operate with a single +3V supply. The devices feature a
successive-approximation ADC, automatic shutdown,
fast wake-up (1.4µs), and a high-speed 3-wire inter-
o Single-Supply Operation
+3V(MAX1087/MAX1089)
+5V(MAX1086/MAX1088)
o AutoShutdown Between Conversions
o Low Power
200µA at 150ksps
130µA at 100ksps
65µA at 50ksps
13µA at 10ksps
1.5µA at 1ksps
0.2µA in Shutdown
face. Power consumption is only 0.5mW (V
= +2.7V)
DD
at the maximum sampling rate of 150ksps.
Autoshutdown™ (0.1µA) between conversions results in
reduced power consumption at slower throughput
rates.
The MAX1086/MAX1087 provide 2-channel, single-
ended operation and accept input signals from 0 to
o True-Differential Track/Hold, 150kHz Sampling Rate
V
. The MAX1088/MAX1089 accept true-differential
REF
inputs ranging from 0 to V
. Data is accessed using
o Software-Configurable Unipolar/Bipolar
Conversion (MAX1088/MAX1089 only)
o SPI, QSPI, MICROWIRE–Compatible Interface for
DSPs and Processors
REF
an external clock through the 3-wire SPI™, QSPI™, and
MICROWIRE™–compatible serial interface. Excellent
dynamic performance, low-power, ease of use, and
small package size, make these converters ideal for
portable battery-powered data acquisition applications,
and for other applications that demand low power con-
sumption and minimal space.
o Internal Conversion Clock
o 8-Pin SOT23 Package
Ordering Information
Applications
Low Power Data Acquisition
Portable Temperature Monitors
Flowmeters
TEMP.
RANGE
PIN-
PACKAGE
TOP
MARK
PART
MAX1086EKA-T
MAX1087EKA-T
MAX1088EKA-T
MAX1089EKA-T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 SOT23
8 SOT23
8 SOT23
8 SOT23
AAEZ
AAEV
AAFB
AAEX
Touch Screens
Pin Configuration
TOP VIEW
V
1
2
3
4
8
7
6
5
SCLK
DOUT
CNVST
REF
DD
AIN1 (AIN+)
AIN2 (AIN-)
GND
MAX1086
MAX1087
MAX1088
MAX1089
SOT23-8
( ) ARE FOR THE MAX1088/MAX1089
AutoShutdown is a trademark of Maxim Integrated Products.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
ABSOLUTE MAXIMUM RATINGS
DD
CNVST, SCLK, DOUT to GND......................-0.3V to (V +0.3V)
REF, AIN1(AIN+), AIN2(AIN-) to GND..........-0.3V to (V +0.3V)
V
to GND.............................................................-0.3V to +6V
Operating Temperature Ranges.........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23(derate 9.70mW/°C above T = +70°C) ....777mW
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V, V
= +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, V
= +4.096V for MAX1086/MAX1088,
DD
REF
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. T = T
to T
unless otherwise
MAX,
SCLK
A
MIN
noted. Typical values at T = +25°C.)
A
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
1.0
1.0
1.0
2.0
DNL
No missing codes over temperature
LSB
0.5
1.0
0.8
0.1
0.1
0.1
LSB
Gain Error (Note 3)
LSB
Gain Temperature Coefficient
Channel-to-Channel Offset
ppm/°C
LSB
Channel-to-Channel Gain Matching
Input Common-Mode Rejection
LSB
CMR
V
= 0V to V ; zero scale input
mV
CM
DD
DYNAMIC SPECIFICATIONS: (f (sine-wave) = 10kHz, V = 4.096Vp-p for MAX1086/MAX1088 or V = 2.5V
IN
IN
IN
PP
for MAX1087/MAX1089, 150ksps, f
= 8MHZ, AIN- = GND for MAX1088/MAX1089)
SCLK
Signal to Noise Plus Distortion
SINAD
61
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-70
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time
SFDR
70
1
dB
MHz
kHz
-3dB point
SINAD>56dB
100
t
3.7
1.4
µs
µs
CONV
T/H Acquisition Time
Aperture Delay
t
ACQ
30
ns
Aperture Jitter
<50
ps
Maximum Serial Clock Frequency
Duty Cycle
f
8
MHz
%
SCLK
30
70
2
_______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V, V
= +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, V
= +4.096V for MAX1086/MAX1088,
DD
REF
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle), AIN- = GND for MAX1088/MAX1089. T = T
to T
unless otherwise
MAX,
SCLK
A
MIN
noted. Typical values at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 4)
V
-V
/2
V
/2
REF
REF
Input Leakage Current
Channel not selected or conversion stopped
0.01
34
1
µA
Input Capacitance
pF
EXTERNAL REFERENCE INPUT
V
DD
Input Voltage Range
V
I
1.0
V
REF
+50mV
V
V
= +2.5V at 150ksps
16
30
45
1
REF
REF
Input Current
µA
= +4.096V at 150ksps
26
REF
Acquisition/Between conversions
DIGITAL INPUTS/OUTPUT (SCLK, CNVST, DOUT)
0.01
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
V
0.8
0.1
V
V
IL
V
V
-1
DD
IH
I
L
µA
pF
V
C
15
IN
I
I
= 2mA
= 4mA
0.4
0.8
SINK
SINK
Output Low Voltage
Output High Voltage
V
OL
V
V
DD
-0.5
V
I
= 1.5mA
SOURCE
V
OH
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
I
CNVST = GND
CNVST = GND
10
µA
L
C
15
pF
OUT
MAX1086/MAX1088
4.75
2.7
5.0
3.0
245
150
15
5.25
3.6
Positive Supply Voltage
Positive Supply Current
Positive Supply Rejection
V
V
DD
MAX1087/MAX1089
f
f
=150ksps
=100ksps
=10ksps
=1ksps
350
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
V
V
= +3V
= +5V
DD
DD
f
f
f
f
f
f
2
I
=150ksps
=100ksps
=10ksps
=1ksps
320
215
22
400
µA
mV
DD
2.5
0.2
0.1
0.1
Shutdown
5
V
V
= 5V 5%; full-scale input
1.0
1.2
DD
DD
PSR
= +2.7V to +3.6V; full-scale input
_______________________________________________________________________________________
3
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
TIMING CHARACTERISTICS (Figures 1 and 2)
(V
= +2.7V to +3.6V, V
= +2.5V for MAX1087/MAX1089, or V
= +4.75V to +5.25V, V
= +4.096V for MAX1086/MAX1088,
DD
REF
DD
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. T = T
to T
unless otherwise
MAX,
SCLK
A
MIN
noted. Typical values at T = +25°C.)
A
PARAMETERS
SCLK Pulse Width High
SCLK Pulse Width Low
SYMBOL
CONDITIONS
MIN
38
TYP
MAX
UNITS
ns
t
CH
t
38
ns
CL
SCLK Fall to DOUT Transition
SCLK Rise to DOUT Disable
CNVST Rise to DOUT Enable
CNVST Fall to MSB Valid
CNVST Pulse Width
t
C
C
C
C
= 30pF
= 30pF
= 30pF
= 30pF
60
500
80
ns
DOT
DOD
LOAD
LOAD
LOAD
LOAD
t
100
30
ns
t
t
ns
DOE
DOV
CSW
3.7
µs
t
ns
Note 1: Unipolar input.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: The absolute input range for the analog inputs is from GND to V
.
DD
• • •
CNVST
SCLK
t
CH
t
CSW
t
CL
• • •
• • •
t
t
DOD
DOE
t
DOT
HIGH-Z
HIGH-Z
DOUT
Figure 1. Detailed Serial-Interface Timing Sequence
V
DD
6kΩ
DOUT
DOUT
6kΩ
C
C
L
L
GND
GND
a) HIGH -Z TO V , V TO V , AND V TO HIGH -Z
a) HIGH -Z TO V , V TO V , AND V TO HIGH -Z
OH OL
OH
OH
OL OH
OL
OL
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
4
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Typical Operating Characteristics
(V
= +3.0V, V
= +2.5V for MAX1087/MAX1089 or V
= +5.0V, V
= +4.096V for MAX1086/MAX1088, 0.1µF capacitor at
DD
REF
DD
REF
REF, f
= 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/1089, T = +25°C, unless otherwise noted.)
SCLK
A
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.0
1.0
0.8
0.6
0.4
0.2
1.0
0.8
0.6
0.4
0.2
MAX1087/MAX1089
MAX1086/MAX1088
MAX1087/MAX1089
0.8
0.6
0.4
0.2
0
0
0
-0.2
-0.2
-0.2
-0.4
-0.6
-0.8
-1.0
-0.4
-0.6
-0.8
-1.0
-0.4
-0.6
-0.8
-1.0
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SUPPLY CURRENT
vs. SAMPLING RATE
SUPPLY CURRENT
vs. SAMPLING RATE
1000
100
10
1000
100
10
1.0
0.8
0.6
0.4
0.2
MAX1086/MAX1088
MAX1087/MAX1089
MAX1086/MAX1088
0
-0.2
-0.4
-0.6
-0.8
-1.0
1
1
0.1
0.001
0.1
0.001
1.0
10
1000
0
200
400
600
800 1000 1200
1.0
10
1000
OUTPUT CODE
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
0.50
0.45
380
330
280
230
180
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
_______________________________________________________________________________________
5
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Typical Operating Characteristics (continued)
(V
= 3.0V, V
= 2.5V for MAX1087/MAX1089 or V
= 5.0V, V
= +4.096V for MAX1086MAX1088, 0.1µF capacitor at REF,
REF
DD
REF
DD
f
= 8MHz, (50% Duty Cycle), AIN- = GND for MAX1088/89, T = +25°C, unless otherwise noted.)
SCLK
A
SHUTDOWN CURRENT
SUPPLY CURRENT
vs. TEMPERATURE
vs. TEMPERATURE
OFFSET ERROR
vs. TEMPERATURE
300
250
200
150
100
50
1.00
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
0.60
-0.80
-1.00
380
330
280
230
180
0
-40
-20
0
20
40
60
80
-40 -20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
-40 -20
0
20
40
60
80
V
TEMPERATURE (°C)
DD
GAIN ERROR
vs. SUPPLY VOLTAGE
FFT PLOT (SINAD)
1.0
0.8
20.00
0.00
0.6
-20.00
-40.00
-60.00
-80.00
-100.00
-120.00
-140.00
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
0
15
30
45
60
V
DD
FREQUENCY (kHz)
6
_______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Pin Description
NAME
PIN
FUNCTION
MAX1086 MAX1088
MAX1087 MAX1089
Positive Supply Voltage. +2.7V to +3.6V (MAX1087/MAX1089); +4.75V to +5.25V
(MAX1086/MAX1088). Bypass with a 0.1µF capacitor to GND.
1
2
3
4
5
V
V
DD
DD
AIN1
AIN2
GND
REF
AIN+
AIN-
GND
REF
Analog Input Channel 1 (MAX1086/MAX1087) or Positive Analog Input (MAX1088/MAX1089)
Analog Input Channel 2 (MAX1086/MAX1087) or Negative Analog Input (MAX1088/MAX1089)
Ground
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
Conversion Start. A rising edge powers-up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1086/MAX1087) or input polarity (MAX1088/MAX1089).
6
CNVST
CNVST
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high-
impedance once data has been fully clocked out.
7
8
DOUT
SCLK
DOUT
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
The serial interface provides easy interfacing to micro-
Detailed Description
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1086/MAX1087 (2–channels, sin-
gle-ended) and the MAX1088/MAX1089 (1–channel,
true-differential).
The MAX1086–MAX1089 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and an on-chip track-and-hold (T/H)
structure to convert an analog signal into a 10-bit digital
result.
True-Differential Analog Input Track/Hold
The equivalent circuit of Figure 4 shows the
MAX1086–MAX1089’s input architecture which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1086/
MAX1087) or AIN+ (MAX1088/MAX1089). The negative
input capacitor is connected to GND (MAX1086/
MAX1087) or AIN- (MAX1088/MAX1089). The T/H
enters its hold mode on the falling edge of CNVST and
the difference between the sampled positive and nega-
tive input voltages is converted. The time required for
the T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
MAX1086–MAX1089
OSCILLATOR
CNVST
SCLK
INPUT SHIFT
REGISTER
CONTROL
AIN1
(AIN+)
10-BIT
SAR
ADC
DOUT
T/H
AIN2
(AIN-)
REF
period of time. The acquisition time, t , is the maxi-
ACQ
mum time needed for the signal to be acquired, plus
the power-up time. It is calculated by the following
equation:
(
) ARE FOR MAX1088/MAX1089
Figure 3. Simplified Functional Diagram
t
= 7 x (R + R ) x 24pF + t
S IN PWR
ACQ
_______________________________________________________________________________________
7
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, AIN2 will be selected for the next
conversion.
REF
GND
DAC
AIN2
AIN1(AIN+)
CIN+
COMPARATOR
+
Selecting Unipolar or Bipolar Conversions
(MAX1088/MAX1089)
HOLD
Initiate true-differential conversions with the
MAX1088/MAX1089’s unipolar and bipolar modes,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
-
CIN-
RIN-
RIN+
GND(AIN-)
exceed AIN- by up to V
. The output format is
REF
HOLD
HOLD
straight binary. In bipolar mode, either input can
TRACK
exceed the other by up to V
/2. The output format is
REF
V
/2
DD
*( ) APPLIES TO MAX1088/1089
two’s complement.
Note: In both modes, AIN+ and AIN- must not exceed
DD
than 50mV.
Figure 4. Equivalent Input Circuit
V
by more than 50mV or be lower than GND by more
where R = 1.5kΩ, R is the source impedance of the
IN
S
If unipolar mode is desired (Figure 5a), drive CNVST
high to power-up the ADC and place the T/H in track
mode with AIN+ and AIN- connected to the input
input signal, and t
= 1µs is the power-up time of the
PWR
device.
Note: t
is never less than 1.4µs and any source
capacitors. Hold CNVST high for t
to fully acquire
ACQ
ACQ
impedance below 300Ω does not significantly affect the
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC will then perform a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
Be sure to clock out all 12 bits (the 10-bit result plus
two sub-bits) of data before driving CNVST high for the
next conversion. If all 12 bits of data are not clocked
out before CNVST is driven high, bipolar mode will be
selected for the next conversion.
ADC‘s AC performance. A high impedance source can
be accommodated either by lengthening t
or by
ACQ
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
Selecting AIN1 or AIN2
(MAX1086/MAX1087)
Select between the MAX1086/MAX1087’s two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power-up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This will place the T/H in track
mode with AIN+ and AIN- connected to the input
t
to fully acquire the signal. Drive CNVST low to
ACQ
capacitors. Now hold CNVST high for t
to fully
ACQ
place the T/H in hold mode. The ADC will then perform
a conversion and shutdown automatically. The MSB is
available at DOUT after 3.7µs. Data can then be
clocked out using SCLK. Be sure to clock out all 12 bits
of data (the 10-bit result plus two sub-bits) before dri-
ving CNVST high for the next conversion. If all 12 bits of
data are not clocked out before CNVST is driven high,
AIN2 will be selected for the next conversion.
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
DOUT after 3.7µs. Data can then be clocked out using
SCLK. If all 12 bits of data are not clocked out before
CNVST is driven high, bipolar mode will be selected for
the next conversion.
Input Bandwidth
The ADCs input tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This will power-up the ADC and place the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for t
to fully
ACQ
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC will then perform a conversion
and shutdown automatically. The MSB is available at
8
_______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
t
CONV
t
ACQ
CNVST
1
4
8
12
SCLK
DOUT
HIGH-Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B4
B3
B2
B1
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5a. Single Conversion AIN1 vs. GND (MAX1086/MAX1087), unipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
t
CONV
t
ACQ
CNVST
1
4
8
12
SCLK
DOUT
HIGH-Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B4
B3
B2
B1
S1
S0
HIGH-Z
SAMPLING INSTANT
Figure 5b. Single Conversion AIN2 vs. GND (MAX1086/MAX1087), bipolar mode AIN+ vs. AIN- (MAX1088/MAX1089)
Analog Input Protection
Internal Clock
The MAX1086–MAX1089 operate from an internal oscilla-
tor, which is accurate within 10% of the 4MHz specified
clock rate. This results in a worse case conversion time
of 3.7µs. The internal clock releases the system micro-
processor from running the SAR conversion clock and
allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
8MHz.
Internal protection diodes which clamp the analog input
to V
and GND allow the analog input pins to swing
DD
from GND - 0.3V to V
+ 0.3V without damage. Both
DD
DD
inputs must not exceed V
by more than 50mV or be
lower than GND by more than 50mV for accurate conver-
sions. If an off-channel analog input voltage exceeds
the supplies, limit the input current to 2mA.
_______________________________________________________________________________________
9
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Output Data Format
Transfer Function
Figures 5a and 5b illustrate the conversion timing for
Figure 6 shows the unipolar transfer function for the
the MAX1086–MAX1089. The 10-bit conversion result is
MAX1086–MAX1089. Figure 7 shows the bipolar transfer
output in MSB first format, followed by two sub-bits (S1
function for the MAX1088/MAX1089. Code transitions
and S0). Data on DOUT transitions on the falling edge
occur halfway between successive-integer LSB values.
of SCLK. All 12-bits must be clocked out before CNVST
transitions again. For the MAX1088/MAX1089, data is
Connection to Standard Interfaces
straight binary for unipolar mode and two’s comple-
ment for bipolar mode. For the MAX1086/MAX1087,
data is always straight binary.
The MAX1086–MAX1089 feature a serial interface that is
fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the seri-
al clock for the ADCs. Select a clock frequency up to
8MHz.
Applications Information
Automatic Shutdown Mode
With CNVST low, the MAX1086–MAX1089 defaults to an
AutoShutdown state (<0.2µA) after power-up and
between conversions. After detecting a rising edge on
CNVST, the part powers up, sets DOUT low and enters
track mode. After detecting a falling-edge on CNVST, the
device enters hold mode and begins the conversion. A
maximum of 3.7µs later, the device completes conver-
sion, enters shutdown and MSB is available at DOUT.
How to Perform a Conversion
1) Use a general purpose I/O line on the CPU to hold
CNVST low between conversions.
2) Drive CNVST high to acquire AIN1(MAX1086/
MAX1087) or unipolar mode (MAX1088/MAX1089).
To acquire AIN2(MAX1086/MAX1087) or bipolar
mode (MAX1088/MAX1089), drive CNVST low and
high again.
External Reference
An external reference is required for the MAX1086–
MAX1089. Use a 0.1µF bypass capacitor for best per-
formance. The reference input structure allows a volt-
3) Hold CNVST high for 1.4µs.
4) Drive CNVST low and wait approximately 3.7µs for
conversion to complete. After 3.7µs, the MSB is
available at DOUT.
age range of +1V to V
+ 50mV.
DD
5) Activate SCLK for a minimum of 12 rising clock
edges. DOUT transitions on SCLK’s falling edge
OUTPUT CODE
MAX1088/MAX1089
OUTPUT CODE
MAX1086–
MAX1089
V
REF
2
FS
=
011 . . . 111
011 . . . 110
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
ZS = 0
-FS =
-V
REF
2
11 . . . 101
000 . . . 010
000 . . . 001
000 . . . 000
V
REF
1LSB =
1024
FS = V
REF
111 . . . 111
111 . . . 110
111 . . . 101
ZS = GND
V
REF
1LSB =
1024
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
- FS
+FS - 1LSB
0
1
2
3
FS
INPUT VOLTAGE (LSB)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
≤
*V
V
/ 2 *V = (AIN+) - (AIN-)
COM
REF IN
Figure 7. Bipolar Transfer Function
10 ______________________________________________________________________________________
Figure 6. Unipolar Transfer Function
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
and is available in MSB-first format. Observe the
SCLK to DOUT valid timing characteristic. Clock
data into the µP on SCLK’s rising-edge.
SCLK’s rising edge. The first 10 bits are the data and
the next two bits are sub-bits (S1, S0). DOUT then
goes high impedance (Figure 9b).
PIC16 and SSP Module and
PIC17 Interface
SPI and MICROWIRE Interface
When using SPI interface (Figure 8a) or MICROWIRE
(Figure 8a and 8b), set CPOL = CPHA = 0. Two 8-bit
readings are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
SCLK’s rising edge. The first 8-bit data stream contains
the first 8-bits of DOUT starting with the MSB. The sec-
ond 8-bit data stream contains the remaining two result
bits (B1, B0) and two trailing sub-bits (S1, S0). DOUT
then goes high impedance.
The MAX1086–MAX1089 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master. This is done by initializing its syn-
chronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit readings (Figure
10b) are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µC on
SCLK’s rising edge. The first 8-bit data stream contains
QSPI Interface
Using the high-speed QSPI interface (Figure 9a) with
CPOL = 0 and CPHA = 0, the MAX1086–MAX1089
support a maximum f
of 8MHz. One 8- to16-bit
SCLK
reading is necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µP on
I/O
SCK
CNVST
SCLK
I/O
SK
SI
CNVST
SCLK
MISO
DOUT
DOUT
V
DD
MICROWIRE
SPI
MAX1086–
MAX1089
MAX1086–
MAX1089
SS
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
Table 1. Detailed SSPCON Register Content
MAX1086–MAX1089
CONTROL BIT
SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
SETTINGS
WCOL
SSPOV
Bit 7
Bit 6
X
X
Write Collision Detection Bit
Receive Overflow Detect Bit
Synchronous Serial Port Enable Bit.
SSPEN
Bit 5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
f
= f
CLK OSC
/ 16.
X = Don’t care
______________________________________________________________________________________ 11
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
CNVST
1ST BYTE READ
4
2ND BYTE READ
12
1
8
16
SCLK
DOUT
HIGH-Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B4
B3
B2
B1
S1
S0
SAMPLING INSTANT
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
the first eight data bits starting with the MSB. The sec-
ond 8-bit data stream contains the remaining bits, D1
through D0, and the two sub-bits S1 and S0.
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
High-frequency noise in the power supply (V ) may
DD
CS
SCK
CNVST
SCLK
degrade the performance of the ADC’s fast comparator.
Bypass V
to the star ground with a 0.1µF capacitor,
DD
MISO
DOUT
located as close as possible to the MAX1086–MAX1089s
power supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
V
DD
QSPI
MAX1086–
MAX1089
SS
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
MAX1086–MAX1089
CONTROL BIT
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
SETTINGS
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
SMP
Bit 7
0
CKE
D/A
P
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
X
X
X
X
X
X
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
X = Don’t care
12 ______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
CNVST
1
4
8
12
16
SCLK
DOUT
HIGH-Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B4
B3
B2
B1
S1
S0
SAMPLING INSTANT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
Definitions
Integral Nonlinearity
V
V
DD
DD
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The sta-
tic linearity parameters for the MAX1086–MAX1089 are
measured using the endpoint method.
SCLK
DOUT
SCK
SDI
I/O
CNVST
PIC16/PIC17
MAX1086–
MAX1089
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
CNVST
1ST BYTE READ
2ND BYTE READ
1
4
8
12
16
SCLK
DOUT
HIGH-Z
B9
MSB
B0
LSB
B8
B7
B6
B5
B4
B3
B2
B1
S1
S0
SAMPLING INSTANT
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
______________________________________________________________________________________ 13
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SUPPLIES
SINAD (dB) = 20 ✕ log (Signal
/ Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
+3V OR +5V
V
= +5V/+3V
GND
LOGIC
R* = 5Ω
0.1µF
ENOB = (SINAD - 1.76) / 6.02
GND
V
+5V/+3V DGND
DD
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DIGITAL
CIRCUITRY
MAX1086–
MAX1089
*OPTIONAL
2
2
2
2
THD = 20 × log
V
+ V + V + V
/ V
1
2
3
4
5
Figure 11. Power-Supply and Grounding Connections
where V is the fundamental amplitude, and V through
5
monics.
1
2
Aperture Definitions
V are the amplitudes of the 2nd- through 5th-order har-
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples. Aperture delay (t ) is
AD
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-to-
digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N-bits):
Chip Information
TRANSISTOR COUNT: 6922
PROCESS: BiCMOS
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
14 ______________________________________________________________________________________
150ksps, 10-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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