MAX11008BETM+ [MAXIM]
Dual RF LDMOS Bias Controller with Nonvolatile Memory; 双通道RF LDMOS偏置控制器，带有非易失存储器
| 型号： | MAX11008BETM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual RF LDMOS Bias Controller with Nonvolatile Memory |
| 文件： | 总67页 (文件大小：664K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4371; Rev 0; 11/08
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
General Description
Features
The MAX11008 controller biases RF LDMOS power
devices found in cellular base stations and other wire-
less infrastructure equipment. Each controller includes
a high-side current-sense amplifier with programmable
gains of 2, 10, and 25 to monitor the LDMOS drain cur-
rent over a range of 20mA to 5A. The MAX11008 sup-
ports up to two external diode-connected transistors to
monitor the LDMOS temperatures while an internal tem-
perature sensor measures the local die temperature. A
12-bit successive-approximation register (SAR) analog-
to-digital converter (ADC) converts the analog signals
from the programmable-gain amplifiers (PGAs), exter-
nal temperature sensors, internal temperature measure-
ment, and two additional auxiliary inputs. The
MAX11008 automatically adjusts the LDMOS bias volt-
ages by applying temperature, AIN, and/or drain cur-
rent samples to data stored in lookup tables (LUTs).
♦ On-Chip 4Kb EEPROM for Storing LDMOS Bias
Characteristics
♦ Integrated High-Side Current-Sense PGA with
Gain of 2, 10, or 25
♦
0ꢀ.5ꢁ Accuracꢂ for Sense ꢃoꢄtage Between
+.5mꢃ and +1250mꢃ
♦ Fuꢄꢄ-Scaꢄe Sense ꢃoꢄtage
+100mꢃ with a Gain of 25
+250mꢃ with a Gain of 10
+1250mꢃ with a Gain of 2
♦ Common-Mode Range, LDMOS Drain ꢃoꢄtage:
+5ꢃ to +32ꢃ
♦ Adjustabꢄe Low-Noise 0 to Aꢃ
Output Gate
DD
Bias ꢃoꢄtage Range
The MAX11008 includes two gate-drive channels, each
consisting of a 12-bit DAC to generate the positive gate
voltage for biasing the LDMOS devices. Each gate-
drive output supplies up to 2mA of gate current. The
gate-drive amplifier is current-limited to 25mA and
features a fast clamp to AGND.
♦ Fast Cꢄamp to AGND for LDMOS Protection
♦ 12-Bit DAC Controꢄ of Gate with Temperature
♦ Internaꢄ Die Temperature Measurement
♦ 2-Channeꢄ Externaꢄ Temperature Measurement
through Remote Diodes
The MAX11008 contains 4Kb of on-chip, nonvolatile
EEPROM organized as 256 bits x 16 bits to store LUTs
and register information. The device operates from
either a 4-wire 16MHz SPI™-/MICROWIRE™-compati-
ble or an I2C-compatible serial interface.
♦ Internaꢄ 12-Bit ADC Measurement for
Temperature, Current, and ꢃoꢄtage Monitoring
♦ User-Seꢄectabꢄe Seriaꢄ Interface
400kHz/1ꢀ.MHz/3ꢀ4MHz I2C-Compatibꢄe Interface
16MHz SPI-/MICROWIRE-Compatibꢄe Interface
The MAX11008 operates from a +4.75V to +5.25V ana-
log supply with a typical supply current of 2mA, and a
+2.7V to +5.25V digital supply with a typical supply of
3mA. The device is packaged in a 48-pin, 7mm x 7mm,
thin QFN package and operates over the extended
(-40°C to +85°C) temperature range.
Applications
Ordering Information
Cellular Base Stations
Microwave Radio Links
Feed-Forward Power Amps
Transmitters
TEMP
ERROR (°C)
PART
PIN-PACKAGE
MAX11008BETM+
48 TQFN-EP*
3
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Industrial Process Control
Note: The device is specified over the -40°C to +85°C operating
temperature range.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, deꢄiverꢂ, and ordering information, pꢄease contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at wwwꢀmaxim-icꢀcomꢀ
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
ABSOLUTE MAXIMUM RATINGS
AV
DV
to AGND .........................................................-0.3V to +6V
to DGND.........................................................-0.3V to +6V
SDA/DIN and SCL/SCLK to DGND ..........................-0.3V to +6V
Continuous Input Current (all terminals)........................... 50mA
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
CS_+, CS_- to AGND .............................................-0.3V to +34V
CS_+ to CS_-
Continuous Power Dissipation (T = +70°C)
48-Pin, 7mm x 7mm, TQFN (derate 27.8mW/°C above
+70°C).....................................................................2222.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
If CS_+ > 6V.........................................................-0.3V to +6V
If CS_+ ≤ 6V .......................................................-0.3V to V
CS_-
Analog Inputs/Outputs to AGND..................................................
...........................-0.3V to the lower of (AV
Digital Inputs/Outputs to DGND
+ 0.3V) and +6V
DD
MAX108
(except SDA/DIN and SCL/SCLK)............................................
............................-0.3V to the lower of (DV + 0.3V) and +6V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +32V, AV
= DV
= +5V 5ꢀ, external V
= +2.5V, external V
= +2.5V, C
= 0.1µF, C = 0.1nF,
GATE_
CS_+
DD
DD
REFADC
REFDAC
REF
V
= V
- V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CS_- A A
SENSE
CS_+
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH-SIDE CURRENT-SENSE PGA
Common-Mode Input Voltage
Range
V
V
,
CS1+
5
32
V
CS2+
Common-Mode Rejection Ratio
CMRR
5V < V
< 32V
110
135
dB
µA
CS_+
V
< 100mV over the common-mode
SENSE
CS_+ Input Bias Current
I
195
1
CS_+
range
V
< 100mV over the common-mode
SENSE
CS_- Input Bias Current
I
µA
CS_-
range
Gain = 25
Gain = 10
Gain = 2
Gain = 25
Gain = 10
Gain = 2
Gain = 25
Gain = 10
Gain = 2
0
100
250
1250
100
250
1250
100
250
1250
0.75
50
Full-Scale Sense Voltage Range
V
0
mV
SENSE
0
75
75
75
20
20
20
Minimum Sense Voltage Range
mV
mV
for 0.75ꢀ V
Accuracy
SENSE
Minimum Sense Voltage Range
for 2.5ꢀ V Accuracy
SENSE
Total PGAOUT Voltage Error
PGAOUT Capacitive Load
PGAOUT Settling Time
V
= 75mV
0.1
ꢀ
pF
µs
SENSE
C
PGAOUT
t
(Note 1)
Settles to within 0.5ꢀ accuracy from
= 3 x full scale
< 25
< 45
HSCS
Saturation Recovery Time
µs
V
SENSE
2
_______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
ELECTRICAL CHARACTERISTICS (continued)
(V
= +32V, AV
= DV
= +5V 5ꢀ, external V
= +2.5V, external V
= +2.5V, C
= 0.1µF, C = 0.1nF,
GATE_
CS_+
DD
DD
REFADC
REFDAC
REF
V
= V
- V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CS_- A A
SENSE
CS_+
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDMOS GATE DRIꢃER (Gain = 2)
AV
0.1
-
-
DD
I
I
=
=
0.1mA
0.1
GATE_
Output Gate-Drive Voltage Range
V
V
GATE_
AV
DD
2mA
0.75
GATE_
0.75
Output Impedance
GATE_ Settling Time
R
Measured at DC
R = 500Ω, C
0.1
45
Ω
GATE_
= 15µF, V
GATE_
=
S
GATE_
t
ms
GATE_
0.5V to 4.5V (Note 1)
R
R
= 0Ω
0
0
0.5
SERIES
Output Capacitive Load
C
nF
GATE_
= 500Ω
15,000
1000
100
SERIES
GATE_ Noise
1kHz to 1MHz
µV
P-P
Maximum Power-On Transient
Output Short-Circuit Current Limit
mV
I
1s, sinking or sourcing
25
mA
SC
Worst case at CODE = 4063, use
external reference (Note 2)
Total Unadjusted Error
TUE
7
25
8
mV
CalCODE = 2457, MaxCODE = 2867,
use external reference, T = +25°C
A
(Note 2)
Total Unadjusted Error without
Offset
TUE
mV
NO_OFFSET
Drift
Gain = 2, MaxCODE = 2867 (Note 2)
15
1
µV/°C
µs
Clamp to Zero Delay
C
= 0.5nF (Note 3)
GATE_
Output-Safe Switch On-
Resistance
R
OPSW
V
clamped to AGND (Note 4)
300
Ω
GATE_
MONITOR ADC (DC characteristics)
Resolution
N
12
-2
Bits
LSB
ADC
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
(Note 5)
(Note 6)
+2
2
ADC
INL
LSB
ADC
2
4
LSB
Gain Error
2
4
LSB
Gain Temperature Coefficient
Offset Temperature Coefficient
0.4
0.4
ppm/°C
ppm/°C
MONITOR ADC DYNAMIC CHARACTERISTICS (1kHz sine-wave input, 2ꢀ5ꢃ , up to 94ꢀ4ksps)
P-P
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
70
-82
86
76
1
dB
dBc
dBc
dBc
MHz
kHz
Up to 5th harmonic
SFDR
IMD
f
= 0.99kHz, f
= 1.02kHz
IN2
IN1
-3dB
Full-Linear Bandwidth
SINAD > 68dB
100
_______________________________________________________________________________________
3
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
ELECTRICAL CHARACTERISTICS (continued)
(V
= +32V, AV
= DV
= +5V 5ꢀ, external V
= +2.5V, external V
= +2.5V, C
= 0.1µF, C = 0.1nF,
GATE_
CS_+
DD
DD
REFADC
REFDAC
REF
V
= V
- V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CS_- A A
SENSE
CS_+
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MONITOR ADC CONꢃERSION RATE
Power-Up Time (External
Reference)
t
1.1
µs
µs
PUEXT
Power-Up Time (Internal
Reference)
t
70
PUINT
MAX108
Acquisition Time
Conversion Time
Aperture Delay
t
0.5
µs
µs
ns
ACQ
t
Internally clocked, T = +25°C
10
CONV
A
t
20
AD
MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)
Input Voltage Range
V
Relative to AGND (Note 7)
0
V
V
ADCIN
REFADC
Input Leakage Current
Input Capacitance
V
= 0 and V = V
0.01
34
µA
pF
IN
IN
AVDD
C
ADCIN
TEMPERATURE MEASUREMENTS
T
T
T
T
T
= +25°C
0.25
1.5
1
A
A
A
A
A
Internal Sensor Measurement
Error
°C
°C
= T
to T
(Note 8)
(Note 9)
3
MIN
MAX
= +25°C
External Sensor Measurement
Error (Note 9)
= T
to T
3
MIN
MIN
MAX
MAX
Relative Temperature Accuracy
Temperature Resolution
= T
to T
0.4
1/8
4
°C
°C/LSB
µA
External Diode Drive Current (Low)
External Diode Drive Current (High)
INTERNAL REFERENCE
3.25
2.49
68
75
µA
REFADC/REFDAC Output
Voltage
V
V
,
REFADC
T
A
= +25°C
2.50
15
2.51
V
REFDAC
REFADC/REFDAC Temperature
Coefficient
TC
TC
,
REFADC
ppm/°C
kΩ
REFDAC
REFADC/REFDAC Output
Impedance
6.5
Capacitive Bypass at
REFADC/REFDAC
270
pF
dB
Power-Supply Rejection Ratio
EXTERNAL REFERENCE
REFADC Input Voltage Range
PSRR
AV
= 5V 5ꢀ
64
DD
V
1.0
0.7
AV
V
REFADC
DD
V
= 2.5V, f
= 100ksps
60
80
REFADC
SAMPLE
REFADC Input Current
I
µA
REFADC
Acquisition/between conversions
0.01
REFDAC Input Voltage Range
REFDAC Input Current
V
2.5
V
REFDAC
Static current when the DAC is not calibrated
0.1
µA
4
_______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
ELECTRICAL CHARACTERISTICS (continued)
(V
= +32V, AV
= DV
= +5V 5ꢀ, external V
= +2.5V, external V
= +2.5V, C
= 0.1µF, C
= 0.1nF,
CS_+
DD
DD
REFADC
REFDAC
REF
GATE_
V
= V
- V
, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
CS_- A A
SENSE
CS_+
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE-DRIꢃER DAC DC ACCURACY
Resolution
N
12
Bits
LSB
LSB
DAC
Integral Nonlinearity
INL
Measured at GATE_
Guaranteed monotonic (Note 10)
2
4
1
DAC
Differential Nonlinearity
DNL
DAC
DIGITAL INPUTS (SCL/SCLK, SDA/DIN, A0/CS, A1/DOUT, A2/NꢀCꢀ, CNVST, OPSAFE1, OPSAFE2)
0.7 x
SDA/DIN and SCL/SCLK only
DV
DD
Input High Voltage
V
V
IH
A0/CS, A1/DOUT, A2/N.C., CNVST,
OPSAFE1, OPSAFE2 only
2.3
0.3 x
DV
SDA/DIN and SCL/SCLK only
DD
Input Low Voltage
Input Hysteresis
V
V
V
IL
A0/CS, A1/DOUT, A2/N.C., CNVST,
OPSAFE1, OPSAFE2 only
0.7
0.08 x
V
SDA/DIN and SCL/SCLK only
HYS
DV
DD
Input Leakage Current
Input Capacitance
Digital inputs at 0 or V
0.1
5
1
µA
pF
DVDD
C
IN
DIGITAL OUTPUTS (SDA/DIN, ALARM, BUSY, DOUT)
DV
- 0.4V
DD
Output High Voltage
V
ALARM and BUSY only, I
= 0.2mA
V
V
OH
SOURCE
SDA/DIN and A1/DOUT, I
(Note 11)
= 3mA,
SINK
0.4
Output Low Voltage
V
OL
ALARM and BUSY only, I
Digital inputs at 0 or DV
= 0.3mA
0.3
1
SINK
Three-State Leakage
I
0.1
5
µA
pF
IL
DD
Three-State Capacitance
POWER SUPPLIES (Note 12)
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
AV
DV
4.75
2.7
5.25
V
V
DD
AV
DD
DD
+ 0.3
AV
= 5V
2
0.4
3
4
2
mA
µA
DD
I
AVDD
Shutdown (Note 13)
DV = 5V
6
mA
µA
DD
Digital Supply Current
I
DVDD
Shutdown
2
32
_______________________________________________________________________________________
5
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1)
(DV
= +2.7V to +5.25V, AV
= +4.75V to +5.25V, V
= V
= 0, external V
AGND
= +2.5V, external V
= +2.5V,
DGND
DD
DD
REFADC
REFDAC
C
REF
= 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
62.5
25
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
SCLK High Time
t
ns
CH
SCLK Low Time
t
t
25
ns
CL
DS
DH
DO
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Rise or Fall to SCLK Rise
CS Pulse-Width High
15
ns
MAX108
t
0
ns
t
C = 30pF
20
50
50
ns
L
t
C = 30pF
L
ns
DV
t
C = 30pF (Note 16)
L
ns
TR
t
12.5
50
0
ns
CSS
t
ns
CSW
Last SCLK Rise to CS Rise
t
ns
CSH
2
I C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV
= +2.7V to +5.25V, AV
= +4.75V to +5.25V, V
= V
= 0, external V
AGND
= +2.5V, external V
= +2.5V,
DGND
DD
DD
REFADC
REFDAC
C
REF
= 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Time (Repeated) for START
Condition
After this period, the first clock pulse is
generated
t
HD:STA
Setup Time for a Repeated
START Condition
t
SU:STA
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t
1.3
0.6
100
0.004
0
µs
µs
ns
µs
ns
ns
LOW
t
HIGH
t
SU:DAT
HD:DAT
Data Hold Time
t
(Note 17)
0.9
300
300
SDA, SCL Rise Time
SDA, SCL Fall Time
t
R
Receiving (Note 18)
Receiving (Note 18)
t
0
F
20 + 0.1
SDA Fall Time
t
Transmitting (Notes 18, 19)
250
ns
µs
pF
F
x C
B
Setup Time for STOP Condition
t
0.6
SU:STO
Capacitive Load for Each Bus
Line
C
(Note 20)
(Note 21)
400
50
B
Pulse Width of Spikes
Suppressed by the Input Filter
t
SP
ns
6
_______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
2
I C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV
= +2.7V to +5.25V, AV
= +4.75V to +5.25V, V
= V
= 0, external V
AGND
= +2.5V, external V = +2.5V,
REFDAC
DGND
DD
DD
REFADC
C
REF
= 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
A
C
= 100pF max
C = 400pF
B
B
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
MIN
MAX
Serial Clock Frequency
f
0
3.4
0
1.7
MHz
ns
SCL
Setup Time (Repeated) START
Condition
Hold Time (Repeated) START
Condition
t
160
160
160
160
SU:STA
t
ns
HD:STA
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
Data Hold Time
t
160
80
10
4
320
120
10
4
ns
ns
ns
ns
ns
LOW
t
HIGH
t
SU:DAT
HD:DAT
t
(Note 17)
70
40
150
80
SCL Rise Time
t
10
20
RCL
After a repeated START
condition and after an
acknowledge bit
SCL Rise Time
t
10
80
20
160
ns
RCL1
SCL Fall Time
t
10
10
40
80
80
20
20
80
ns
ns
ns
ns
ns
FCL
SDA Rise Time
t
160
160
RDA
SDA Fall Time
t
10
20
FDA
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
t
160
160
SU:STO
C
(Note 20)
(Note 21)
100
10
400
10
B
Pulse Width of Spikes Suppressed
by the Input Filter
t
0
0
ns
SP
MISCELLANEOUS TIMING CHARACTERISTICS (Note 15)
(DV
= +2.7V to +5.25V, AV
= +4.75V to +5.25V, V
= V
= 0, external V
AGND
= +2.5V, external V
= +2.5V,
DGND
DD
DD
REFADC
REFDAC
C
REF
= 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Time to Wait After a Write
Command Before Reading Back
Data from the Same Location
t
(Note 22)
1
µs
RDBK
CNVST Active-Low Pulse Width in
ADC Clock Mode 01
t
t
20
20
ns
ns
CNV01
CNV11
CNVST Active-Low Pulse Width in
ADC Clock Mode 11 to Initiate a
Temperature Conversion
CNVST Active-Low Pulse Width in
ADC Clock Mode 11 for ADCIN1/2
Acquisition
t
1.5
µs
ACQ11A
ADC Power-Up Time (External
Reference)
t
1.1
70
µs
µs
APUEXT
ADC Power-Up Time (Internal
Reference)
t
APUINT
_______________________________________________________________________________________
.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MISCELLANEOUS TIMING CHARACTERISTICS (Note 15) (continued)
(DV
= +2.7V to +5.25V, AV
= +4.75V to +5.25V, V
= V
= 0, external V
AGND
= +2.5V, external V
= +2.5V,
DGND
DD
DD
REFADC
REFDAC
C
REF
= 0.1µF, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
t
CONDITIONS
MIN
TYP
MAX
UNITS
DAC Power-Up Time (External
Reference)
2
µs
DPUEXT
DAC Power-Up Time (Internal
Reference)
t
70
µs
µs
DPUINT
MAX108
Acquisition Time (Internally Timed
in ADC Clock Modes 00 or 01)
t
0.6
10
ACQ
Conversion Time (Internally
Clocked)
t
Internally clocked, T = +25°C
A
µs
µs
µs
CONV
Delay to Start of Conversion Time
t
(Note 23)
1.3
70
CONVW
Temperature Conversion Time
(Internally Clocked)
t
CONVT
Note 1: Output settles to within 0.5ꢀ of final value.
Note 2: Total unadjusted errors are for the entire gate-drive channel including the 12-bit DAC, and the gate driver is measured at
the GATE1 and GATE2 outputs.
Note 3: V
= V
- 0.1. Measured from when OPSAFE1 or OPSAFE2 is set high.
GATE_
DD
Note 4: During power-on-reset, the output safe switch is closed. The output safe switch is opened under user software control.
Note 5: Guaranteed to be 11 bits linearly accurate.
Note 6: Offset nulled.
Note .: The absolute range for analog inputs is from 0 to V
.
AVDD
Note 8: Internal temperature-sensor performance is guaranteed by design.
Note 9: The MAX11008 and the external sensor are at the same ambient temperature. External sensor measurement error is tested
with a diode-connected 2N3904.
Note 10:Guaranteed monotonicity. Accuracy is degraded at lower V
.
REFDAC
Note 11:SDA/DIN is an open-drain output only when in I2C mode. A1/DOUT is an open-drain output only when in SPI mode.
Note 12:Supply-current limits are valid only when digital inputs are set to DGND or supply voltage. Timing specifications are only
guaranteed when inputs are driven rail-to-rail.
Note 13:Shutdown supply currents are typically 0.4µA for AV ; maximum specification is limited by automated test equipment.
DD
Note 14:All times are referred to the 50ꢀ point between V and V levels.
IH
IL
Note 15:Guaranteed by design. Not production tested.
Note 16:DOUT will go into three-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled
before it goes to three-state.
Note 1.:A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 18:t and t measured between 0.3 x DV
and 0.7 x DV
.
R
F
DD
DD
Note 19:C = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
B
linearly interpolated.
Note 20:An appropriate bus pullup resistance must be selected depending on board capacitance.
Note 21:Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 22:When a command is written to the serial interface, the command is passed by the internal oscillator clock and executed.
There is a small synchronization delay before the new value is written to the appropriate register. If the serial interface
attempts to read the new value back before t , the new data is not corrupted; however, the result of the read command
RDBK
may not reflect the new value.
Note 23:This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from
the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the
write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of
the wrong ADC channel).
8
_______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Typical Operating Characteristics
(AV = DV = 5V, external V
= 2.5V, external V
= 2.5V, V
= V
= 32V, C
= 0.1µF, T = +25°C, unless oth-
DD
DD
REFADC
REFDAC
CS_-
CS_+
REF A
erwise noted.)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. TEMPERATURE (G = 2)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.10
2.09
2.08
2.07
2.06
0.2
3.5
DV = 5V
INT REF AND DACS TURNED ON
AV = 5V
DD
WD OSC TURNED ON
DD
0
-0.2
-0.4
-0.6
-0.8
3.0
2.5
2.0
1.5
1.0
AFTER
CALIBRATION
BEFORE
CALIBRATION
4.7
4.8
4.9
5.0
5.1
5.2
5.3
-40
-10
20
50
80
110
2.70
3.22
3.74
4.26
4.78
5.30
AV (V)
DD
TEMPERATURE (°C)
DV (V)
DD
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. TEMPERATURE (G = 10)
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. TEMPERATURE (G = 25)
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. SENSE VOLTAGE (G = 2)
0.3
0
0.4
0.2
1.0
0.8
0.6
0.4
0.2
0
OUTPUT AT PGAOUT_
CMV = 32V
0
-0.2
-0.4
-0.6
-0.8
-0.3
-0.6
-0.9
AFTER
CALIBRATION
BEFORE
CALIBRATION
AFTER
CALIBRATION
BEFORE
CALIBRATION
-40
-10
20
50
80
110
0
250
500
V
750
1000
1250
-40
-10
20
50
80
110
TEMPERATURE (°C)
(mV)
TEMPERATURE (°C)
SENSE
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. SENSE VOLTAGE (G = 10)
CURRENT-SENSE AMPLIFIER OUTPUT
ERROR vs. SENSE VOLTAGE (G = 25)
CURRENT-SENSE AMPLIFIER
OUTPUT ERROR vs. CMV
0.30
0.25
0.20
0.15
0.10
0.05
0
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
V
= 75mV
SENSE
OUTPUT AT PGAOUT_
CMV = 32V
OUTPUT AT PGAOUT_
CMV = 32V
G = 2
G = 25
G = 10
5
10
15
20
25
30
35
0
50
100
150
200
250
0
20
40
60
80
100
COMMON-MODE VOLTAGE (V)
V
(mV)
V
(mV)
SENSE
SENSE
_______________________________________________________________________________________
9
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Typical Operating Characteristics (continued)
(AV = DV = 5V, external V
= 2.5V, external V
= 2.5V, V
= V
= 32V, C
= 0.1µF, T = +25°C, unless oth-
A
DD
DD
REFADC
REFDAC
CS_-
CS_+
REF
erwise noted.)
CURRENT-SENSE TRANSIENT
CURRENT-SENSE TRANSIENT
RESPONSE (G = 10)
CURRENT-SENSE TRANSIENT
RESPONSE (G = 2)
RESPONSE (G = 25)
MAX11008 toc10
MAX11008 toc11
MAX11008 toc12
V
V
SENSE1
200mV/div
0V
SENSE1
V
SENSE1
1V/div
0V
100mV/div
MAX108
0V
0V
V
V
PGAOUT1
1V/div
PGAOUT1
V
PGAOUT1
1V/div
1V/div
0V
0V
2µs/div
1µs/div
1µs/div
GATE VOLTAGE TOTAL UNADJUSTED
ERROR vs. TEMPERATURE
GATE POWER-UP TIME
GATE_ SETTLING TIME vs. C
GATE
MAX11008 toc14
-3.75
-3.90
-4.05
-4.20
-4.35
-4.50
2.5
2.0
1.5
1.0
0.5
0
V
SCL
5V/div
V
SDA
5V/div
V
GATE1
1V/div
R
= 500Ω
S
50% OF SDA STOP EDGE TO
0.5% OF FINAL V
4V TRANS ON GATE_ (IODAC_)
0V
GATE_
-40
-11
18
47
76
105
1µs/div
0
100
200
300
(pF)
400
500
TEMPERATURE (°C)
C
GATE_
DAC INTEGRAL NONLINEARITY
vs. INPUT CODE
DAC DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
MAJOR CARRY TRANSITION GLITCH
MAX11008 toc17
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
V
0.2
0.2
GATE_
1mV/div
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
CODE 7FF TO 800
= 100pF
C
GATE_
10µs/div
0
1024
2048
3072
4096
0
1024
2048
3072
4096
INPUT CODE
INPUT CODE
10 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Typical Operating Characteristics (continued)
(AV = DV = 5V, external V
= 2.5V, external V
= 2.5V, V
= V
= 32V, C = 0.1µF, T = +25°C, unless oth-
REF A
DD
DD
REFADC
REFDAC
CS_-
CS_+
erwise noted.)
ADC INTEGRAL NONLINEARITY
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
vs. OUTPUT CODE
ADC SINAD vs. FREQUENCY
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
80
75
70
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
65
60
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0.1
1
10
100
1000
OUTPUT CODE
OUTPUT CODE
FREQUENCY (kHz)
DIGITAL SUPPLY CURRENT
vs. SAMPLING RATE
ADC INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
ADC SFDR vs. FREQUENCY
2.5026
2.5024
2.5022
2.5020
2.5018
8
7
6
5
4
3
100
90
80
70
60
50
AV = DV = 5V
AV = DV
DD
DD
DD
DD
0.1
1
10
100
1000
4.750
4.875
5.000
5.125
5.250
0.1
1
10
100
1000
SAMPLING RATE (ksps)
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
______________________________________________________________________________________ 11
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Typical Operating Characteristics (continued)
(AV = DV = 5V, external V
= 2.5V, external V
= 2.5V, V
= V
= 32V, C
= 0.1µF, T = +25°C, unless oth-
DD
DD
REFADC
REFDAC
CS_-
CS_+
REF A
erwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR vs. TEMPERATURE
2.52
2.51
2.50
2.49
2.48
2.0
1.5
1.0
0.5
0
4
3
2
1
0
V
REFADC
MAX108
V
REFDAC
-50 -25
0
25
50
75 100 125
4.750
4.875
5.000
5.125
5.250
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
AV (V)
DD
TEMPERATURE (°C)
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
RELATIVE TEMPERATURE
ERROR vs. TEMPERATURE
ADC GAIN EROR vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0
4
3
0.8
0.6
0.4
INTERNAL TEMP
SENSOR
2
0.2
1
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
EXTERNAL TEMP
SENSOR
-1
-2
-3
4.750
4.875
5.000
5.125
5.250
-50 -25
0
25
50
75 100 125
-40
-11
18
47
76
105
AV (V)
DD
TEMPERATURE (°C)
TEMPERATURE (°C)
12 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Pin Description
PIN
NAME
FUNCTION
1, 31
DGND
Digital Ground. Connect both DGND inputs to the same potential.
Output Safe Switch Logic Input 1. Drive OPSAFE1 high to close the output safe switch and clamp
GATE1 to AGND. Drive OPSAFE1 low to open the switch.
2
3
4
OPSAFE1
A0/CS
2
Address-Select Input 0/Chip-Select Input. In I C mode, this is the address-select input 0. See Table
1. In SPI mode, this is the chip-select input.
Active-Low Conversion Start Input. Drive CNVST low to begin a conversion when in clock modes 01
and 11.
CNVST
2
5
6
SPI/I2C
Interface-Select Input. Connect to DGND for I C interface. Connect to DV
for SPI interface.
DD
ALARM
Alarm Output
Output Safe Switch Logic Input 2. Drive OPSAFE2 high to close the output safe switch and clamp
GATE2 to AGND. Drive OPSAFE2 low to open the switch.
7
OPSAFE2
8
REFDAC DAC Reference Input/Output
REFADC ADC Reference Input/Output
9
10
11
12
13
14
15
16
17
18
DXP1
DXN1
Temperature Diode Positive Input 1. Connect DXP1 to the anode of the external diode.
Temperature Diode Negative Input 1. Connect DXN1 to the cathode of the external diode.
Temperature Diode Positive Input 2. Connect DXP2 to the anode of the external diode.
Temperature Diode Negative Input 2. Connect DXN2 to the cathode of the external diode.
ADC Auxiliary Input 1
DXP2
DXN2
ADCIN1
ADCIN2
ADC Auxiliary Input 2
PGAOUT2 Programmable-Gain Amplifier Output 2
GATE2
GATE1
Gate-Drive Amplifier Output 2
Gate-Drive Amplifier Output 1
19, 25, 30,
34–39, 42, 48
N.C.
No Connection. Not internally connected. Leave unconnected.
20, 24
AV
Analog-Supply Input. Connect both AV
inputs to the same potential.
DD
DD
21, 22, 23
AGND
CS2+
CS2-
Analog Ground. Connect all AGND inputs to the same potential.
26
27
28
29
Current-Sense Positive Input 2. CS2+ is the external sense-resistor connection to the LDMOS 2 supply.
Current-Sense Negative Input 2. CS2- is the external sense-resistor connection to the LDMOS 2 drain.
Current-Sense Negative Input 1. CS1- is the external sense-resistor connection to the LDMOS 1 drain.
Current-Sense Positive Input 1. CS1+ is the external sense-resistor connection to the LDMOS 1 supply.
CS1-
CS1+
Digital-Supply Input. Connect all DV
inputs to the same potential. Connect a 0.1µF capacitor to
DD
32, 33, 47
DV
DD
DV
.
DD
40
41
PGAOUT1 Programmable-Gain Amplifier Output 1
2
Address-Select Input 2/N.C. In I C mode, this pin is the address-select input 2. See Table 1. In SPI
mode, this is a no connection pin.
A2/N.C.
2
43
44
SCL/SCLK Serial-Clock Input. SCL is the I C-compatible clock input. SCLK is the SPI-compatible clock input.
2
SDA/DIN Serial-Data Input/Output. SDA is the I C-compatible input/output. DIN is the SPI-compatible data input.
2
Address-Select Input 1/Data Out. In I C mode, this is the address-select input 1. See Table 1. In SPI
mode, this is the serial-data output. Data is clocked out on the falling edge of SCLK. DOUT is a high-
45
A1/DOUT
impedance output when CS is driven high.
46
—
BUSY
EP
Busy Output. BUSY goes high to indicate activity.
Exposed Pad. Connect EP to AGND. Internally connected to AGND.
______________________________________________________________________________________ 13
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Functional Diagram
A2/N.C.
A1/DOUT
A0/CS
DV
PGAOUT1
AV
DD
DD
MAX11008
SCL/SCLK
SDA/DIN
SPI/I2C
SERIAL INTERFACE
MAX108
CS1+
CS1-
PGA 1
FIFO
A
= 2
GATE1
V
12-BIT DAC1
OPSAFE1
REGISTER MAP
AND DIGITAL
CONTROL
EEPROM
ALARM
CS2+
BUSY
PGA 2
CS2-
PGAOUT2
12-BIT DAC 2
A
V
= 2
GATE2
OPSAFE2
DXP1
DXN1
REFDAC
EXTERNAL
TEMPERATURE
SENSOR
INTERNAL
TEMPERATURE
SENSOR
PROCESSING
DXP2
DXN2
2.5V
REFERENCE
ADCIN1
ADCIN2
REFADC
MUX
12-BIT ADC
DGND
CNVST
AGND
14 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
2
Typical Application Circuits—I C Interface
DV
DD
AV
DD
32V
0.1µF
0.1µF
4.7kΩ
DV
AV
DD
DD
4.7kΩ
CS1+
CS1-
5V
C *
R
F
SENSE
SCL/SCLK
SDA/DIN
R *
F
A0/CS
CS2+
CS2-
A1/DOUT
A2/N.C.
C *
F
R
SENSE
µC
R *
F
OPSAFE1
MAX11008
GATE2
OPSAFE2
ALARM
BUSY
RF OUT
CNVST
SPI/I2C
RF IN
LDMOS 1
DXP2
DXN2
REFADC
REFDAC
EXTERNAL
2.5V
REFERENCE
0.1µF
0.1µF
GATE1
DXP1
PGAOUT1
PGAOUT2
RF OUT
ADCIN1
ADCIN2
DXN1
RF IN
LDMOS 2
DGND
AGND
2
*SDA RESISTOR VALUE VARIES WITH LOAD AND SCL FREQUENCY. SEE THE I C SERIAL INTERFACE SECTION.
*SELECT R AND C BASED ON DESIRED FILTER CUTOFF FREQUENCY WHERE f = 1/(2 π R C ).
F
F
CUTOFF
F F
LIMIT R TO 100Ω TO MINIMIZE OFFSET ERRORS.
F
______________________________________________________________________________________ 15
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Typical Application Circuits—SPI Interface
DV
DD
AV
DD
32V
0.1µF
0.1µF
MAX108
DV
AV
DD
DD
CS1+
CS1-
5V
C *
R
F
SENSE
SCL/SCLK
SDA/DIN
A0/CS
R *
F
CS2+
CS2-
A1/DOUT
C *
F
R
SENSE
µC
R *
F
OPSAFE1
OPSAFE2
MAX11008
GATE2
ALARM
BUSY
RF OUT
CNVST
RF IN
LDMOS 1
DV
DD
DXP2
DXN2
SPI/I2C
REFADC
REFDAC
EXTERNAL
2.5V
REFERENCE
0.1µF
0.1µF
GATE1
DXP1
PGAOUT1
PGAOUT2
RF OUT
ADCIN1
ADCIN2
DXN1
RF IN
LDMOS 2
DGND
AGND
*SELECT R AND C BASED ON DESIRED FILTER CUTOFF FREQUENCY WHERE f
= 1/(2 π R C ).
F F
F
F
CUTOFF
LIMIT R TO 100Ω TO MINIMIZE OFFSET ERRORS.
F
16 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Digital Serial Interface
Detailed Description
The MAX11008 features both an I2C and an SPI-com-
The MAX11008 sets and controls the bias conditions
patible serial interface. Connect SPI/I2C to DGND to
for dual RF LDMOS power devices found in cellular
base-station power amps. Each device includes two
high-side current-sense amplifiers with programmable
gains of 2, 10, and 25 to monitor the LDMOS transistor
drain current over the 20mA to 5A range. Two external
diode-connected transistors monitor the LDMOS tran-
sistor temperatures while an internal temperature sen-
sor measures the local die temperature of the
MAX11008. The 12-bit ADC is interfaced to a 7:1 multi-
plexer and converts the signals from the PGA outputs,
internal and external temperature readings, or the two
auxiliary analog inputs into digital data results that can
be stored in the FIFO.
select the I2C serial-interface operation, or to DV
to
DD
select the SPI serial-interface operation. Do not alter
interface mode during operation.
SPI Seriaꢄ Interface
Connect SPI/I2C to DV
to select the SPI interface.
DD
The SPI serial interface consists of a serial data input
(DIN), a serial clock line (SCLK), a chip select (CS),
and a serial data output (DOUT). The use of serial data
output (DOUT) is optional and is only required when
data is to be read back by the master device. The
MAX11008 is SPI compatible within the range of V
=
DD
+2.7V to +5.25V. DIN, SCLK, CS, and DOUT facilitate
bidirectional communication between the MAX11008
and the master at rates up to 20MHz.
On the control side, two gate-drive channels, driven
from two 12-bit DACs and a gain stage of 2, generate a
positive gate voltage bias for the LDMOS. Each gate-
drive output supports up to 2mA of gate current. The
gate-drive amplifier is current-limited to 25mA and
features a fast clamp to analog ground that operates
independently of the serial interface.
Figure 1 illustrates the 4-wire interface timing diagram.
The MAX11008 is a transmit/receive slave-only device,
relying upon a master to generate a clock signal. The
master initiates data transfer on the bus and generates
the SCLK signal to permit data transfer.
The MAX11008 includes an on-chip, nonvolatile
EEPROM that stores LUTs and register information. The
LUTs are designed to store gate voltage vs. temperature
curves for the LDMOS FET. The data is used for temper-
ature compensation of the LDMOS FET’s bias point.
The LUTs can also contain compensation data for anoth-
er independent parameter: either sense voltage or
AIN voltage.
t
CSW
CS
t
t
CSS
CSS
t
CL
t
t
CP
t
CH
CSH
SCLK
t
t
DS
DH
D22
D1
D0
D23
DIN
t
t
TR
DO
t
DV
DOUT
Figure 1. SPI Serial-Interface Timing
______________________________________________________________________________________ 1.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
The SPI bus cycles are 24 bits long. Data can be sup-
plied as three 8-bit bytes or as a continuous 24-bit
stream. CS must remain low throughout the 24-bit
sequence. The first 8-bit byte is a command byte
C[7:0]. The next 16 bits are data bits D[15:0]. Clock
signal SCLK can idle low or high, but data is always
clocked in on the rising edge of SCLK (CPOL = CPHA).
When reading data from the MAX11008, 24 clock
cycles must be completed before CS is driven high. If
CS is driven high before the completion of the 24th
falling edge, DOUT immediately three-states, the inter-
face resets in preparation for the next command, and
the data being read is lost.
Write Format
Use the following sequence to write 16 bits of data to a
MAX11008 register (see Figure 2):
SPI data transfers begin with the falling edge of CS.
Data is clocked into the device on the rising edges of
SCLK and clocked out of the device on the falling
edges of SCLK. For correct bus cycles, CS should
frame the data and should not return to a 1 until after
the last active rising clock edge. See Figure 2 for timing
details. A rising edge of CS causes DOUT to three-
state and data reads should be performed accordingly.
See Figures 1 and 3.
MAX108
1) Drive CS low to select the device.
2) Send the appropriate write command byte (see
Table 6 for the register address map). The com-
mand byte is clocked in on the rising edge of SCLK.
3) Send 16 bits of data D[15:0] starting with the most
significant bit (MSB). Data is clocked in on the rising
edges of SCLK.
When writing instructions to the MAX11008, 24 clock
cycles must be completed before CS is driven high.
The MAX11008 executes the instruction only after the
24th clock cycle has been received and CS is driven
high. To abort unwanted instructions, CS can be driven
high at any time before the 23rd rising clock edge.
4) Drive CS high to conclude the command.
A RISING EDGE OF CS
DURING THIS PERIOD
COMPLETES A VALID WRITE
COMMAND
CS
SCLK
CR/W- C6
C5
C4
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DIN
Figure 2. SPI Write Sequence
18 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Read Format
Use the following sequence to read 16 bits of data from
a MAX11008 register (see Figure 3):
I2C Seriaꢄ Interface
Connect SPI/I2C to DGND to select the I2C interface. The
I2C serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). The MAX11008 is I2C com-
1) Drive CS low to select the device.
patible within the DV
= 2.7V to 5.25V range. SDA and
DD
2) Send the appropriate read command byte (see
Table 6 for the register address map). The com-
mand byte is clocked in on the rising edges of
SCLK.
SCL facilitate bidirectional communication between the
MAX11008 and the master at rates up to 400kHz for fast
mode and up to 3.4MHz for high-speed mode (HS
mode). See the Bus Timing and HS I2C Mode sections
for more information on data-rate configurations.
3) Receive 16 bits of data. The first 4 bits of data are
always high. Data is clocked out on the falling edges
of SCLK.
Figure 4 shows the 2-wire interface timing diagram. The
MAX11008 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfers
on the bus and generates the SCL signal to permit data
transfer.
4) Drive CS high.
CS
SCLK
R/W
C6
C5
C4
C3
C2
C1
C0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DIN
X
D15
D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Figure 3. SPI Read Sequence
2
a) F/S-MODE I C SERIAL INTERFACE TIMING
t
R
t
F
SDA
t
BUF
t
t
HD, DAT
SU, DAT
t
HD, STA
t
t
SU, ST0
t
SU, STA
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
F
S
Sr
A
P
S
2
b) HS-MODE I C SERIAL INTERFACE TIMING
t
t
RDA
RDA
SDA
t
BUF
t
t
HD, DAT
SU, DAT
t
HD, STA
t
t
SU, ST0
SU, STA
t
LOW
SCL
t
HIGH
t
t
HD, STA
RCL
t
t
RCL
RCL
S
Sr
A
P
S
HS MODE
F/S MODE
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 4. I2C Serial-Interface Timing Diagram
______________________________________________________________________________________ 19
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
A master device communicates to the MAX11008 by
transmitting the proper slave address followed by a
command and/or data words. Each transmit sequence
is framed by a START (S) or repeated START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge clock pulse.
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (see Figure 5). A repeated
START condition (Sr) can be used in place of a STOP
condition to leave the bus active and the mode
unchanged (see the HS I2C Mode section).
Acknowꢄedge Bits and Not-Acknowꢄedge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX11008 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth clock pulse)
and keep it low during the high period of the clock
pulse (see Figure 6).
The MAX11008 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor (750Ω or greater) to
generate a logic-high voltage (see the Typical
Application Circuits). Series resistors are optional for
noise filtering. These series resistors protect the input
stages of the MAX11008 from high-voltage spikes on
the bus line, and minimize crosstalk and undershoot of
the bus signals.
MAX108
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the I2C bus is not busy.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master reattempts com-
munication at a later time.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
S
Sr
P
SDA
SCL
S = START.
Sr = REPEATED START.
P = STOP.
Figure 5. START and STOP Conditions
NOT ACKNOWLEDGE
ACKNOWLEDGE
S
SDA
SCL
1
2
8
9
Figure 6. Acknowledge Bits
20 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Sꢄave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address and a read/write (R/W) bit (see Figure
7). When the device recognizes its slave address, it is
ready to accept or send data depending on the R/W
bit. When the MAX11008 recognizes its slave address,
it issues an ACK by pulling SDA low for one clock cycle
and is ready to accept or send data depending on the
R/W bit that was sent.
Bus Timing
At power-up, the bus timing is set for I2C fast-mode
(F/S mode), which allows I2C clock rates up to 400kHz.
The MAX11008 can also operate in high-speed mode
(HS mode) to achieve I2C clock rates up to 3.4MHz.
See Figure 4 for I2C bus timing.
HS I2C Mode
Select HS mode by addressing all devices on the bus
with the HS-mode master code 0000 1XXX (X = don’t
care). After successfully receiving the HS-mode master
code, the MAX11008 issues a NACK, allowing SDA to
be pulled high for one clock cycle (see Figure 8). After
the NACK, the MAX11008 operates in HS mode. The
master must then send a repeated START (Sr) followed
by a slave address to initiate HS-mode communication.
If the master generates a STOP condition, the
The MAX11008 has eight user-selectable slave address-
es, which are set through inputs A0, A1, and A2 (see
Table 1). This feature allows up to eight MAX11008
devices to share the same bus inputs. The 4 MSBs D[7:4]
are factory set, and the 3 LSBs are user-selectable.
Tabꢄe 1ꢀ Sꢄave Address Seꢄect
A2
0
A1
0
A0
0
ADDRESS
0101000
0101001
0101010
0101011
0101100
0101101
0101110
0101111
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
S
SDA
SCL
R/W
8
A
1
4
0
1
2
0
3
A2
5
A1
6
A0
7
9
1
Figure 7. Slave Address Bits
Sr
SDA
0
1
0
2
0
3
0
4
1
5
X
6
X
7
X
8
A
9
HS MODE
F/S MODE
Figure 8. F/S-Mode to HS-Mode Transfer
______________________________________________________________________________________ 21
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX11008 returns to F/S mode. Use a repeated START
condition in place of a STOP condition to leave the bus
active and the mode unchanged. Figure 9 summarizes
the data bit transfer format for HS-mode communication.
slave. The MSB of the register address byte is the
read/write bit for the destination register address of the
slave and must be set to 0 for a write cycle (see the
Register Address Map section). After receiving the
byte, the slave issues another acknowledge, pulling
SDA low for one clock cycle. The master then writes
two data bytes, receiving an ACK from the slave after
each byte is sent. The master ends the write cycle by
issuing a STOP condition. When operating in HS mode,
a STOP condition returns the bus into F/S mode (see
the HS I2C Mode section). Figure 10 shows a complete
write cycle.
Register Address/Data Bꢂtes (Write Cꢂcꢄe)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (see Figure
5 and Table 1) and a write bit (R/W = 0). Once the
slave address is recognized and the write bit is
received, the MAX11008 (I2C slave) issues an ACK by
pulling SDA low for one clock cycle. The master then
sends the register address byte (command byte) to the
MAX108
MASTER TO SLAVE
SLAVE TO MASTER
F/S MODE
F/S MODE
HS MODE
A
S
N
Sr
SLAVE ADDRESS
R/W
DATA
A
P
MASTER CODE
HS MODE CONTINUES
SLAVE ADD
N BYTES + ACK
Sr
Figure 9. Data-Transfer Format in HS Mode
MASTER TO SLAVE
SLAVE TO MASTER
4-BYTE WRITE CYCLE
8
8
NUMBER OF BITS
1
7
1
1
8
1
1
1
1
REGISTER ADDRESS
BYTE
SLAVE
ADDRESS
S
W A
A
DATA BYTE
A
DATA BYTE
A P OR Sr
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS
Figure 10. Write Cycle
22 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Register Address/Data Bꢂtes (5-Bꢂte Read Cꢂcꢄe)
contents of the register that was addressed in the pre-
vious command byte) to the master. Finally, the master
issues a NACK followed by a STOP condition (P), end-
ing the read cycle. Figure 11 shows a complete 5-byte
read cycle.
A read cycle begins with the master issuing a START
condition followed by a 7-bit address, (see Figure 5
and Table 1) and a write bit (R/W = 0) to instruct the
MAX11008 interface that it is about to receive data.
Once the slave address is recognized and the write bit
is received, the MAX11008 (I2C slave) issues an ACK
by pulling SDA low for one clock cycle. The master
then sends the register address byte (command byte)
to the slave. The MSB of the register address byte is
the read/write bit for the destination register address of
the slave and must be set to 1 for a read cycle (see the
Register Address Map section). After this byte is
received, another acknowledge bit is sent to the master
from the slave. The master then issues a repeated
START (Sr) condition. Following a repeated START (Sr),
the master writes the slave address byte again with a
read bit (R/W = 1). After a third acknowledge signal
from the slave, the data direction on the SDA bus
reverses and the slave writes the 2 data bytes (the
Defauꢄt Read Cꢂcꢄe (3-Bꢂte Read Cꢂcꢄe)
The MAX11008 2-wire interface has a unique feature for
read commands. To avoid the necessity of sending 2
slave address bytes in one read cycle (see the 5-byte
read cycle in Figure 11), the MAX11008 2-wire interface
recognizes a single slave address byte with a read bit
(R/W = 1). In this case, the interface outputs the con-
tents of the last read device register. This default read
feature is useful when the master must perform multiple
consecutive reads from the same device register.
Figure 11 shows a complete 3-byte read cycle.
MASTER TO SLAVE
SLAVE TO MASTER
5-BYTE READ CYCLE
1
7
1
1
8
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SLAVE
ADDRESS
SLAVE
ADDRESS
S
W A
COMMAND BYTE
A Sr
R
A
DATA BYTE
A
DATA BYTE
N P OR Sr
3-BYTE READ CYCLE
7
1
1
1
8
1
8
1
1
NUMBER OF BITS
SLAVE
ADDRESS
S
R
A
DATA BYTE
A
DATA BYTE
N P OR Sr
Figure 11. 5-Byte and 3-Byte Read Cycle
______________________________________________________________________________________ 23
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Any source impedance below 300Ω does not affect the
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening t or by
placing a 1µF capacitor between the positive and neg-
ative analog inputs. The combination of the analog-
input source impedance and the capacitance at the
analog input creates an RC filter that limits the analog
input bandwidth.
12-Bit ADC
The MAX11008 12-bit ADC uses a SAR conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert the PGA outputs (PGAOUT1 and PGAOUT2),
temperature measurements, and single-ended auxiliary
input voltages (ADCIN1 and ADCIN2) into 12-bit digital
data when in ADC monitor mode (see the Hardware
Configuration Register (HCFIG) (Read/Write) section).
All nontemperature measurements are converted using
a unipolar transfer function (see Figure 13), and all tem-
perature measurements are converted using a bipolar
transfer function (see Figure 14).
ACQ
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. Anti-alias filtering of the input sig-
nals is necessary to prevent high-frequency
components from aliasing into the frequency band of
interest.
MAX108
Anaꢄog Input T/H
Figure 12 shows the equivalent circuit for the ADC input
architecture of the MAX11008. In track mode, an input
capacitor is connected to the input signal (ADCIN1,
ADCIN2, PGAOUT1, PGAOUT2, or temperature sensor
processor output). Another input capacitor is connect-
ed to AGND. After the T/H enters hold mode, the differ-
ence between the sampled positive and negative input
voltages is converted. The charging rate of the input
capacitance determines the time required for the T/H to
acquire an input signal. If the input signal’s source
impedance is high, the required acquisition time
lengthens accordingly.
Anaꢄog Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
and AGND, allowing
DD
the inputs to swing from (AGND - 0.3V) to (AV
+
DD
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
DD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
REFADC
CAPACITIVE
DAC
ADCIN1
ADCIN2
PGAOUT1
PGAOUT2
TRACK
COMPARATOR
CIN+
TEMP SENSOR READING
HOLD
CIN-
AGND
TRACK
HOLD
HOLD
TRACK
AV /2
DD
ALL SWITCHES SHOWN IN TRACK MODE.
Figure 12. Analog Input Track and Hold
24 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
ADC Transfer Functions
Figure 13 shows the unipolar transfer function for non-
temperature measurements, and Figure 14 shows the
bipolar transfer function used for temperature measure-
ments. Code transitions occur halfway between suc-
cessive-integer LSB values. Output coding is binary,
ADC Conversion Scheduꢄing
The MAX11008 ADC multiplexer scans and converts
the selected inputs in the order shown in Table 2 (see
the ADC Conversion Register (ADCCON) (Write Only)
section) when more than one channel is selected. The
results are stored in the FIFO when in ADC monitoring
mode. The BUSY signal is set at the start and reset at
the end of a scan except when the continuous convert
bit is set at which time BUSY does not then respond to
ADC conversions.
with 1 LSB = V
/4096 for nontemperature mea-
REFADC
surements, and 1 LSB = +0.125°C for temperature
measurements. All signed binary results use two’s com-
plement format.
Writing a conversion command before a conversion is
complete cancels the pending conversion. Avoid
addressing the device using the serial interface while
the ADC is converting.
V
REFADC
1111 1111 1111
1111 1111 1110
1111 1111 1101
1111 1111 1100
FULL-SCALE TRANSITION
Tabꢄe 2ꢀ Order of ADC Conversion Scan
ORDER OF SCAN
DESCRIPTION OF CONꢃERSION
Internal device temperature
1
2
3
4
5
6
7
1 LSB = V
/4096
External diode 1 temperature
Output of PGA 1 for current sense
Auxiliary input 1 (ADCIN1)
REFADC
External diode 2 temperature
Output of PGA 2 for current sense
Auxiliary input 2 (ADCIN2)
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
ADC Cꢄock Modes
0
1
2
3
4093 4095
The MAX11008 offers three conversion/acquisition
modes (known as clock modes) selectable through
configuration register bits CKSEL1 and CKSEL0.
INPUT VOLTAGE (LSB)
Figure 13. ADC Transfer Function
If the ADC conversion requires the internal reference
(temperature measurement or voltage measurement with
internal reference selected) and the reference has not
been previously forced on (FBGON = 1), the device
inserts a typical delay of 72µs, for the reference to settle,
before commencing the ADC conversion. The reference
remains powered up while there are pending conver-
sions. If the reference is not forced on, it automatically
powers down at the end of a scan or when CONCONV in
the ADC Conversion register is set back to 0.
0111 1111 1111
0111 1111 1110
0111 1111 1101
1 LSB = +0.125°C
0000 0000 0001
0000 0000 0000
1111 1111 1111
Internally Timed Acquisitions
and Conversions
Cꢄock Mode 00
In clock mode 00, power-up, acquisition, conversion,
and power-down are all initiated by writing to the ADC
Conversion register and performed automatically using
the internal oscillator. This is the default clock mode.
The ADC sets the BUSY output high, powers up, and
scans all requested channels storing the results in the
FIFO if the ADCMON bit has been set. After the scan is
1000 0000 0010
1000 0000 0001
1000 0000 0000
-256
0
+255
TEMPERATURE (°C)
Figure 14. Temperature Transfer Function
______________________________________________________________________________________ 25
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
complete the ADC powers down, BUSY is pulled low,
and the results for all of the selected channels are
available in the FIFO.
Externally Timed
Acquisitions and Conversions
Cꢄock Mode 10
Clock mode 10 is reserved. Do not use this clock
mode.
The duration of the BUSY pulse is additive, depending
on the channel conversion sequence selected. The
BUSY pulse is set typically for 72µs by temperature
conversions; 52µs by PGAOUT conversions, and 7µs
by ADCIN conversions.
Cꢄock Mode 11
In clock mode 11, set the FBGON bit. Conversions are
initiated one at a time through CNVST and performed
using the internal oscillator. In this mode, the acquisition
time is controlled by the time CNVST is low. CNVST is
resynchronized by the internal oscillator, resulting in a
one-clock cycle (typically 320ns) uncertainty in the exact
sampling instant. Different timing parameters apply
depending if the conversion is temperature, from ADCIN,
or from PGAOUT (as specified in the Clock Mode 00
section). Figure 15 shows a conversion time example.
Cꢄock Mode 01
In clock mode 01, power-up, acquisition, conversion,
and power-down are all initiated through a single pulse
on CNVST and performed automatically using the inter-
nal oscillator. Initiate a scan by writing to the ADC con-
version register and setting CNVST low for at least
20ns. The ADC sets the BUSY output high, powers up,
and scans all requested channels storing the results in
the FIFO if the ADCMON bit has been set. After the
scan is complete, the ADC powers down, BUSY is
pulled low, and the results for all of the selected chan-
nels are available in the FIFO. The BUSY pulse behav-
ior is identical to that of clock mode 00.
MAX108
Both internal and external temperature conversions are
internally timed. Pull CNVST low for a minimum of 20ns
(t
) to trigger a temperature conversion. The BUSY
CNV11
output goes high and the temperature conversion result
is available in the FIFO (if the ADCMON bit is set) 72µs
(typ) after BUSY goes low again.
INTERNAL TEMPERATURE READING, PGA1 OUTPUT, AND ADCIN1 CONVERSION TIMING IN CLOCK MODE 11
t
= 20ns (typ)
CNV
t
= 1.5µs (typ)
ACQ
t
= 30µs (typ)
ACQ
CNVST
BUSY
IDLE MODE,
REF AND
TEMP
SENSOR
POWERED
IDLE MODE,
REF AND
TEMP
SENSOR
POWERED
TEMPERATURE
CONVERSION
70µs (typ)
PGA 1
CONVERSION
22µs (typ)
PGA 1
ACQUISITION
INTERNAL
OPERATIONS
END OF
SCAN
WRITE TO ADC
CONVERT REGISTER TO
SET UP ADC SCAN
FBGON = 1,
TEMPERATURE
CONVERSION RESULT
AVAILABLE IN FIFO
ADCIN 1
PGA 1 OUTPUT
CONVERSION
RESULT AVAILABLE
IN FIFO
CONVERSION
RESULT AVAILABLE
IN FIFO
ADCMON = 1
Figure 15. ADC Clock Mode 11 Example
26 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
powers down the ADC, and goes idle. The BUSY out-
put stays low and the new clock mode is observed.
For a PGAOUT conversion, set CNVST low for a mini-
mum of 30µs or maximum of 40µs. The BUSY output
goes high at the start of the CNVST pulse and the
PGAOUT conversion result is available in the FIFO (if the
ADCMON bit has been set) 52µs (typ) after BUSY goes
low again.
Turning the Continuous Conversion Bit
(CONCONꢃ) On and Off
When switching between continuous and single conver-
sion modes, the clock mode requires resetting to avoid
hanging the ADC sequencing routine.
For an ADCIN conversion, set CNVST low for at least
1.5µs. The BUSY output goes high at the end of the
CNVST pulse and the ADCIN conversion result is avail-
able in the FIFO (if the ADCMON bit is set) 7µs (typ) after
BUSY goes low again.
For example, the following is the command sequence to
switch from continuous to single conversion and revert to
continuous conversion:
1) Write ADCCON (00000000 10110111).
For ease of operation, all CNVST pulses can use a 30µs
width irrespective of the source being converted. In the
case of ADC conversions, the BUSY pulse width is
extended accordingly. For clock modes 00 and 01, the
BUSY pulse width duration depends on the channel con-
version sequence selected.
2) Turn off the selected channels, but leave the continu-
ous convert bit asserted. Write ADCCON (00000000
10000000).
3) Turn off the continuous convert bit. Write ADCCON
(00000000 00000000).
Continuous conversion is not supported in this clock
mode (see Table 20 for the ADC Conversion register).
4) Change from the current clock mode (00 in this case)
to any other one. Write HCFIG (00000100 00011000).
Changing Cꢄock Modes During ADC Conversions
If a change is made to the clock mode in the configura-
tion register while the ADC is already performing a con-
version (or series of conversions), the following
describes how the MAX11008 responds:
5) Change the clock mode back. Write HCFIG
(00000100 00001000).
6) Clear the FIFO. Write SCLR (00000000 00000100).
7) Perform the single conversion. Write ADCCON
(00000000 00110111).
• When CKSEL = 00 and is then changed to another
value, the ADC completes the already triggered series
of conversions and then goes idle. The BUSY output
remains high until the conversions are completed. The
MAX11008 then responds in accordance with the new
CKSEL mode.
8) Read the FIFO five times to capture the results of the
single conversions. Read FIFO.
9) Turn continuous convert back on. Write ADCCON
(00000000 10110111).
The alternative to this command sequence is to leave
continuous conversion on and just read the FIFO. When
using this method, decode the channel tag to determine
which channel has been read.
• When CKSEL = 01 and is then changed to another
value and if the device is waiting for the initial external
trigger, the MAX11008 immediately exits clock mode
01, powers down the ADC, and goes idle. The BUSY
output stays low and the new clock mode is observed.
If a conversion sequence has started, the ADC com-
pletes the requested conversions and then goes idle.
The BUSY output remains high until the conversions
are completed. The MAX11008 then responds in
accordance with the new CKSEL mode.
12-Bit DACs
In addition to the 12-bit ADC, the MAX11008 also
includes two voltage-output, 12-bit, monotonic DACs
with typically less than 2 LSB integral nonlinearity
error and less than 1 LSB differential nonlinearity
error. Each DAC also has a 45ms settling time and
ultra-low glitch energy (4nV·s). The 12-bit DAC codes
• When CKSEL = 11 and is then changed to another
value and if the device is waiting for an external trig-
ger, the MAX11008 immediately exits clock mode 11,
are unipolar binary with 1 LSB = V
/4096.
REFDAC
______________________________________________________________________________________ 2.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Figure 16 shows the functional diagram of the
Output Clamp
The MAX11008 features an output clamp mode that
protects the external LDMOS transistors by connecting
the gate-drive amplifier outputs (GATE_) to AGND. The
clamp mode can be controlled by the OPSAFE_ digital
inputs or by setting the appropriate ALMCLMP[1:0] bits
in the Alarm Hardware Configuration register (see
Table 14). When using the OPSAFE_ digital inputs, pull
OPSAFE_ high to enter clamp mode and pull OPSAFE_
low to exit clamp mode. The clamp can also be activat-
ed automatically from the alarm trip point setting regis-
ters; see the Alarm Software Configuration Register
(ALMSCFIG) (Read/Write) section.
MAX11008 DACs. Each DAC includes an input and
output register. The input registers hold the result of the
most recent write operation, and the output registers
hold the current output code for the respective DAC.
Data written to a DAC input register is transferred to its
output register by writing to the Load DAC register (see
Table 22). Alternatively, write data directly to the output
register using the DAC Input and Output Data register.
The analog output voltages of the DACs (before amplifi-
cation by the gate-drive amplifiers) are calculated with
the following equation:
MAX108
V
×CODE
4096
Self-Calibration
Calibrate channel 1 and channel 2 by writing to the
PGA Calibration Control register. The MAX11008 func-
tions after power-up without a calibration. Command a
calibration after powering up the device by setting the
TRACK bit to 0 and the DOCAL bit to 1 (see Table 19).
Subsequently, set the TRACK, DOCAL, and SELFTIME
bits to 1 to enable automatic self-calibration (approxi-
mately every 13ms). This minimizes loss of perfor-
mance over temperature and supply-voltage variation.
Alternatively, run self-calibration manually to control the
timing of the operation. Set the TRACK and DOCAL bits
to 1 and the SELFTIME bit to 0 to perform manually trig-
gered self-calibration.
DACREF
V
=
DAC
where V
is the value of the internal or external
reference voltage and CODE is the decimal value of the
12-bit code contained in the output register.
DACREF
Gate-Drive Amplifiers
The gate-drive amplifiers are proportional to the analog
outputs of the 12-bit DACs and provide the necessary
gate voltage to drive the external LDMOS transistors.
Both amplifiers have a fixed gain of 2V/V and are capa-
ble of sourcing or sinking up to 2mA of current. Output
short-circuit protection prevents output currents from
exceeding 25mA.
The self-calibration algorithm cancels offsets at the
PGA-drive amplifier inputs in approximately 50µV incre-
ments to improve accuracy. The self-calibration routine
can be commanded when the DACs are powered
down, but the results will not be accurate. For best
results, run the calibration after the DAC power-up time,
The gate output is equal to the DAC output voltage
amplified by 2.
V
= 2 x V
DAC
GATE_
See the Software Configuration Registers and
Temperature/APC LUT Configuration Registers sections
for information on how the gate voltages are controlled
by temperature and APC samples.
t
. The ADC’s operation is suspended during a
DPUEXT
self-calibration. The BUSY output returning low indi-
cates the end of the self-calibration routine. Wait until
the end of the self-calibration routine before requesting
an ADC conversion.
CHANNEL 1/CHANNEL 2
DAC INPUT REGISTERS
CHANNEL 1/CHANNEL 2
CHANNEL 1/
CHANNEL 2 DAC
DAC OUTPUT REGISTERS
LDDACCH_
SET TO 1 IN
LOAD DAC
REGISTER
Figure 16. DAC Functional Diagram
28 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
In clock mode 00, initiate temperature conversions by
writing 0x13 to the ADC Conversion register. In clock
mode 01, initiate temperature conversions by writing
0x13 to the ADC Conversion register and pulse CNVST
low. In clock mode 11, initiate temperature conversions
by writing 0x13 to the ADC Conversion register and
pulse CNVST low for each channel conversion. Set the
corresponding data bits for the temperature sensor to
be measured to 1 (see the ADC Conversion Register
(ADCCON) (Write Only) section and Table 20) for all
three clock modes. Set the high and low external tem-
perature thresholds through the temperature threshold
registers. See the Low Temperature Threshold
Registers (TL1, TL2) (Read/Write) section, High
Temperature Threshold Registers (TH1, TH2)
(Read/Write) section, and Tables 7 and 8).
ADC and DAC References
The MAX11008 provides an internal low-noise +2.5V
reference for the ADCs, DACs and temperature sensor.
When using the internal reference the REFDAC and
REFADC inputs can either be left open or to improve
noise performance, bypassed with a 0.1µF capacitor to
AGND. Connect a voltage source to the REFADC input
ranging between +1V to AV
to configure the device
DD
for external ADC reference mode. Connect a voltage
source to the REFDAC input ranging between +0.7V to
+2.5V to configure the device for external DAC refer-
ence mode. When using an external voltage reference,
bypass the REFDAC and REFADC inputs with a 0.1µF
capacitor to AGND. Bits D[3:0] within the Hardware
Configuration register control the source of the DAC
and ADC references. See Table 11.
The reference voltage for the temperature measure-
ments is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where only temperature
measurements are requested, temperature conversions
are carried out in the following order: INTEMP,
EXTEMP1, then EXTEMP2. If the ADCMON bit is set
when the conversions are performed, the temperature
readings are available in the FIFO.
Temperature Sensors
The MAX11008 measures the internal die temperature
and two external LDMOS transistor temperatures through
one internal and two external diode-connected transis-
tors. The MAX11008 performs temperature measure-
ments by changing the bias current of each diode from
4µA to 68µA to produce a temperature-dependent bias
voltage difference. The internal ADC converts the volt-
age difference to a digital value. The conversion result at
4µA is subtracted from the conversion results at 68µA to
calculate a digital value that is proportional to absolute
temperature. The output data sent to the master will be
the resultant digital code minus an offset value to adjust
from Kelvin to Celsius. Temperature data is delivered to
the master as a 12-bit signed (two’s complement) frac-
tional number with the 3 LSBs being the fractional bits.
This provides a temperature measurement resolution of
1/8°C. See Table 3 for examples of the signed fractional
number digital temperature codes.
The temperature-sensing circuits power up at the start
of an ADC conversion scan. The temperature-sensing
circuits remain powered on until the end of the scan to
avoid a 50µs delay caused by the internal reference
power-up time required for each individual temperature
channel. The temperature-sensor circuits remain pow-
ered up when the ADC conversion register’s continu-
ous convert bit (CONCONV, see Table 20) is set to 1
and the current ADC conversion includes a tempera-
ture channel. The temperature-sensor circuits remain
powered up until the CONCONV bit is set low.
Tabꢄe 3ꢀ Signed Fractionaꢄ Number
Temperature-Code Exampꢄes
The external temperature-sensor drive current ratio has
been optimized for a 2N3904 npn transistor with an ide-
ality factor of 1.0065. The nonideality offset is removed
internally by a preset digital coefficient. Using a transis-
tor with a different ideality factor produces a proportion-
ate difference in the absolute measured temperature.
For more details on this topic and others related to
using an external temperature sensor, refer to
Application Note 1057: Compensating for Ideality
Factor and Series Resistance Differences between
Thermal Sense Diodes and Application Note 1944:
Temperature Monitoring Using the MAX1253/54 and
MAX1153/54.
TEMPERATURE
(°C)
DIGITAL CODE
[D11:0]
-40
-1.625
0
1110 1100 0000
1111 1111 0011
0000 0000 0000
0000 1101 1001
0011 0100 1000
+27.125
+105
______________________________________________________________________________________ 29
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
be written to the EEPROM (see the LUT Streaming
High-Side Current-Sense
Amplifiers and PGAs
Mode section), or data that is to be read from the
EEPROM (see the Message Mode section). The data
remains in the FIFO until it can be read by the master
device through the serial data line (see the ADC
Monitoring Mode or Message Mode section) or written
to the EEPROM (see the LUT Streaming Mode section).
The proceeding sections describe the various modes
of operation and data flow control that involve the FIFO.
The MAX11008 provides dual high-side current-sense
and differential amplifier capability. The current-sense
amplifiers provide a 5V to 32V input common-mode
range. Both CS_+ and CS_- must be within the speci-
fied common-mode range for proper operation of each
amplifier.
The sense amplifiers measure the load current, I
,
LOAD
, between
through an external sense resistor, R
SENSE
ADC Monitoring Mode
Setting the ADCMON (D10) bit in the Hardware
Configuration register (see Table 11) places the
MAX11008 into ADC monitoring mode. The 12-bit ADC
conversion result of the selected channel is placed into
the FIFO along with a 4-bit channel tag. The 4-bit chan-
nel tag is primarily used to indicate the origin of the
conversion, and can also be used to indicate that the
conversion data may be corrupted during FIFO over-
flow or that the FIFO is currently empty (see Tables 24
and 24a).
MAX108
the CS_+ and CS_- inputs. The full-scale sense voltage
range (V = V - V ) depends on the pro-
SENSE
CS_+
CS_-
grammed gain (see the Electrical Characteristics sec-
tion). The sense amplifiers provide a voltage output at
PGAOUT1 and/or PGAOUT2, where the output voltage
is determined by the following equation:
V
= A
x (V
- V
)
CS_-
PGAOUT_
PGA
CS_+
where A
is the selected gain setting of the PGA (2,
PGA
10, or 25).
The PGA outputs are routed to the internal 12-bit ADC to
internally monitor and/or read through the serial interface.
The PGA scales the sensed voltages to fit the input range
for the ADC. Program the PGA with gains of 2, 10, and 25
by setting the PG_SET_ bits in the Hardware
Configuration register (see Tables 11 and 11c).
When multiple conversions are made, the FIFO may
overflow if data is placed into the FIFO faster than it is
read out. In this case, the FIFO stores the seven most
recent ADC conversions. When the 8th conversion
result enters the FIFO, the oldest conversion is discard-
ed, thereby leaving the seven most recent results. The
FIFOOVER bit (D8) in the Flag register (see Table 26) is
set to 1 when FIFO overflow occurs.
To increase the accuracy of drain current measure-
ments, the MAX11008 features a PGA output offset volt-
age calibration function. The PGA calibration function
has two modes of operation: acquisition mode and
tracking mode. In acquisition mode, the calibration rou-
tine operates continuously until the offset error of the
PGA is minimized. In tracking mode, the calibration
routine operates intermittently and has higher noise
thresholds (more averaging). Typically, the first calibra-
tion is performed in acquisition mode and all subse-
quent calibrations are performed in tracking mode. The
PGA Calibration Control register selects the PGA cali-
bration mode and controls when calibrations occur
(see the PGA Calibration Control Register (PGACAL)
(Write Only) section).
If the FIFO is full and overflowing on each ADC conver-
sion, there is a narrow timing window in which reading
the FIFO produces invalid data. The MAX11008 detects
this hazard and flags the data as unreliable by using
the channel tag error (1110). Only the data being read
through the serial interface is invalid. The ADC sample
used internally for V
calculations is valid. To avoid
GATE_
overflow, systematically remove data from the FIFO.
If the ADC data is read out of the FIFO faster than data
is transferred into the FIFO, essentially emptying the
FIFO, a data word containing the empty FIFO tag
(1111) and the current status of the Flag register is
read from the FIFO.
Since PGA calibration affects the accuracy of ADC
conversion results, avoid performing PGA calibrations
when ADC conversions are in progress. Wait at least
LUT Streaming Mode
The LUT streaming mode is used to write data to the
EEPROM. Place the MAX11008 in LUT streaming mode
by writing to the LUT Streaming register (see Table 27)
and disabling the internal watchdog oscillator in the
Software Shutdown register. The FIFO is cleared when
entering LUT streaming mode, so important data
remaining in the FIFO should be read before entering
this mode. Write the data that is to be transferred to the
EEPROM to the FIFO. The MAX11008 automatically
2µs (t
) after DAC power-up before performing a
DPUEXT
PGA calibration.
First-In-First-Out (FIFO)
The MAX11008 utilizes a bidirectional FIFO that can
store up to eight 16-bit data words. The data stored in
the FIFO may consist of ADC conversion results (see
the ADC Monitoring Mode section), user data that is to
30 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
moves the data from the FIFO and writes it to the
EEPROM data, so it is necessary to use data flow-con-
trol methods to safely read the EEPROM.
EEPROM. The MAX11008 remains in LUT streaming
mode until the specified amount of data is written to the
EEPROM. Set the internal watchdog oscillator when
LUT streaming mode is exited. If the FIFO is emptied
before all of the data is written to the EEPROM, the
MAX11008 waits until more data is placed into the
FIFO. If data is placed into the FIFO faster than it can
be written to the EEPROM causing the FIFO to fill com-
pletely, the FIFOOVER bit in the Flag register is set to 1
and all subsequent writes to the FIFO are ignored until
there is space for another data word.
The BUSY output goes high during message mode and
returns low after all of the specified EEPROM data is
read from the FIFO.
FIFO data flow control in message mode can be imple-
mented with the following methods:
1) Open Loop—Read data from the FIFO at a rate no
greater than 1 word per 50µs, which guarantees that
the FIFO does not empty completely before all of the
specified data is copied from the EEPROM.
The BUSY output goes high during LUT streaming
mode and returns low after all of the data is written to
the EEPROM.
2) Software Flow Control—Check the FIFOEMP bit (D9)
in the Flag register (see Table 26) in between FIFO
read commands to ensure that the FIFO is not
empty.
FIFO data flow control in the LUT streaming mode can
be implemented with the following methods:
3) FIFO Status Monitoring—By setting the FIFOSTAT bit
(D11) to 1 in the Hardware Configuration register, the
ALARM output is used to indicate FIFO status. When
the FIFO is empty, the ALARM output goes low and
returns high after more data is copied into the FIFO.
1) Open Loop—Write data to the FIFO at a rate that
does not exceed 1 word per 60µs to guarantee that
the FIFO does not overflow.
2) Software Flow Control—Check the FIFOOVER bit
(D8) in the Flag register (see Table 26) in between
FIFO write commands to ensure that the FIFO is not
full; then write data to the FIFO.
BUSY Output
The BUSY output goes high to show that the MAX11008
is busy for the reasons listed below:
3) FIFO Status Monitoring—By setting the FIFOSTAT bit
(D11) to 1 in the Hardware Configuration register,
the ALARM output is used to indicate FIFO status.
When the FIFO is full, the ALARM output goes low
and returns high when there is space in the FIFO for
another data word. See Figures 17 and 18.
1) The ADC is in the middle of a user-commanded con-
version cycle (but not in continuous convert mode).
2) Power-up initializations are being performed.
3) A V
calculation is being made.
GATE_
4) Data is being read from the EEPROM (message
mode).
Message Mode
Use the message mode to read data from the
EEPROM. Write to the user Message register to place
the MAX11008 into message mode (see Table 23). The
FIFO is cleared when entering message mode, so
important data contained in the FIFO should be read
before entering this mode. The specified EEPROM data
is copied into the FIFO and is read by issuing a FIFO
read command. The MAX11008 remains in message
mode until all of the specified EEPROM data is copied
into and read from the FIFO. If the EEPROM data is
copied into the FIFO faster than it is read causing the
FIFO to fill completely, the copying action is suspended
until a data word is read out of the FIFO and the
FIFOOVER bit is set to indicate a not-full condition. If
the EEPROM data is read out of the FIFO faster than it
can be copied causing the FIFO to empty completely, a
data word containing the empty FIFO tag (1111) and
current status of the Flag register is read from the FIFO.
This underflow data is indistinguishable from arbitrary
5) Data is being written to the EEPROM (LUT streaming
mode).
6) One of the PGAs is undergoing calibration.
The serial interface remains active regardless of the state
of the BUSY output. Wait until BUSY goes low to read the
current conversion data from the FIFO. When BUSY is
high, as a result of an ADC conversion, do not enter a
second conversion command until BUSY has gone low
to indicate the previous conversion is complete.
In multiple conversion mode (CKSEL1, CKSEL0 = 01 or
CKSEL1, CKSEL0 = 00), the BUSY signal remains high
until all channels have been scanned and the data from
the final channel has been moved into the FIFO and
checked for alarm limits if enabled (see the Alarm
Software Configuration Register (ALMSCFIG)
(Read/Write) section). In continuous-conversion mode
(CONCONV = 1), the BUSY signal does not go high as
a result of ADC conversions; however, BUSY does go
high when CONCONV is cleared and BUSY remains
______________________________________________________________________________________ 31
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
COUNT = 0
MAX108
NO
COUNT < MAX
EXIT
YES
NO
FIFO FULL
WAIT 60µs
FLAG (FIFO_OVER_FLOW) = 0
YES
WRITE DATA TO FIFO
COUNT = COUNT + 1
Figure 17. Software Flow Control Example (Pseudo Code)
32 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
COUNT = 0
NO
COUNT < MAX
EXIT
YES
NO
FIFO FULL
WAIT 60µs
ALARM = 1
YES
WRITE DATA TO FIFO
COUNT = COUNT + 1
Figure 18. Hardware Flow Control Example (Pseudo Code)
______________________________________________________________________________________ 33
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
high until the current scan is complete and the ADC
sequence halts. In single-conversion mode (CKSEL1,
CKSEL0 = 11), the BUSY signal remains high until the
ADC has completed the current conversion (not the
entire scan), the data has been moved into the FIFO,
and the alarm limits for the channel have been checked
(if alarm is enabled).
configure the temperature alarm thresholds for channel 1
or channel 2 to window mode. Set the IWIN1 bit (D0) or
IWIN2 bit (D4) to 1 in the Alarm Software Configuration
register to set the current alarm thresholds for channel 1
or channel 2 to window mode. In window mode, temper-
ature/current measurements are compared to the set
temperature/current high and low thresholds. If a mea-
sured value is outside the configured window values
(between the set high and low thresholds) and that cor-
responding channel is configured to cause an alarm
condition, the alarm asserts. The alarm remains internally
asserted until the measured values from that channel fall
back into the window and past the configurable hystere-
sis. The external behavior of ALARM and the gate
clamps are controlled by the settings of the ACOMP and
ALMCLMP_ bits in the Alarm Hardware Configuration
register. The amount of built-in hysteresis can be varied
from 8 LSBs to 64 LSBs by setting ALMHYST[1:0] bits
(D6 and D7) in the Alarm Hardware Configuration regis-
ter (see Tables 14 and 14a). See Figures 19 and 20 for
window-mode threshold examples.
Alarm Function
The MAX11008 features a multipurpose alarm function
that indicates when a temperature sensor or a current-
sense amplifier reading exceeds the threshold values
specified in the High Temperature Threshold, Low
Temperature Threshold, High Current Threshold, and
Low Current Threshold registers (see Tables 7 to 10).
The thresholds for each temperature sensor and cur-
rent-sense amplifier channel are set individually and
can be configured to operate in window mode or hys-
teresis mode (see the Window Mode and Hysteresis
Mode sections). Alarm indication is provided by the
ALARM output while information on the source of the
alarm is contained in the Flag register (see Table 26).
The enabling of the various alarms, the polarity of the
ALARM output (active-high or active-low), the ALARM-
output modes, the alarm-threshold modes, and the
methods by which the MAX11008 services an alarm are
controlled with the Alarm Software Configuration regis-
ter and Alarm Hardware Configuration register (see
Tables 12 and 14).
MAX108
Hꢂsteresis Mode
Set the TWIN1 bit (D2) or TWIN2 bit (D6) to 0 in the
Alarm Software Configuration register (see Table 12) to
set the temperature alarm thresholds for channel 1 or
channel 2 to hysteresis mode. Set the IWIN1 bit (D0) or
IWIN2 bit (D4) to 0 to set the current alarm thresholds
for channel 1 or channel 2 to hysteresis mode. In hys-
teresis mode, temperature or current measurements
are compared to the set temperature/current high and
low thresholds. If a measured value is above the set
high threshold and the corresponding channel is con-
figured to cause an alarm condition, the alarm asserts.
ALARM remains internally asserted until the measured
values from that channel fall back below the low thresh-
old setting. The external behavior of ALARM and the
gate clamps are controlled by the settings of the
ACOMP and ALMCLMP_ bits in the Alarm Hardware
Configuration register. See Figures 21 and 22 for hys-
teresis-mode threshold examples.
ALARM-Output Modes
The ALARM output operates in comparator mode or
interrupt mode based on the setting of the ACOMP bit
(D8) in the Alarm Hardware Configuration register (see
Table 14).
When configured for comparator mode, the ALARM
output is asserted when the measured current or tem-
perature value exceeds the set threshold level and is
deasserted when the value returns below the set
threshold level.
When configured for interrupt mode, the ALARM output
is asserted when the measured current/temperature
value exceeds the set threshold level and remains
asserted until the Flag register is read, at which time
the ALARM output is deasserted. The alarm output is
only asserted again if the alarm channel recovers and
then re-trips (or if a different alarm channel trips).
V
GATE
_ Output Equation
Based on the monitored LDMOS current analog input
voltage and temperature values, the MAX11008 logically
decides if the calculated bias voltage, V , driving the
GATE_
gate of the RF LDMOS, should be recalculated and
adjusted to maintain the desired RF LDMOS drain cur-
rent. The MAX11008 independently monitors and calcu-
See Figures 19 and 20 for examples of both ALARM-
output modes.
lates the V
voltage for both channel 1 and channel
GATE_
2. The MAX11008 implements the following equation
when calculating V for each DAC channel:
Window Mode
Set the TWIN1 bit (D2) or TWIN2 bit (D6) to 1 in the
Alarm Software Configuration register (see Table 12) to
GATE_
34 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
(MEASUREMENT VALUE
TEMPERATURE OR CURRENT)
HIGH THRESHOLD
BUILT-IN HYSTERESIS
BUILT-IN HYSTERESIS
LOW THRESHOLD
TIME
ALARM
OUTPUT
COMPARATOR MODE
(ACTIVE LOW)
INTERRUPT MODE
(ACTIVE LOW)
TIME
ALARM FLAG
ALARM FLAG
ALARM FLAG
REGISTER READ
REGISTER READ
REGISTER READ
Figure 19. ALARM Output Signal Example—Alarm Thresholds Configured for Window Mode
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE FALLS
BELOW THIS LEVEL*
HIGH THRESHOLD
BUILT-IN 8–64 LSBs
OF HYSTERESIS
RANGE OF VALUES THAT DO
NOT CAUSE AN ALARM
BUILT-IN 8–64 LSBs
OF HYSTERESIS
LOW THRESHOLD
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE RISES
ABOVE THIS LEVEL*
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR LOW
THRESHOLD REGISTER)
*ONLY WHEN ALARM IS CONFIGURED FOR COMPARATOR MODE. WHEN IN INTERRUPT
MODE, FLAG REGISTER MUST BE READ FOR ALARM TO BE DEASSERTED.
Figure 20. Window-Mode Alarm-Threshold Diagram
______________________________________________________________________________________ 35
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MEASUREMENT VALUE
(TEMPERATURE OR CURRENT)
HIGH THRESHOLD
LOW THRESHOLD
MAX108
TIME
ALARM OUTPUT
COMPARATOR MODE
(ACTIVE LOW)
INTERRUPT MODE
(ACTIVE LOW)
TIME
ALARM FLAG
REGISTER
READ
ALARM FLAG
REGISTER
READ
Figure 21. ALARM Output Signal Example—Alarm Thresholds Configured for Hysteresis Mode
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
HIGH THRESHOLD
LOW THRESHOLD
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL*
RANGE OF VALUES THAT WILL
NOT CAUSE AN ALARM
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR LOW
THRESHOLD REGISTER)
*ONLY WHEN ALARM IS CONFIGURED FOR COMPARATOR MODE. WHEN IN INTERRUPT
MODE, FLAG REGISTER MUST BE READ FOR ALARM TO BE DEASSERTED.
Figure 22. ALARM Output Signal Example—Alarm Thresholds Configured for Hysteresis Mode
36 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
V
= (2 x V
x CODE)/4096
5) The V
equation is now calculated and
GATE_
GATE_
REFDAC
depending on the status of the LDAC_ bit, output to
the appropriate DAC. The actual value of the DAC
output depends on the values within the LUT. It is
= [2 x V
x (VSET_ + LUTTEMP{Temp} +
REFDAC
LUTAPC{APC})]/4096
where:
possible that the new value for V
is the same
GATE_
V
V
= actual gate voltage.
as the last value for V
, even though the hys-
GATE_
GATE_
teresis in step 2 was exceeded.
= factory-set DAC code at TCAL.
SET_
If averaging is enabled for either the temperature or
APC parameter, the V
LUTTEMP{Temp} = interpolated lookup value in the
TEMP table for the sampled temperature.
calculation process is the
GATE_
same. The difference is that the value for the ADC sam-
ple (step 1 and step 3) is replaced by an ADC average.
The MAX11008 measures 16 samples to acquire an ini-
tial average. When averaging is enabled, the first 15
LUTAPC{APC} = interpolated lookup value in the APC
table for the APC parameter.
TCAL = temperature at which LUTTEMP{TCAL} returns
0; i.e., the calibration temperature.
samples do not trigger a new average, and a V
GATE_
calculation is not triggered. After the average is
acquired, each new ADC sample produces a new
rolling average. The rolling average is calculated with
the following equations.
V
is a 12-bit unsigned DAC code (0 to 4095).
SET_
LUTTEMP{Temp} and LUTAPC{APC} are the result of
lookup operations and are 16-bit signed numbers in
DAC CODE units. The MAX11008 calculates the sum of
(V
+ LUTTEMP{Temp} + LUTAPC{APC}) with 16-bit
In acquire mode:
SET_
signed arithmetic and limits that result to the 12-bit res-
olution of the DAC (0 to 4095) to arrive at the final out-
put DAC CODE.
15
Average =
Sample/16
∑
j = 0
The LUT values for Temp (LUTTEMP{Temp}) and APC
(LUTAPC{APC}) are the result of lookup table opera-
tions (LUT operations). The values are directly stored in
the LUT sections of the EEPROM. They are 16-bit
signed (two’s complement) quantities, but to prevent
mathematical overflow, their magnitude should be limit-
ed to 12-bit quantities (-4096 to +4095, which is the full
range of the DAC ignoring the sign).
Average is only valid after 16 samples.
In tracking mode:
Average = 15/16 Average + 1/16 Sample
= 15/16 Average + 1/16 (Average + Difference)
where:
Difference = Sample - Average
= Average + 1/16 Difference
= Average + 1/16 (Limited Difference)
When averaging is disabled, V
ceed as follows:
operations pro-
GATE_
1) A new ADC sample is measured and compared to
the last sample used for a V calculation.
The limited difference between the sample and the
average is a maximum value that is set by the T_LIMIT
and A_LIMIT bits, which are used to reject spurious
noise. Difference limiting may be set from 1 LSB to 64
LSBs, or may be disabled altogether.
GATE_
2) The absolute difference between the two ADC mea-
surements is compared to the hysteresis setting. If
the difference is equal to or greater than the hystere-
sis setting, the new sample is used to recalculate
V
. If the hysteresis setting is not exceeded, the
By setting the A_AVGCTL and T_AVGCTL bits, the
average tracking formula can be altered to add 1/4 of
the difference on each calculation, rather than 1/16.
This reduces the filter’s time constant and allows the
average to track faster moving signals, and is most
suited to the APC channel. The A_AVGCTL and
T_AVGCTL bits do not alter the formula for acquiring
the initial average.
GATE_
following steps are bypassed and V
recalculated.
is not
GATE_
3) The ADC sample is converted to a pointer for the
LUT. The mechanism for this is explained in the fol-
lowing section, but the process turns the 12-bit ADC
sample into an n-bit pointer.
4) The lookup operation is performed, and if required,
an interpolation between two table values is calcu-
lated. The result from the lookup table is stored as
either LUTTEMP{Temp} or LUTAPC{APC}.
If the APC[11:0] value is used instead of an ADC sam-
ple for the APC sample, all averaging and hysteresis
functions are bypassed. The serial interface directly
controls the APC[11:0] value and triggers a V
culation each time it is written.
cal-
GATE_
______________________________________________________________________________________ 3.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 4ꢀ EEPROM Address Map
WORD ADDRESS
INTERFACE (CUSTOMER) COMMAND
BIN
DEC
0
HEX
0
MNEMONIC
TABLE
COMMENT
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
0001 1111
—
—
—
1
1
—
2
2
—
—
3
3
—
—
4
4
—
—
MAX108
5
5
—
—
6
6
—
—
7
7
—
—
Unused. User data may
be stored here.
8
8
—
—
9
9
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
—
—
—
—
—
—
—
—
—
—
—
—
EE_TH1
EE_TL1
EE_1H1
EE_IL1
EE_TH2
EE_TL2
EE_IH2
EE_IL2
EE_HCFIG
EE_ALMSCF
EE_SCFIG
EE_ALMHCF
EE_VSET1
EE_HIST_AP
EE_VSET2
EE_HIST_AP
7
8
9
Nonvolatile alarm trip
points (DPRAM
locations)
10
7
8
9
10
11
12
13
14
Nonvolatile configuration
(DPRAM locations)
15
16a, 16b
15
16a, 16b
38 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 4ꢀ EEPROM Address Map (continued)
WORD ADDRESS
INTERFACE (CUSTOMER) COMMAND
COMMENT
BIN
DEC
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
HEX
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
4A
4B
4C
4D
4E
4F
MNEMONIC
—
TABLE
—
—
—
—
—
—
—
—
—
—
—
—
17
18
17
18
19
20
21
22
—
—
—
—
—
—
—
—
5
0010 0000
0010 0001
0010 0010
0010 0011
0010 0100
0010 0101
0010 0110
0010 0111
0010 1000
0010 1001
0010 1010
0010 1011
0010 1100
0010 1101
0010 1110
0010 1111
0011 0000
0011 0001
0011 0010
0011 0011
0011 0100
0011 0101
0011 0110
0011 0111
0011 1000
0011 1001
0011 1010
0011 1011
0011 1100
0011 1101
0011 1110
0011 1111
—
—
—
—
—
Unused. User data may
be stored here.
—
—
—
—
—
—
EE_IDAC1
EE_IODAC1
EE_IDAC2
EE_IODAC2
EE_PGACAL
EE_ADCCON
EE_SSHUT
EE_LDAC
Reserved
Reserved
Reserved
MAGIC NUMBER
Reserved
Reserved
Reserved
Reserved
EE_TLUT1
EE_ALUT1
EE_TLUT2
EE_ALUT2
—
—
—
—
—
—
—
—
—
—
—
AA55
—
—
—
—
5
LUT configuration
5
5
______________________________________________________________________________________ 39
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
By correctly configuring the initialization values stored
within the EEPROM, the MAX11008 can automatically
enter V compensation mode without the need for
a host processor. This autonomous operation is useful
in some application areas where a host controller is not
desired.
EEPROM
The MAX11008 features 4Kb of EEPROM capable of
storing up to 256 16-bit data words. The first 64 data
words of the EEPROM contain configuration data (see
Table 4) while the remaining 192 data words are pro-
grammable and used for storing temperature and APC
LUTs. The MAX11008 utilizes the LUT values to perform
GATE_
Changes made to the working registers during opera-
tion are volatile. To change a register’s nonvolatile ini-
tialization value, the corresponding EEPROM location
must be written by the LUT streaming protocol.
gate voltage calculations (see the V
_ Output
GATE
Equation section). See the First-In-First-Out (FIFO), LUT
Streaming Mode, and Message Mode sections for more
information on how to program and read from the
EEPROM. See the Temperature/APC LUT Configuration
Registers section for information on how to configure
the LUTs and how values are retrieved from the LUTs
MAX108
Magic Number
The address location 0x37 of the EEPROM is referred
to as the magic address. If the magic address is pro-
grammed with the magic number (0xAA55), the values
stored in address locations 0x10–0x1F and 0x2C–0x33
are loaded into the working registers (see the Register
Address Map section) during power-up initialization.
Address locations 0x10–0x1F are unconditionally
loaded into the working registers, whereas address
locations 0x2C–0x33 are only loaded if bit D15
(WCTRAM) of the address is set to 1. If magic address
location 0x37 is not programmed with the magic num-
ber (0xAA55), the EEPROM is determined to be unpro-
grammed; the power-up initialization load is then
bypassed and the working registers default to their
power-on reset value.
for V
calculations. See Table 5.
GATE_
Nonvoꢄatiꢄe Initiaꢄization ꢃaꢄues
Upon power-on reset, the data contained within specif-
ic EEPROM locations is copied directly to correspond-
ing locations within the register address map
depending on the state of the magic number (see the
Magic Number section).
• Locations 0x10–0x1F are directly copied to their cor-
responding locations within the register address
map.
• Locations 0x2C–0x33 are conditionally copied to
their corresponding locations within the register
address map. Set the MSB (labeled WCTRAM) to 1
for locations 0x2C–0x33 to be copied to the register
address map (see Table 4a).
LUT ꢃaꢄues
The values stored within the LUT section of the
EEPROM are 16-bit signed (two’s complement)
Tabꢄe 4aꢀ EEPROM Address Bit Map
HEX
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1D
1E
1F
1F
2C
2D
2E
2F
30
31
32
33
37
3C
3D
3E
3F
MNEMONIC
EE_TH1
TABLE
7
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
D11
D11
D11
D11
D11
D11
D11
D11
BIT 10
D10
D10
D10
D10
D10
D10
D10
D10
BIT 9
D9
BIT 8
D8
BIT .
D7
BIT 6
D6
BIT 5
D5
BIT 4
D4
BIT 3
BIT 2
D2
BIT 1
D1
BIT 0
D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3
EE_TL1
8
X
D9
D8
D7
D6
D5
D4
D3
D3
D2
D1
D0
EE_IH1
9
X
D9
D8
D7
D6
D5
D4
D2
D1
D0
EE_IL1
10
7
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EE_TH2
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EE_TL2
8
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EE_IH2
9
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EE_IL2
10
11
12
13
14
15
16a
16b
15
16a
16b
17
18
17
18
19
20
21
22
—
5
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EE_HCFIG
EE_ALMSCF
EE_SCFIG
EE_ALMHCF
EE_VSET1
EE_HIST_AP
EE_HIST_AP
EE_VSET2
EE_HIST_AP
EE_HIST_AP
EE_IDAC1
EE_IODAC1
EE_IDAC2
EE_IODAC2
EE_PGACAL
EE_ADCCON
EE_SSHUT
EE_LDAC
MAGIC NUMBER
EE_TLUT1
EE_ALUT1
EE_TLUT2
EE_ALUT2
T1AVGCTL T1LIMIT2
T1LIMIT1
T1LIMIT0 FIFOSTAT ADCMON
PG2SET1
A1AVG
PG2SET0
T1AVG
TSRC2
PG1SET1
TALARM2
PG1SET1
TWIN2
CKSEL1
IALARM2
LDAC1
CKSEL0
IWIN2
TCOMP1
ADCREF1
TALARM1
APCCOMP1
ADCREF0
TWIN1
TSRC1
DACREF1
IALARM1
DACREF0
IWIN1
X
X
X
X
A2AVG
LDAC2
X
T2AVG
T2AVGCTL T2LIMIT2
T2LIMIT1
T1LIMIT0
TCOMP2 APCCOMP2
APCSRC21 APCSRC20
APCSRC11 APCSRC10
X
X
X
X
AVGMON
D10
D10
X
INTEMP2
D9
D9
X
ALMCMP ALMHYST1 ALMHYST0 ALMCLMP21 ALMCLMP20 ALMCLMP11 ALMCLMP10
ALMPOL
D1
ALMOPN
D0
X
X
X
X
D11
D11
X
D8
D8
X
D7
D6
D6
D5
D5
D4
D3
D3
D2
D2
T1HIST3
T1HIST3
X
T1HIST2
T1HIST1
T1HIST0
D7
D4
A1LIMIT0
D4
D1
D0
T1HIST2
T1HIST1
T1HIST0
A1AVGCTL
A1LIMIT2
D6
A1LIMIT1
D5
A1HIST3
D3
A1HIST2
D2
A1HIST1
D1
A1HIST0
D0
X
X
X
D11
D11
X
D10
D10
X
D9
D9
X
D8
D8
X
D7
T1HIST3
T2HIST3
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
WCTRAM
1
T1HIST2
T1HIST1
T1HIST0
D7
D6
D5
D4
D3
D2
D1
D0
T2HIST2
T2HIST2
T2HIST0
A2AVGCTL
A2LIMIT2
D6
A2LIMIT1
D5
A2LIMIT0
D4
A2HIST3
D3
A2HIST2
D2
A2HIST1
D1
A2HIST0
D0
X
X
X
D11
D11
D11
D11
X
D10
D10
D10
D10
X
D9
D9
D9
D9
X
D8
D8
D8
D8
X
D7
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
D7
X
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
TRACK
CS1
OSCPD
X
DOCAL
EXTEMP1
DAC2PD
DAC_CH2
0
SELFTIME
INTEMP
DAC1PD
DAC_CH1
1
X
X
X
X
CONCONV
X
ADCIN2
X
CS2
X
EXTTEMP2
X
ADCIN1
FBGON
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
0
1
0
1
0
1
POFF5
POFF5
POFF5
POFF5
POFF4
POFF4
POFF4
POFF4
POFF3
POFF3
POFF3
POFF3
POFF2
POFF2
POFF2
POFF2
POFF1
POFF1
POFF1
POFF1
POFF0
POFF0
POFF0
POFF0
INT1
INT1
INT1
INT1
INT0
INT0
INT0
INT0
PSIZE1
PSIZE1
PSIZE1
PSIZE1
PSIZE0
PSIZE0
PSIZE0
PSIZE0
TSIZE2
TSIZE2
TSIZE2
TSIZE2
TSIZE1
TSIZE1
TSIZE1
TSIZE1
TSIZE0
TSIZE0
TSIZE0
TSIZE0
SOT2
SOT2
SOT2
SOT2
SOT1
SOT1
SOT1
SOT1
SOT0
SOT0
SOT0
SOT0
5
5
5
40 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
quantities. But to avoid the possibility of mathematical
(see Table 5b). When INT = 00 the LUT pointer has no
fractional bits and no interpolation is performed. When
INT = 00, every LUT pointer corresponds directly to a
table entry. If INT = 01, the LUT pointer has 1 fractional
bit, which represents a fractional 1/2. This represents
an LUT pointer that falls midway between two table
entries, and the MAX11008 performs a linear interpola-
tion between those two entries. Similarly, INT = 10 pro-
vides 2 fractional bits (1/4 resolution or 4:1
interpolation), and INT = 11 provides 3 fractional bits
(1/8 resolution or 8:1 interpolation). See the Calculating
an LUT Pointer from an ADC Sample/APC Parameter
section for a detailed description and examples on cal-
culating LUT pointer values.
overflow, the magnitude of the values should be limited
to 12 bits (-4096 to +4095, which allows full movement
over the range of the 12-bit DAC).
Temperature/APC LUT Configuration Registers
The LUT Configuration register (see Table 5) specifies
the location and the size of the temperature and auto-
matic power control (APC) LUTs. The EEPROM can be
configured to have a total of four LUTs (one tempera-
ture LUT for each temperature-sensor channel and one
APC LUT for each DAC channel). These registers can
only be programmed when the device is in LUT stream-
ing mode and are set while data is being streamed into
the LUT. The data contained in the LUT Configuration
registers is stored in the EEPROM.
The SOT bits set the starting addresses of each corre-
sponding LUT in the EEPROM (see Table 5d). Each
table starts at one of six possible locations within the
EEPROM memory space. It is also possible to make
several LUT tables occupy the same memory space
within the EEPROM by simply setting identical SOT val-
ues. This is useful when temperature or APC data is
common to both channels. This allows a single shared
table of double the resolution to be implemented
instead of two separate identical tables.
When V
calculations are made using temperature
GATE_
and/or APC LUT values, the MAX11008 uses a LUT
pointer to retrieve the correct values for the calculation.
The LUT pointer value is derived from the most recent
12-bit ADC measurement or directly transferred from
the APC Parameter register (see Table 16). The source
of the LUT pointer value depends on the settings of the
Software Configuration register (see Table 13). PSIZE
determines the size of the LUT pointer (see Table 5a).
TSIZE specifies the size of the table (see Table 5c). It is
permissible to use an LUT pointer that is larger than the
table indexed. An 8-bit pointer functions properly with a
LUT of 32 data locations. The LUT pointer values that
extend beyond the table are limited to the upper (or
lower) bound of the table. This technique increases the
effective table resolution when the dynamic range of
ADC samples is limited.
Tables 5e and 5f contain examples on how to configure
the LUTs in EEPROM using the TSIZE, SOT, and
PSIZE bits.
Caꢄcuꢄating an LUT Pointer from an ADC
Sampꢄe/APC Parameter
Calculate the LUT pointer value using the following
steps:
1) The 12-bit ADC value is first shifted to the right by
the number of bits as determined by the following
equation:
The POFF bits set the offset value that is added to the
resulting LUT pointer value. POFF is a signed 6-bit value
that is used to apply both positive and negative offset
values to the LUT pointer. The range of acceptable off-
set values depends on PSIZE (see Table 5a). POFF is
typically used for temperature LUTs that have LUT data
for 0°C measurements located at the center of the LUT.
For example, if a temperature LUT has 64 data locations
(locations 0 through 63), the data for 0°C is located at
the center of the LUT (location 31). If a temperature
measurement is made at 0°C, the resulting ADC conver-
sion is 0, which instructs the LUT pointer to retrieve data
from the first location (location 0) in the LUT. To retrieve
the correct data for 0°C (location 31), a pointer offset of
31 needs to be added to the LUT pointer.
12-bit ADC value right shift = 7 - PSIZE - INT
where PSIZE and INT are the decimal values of
PSIZE and INT in the LUT Configuration register. The
LUT pointer is interpreted as a fixed-point fractional
number where PSIZE specifies the number of inte-
ger bits and INT specifies the number of fractional
bits.
2) The pointer offset value is left-shifted in the following
manner:
If PSIZE = 00 or 01, no shifting is performed.
If PSIZE = 10, POFF is shifted to the left by 1 bit.
If PSIZE = 11, POFF is shifted to the left by 2 bits.
POFF is interpreted as a signed number.
To increase the accuracy of V
calculations, the
GATE_
MAX11008 can linearly interpolate intermediate temper-
ature and APC compensation values from the two clos-
est LUT data locations. To accomplish this, fractional
bits are added to the LUT pointer by setting the INT bits
3) The resulting POFF value is added to the LUT point-
er value.
______________________________________________________________________________________ 41
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
4) The resulting LUT pointer value is bound-limited to
ensure it fits within the corresponding LUT. Negative
pointer values are limited to zero, and pointer values
that extend beyond the range of the LUT are limited
to the last entry.
where PTR is the calculated LUT pointer value with
fractional bits, ADD1 and ADD2 are the two LUT
addresses closest to the value of PTR, and DATA1 and
DATA2 are the LUT data values stored at ADD1 and
ADD2.
5) The final LUT pointer value is calculated by shifting
SOT to the left by 5 bits and then adding it to the
current LUT pointer value. If no linear interpolation
(INT = 00) is to be performed, the resulting LUT
pointer value is equal to the absolute EEPROM
address from which the LUT data is retrieved. If lin-
ear interpolation is to be performed (INT = 01, 10, or
11), the two LUT addresses that are closest to the
resulting LUT pointer value and their corresponding
data values are entered into the following equation
to calculate the interpolated data value that is used
LUT Pointer Exampꢄe 1 (No Interpoꢄation)
POFF = 001000 (offset of +8).
INT = 00 (no interpolation/LUT pointer does not have
any fractional bits).
MAX108
PSIZE = 00 (5-bit LUT pointer not including any frac-
tional bits).
TSIZE = 001 (LUT has 32 data locations).
SOT = 010 (LUT starts at EEPROM address 40 hex).
Tabꢄe 5bꢀ Fractionaꢄ Bits Added to LUT
Pointer for Linear Interpoꢄation
in the V
calculation:
GATE_
PTR − ADD1
ADD2 − ADD1
⎛
⎞
Interpolated Data = DATA1 +
x (DATA2 − DATA1)
⎟
⎜
⎝
⎠
NUMBER OF FRACTIONAL BITS ADDED TO
INT
LUT POINTER
00
01
10
11
0
Tabꢄe 5ꢀ Temperature/APC LUT
Configuration Register
1 ≥ 1:2 interpolation
2 ≥ 1:4 interpolation
3 ≥ 1:8 interpolation
DATA
BITS
BIT
RESET
FUNCTION
NAME STATE
Tabꢄe 5cꢀ Seꢄectabꢄe LUT Sizes
D[15:10] POFF
000000 POFF bits.
Interpolation degree select bits.
See Table 5b.
TSIZE
000
001
010
011
100
101
110
111
LUT SIZE
D[9:8]
INT
00
Unused
LUT pointer size bit. See Table
5a.
Table size of 32 data locations
Table size of 64 data locations
Table size of 96 data locations
Table size of 128 data locations
Table size of 160 data locations
Table size of 192 data locations
Unused
D[7:6]
D[5:3]
D[2:0]
PSIZE
TSIZE
SOT
00
000
000
LUT size bit. See Table 5c.
Start of table address bits. See
Table 5d.
Tabꢄe 5aꢀ LUT Pointer Sizes and Offset
Ranges
Tabꢄe 5dꢀ Seꢄectabꢄe LUT Starting
Addresses
PSIZE
LUT POINTER SIZE
POFF OFFSET RANGE*
5-bit pointer (access up
to 32 data locations)
00
-32 to +31
SOT
000
001
010
011
100
101
110
111
STARTING ADDRESS IN EEPROM (HEX)
Unused
Unused
0x40
6-bit pointer (access up
to 64 data locations)
01
10
11
-32 to +31
7-bit pointer (access up
to 128 data locations)
-64 to +62 (in steps of 2)
-128 to +124 (in steps of 4)
0x60
0x80
8-bit pointer (access up
to 256 data locations)
0xA0
0xC0
0xE0
*POFF is either a negative or positive number. When POFF is
negative its value is represented in two’s complement format.
42 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 5eꢀ LUT Configuration Exampꢄes
REGISTER
ENTRY
CONFIGURATION 1
(EXAMPLE)
POFF = 010100
INT = 00
CONFIGURATION 2
(EXAMPLE)
POFF = 010100
INT = 00
CONFIGURATION 3
(EXAMPLE)
POFF = 100000
INT = 00
CONFIGURATION 4
(EXAMPLE)
Unused (TCOMP in
Software Configuration
register should be set to 0)
Temperature
LUT1
PSIZE = 01
TSIZE = 010
SOT = 100
0x5054
PSIZE = 01
TSIZE = 010
SOT = 100
0x5054
PSIZE = 10
TSIZE = 100
SOT = 010
0x40A2
POFF = 000000
INT = 00
POFF = 000000
INT = 00
POFF = 000000
INT = 00
POFF = 000000
INT = 00
APC
LUT1
PSIZE = 00
TSIZE = 001
SOT = 010
0x000A
PSIZE = 01
TSIZE = 010
SOT = 010
0x0052
PSIZE = 10
TSIZE = 100
SOT = 100
0x00A4
PSIZE = 11
TSIZE = 110
SOT = 010
0x00F2
POFF = 100000
INT = 00
PSIZE = 10
TSIZE = 010
SOT = 110
0x4096
POFF = 010100
INT = 00
PSIZE = 01
TSIZE = 010
SOT = 110
0x5056
POFF = 100000
INT = 00
PSIZE = 10
TSIZE = 010
SOT =010
Unused (TCOMP in
Software Configuration
register should be set to 0)
Temperature
LUT2
0x4092
POFF = 000000
INT = 00
POFF = 000000
INT = 00
POFF = 000000
INT = 00
POFF = 000000
INT = 00
APC
LUT2
PSIZE = 00
TSIZE = 001
SOT = 011
0x000B
PSIZE = 01
TSIZE = 010
SOT = 010
0x0052
PSIZE = 01
TSIZE = 010
SOT = 010
0x00A4
PSIZE = 11
TSIZE = 110
SOT = 010
0x00F2
Tabꢄe 5fꢀ ꢃisuaꢄ Exampꢄe of LUT
WORD
ADDRESS
CONFIGURATION 1
(EXAMPLE)
CONFIGURATION 2
(EXAMPLE)
CONFIGURATION 3
CONFIGURATION 4
(EXAMPLE)
(EXAMPLE)
0x00 to 0x0F
0x10 to 0x3F
Dedicated user message
Configuration data
APC LUT1
32 x 16 bits
0x40 to 0x5F
0x60 to 0x7F
Unified APC LUT
64 x 16 bits
Unified Temperature LUT
64 x 16 bits
APC LUT2
32 x 16 bits
Unified APC LUT
192 x 16 bits
0x80 to 0x9F
0xA0 to 0xBF
0xC0 to 0xDF
0xE0 to 0xFF
Temperature LUT1
64 x 16 bits
Temperature LUT1
64 x 16 bits
Unified APC LUT
128 x 16 bits
Temperature LUT2
64 x 16 bits
Temperature LUT2
64 x 16 bits
______________________________________________________________________________________ 43
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
ADC sample = 495 hex
Since the LUT pointer is a fixed point fractional num-
ber with 7 integer bits and 2 fractional bits, the LUT
pointer value of 1CD hex is interpreted as 73.4 hex
(115.25 decimal).
<< x indicates a logical shift left by x number of bits.
>> x indicates a logical shift right by x number of bits.
1) LUT pointer = ADC sample >> (7 - PSIZE - INT)
= 495 hex >> (7 - 0 - 0)
3) POFF = POFF << 1
= 101000 bin << 1
= 1010000 bin
= 495 hex >> 7
= D0 hex (-48 decimal)
= 9 hex (9 decimal)
4) LUT pointer = LUT pointer + POFF
= 73.4 hex (115.25 decimal) + D0 hex (-48 decimal)
= 43.4 hex (67.25 decimal)
2) POFF = POFF << 0
MAX108
= 001000 bin << 0
= 001000 bin
5) Test LUT pointer is within the table size
Is 0 ≤ LUT pointer ≤ 127?
= 8 hex (8 decimal)
Yes, LUT pointer does not need limiting.
LUT pointer = 43.4 hex (67.25 decimal).
3) LUT pointer = LUT pointer + POFF
= 9 hex + 8 hex
= (100 << 5) + LUT pointer
= 80 hex + 43.4 hex
= C3.4 hex (195.25 decimal)
= 11 hex (17 decimal)
4) Test LUT pointer is within the table size
Is 0 ≤ LUT pointer ≤ 31?
The EEPROM address is a fixed-point fractional num-
ber (C3.4 hex), which falls between table entries at
address C3 hex and C4 hex. Linear interpolation is per-
formed between these two entries.
Yes, LUT pointer does not need limiting to table size.
LUT pointer = 11 hex (17 decimal)
5) EEPROM address = (SOT << 5) + LUT pointer
= (010 << 5) + 11 hex
ADD1 = C3 hex (195 decimal)
ADD2 = C4 hex (196 decimal)
= 40 hex + 11 hex
= 51 hex (81 decimal)
The interpolated data is calculated using ADD1 and
ADD2 and the corresponding data stored at these
address locations using the linear interpolation equation:
6) The LUT data at EEPROM address 51 hex is used
for the V
calculation.
GATE_
LUT Pointer Exampꢄe 2 (With Interpoꢄation)
POFF = 101000 (offset of -24)
EEPROM Address − ADD1
ADD2 − ADD1
⎛
⎞
Interpolated Data = LUT[ADD1] +
x (LUT[ADD2] − LUT[ADD1])
⎜
⎝
⎟
⎠
INT = 10 (linear interpolation required/LUT pointer has
2 fractional bits)
195.25 − 195
196 − 195
⎛
⎞
PSIZE = 10 (7-bit LUT pointer not including any frac-
tional bits)
Interpolated Data = LUT[C3 Hex] +
x (LUT[C4 Hex] − LUT[C3 Hex])
⎜
⎝
⎟
⎠
TSIZE = 100 (LUT has 128 data locations)
SOT = 100 (LUT starts at EEPROM address 80 hex)
ADC sample = E6A hex
Interpolated Data = LUT[C3 Hex] + (0.25) x (LUT[C4 Hex]
− LUT[C3 Hex])
<< x indicates a logical shift left by x number of bits.
>> x indicates a logical shift right by x number of bits.
1) LUT pointer = ADC sample >> (7 - PSIZE - INT)
2) = E6A hex >> (7 - 2 - 2)
where LUT[C3 hex] and LUT[C4] are the data values
stored at EEPROM addresses C3 hex and C4 hex.
Register Address Map
Table 6 lists the addresses for all of the 16-bit registers
that are accessible through the serial interface. To read
from and write to these registers, follow the proper SPI
or I2C read and write sequences described in the
Digital Serial Interface section. Bit C7 in the command
byte controls whether data is written to or read from the
register. This is not the same bit as the I2C read/write
= E6A hex >> 3
= 1CD hex (461 decimal)
= 111001101 bin
= 1110011.01 bin in 7.2 fixed-point format
= 73.4 hex in 7.2 fixed-point format (115.25 decimal)
44 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
that is sent with the slave address (see the Register
(1111 1111 1111) by default. After initial power-up, the
high current threshold can be set to the desired value.
The high current threshold value can be initialized from
the EEPROM.
Address/Data Bytes (5-Byte Read Cycle) section).
Tables 7 to 27 describe each register in detail.
Register Descriptions
High Temperature Threshoꢄd Registers (TH1, TH2)
(Read/Write)
Low Current Threshoꢄd Registers (IL1, IL2)
(Read/Write)
The Low Current Threshold registers set the lower
alarm thresholds for each current-sense amplifier chan-
nel (see Table 10). The current threshold value is
entered into the register in the same format as the ADC
current conversion results, which is a 12-bit unsigned
binary. See the Alarm Function section for more infor-
mation on configuring the alarm thresholds.
The High Temperature Threshold registers set the
upper alarm thresholds for each temperature sensor
channel (see Table 7). The temperature value is
entered into the register in the same format as the ADC
temperature conversion results, which is a 12-bit
signed (two’s complement) fixed-point number with the
3 LSBs being the fractional bits. See the Alarm Function
section for more information on configuring the alarm
thresholds.
When the MAX11008 is powered up for the first time,
the low current threshold is set to the minimum value
(0000 0000 0000) by default. After initial power-up, the
low current threshold can be set to the desired value.
The low current threshold value can be initialized from
the EEPROM.
When the MAX11008 is powered up for the first time,
the high temperature threshold is set to the maximum
value (0111 1111 1111 = +255.875°C) by default. After
initial power-up, the high temperature threshold can be
set to the desired value. The high temperature thresh-
old value can be initialized from the EEPROM.
Hardware Configuration Register (HCFIG)
(Read/Write)
Select FIFO status indication through the ALARM out-
put, ADC monitoring mode, ADC clock modes, PGA
gain settings, DAC reference modes, and ADC refer-
ence modes by setting bits D[11:0] in the Hardware
Configuration register (see Table 11).
Low Temperature Threshoꢄd Registers (TL1, TL2)
(Read/Write)
The Low Temperature Threshold registers set the lower
alarm thresholds for each temperature sensor channel
(see Table 8). The temperature value is entered into the
register in the same format as the ADC temperature
conversion results, which is a 12-bit signed (two’s com-
plement) fixed-point number with the 3 LSBs being the
fractional bits. See the Alarm Function section for more
information on configuring the alarm thresholds.
Set T1AVGCTL to 1 to enable the channel 1 averaging-
equation bit. The T1AVGCTL bit controls the averaging
equation for channel 1 while the device is in tracking
mode. The T1AVGCTL bit only affects the tracking
mode of the averaging. The bit does not affect the
acquirement of the initial average. The initial average
always requires 16 samples to generate a valid aver-
age. Set T1AVGCLT to 0 for the average plus 1/16 dif-
ference. Set T2AVGCLT to 1 for the average plus 1/4
difference. See Table 11a.
When the MAX11008 is powered up for the first time,
the low temperature threshold is set to the minimum
value (1000 0000 0000 = -256.0°C) by default. After ini-
tial power-up, the low temperature threshold can be set
to the desired value. The low temperature threshold
value can be initialized from the EEPROM.
Program T1LIMIT[2:0] to enable and set the difference
limiter for channel 1 temperature averaging. The chan-
nel 1 temperature average must be enabled for the
contents of T1LIMIT[2:0] to have any effect on the mea-
sured data (see the Alarm Software Configuration
Register (ALMSCFIG) (Read/Write) section). The
T1LIMIT[2:0] field only affects the tracking mode of the
average function. When tracking the average, the dif-
ference between the current average and the new sam-
ple is calculated. The difference is then added into the
average according to the T1AVGCTL bit. However,
before being added, the difference is limited according
to the T1LIMIT[2:0] field. See Table 11b.
High Current Threshoꢄd Registers (IH1, IH2)
(Read/Write)
The High Current Threshold registers set the upper
alarm thresholds for each current-sense amplifier chan-
nel (see Table 9). The current threshold value is
entered into the register in the same format as the ADC
current conversion results, which is a 12-bit unsigned
binary. See the Alarm Function section for more infor-
mation on configuring the alarm thresholds.
When the MAX11008 is powered up for the first time,
the high current threshold is set to the maximum value
______________________________________________________________________________________ 45
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 6ꢀ Register Address Map
COMMAND BITS
SEE
HEX CODE
REGISTER
MNEMONIC
TABLE
C. C6 C5 C4 C3 C2 C1 C0 WRITE READ
Channel 1 High Temperature Threshold
Channel 2 High Temperature Threshold
Channel 1 Low Temperature Threshold
Channel 2 Low Temperature Threshold
Channel 1 High Current Threshold
Channel 1 Low Current Threshold
Channel 2 High Temperature Threshold
Channel 2 Low Temperature Threshold
Hardware Configuration
TH1
TH2
7
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
20
28
22
2A
24
26
2C
2E
30
32
34
36
38
3C
3A
3E
58
5C
5A
5E
60
62
64
66
6E
72
74
7E
—
A0
A8
A2
AA
A4
A6
AC
AE
B0
B2
B4
B6
B8
BC
BA
BE
—
7
TL1
8
TL2
8
MAX108
IH1
9
IL1
9
IH2
10
10
11
12
13
14
15
15
16
16
17
17
18
18
19
20
21
22
23
24
25
27
26
IL2
HCFIG
ALMSCFIG
SCFIG
ALMHCFIG
VSET1
VSET2
HIST_APC1
HIST_APC2
IDAC1
IDAC2
IODAC1
IODAC2
PGACAL
ADCCON
SSHUT
LDAC
—
Alarm Software Configuration
Software Configuration
Alarm Hardware Configuration
VSET1
VSET2
APC1 Parameter
APC2 Parameter
DAC1 Input (Write Only)
DAC2 Input (Write Only)
0
—
DAC1 Input and Output (Write Only)
DAC2 Input and Output (Write Only)
PGA Calibration Control ( Write Only)
ADC Conversion (Write Only)
Software Shutdown (Write Only)
Load DAC (Write Only)
0
—
0
—
0
—
0
—
0
—
0
—
Message (Write Only)
0
—
FIFO
—
RW
0
80
—
Software Clear (Write Only)
LUT Streaming (Write Only)
Flag (Read Only)
SCLR
—
0
—
—
1
F6
The following properties of the register address map should be noted:
• All register data is volatile.
• Data stored in locations TH1, TH2, TL1, TL2, IH1, IH2, IL1, IL2, HCFIG, ALMSCFIG, SCFIG, ALMHCFIG, VSET1,
VSET2, IDAC1, IDAC2, IODAC1, IODAC2, PGACAL, ADCCON, SSHUT, and LDAC can be loaded from EEPROM
at power-up or after a full reset.
• Write to the FIFO register only in LUT streaming mode (see the LUT Streaming Mode section).
46 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Set FIFOSTAT to 1 to use the ALARM output to monitor
Program ADCREF[1:0] to establish the source of the
ADC reference (see Table 11e). Program the
DACREF[1:0] to establish the source of the DAC refer-
ence (see Table 11f). See the ADC and DAC
References section for more information on configuring
the data converter references.
the data flow of the FIFO while in LUT streaming mode
or message mode. See the LUT Streaming Mode and
Message Mode sections for more information on these
modes of operation and how to use the ALARM output
for FIFO flow control.
Set ADCMON to 1 to copy ADC conversion results into
the FIFO where it can be read out through the serial
interface. See the ADC Monitoring Mode section for
more information on reading conversion results from
the FIFO. ADCMON and AVGMON cannot be active at
the same time.
Aꢄarm Software Configuration Register (ALMSCFIG)
(Read/Write)
Configure the software alarm functions with bits D[11:0]
in the Alarm Software Configuration register (see Table
12). Bits D[15:12] are don’t-care bits.
Set A_AVG to 1 to enable the APC averaging and filter-
ing function for channel 1 and channel 2. The
APCSRC_ field in the SCFG register controls the source
of the sample.
Program PG_SET[1:0] to set the channel 1 and channel
2 current-sense amplifier gain (see Table 11c).
Program CKSEL[1:0] to set the conversion and acquisi-
tion timing clock modes (see Table 11d). See the
Internally Timed Acquisitions and Conversions section
for detailed descriptions of each clock mode.
Tabꢄe .ꢀ High Temperature Threshoꢄd Register
DATA BITS
D[15:12]
BIT NAME
Unused
RESET STATE
FUNCTION
X
Unused bits.
D[11:D0]
THI[11:0]
0111 1111 1111 High temperature threshold data bits.
X = Don’t care.
Tabꢄe 8ꢀ Low Temperature Threshoꢄd Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
X
Unused bits.
TLO[11:0]
1000 0000 0000 Low temperature threshold data bits.
X = Don’t care.
Tabꢄe 9ꢀ High Current Threshoꢄd Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
X
Unused bits.
IHI[11:0]
1111 1111 1111 High current threshold data bits.
X = Don’t care.
Tabꢄe 10ꢀ Low Current Threshoꢄd Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
X
Unused bits.
ILO[11:0]
0000 0000 0000 Low current threshold data bits.
X = Don’t care.
______________________________________________________________________________________ 4.
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 11ꢀ Hardware Configuration Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
Channel 1 averaging-equation bit. This bit controls the averaging equation
for channel 1 while the device is in tracking mode. See Table 11a.
D15*
T1AVGCTL
0
Channel 1 difference-limiter bits. Set T1LIMIT[2:0] to enable the difference
limiter for channel 1 temperature averaging. See Table 11b.
D[14:12]*
D11
T1LIMIT[2:0]
FIFOSTAT
000
0
If the FIFOSTAT bit is set to 1, the ALARM output is used to monitor data
flow into/out of the FIFO and EEPROM while in the message and LUT
streaming modes.
MAX108
ADC monitor enable bit. If ADCMON is set to 1, the result from the ADC
conversion is copied into the FIFO, from where it can be read over the
serial interface. If ADCMON = 0, the result is not copied into the FIFO.
ADCMON and AVGMON cannot be active at the same time.
D10
ADCMON
0
D[9:8]
D[7:6]
D[5:4]
D[3:2]
D[1:0]
PG2SET[1:0]
PG1SET[1:0]
CKSEL[1:0]
00
00
00
00
00
PGA2 gain-setting bits. See Table 11c.
PGA1 gain-setting bits. See Table 11c.
Clock mode and CNVST bits. See Table 11d.
ADC reference select bits. See Table 11e.
DAC reference select bits. See Table 11f.
ADCREF[1:0]
DACREF[1:0]
X = Don’t care.
*Write only.
Tabꢄe 11aꢀ Channeꢄ 1 Averaging Equation
(T1AꢃGCTL)
D15
0
CHANNEL 1 AꢃERAGING EQUATION
Average = average + 1/16 difference.
Average = average + 1/4 difference.
1
Tabꢄe 11bꢀ Channeꢄ 1 Difference-Limiter Bits (T1LIMIT[2:0])
D14
0
D13
0
D12
0
CHANNEL 2 DIFFERENCE-LIMITER BITS (T2LIMIT[2:0])
No limiting is applied.
0
0
1
Difference is limited to 1 LSB (1/8 of a degree).
Difference is limited to 3 LSBs (3/8 of a degree).
Difference is limited to 7 LSBs (7/8 of a degree).
Difference is limited to 15 LSBs (1 7/8 degrees).
Difference is limited to 31 LSBs (3 7/8 degrees).
Difference is limited to 63 LSBs (7 7/8 degrees).
Difference is limited to 127 LSBs (15 7/8 degrees).
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
48 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 11cꢀ PGA1 and PGA2 Gain Setting
Bits (PG_SET[1:0])
PG_SET1
PG_SET0
PGA GAIN
0
0
1
0
1
X
2
10
25
X = Don’t care.
Tabꢄe 11dꢀ Cꢄock Mode and CNVST Bit (CKSEL[1:0])
CKSEL1
CKSEL0
ADC CONꢃERSION TYPE
Internally timed acquisitions and conversions start by writing to the ADC Conversion register
and enabling one or more channels. See the ADC Conversion Register (ADCCON) (Write
Only) section. All of the selected channels are sequentially converted each time the ADC
Conversion register is written to.
0
0
Internally timed acquisitions and conversions start by asserting a low pulse at CNVST
whenever one or more channels are enabled in the ADC Conversion register. All of the
selected channels are sequentially converted each time a low pulse is asserted at CNVST.
Reserved. Do not use.
Selected channels are converted individually each time CNVST is pulled low. Each low pulse
on CNVST converts the next channel in the sequence.
0
1
1
1
0
1
X = Don’t care.
Tabꢄe 11eꢀ ADC Reference Configuration Bits (ADCREF[1:0])
ADCREF1
ADCREF0
ADC REFERENCE
ADC uses external reference voltage supplied at the ADCREF input.
ADC uses internal reference voltage.
0
1
X
0
ADC uses internal reference voltage. Connect external decoupling capacitor at REFADC for
better noise performance.
1
1
X = Don’t care.
Tabꢄe 11fꢀ DAC Reference Configuration Bits (DACREF[1:0])
DACREF1
DACREF0
DAC REFERENCE
DAC uses external reference voltage supplied at the DACREF input.
DAC uses internal reference voltage.
0
1
X
0
DAC uses internal reference voltage. Connect external decoupling capacitor at REFDAC for
better noise performance.
1
1
X = Don’t care.
______________________________________________________________________________________ 49
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Set T_AVG to 1 to enable the temperature averaging
and filtering function for channel 1 and channel 2. The
TSRC_ field in the SCFG register controls the source of
the sample.
acquirement of the initial average. The initial average
always requires 16 samples to generate a valid aver-
age. Set T2AVGCLT to 0 for average plus 1/16 of the
difference. Set T2AVGCLT to 1 for average plus 1/4 of
the difference. See Table 13a.
Set TALARM_ to 1 to enable and to 0 to disable the
alarm function for channel 1 and channel 2 temperature
measurements.
Program T2LIMIT[2:0] to enable and set the difference
limiter for channel 2 temperature averaging. The chan-
nel 2 temperature average must be enabled for the
contents of the T2LIMIT[2:0] field to have any effect on
the measured data (see the Alarm Software
Configuration Register (ALMSCFIG) (Read/Write) sec-
tion). The T2LIMIT[2:0] field only affects the tracking
mode of the average function. When tracking the aver-
age, the difference between the current average and
the new sample is calculated. The difference is then
added into the average according to the T2AVGCTL
bit, but before being added the difference is limited
according to the T2LIMIT[2:0] field. See Table 13b.
Set TWIN_ to 0 to configure the channel 1 and channel 2
temperature alarms for hysteresis mode, and set TWIN_
to 1 to configure the channel 1 and channel 2 tempera-
ture alarms for window mode. See the Hysteresis Mode
and Window Mode sections for detailed descriptions of
each alarm mode. Use the Alarm Hardware
Configuration register to set the value of hysteresis when
in window mode (see Tables 14 and 14a).
MAX108
Set IALARM_ to 1 to enable and to 0 to disable the
alarm function for channel 1 and channel 2 current
measurements.
Set LDAC_ to 0 to load the V
calculation result
GATE_
Set IWIN_ to 0 to configure the channel 1 and channel
2 current-sense alarm for hysteresis mode, and set
IWIN_ to 1 to configure the channel 1 and channel 2
current-sense alarm for window mode. See the
Hysteresis Mode and Window Mode sections for
detailed descriptions of each alarm mode. Use the Alarm
Hardware Configuration register to set the value of hys-
teresis when in window mode (see Tables 14 and 14a).
into the channel 1 and channel 2 DAC input and output
registers, forcing the V output to change as soon
GATE_
as the V
calculation is completed. Set LDAC_ to 1
GATE_
to load the calculation result into the channel 1 and
channel 2 DAC input registers. Transfer the results from
the input register to the output register by writing to the
Load DAC register (see the Load DAC Register (LDAC)
(Write Only) section).
Set TCOMP_ to 1 to allow V
triggered by changes in channel 1 and channel 2 tem-
perature measurements. In this mode, the V cal-
culation includes a temperature LUT value. The
temperature measurement values that trigger V
GATE_
calculations depend on the settings of T_HIST[3:0] in
the APC Parameter register.
calculations to be
Software Configuration Register (SCFIG)
(Read/Write)
GATE_
Bits D[15:0] in the Software Configuration register (see
GATE_
Table 13) control the parameters that trigger V
GATE_
calculation
calculations, how the results of the V
GATE_
are applied (APC and/or temperature compensation),
and whether the calculation result is written to the DAC
input register only or to both input and output registers.
The register also determines the source of the APC and
temperature parameters, which are used to calculate
the LUT pointer for retrieving LUT values (see the
Temperature/APC LUT Configuration Registers sec-
tion). The data stored in the Software Configuration reg-
ister can be initialized from the EEPROM. Table 13d
Set APCCOMP_ to 1 to allow V
triggered by changes in channel 1 and channel 2 cur-
rent-sense measurements or the APC parameter in the
APC Parameter register. In this mode, the V
culation includes an APC LUT value. The current mea-
surement values that trigger V calculations
depend on the settings of A_HIST[3:0] in the APC
Parameter register.
calculations to be
GATE_
cal-
GATE_
GATE_
summarizes all of the possible V
calculation trig-
GATE_
ger conditions that can be set by the Software
Configuration register.
Set TSRC_ to 0 to use the channel 1 and channel 2
external temperature sensor as the source of the temper-
Set T2AVGCTL to 1 to enable the channel 2 averaging-
equation bit. The T2AVGCTL bit controls the averaging
equation for channel 2 while the device is in tracking
mode. The T2AVGCTL bit only affects the tracking
mode of the averaging. The bit does not affect the
ature parameter for V
calculations. Set TSRC_ to 1
GATE_
to use the internal temperature sensor as the source of
the temperature parameter for V calculations.
GATE_
Set APCSRC[1:0] to select the source of the APC para-
meter used for V calculations (see Table 13c).
GATE_
50 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Aꢄarm Hardware Configuration Register
T_HIST_APC Registers (HIST_APC1, HIST_APC2)
(Read/Write)
(ALMHCFIG) (Read/Write)
Configure the hardware alarm functions with bits
D[10:0] in the Alarm Hardware Configuration register
(see Table 14). Bits D[15:11] are don’t-care bits.
The T_HIST_APC registers are dual-functionality regis-
ters. The function of the T_HIST_APC registers
depends upon the value of APCSRC_[1:0] bits in the
Software Configuration register (see Table 13). If
APCSRC_[1:0] = 00, the T_HIST_APC registers hold the
APC parameter and the temperature hysteresis controls
(see Table 16a). If APCSRC_[1:0] = 10 or 11, the
T_HIST_APC registers hold the APC averaging and
hysteresis controls as well as temperature hysteresis
controls (see Table 16b).
Set AVGMON to 1 to write ADC averages to the FIFO.
The tracking average has a unique channel tag and is
distinguishable from the raw sample. The average mon-
itoring is automatically suspended when in LUT stream-
ing and message modes. ADCMON and AVGMON
cannot be active at the same time.
Set INTEMP2 to 1 to configure the channel 2 tempera-
ture alarm to monitor the internal temperature sensor
readings rather than the channel 2 external tempera-
ture sensor. The status of the alarm is indicated by the
channel 2 temperature flags in the flag register. The
current-sense alarm for channel 2 is no longer available
in this mode.
The T_HIST register bits T_HIST[3:0] set the temperature
hysteresis limits for both channel 1 and channel 2 V
GATE_
calculations. After a new temperature sample, the device
proceeds in performing a V calculation if that sam-
GATE_
ple differs from the previous sample used for a V
GATE_
calculation by an amount greater than the hysteresis set-
ting (see Table 16c). Set APCCOMP_ and TCOMP_ to 0
before T_HIST is changed.
Set ALMCOMP to 1 to configure the ALARM output for
comparator mode, and set ALMCOMP to 0 to configure
the ALARM output for interrupt mode. See the ALARM-
Output Modes section for a detailed description of
each type of ALARM output mode.
The APC register bits (APC[11:0]) set the value that is
converted into the LUT pointer value, which is subse-
quently used to retrieve the APC LUT value for V
GATE_
calculations (see Table 16a). This value is used only
when APCSRC_1 is set to 0 in the Software
Configuration register. Writing to this register triggers a
Program ALMHYST[1:0] to set the amount of hysteresis
that is applied to the alarm thresholds when the alarm
function is configured for window mode (see Table
14a). See the Window Mode section for a detailed
description of how the hysteresis is applied.
V
calculation when APCSRC_1 is set to 0 and
GATE_
APCCOMP_ is set to 1 in the Software Configuration
register.
Set ALMCLMP[1:0] to control the methods to clamp the
GATE_ to AGND when an alarm is triggered (see Table
14b).
The A_AVGCTL bit controls the averaging equation
for APC while the device is in tracking mode. The
A_AVGCTL bit only affects the tracking mode of the
averaging. The bit does not affect the acquirement
of the initial average. The initial average always
requires 16 samples to generate a valid average. Set
A_AVGCLT to 0 for average plus 1/16 of the difference.
Set A_AVGCTL to 1 for average plus 1/4 of the differ-
ence (see Table 16c).
Set ALMPOL to 1 to configure the ALARM output to be
active-low, and set ALMPOL to 0 to configure the
ALARM output to be active-high.
Set ALMOPEN to 1 to configure the ALARM output for
an open-drain output (pullup resistor required), and set
ALMOPEN to 0 for a push-pull output.
Program A_LIMIT[2:0] to enable and set the difference
limiter for APC averaging. The APC average must be
enabled for the contents of the A_LIMIT[2:0] field to
have any effect on the measured data. The
A_LIMIT[2:0] field only affects the tracking mode of the
average function. When tracking the average, the dif-
ference between the current average and the new sam-
ple is calculated. The difference is then added into the
average according to the A_AVGCTL bit, but before
being added the difference is limited according to the
A_LIMIT[2:0] field (see Table 16d).
ꢃSET Registers (ꢃSET1, ꢃSET2) (Read/Write)
The VSET registers set the nominal GATE_ output code
without any temperature or APC compensation (see
Table 15). This value is input into the V
calcula-
GATE_
tion (see the V
_ Output Equation section). Writing
GATE
to this register triggers a V
calculation, and the
GATE_
result of that calculation is loaded into either the DAC_
input register or the DAC_ input and output registers
depending on the state of the LDAC_ bit in the Software
Configuration register. Bits D[15:12] are don’t-care bits.
______________________________________________________________________________________ 51
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 12ꢀ Aꢄarm Software Configuration Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:12]
Unused
X
Unused bits.
Channel 2 APC averaging and filtering bit.
Set to 1 to enable the APC averaging and filtering function for channel 2.
The source of the sample is controlled by the APCSRC2 field in the Software
Configuration register.
D11*
D10*
D9*
A2AVG
T2AVG
A1AVG
T1AVG
0
0
0
0
MAX108
Channel 2 temperature averaging and filtering bit.
Set to 1 to enable the temperature averaging and filtering function for
channel 2. The source of the sample is controlled by the TSRC2 field in the
Software Configuration register.
Channel 1 APC averaging and filtering bit.
Set to 1 to enable the APC averaging and filtering function for channel 1.
The source of the sample is controlled by the APCSRC1 field in the Software
Configuration register.
Channel 1 temperature averaging and filtering bit.
Set to 1 to enable the temperature averaging and filtering function for
channel 1. The source of the sample is controlled by the TSRC1 field in the
Software Configuration register.
D8*
Channel 2 temperature alarm enable bit. Set TALARM2 to 1 to enable the
channel 2 temperature alarm.
D7
D6
TALARM2
TWIN2
0
0
Channel 2 temperature alarm window bit. Set to 0 for hysteresis mode, and
set to 1 for window mode. See the Hysteresis Mode and Window Mode
sections.
Channel 2 current alarm enable bit. Set IALARM2 to 1 to enable the channel
2 current alarm.
D5
D4
D3
IALARM2
IWIN2
0
0
0
Channel 2 current alarm window bit. Set to 0 for hysteresis mode, and set to
1 for window mode. See the Hysteresis Mode and Window Mode sections.
Channel 1 temperature alarm enable bit. Set TALARM1 to 1 to enable the
channel 1 temperature alarm.
TALARM1
Channel 1 temperature alarm window bit. Set to 0 for hysteresis mode, and
set to 1 for window mode. See the Hysteresis Mode and Window Mode
sections.
D2
TWIN1
0
Channel 1 current alarm enable bit. Set IALARM1 to 1 to enable the channel
1 current alarm.
D1
D0
IALARM1
IWIN1
0
0
Channel 1 current alarm window bit. Set to 0 for hysteresis mode, and set to
1 for window mode. See the Hysteresis Mode and Window Mode sections.
X = Don’t care.
*Write only.
52 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 13ꢀ Software Configuration Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
Channel 2 averaging-equation bit. This bit controls the averaging equation
for channel 2 while the device is in tracking mode. See Table 13a.
D15*
T2AVGCTL
0
Channel 2 difference-limiter bits. Set T2LIMIT[2:0] to enable the difference
limiter for channel 2 temperature averaging. See Table 13b.
D[14:12]*
D11
T2LIMIT[2:0]
LDAC2
000
0
Channel 2 LDAC control bit. Set to 0 to load calculation results into the DAC
2 input and output registers. Set to 1 to load calculation results into the
DAC 2 input register only.
Channel 2 temperature compensation enable bit. Set to 1 to allow V
calculations to be triggered by channel 2 temperature measurements.
GATE2
D10
TCOMP2
0
Channel 2 APC parameter compensation enable bit. Set to 1 to allow
D9
APCCOMP2
0
V
calculations to be triggered by channel 2 current-sense
GATE2
measurements or APC2 parameter changes.
Channel 2 temperature sensor select bit. Set to 0 to use the channel 2
external temperature sensor as the source of the temperature parameter for
D8
D[7:6]
D5
TSRC2
APCSRC2[1:0]
LDAC1
0
00
0
V
calculations. Set to 1 to use the internal temperature sensor.
GATE2
Channel 2 APC parameter select bits. Set APCSRC2[1:0] to select the data
source for V calculations. See Table 13c.
GATE2
Channel 1 LDAC control bit. Set to 0 to load calculation results into the DAC
1 input and output registers. Set to 1 to load calculation results into the
DAC 1 input register only.
Channel 1 temperature compensation enable bit. Set to 1 to allow V
calculations to be triggered by channel 1 temperature measurements.
GATE1
D4
TCOMP1
0
Channel 1 APC parameter compensation enable bit. Set to 1 to allow
D3
APCCOMP1
0
V
calculations to be triggered by channel 1 current-sense
GATE1
measurements or APC1 parameter changes.
Channel 1 temperature sensor select bit. Set to 0 to use the channel 1
external temperature sensor as the source of the temperature parameter for
D2
TSRC1
0
V
calculations. Set to 1 to use the internal temperature sensor.
GATE1
Channel 1 APC parameter select bits. Set APCSRC1[1:0] to select the data
source for V calculations. See Table 13c.
D[1:0]
APCSRC1[1:0]
00
GATE1
X = Don’t care.
*Write only.
______________________________________________________________________________________ 53
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 13aꢀ Channeꢄ 2 Averaging Equation
(T2AꢃGCTL)
D15
0
CHANNEL 2 AꢃERAGING EQUATION
Average = average + 1/16 difference.
Average = average + 1/4 difference.
1
Tabꢄe 13bꢀ Channeꢄ 2 Difference Limiter Bits (T2LIMIT[2:0])
MAX108
D14
0
D13
0
D12
0
CHANNEL 2 DIFFERENCE LIMITER
No limiting is applied.
0
0
1
Difference is limited to 1 LSB (1/8 of a degree).
Difference is limited to 3 LSBs (3/8 of a degree).
Difference is limited to 7 LSBs (7/8 of a degree).
Difference is limited to 15 LSBs (1 7/8 degrees).
Difference is limited to 31 LSBs (3 7/8 degrees).
Difference is limited to 63 LSBs (7 7/8 degrees).
Difference is limited to 127 LSBs (15 7/8 degrees).
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Tabꢄe 13cꢀ APC Parameter Source Seꢄect Bits (APCSRC_1, APCSRC_0)
APCSRC_1
APCSRC_0
APC PARAMETER SOURCE SELECT
Value stored in APC parameter register.
0
0
1
1
0
1
0
1
Reserved. Do not use.
Drain current samples.
External input samples (AIN input).
The A_HIST register bits A_HIST[3:0] set the APC hys-
teresis limits for both channel 1 and channel 2 V
this register does not trigger a V
calculation, but
GATE_
the GATE_ output is immediately updated with the
value that is written to this register. Bits D[15:12] are
don’t-care bits. The contents of the DAC Input and
Output registers are not stored in the EEPROM.
GATE_
calculations. After a new APC sample, the device pro-
ceeds in performing a V calculation if that sample
GATE_
differs from the previous sample used for a V
cal-
GATE_
culation by an amount greater than the hysteresis set-
ting (see Table 16e). Set APCCOMP_ and TCOMP_ to 0
before A_HIST is changed.
PGA Caꢄibration Controꢄ Register (PGACAL)
(Write Onꢄꢂ)
The PGA Calibration Control register selects the PGA
calibration mode and controls when calibrations occur
(see Table 19). Bits D[15:3] are don’t-care bits. The
data contained in the PGA Calibration Control register
is stored in the EEPROM.
DAC Input Registers (IDAC1, IDAC2) (Write Onꢄꢂ)
DAC_[11:0] set the value of the DAC Input registers
(see Table 17). Bits D[15:12] are don’t-care bits. The
GATE_ output is not updated with this value until it is
transferred to the DAC Output register. Write to the
Load DAC register to transfer the contents of the DAC
Input register to the DAC Output register. Write directly
to the DAC Input register to manipulate the DAC output
Set TRACK to 0 to perform the next PGA calibration in
acquisition mode, and set TRACK to 1 to perform the
next PGA calibration in tracking mode. Leave TRACK
set to 0 the first time a PGA calibration is performed
after power-up.
without triggering a V
calculation.
GATE_
DAC Input and Output Registers (IODAC1, IODAC2)
(Write Onꢄꢂ)
DAC_[11:0] set the values of the input and output regis-
ters of the respective DACs (see Table 18). Writing to
Set DOCAL to 1 to perform calibrations of PGA1 and
PGA2. DOCAL resets to 0 after the PGA calibration rou-
tine is complete. If either channel is powered down, the
PGA calibration for that channel is bypassed.
54 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 13dꢀ ꢃ _ Caꢄcuꢄation Trigger Condition
GATE
SOFTWARE CONFIGURATION
SETTINGS
ꢃ
CALCULATION TRIGGER CONDITIONS
GATE_
TCOMP_ = 1
APCCOMP_ = 1
APCSRC_1 = 0
APCSRC_0 = 0
•
•
•
Temperature measurements vary enough to exceed the hysteresis settings
A write command to the APC_ Parameter register
A write command to the VSET register through the serial interface
•
•
Temperature measurements vary enough to exceed the hysteresis settings
Current-sense measurements or ADCIN_ samples vary enough to cause a new LUT
value to be retrieved (depends on PSIZE and INT values in the LUT Configuration
registers)
TCOMP_ = 1
APCCOMP_ = 1
APCSRC_1 = 1
APCSRC_0 = X
•
A write command to the VSET register through the serial interface
TCOMP_ = 1
APCCOMP_ = 0
APCSRC_1 = X
APCSRC_0 = X
•
•
Temperature measurements vary enough to exceed the hysteresis settings
A write command to the VSET register through the serial interface
TCOMP = 0
APCCOMP = 1
APCSRC_1 = 0
APCSRC_0 = 0
•
•
A write command to the APC_ register through the serial interface
A write command to the VSET register through the serial interface
TCOMP = 0
APCCOMP = 1
APCSRC_1 = 1
APCSRC_0 = X
•
•
Current-sense measurements vary enough to exceed the hysteresis settings
A write command to the VSET register through the serial interface
TCOMP = 0
APCCOMP = 0
APCSRC_1 = X
APCSRC_0 = X
•
A write command to the VSET register through the serial interface
X = Don’t care.
Set SELFTIME to 1 and DOCAL to 1 to perform calibra-
tions of PGA1 and PGA2 on a self-timed periodic basis
(approximately every 13ms). When SELFTIME is set to
0, writing to PGACAL with DOCAL set to 1 manually
triggers PGA calibration.
Bits D[6:0] select which channels are converted. Select
which channel is to be converted by setting the corre-
sponding bit to 1. Any channel that is set to 0 will not
be converted. Depending on the ADC clock mode that
is selected in the Hardware Configuration register (see
the Internally Timed Acquisitions and Conversions sec-
tion and Table 11), writing to the ADC Conversion reg-
ister initiates an ADC conversion of the selected
channel or the next selected channel in the sequence if
more than one channel is selected (see the ADC
Conversion Scheduling section). Bits D[15:8] are don’t-
care bits.
ADC Conversion Register (ADCCON) (Write Onꢄꢂ)
Write to the ADC Conversion register to select which
channels are converted and to set the ADC for continu-
ous conversion of each selected channel (see Table
20). Set CONCONV to 1 to configure the ADC to per-
form continuous conversions of the selected channels.
______________________________________________________________________________________ 55
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 14ꢀ Aꢄarm Hardware Configuration Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:11]
Unused
XXXXX
Unused bits.
ADC average monitor enable bit. Set AVGMON to 1 to average the ADC
sample. The ADC average is written to the FIFO. The tracking average has a
unique channel tag and is distinguishable from the raw sample. The average
monitoring is automatically suspended when in LUT streaming and message
modes. ADCMON and AVGMON cannot be active at the same time.
D10*
AVGMON
0
MAX108
Channel 2 temperature alarm select bit. Set to 1 to configure the channel 2
temperature alarm to monitor the internal temperature sensor instead of the
external temperature sensor. The status of the alarm is indicated by the
channel 2 temperature flags in the flag register. The current-sense alarm for
channel 2 is no longer available in this mode.
D9
D8
INTEMP2
0
0
ALARM comparator enable bit. Set to 1 to configure the ALARM output for
comparator mode. Set to 0 to configure the ALARM output for interrupt
mode.
ALMCOMP
D[7:6]
D[5:4]
D[3:2]
ALMHYST[1:0]
ALMCLMP2[1:0
ALMCLMP1[1:0
00
00
00
ALARM hysteresis select bits. See Table 14a.
Channel 2 clamp-mode select bits. See Table 14b.
Channel 1 clamp-mode select bits. See Table 14b.
ALARM polarity select bit. Set to 1 to configure the ALARM output to be
active-low. Set to 0 for active-high.
D1
D0
ALMPOL
0
0
ALARM output configuration select bit. Set to 1 for open-drain ALARM
output. Set to 0 for push-pull ALARM output.
ALMOPEN
X = Don’t care.
*Write-only.
Tabꢄe 14aꢀ ALARM Hꢂsteresis Seꢄect Bits (ALMHYST[1:0])
ALMHYST1
ALMHYST0
ALARM HYSTERESIS SELECT
0
0
1
1
0
1
0
1
8 LSBs of hysteresis (+1°C)
16 LSBs of hysteresis (+2°C)
32 LSBs of hysteresis (+4°C)
64 LSBs of hysteresis (+8°C)
Software Shutdown Register (SSHUT) (Write Onꢄꢂ)
Write to the Software Shutdown register to power down
the MAX11008 or specific sections of the MAX11008 to
optimize power consumption (see Table 21). Bits
D[15:6] are don’t-care bits.
Set FBGON to 1 to force the internal voltage reference
to remain powered up. This optimizes ADC conversion
times since the internal voltage reference does not
automatically power down in between conversions
(power-up time for internal reference is typically 50µs),
but it also increases the power dissipation of the
MAX11008. Set FBGON to 0 to power the internal volt-
age reference on and off as required by the ADC.
Set FULLPD to 1 to power down all sections of the
MAX11008 except for the serial interface. FULLPD
takes precedence over all of the other power-down
bits. Any commands (other than writing to the Software
Shutdown register) sent to the MAX11008 while in full
power-down mode are ignored. Set FULLPD to 0 to exit
full power-down mode.
Set WDGPD to 1 to power down the internal watchdog
oscillator. The watchdog oscillator monitors the internal
circuit’s operation. It is not accessible outside of the
MAX11008. Power down the internal watchdog ocillator
when entering LUS streaming mode.
56 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Table 14b. Clamp-Mode Select Bits (ALMCLMP[1:0])
ALMCLMP1
ALMCLMP0
CLAMP MODE
Alarm report
Clamp gate
ALARM CLAMP SELECT
If an alarm is triggered by a current or temperature conversion, the ALARM
bit is set (1) in the alarm Flag register. No further action is taken.
0
0
0
1
The GATE_ output clamps to AGND immediately, independent of alarms.
The GATE_ output is clamped to AGND in response to any alarm trip on the
Clamp gate on corresponding channel. A subsequent ADC conversion, which shows the
1
1
0
1
alarm with clear
alarm condition has been removed, clears the clamp condition
automatically.
The GATE_ output is clamped to AGND in response to any alarm trip on the
corresponding channel. The clamp does not clear automatically. If an alarm
is triggered, the 11 value is overwritten to 01, causing a permanent clamp
condition. A subsequent write to rest ALMCLMP[1:0] to 11 clears the clamp
condition.
Clamp gate on
alarm without
clear
Table 15. VSET Registers
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
0000
NA
Unused bits.
VSET_ bits.
VSET_[11:0]
NA = Not applicable.
Set OSCPD to 1 to power down the internal oscillator.
When the internal oscillator is powered down, all inter-
nal operations of the MAX11008 are suspended.
OSCPD automatically resets back to 0 when the next
command is received by the serial interface.
transfer the contents of the DAC1 Input register to the
DAC1 Output register. Set LDDACCH2 to 1 to transfer
the contents of the DAC2 Input register to the DAC2
Output register. Bits D[15:2] are don’t-care bits.
Message Register (MR) (Write Only)
Write to the Message register to place the MAX11008
into message mode (see the Message Mode section
and Table 23). MSGL[7:0] specifies the number of data
words (each data word is 16 bits long) to be read from
the EEPROM. The message read from the EEPROM is
between 1 and 256 words long. Write MSGL = 0 (deci-
mal) to request a message length of 1, MSGL = 255
(decimal) to request a message length of 256.
MSGA[7:0] specifies the starting address of the mes-
sage to be read from the EEPROM.
Powering down the oscillator and leaving the watchdog
oscillator powered up may allow the watchdog timer to
overflow. The overflow of the watchdog timer forces the
MAX11008 to reset, reinitialize, and transmit a pulse on
the ALARM output.
Set DAC_PD to 1 to power down DAC_ and PGA_.
Values can still be written to the DAC Input and Output
registers when DAC_ is powered down.
Load DAC Register (LDAC) (Write Only)
Write to the Load DAC register to transfer the contents
of the DAC input registers to the DAC output registers
(see Table 22). The Load DAC register is a write-only
register that executes when written to, but does not
have storage. This function facilitates the simultaneous
update of both DAC outputs. Set LDDACCH1 to 1 to
FIFO Register (FIFO) (Read/Write)
When in message mode or ADC monitoring mode, the
FIFO register is a read-only register (see Table 24). In
message mode, the specified EEPROM data words
(each data word is 16 bits long) are copied into the
______________________________________________________________________________________ 57
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
FIFO (see the Message Mode section) so that the data
words can be read out through the serial interface. In
message mode the FIFO is eight deep, and does not
overflow.
FIFO is seven deep, and always contains the most
recent seven data items. The oldest data placed into
the FIFO is always read out first.
When in LUT streaming mode, the FIFO register is a
write-only register. In LUT streaming mode, write the
data word that is to be written to the EEPROM into the
FIFO register (see the LUT Streaming Mode section). In
this mode the FIFO is eight deep, and is prevented
from overflow. Data written to the FIFO when it is full is
ignored.
In ADC/average monitoring mode, the 12-bit ADC con-
version results of each selected channel are copied
into the FIFO so that the conversion results can be read
out through the serial interface (see the ADC Monitoring
Mode section). Each conversion result includes a 4-bit
channel tag that indicates the source of the conversion
(see Table 24a). In ADC/average monitoring mode the
MAX108
Tabꢄe 16aꢀ APC Parameter Register (ꢃaꢄid when APCSRC[1:0] = 00)
DATA
BITS
BIT NAME
RESET STATE
FUNCTION
Hysteresis limit bits. The T_HIST[3:0] bits set the temperature hysteresis limits for
D[15:12]
D[11:0]
T_HIST[3:0]
APC[11:0]
0000
NA
both channel 1 and channel 2 for V
calculations. See Table 14a.
GATE_
APC parameter bits.
NA = Not applicable.
Tabꢄe 16bꢀ APC Parameter Register (ꢃaꢄid when APCSRC[1:0] = 10 or 11)
DATA BITS
D[15:12]
D[11:8]
D7
BIT NAME
T_HIST[3:0]
Unused
RESET STATE
FUNCTION
Temperature hysteresis limit bits. The T_HIST[3:0] bits set the temperature
hysteresis limits for both channel 1 and channel 2 for V
Table 16c. Set APCCOMP_ and TCOMP_ to 0 before T_HIST is changed.
0
NA
0
calculations. See
GATE_
—
APC parameter bit. Controls the averaging equation for channel 1 and
channel 2. Set A_AVGCLT to 0 for average plus 1/16 difference. Set
A_AVGCLT to 1 for average plus 1/4 difference.
A_AVGCTL
APC difference limiter bits. Set A_LIMIT[2:0] to enable the difference limiter for
channel 1 and channel 2 APC averaging. See Table 16d.
D[6:4]
D[3:0]
A_LIMIT[2:0]
A_HIST[3:0]
0
0
APC hysteresis limit bits. The A_HIST[3:0] bits set the APC hysteresis limits for
both channel 1 and channel 2 for V
calculations. See Table 16e. Set
GATE_
APCCOMP_ and TCOMP_ to 0 before A_HIST is changed.
58 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 16cꢀ Temperature Hꢂsteresis Limit
Register Bits
Tabꢄe 16eꢀ APC Hꢂsteresis Limit
Register Bits
AxHIST[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FUNCTION
1 LSB. I.e., no hysteresis
TxHIST[3:0]
FUNCTION
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 LSB (1/8 of a degree). I.e., no hysteresis
2 LSBs (1/4 of a degree)
3 LSBs (3/8 of a degree)
4 LSBs (1/2 of a degree)
5 LSBs (5/8 of a degree)
6 LSBs (3/4 of a degree)
7 LSBs (7/8 of a degree)
8 LSBs (1 degree)
2 LSBs
3 LSBs
4 LSBs
5 LSBs
6 LSBs
7 LSBs
8 LSBs
9 LSBs
10 LSBs
11 LSBs
12 LSBs
13 LSBs
14 LSBs
15 LSBs
16 LSBs
9 LSBs (1 1/8 of a degree)
10 LSBs (1 1/4 of a degree)
11 LSBs (1 3/8 of a degree)
12 LSBs (1 1/2 of a degree)
13 LSBs (1 5/8 of a degree)
14 LSBs (1 3/4 of a degree)
15 LSBs (1 7/8 of a degree)
16 LSBs (2 degrees)
Tabꢄe 16dꢀ APC Difference Limiter for
Averaging
A_LIMIT[2:0]
000
FUNCTION
No limiting is applied
001
Difference is limited to 1 LSB (1/8 of a degree)
Difference is limited to 3 LSBs (3/8 of a degree)
Difference is limited to 7 LSBs (7/8 of a degree)
Difference is limited to 15 LSBs (1 7/8 degrees)
Difference is limited to 31 LSBs (3 7/8 degrees)
Difference is limited to 63 LSBs (7 7/8 degrees)
010
011
100
101
110
Difference is limited to 127 LSBs (15 7/8
degrees)
111
______________________________________________________________________________________ 59
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Software Cꢄear Register (SCLR) (Write Onꢄꢂ)
Write to the Software Clear register to clear the internal
registers with a single write command (see Table 25).
Bits D[15:7] are don’t-care bits.
Set FIFOCLR to 1 to clear the FIFO. This function is
instantaneous and does not affect BUSY.
Set DAC_RST to 1 to clear the contents of the DAC
Input and Output registers. This function is instanta-
neous and does not affect BUSY.
FULLRST and ARMRST operate in conjunction with
each other to allow a full hardware reset of the device.
If ARMRST has been set to 1 by a previous write com-
mand, setting FULLRST to 1 initiates a full reset of the
MAX11008. ARMRST can only be set to 1 when the
FULLRST is set to 0 in the same data word. This pro-
vides protection from accidental resets since two write
commands are needed to initiate a full reset. To per-
form a full reset, first write a data word with FULLRST
set to 0 and ARMRST set to 1. Then write another data
word with FULLRST set to 1 and ARMRST set to 0.
Fꢄag Register (FLAG) (Read Onꢄꢂ)
The Flag register indicates if the MAX11008 is currently
in the middle of an internal calculation, if a full reset has
been performed, and the status of the FIFO. The Flag
register also indicates the source of an alarm when an
alarm threshold is exceeded (see Table 26). Bits
D[15:12] are don’t-care bits.
MAX108
ALUBUSY is set to 1 when the MAX11008 is performing
an internal calculation (see the Busy Output section)
and returns to 0 when the calculation is complete.
Set the ALMSCLR bit to 1 to clear all alarm threshold
registers and their respective flags in the Flag register.
RESTART is set to 1 if a full reset or watchdog initiated
reset was performed (see the Software Clear Register
(SCLR) (Write Only) section) and returns to 0 after the
Flag register is read. RESTART is initially set to 0 when
power is first applied (a power-on reset condition).
Set the AVGCLR bit to 1 to clear the average and hys-
teresis memory for all lookup operations. Setting the
AVGCLR bit reacquires the average and performs a
new LUT operation.
Tabꢄe 1.ꢀ DAC Input Registers
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
XXXX
NA
Unused bits.
DAC Input register data bits.
DACIP_[11:0]
X = Don’t care.
NA = Not applicable.
Tabꢄe 18ꢀ DAC Input and Output Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
Unused
RESET STATE
FUNCTION
X
Unused bits.
DAC Input and Output register data bits.
DAC_[11:0]
NA
X = Don’t care.
NA = Not applicable.
60 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
FIFOEMP is set to 1 when the FIFO is empty. Once data
is placed into the FIFO, FIFOEMP is set to 0.
when the FIFO is full and immediately returns to 0 once
a data word is moved out of the FIFO.
When in ADC monitoring mode, FIFOOVER is set to 1
when a FIFO overflow occurs. FIFOOVER remains at 1,
even if the FIFO is subsequently read and no longer
full. FIFOOVER is reset by reading the Flag register.
When in LUT streaming mode or message mode, the
FIFO is not permitted to overflow and FIFOOVER then
denotes when the FIFO is full. FIFOOVER is set to 1
HIGHI_ is set to 1 when the individual channel 1 and
channel 2 current-sense measurements exceed the
individual channel 1 and channel 2 high current thresh-
old and returns to 0 after the Flag register is read.
HIGHI2 is replaced by HIGHT2 when the INTEMP2 bit
is set in the Alarm Hardware Configuration register.
Tabꢄe 19ꢀ PGA Caꢄibration Controꢄ Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:3]
Unused
X
Unused bits.
Acquisition/tracking bit. Set to 0 to force the next current-sense calibration
to run in acquisition mode. Set to 1 to force the next calibration to run in
tracking mode. Set TRACK to 0 the first time through a calibration.
D2
D1
D0
TRACK
DOCAL
0
0
0
Single calibration select bit. Set to 1 perform single or self-timed
calibrations of PGA1 and PGA2. DOCAL resets to 0 after calibration.
Self-timed calibration select bit. Set to 1 to perform calibrations of PGA1
and PGA2 on a self-timed periodic basis (approximately every 13ms).
When set to 0, calibrations only occur when DOCAL is set to 1.
SELFTIME
X = Don’t care.
NA = Not applicable.
Tabꢄe 20ꢀ ADC Conversion Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:8]
Unused
X
Unused bits.
Continuous conversion select bit. Set to 1 to perform continuous
conversions of the selected channels.
D7
CONCONV
0
D6
D5
D4
D3
D2
D1
D0
ADCIN2
CS2
0
0
0
0
0
0
0
ADCIN2 conversion select bit.
CS2 current-sense conversion select bit.
External temperature sensor 2 conversion select bit.
ADCIN1 conversion select bit.
EXTEMP2
ADCIN1
CS1
CS1 current-sense conversion select bit.
External temperature sensor 1 conversion select bit.
Internal temperature sensor conversion select bit.
EXTEMP1
INTEMP
X = Don’t care.
NA = Not applicable.
______________________________________________________________________________________ 61
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
LOWI_ is set to 1 when the individual channel 1 and
channel 2 current-sense measurements exceed the
individual channel 1 and channel 2 low current thresh-
old and returns to 0 after the Flag register is read.
LOWI2 is replaced by LOWT2 when the INTEMP2 bit is
set in the Alarm Hardware Configuration register.
LUTSL[7:0] to 255 instructs the MAX11008 to expect a
LUT of length 256.
Bits LUTSA[7:0] specify the starting address of the data
that is to be written to the EEPROM. The MAX11008
counts the number of words that are written to the FIFO.
The device remains in LUT streaming mode until all the
indicated words are received.
HIGHT_ is set to 1 when the individual channel 1 and
channel 2 temperature measurements exceed the indi-
vidual channel 1 and channel 2 high temperature
threshold and returns to 0 after the Flag register is
read. HIGHT2 is unused when the INTEMP2 bit is set in
the Alarm Hardware Configuration register. When
INTEMP2 is set, HIGHT2 returns a 1 or 0.
Applications Information
External Temperature Sensor
Considerations
MAX108
To optimize the performance of the temperature sen-
sors, place the MAX11008 as close as possible to the
remote diodes. Traces of DXP_ and DXN_ should not
be routed across noisy digital lines and buses.
Minimize the noise that is coupled into the DXP_ and
DXN_ traces by shielding them with ground traces on
each side of the pair of temperature sensor traces (see
Figure 23). Routing the DXP_ and DXN_ traces over the
analog ground plane (AGND) also helps minimize
noise. Use wide traces (10 mils or wider) to minimize
the trace inductance of the DXP_ and DXN_ traces.
LOWT_ is set to 1 when the individual channel 1 and
channel 2 temperature measurements exceed the indi-
vidual channel 1 and channel 2 low temperature thresh-
old and returns to 0 after the Flag register is read.
LOWT2 is unused when the INTEMP2 bit is set in the
Alarm Hardware Configuration register. When INTEMP2
is set, LOWT2 returns a 1 or 0.
LUT Streaming Register (LUTSTRM) (Write Onꢄꢂ)
Write to the LUT Streaming register to place the
MAX11008 into LUT streaming mode (see the LUT
Streaming Mode section and Table 27).
Layout, Grounding, and Bypassing
Ensure that digital and analog signal lines are separat-
ed from each other. Use separate ground planes for
AGND and DGND. Connect both ground planes to a
single point on the PCB (star ground point). Do not run
analog and digital signals parallel to one another
(especially clock signals), and do not run digital lines
underneath the MAX11008 package. High-frequency
Bits LUTSL[7:0] specify the number of data words
(each data word is 16 bits long) that are to be written to
the EEPROM. The minimum and maximum number of
data words that can be written to the EEPROM are 1
and 256, respectively. Setting LUTSL[7:0] to 0 instructs
the MAX11008 to expect a LUT of length 1. Setting
noise in the AV
power supply may affect performance.
DD
Tabꢄe 21ꢀ Software Shutdown Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:6]
Unused
X
Unused bits.
Full power-down bit. Set to 1 to power down all sections of the MAX11008.
Set to 0 to exit full power-down mode.
D5
D4
D3
FULLPD
FBGON
WDGPD
0
0
0
Reference power-on bit. Set to 1 to force internal voltage reference to
remain on at all times (except when FULLPD is set to 1). Set to 0 to only
power internal reference when an ADC conversion is performed.
Watchdog oscillator power-down bit. Set to 1 to power down internal
watchdog oscillator.
D2
D1
D0
OSCPD
DAC2PD
DAC1PD
0
1
1
Internal oscillator power-down bit. Set to 1 to power down internal oscillator.
Channel 2 DAC power-down bit. Set to 1 to power down DAC2 and PGA2.
Channel 1 DAC power-down bit. Set to 1 to power down DAC1 and PGA1.
X = Don’t care.
62 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Bypass the AV
supply with a 0.1µF capacitor to
as physically close as possible to the DV
input. If the
DD
DD
AGND, and place the capacitor as physically close as
power supply is very noisy, connect a 10Ω resistor in
series with the supply input to improve power-supply fil-
tering.
possible to the AV
with a 0.1µF capacitor to DGND, and place the capacitor
input. Bypass the DV
supply
DD
DD
Tabꢄe 22ꢀ Load DAC Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:2]
Unused
X
Unused bits.
Channel 2 load DAC bit. Set to 1 to transfer DAC2 input register contents to
DAC2 output register.
D1
D0
LDDACCH2
LDDACCH1
NA
NA
Channel 1 load DAC bit. Set to 1 to transfer DAC1 input register contents to
DAC1 output register.
X = Don’t care.
NA = Not applicable.
Tabꢄe 23ꢀ Message Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
Message length bits. Specifies the length of the message to be read from
the EEPROM in words. The actual length read is MSGL + 1.
D[15:8]
MSGL[7:0]
0000 0000
Message address bits. Specifies the starting address of the message to be
read from the EEPROM.
D[7:0]
MSGA[7:0]
0000 0000
Tabꢄe 24ꢀ FIFO Read Register
DATA BITS
D[15:12]
D[11:0]
BIT NAME
RESET STATE
FUNCTION
DATA[15:12]/
TAG[3:0]
Message mode data bits/LUT streaming mode data bits/ADC channel tag
bits. See Table 24a.
0000
DATA[11:0]
0000 0000 0000 Message data bits/ADC data bits.
AGND TRACE
DXP_ TRACE
DXN_ TRACE
AGND TRACE
10mils
10mils
10mils
10mils
Figure 23. Recommended DXP_ and DXN_ PCB Trace Layout
______________________________________________________________________________________ 63
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 24aꢀ FIFO Read Channeꢄ Tags (TAG[3:0])
CHANNEL TAGS
ADC DATA DESCRIPTION
TAG3 TAG2 TAG1 TAG0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
Internal temperature sensor measurement. ADCMON bit must be set.
Channel 1 external temperature measurement. ADCMON bit must be set.
Channel 1 drain current measurement. ADCMON bit must be set.
ADCIN1 input measurement. ADCMON bit must be set.
Channel 2 external temperature measurement. ADCMON bit must be set.
Channel 2 drain current measurement. ADCMON bit must be set.
ADCIN2 input measurement. ADCMON bit must be set.
Channel 1 temperature average. AVGMON bit must be set.
Channel 1 APC average. AVGMON bit must be set.
MAX108
Channel 2 temperature average. AVGMON bit must be set.
Channel 2 APC average. AVGMON bit must be set.
Error tag. Indicates data may be corrupted.
Empty FIFO tag. This tag appears during a FIFO read if the FIFO is empty at the time the read
command is made. In addition to this channel tag, the current value of the Flag register is
provided in place of the ADC data.
1
1
1
1
Tabꢄe 25ꢀ Software Cꢄear Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:7]
Unused
X
Unused bits.
Full reset bit. If ARMRST has been set to 1 in a previous write operation, set
FULLRST to 1 to perform a full reset. Otherwise, a full reset will not be
performed and the value of FULLRST remains unchanged.
D6
FULLRST
NA
Full reset enable bit. Set to 1 at the same time FULLRST is set to 0 to
enable full reset capabilities.
D5
D4
D3
ARMRST
ALMSCLR
AVGCLR
0
Alarm threshold registers reset bit. Set to 1 to clear all alarm threshold
registers and their respective flags in the Flag register.
NA
NA
Average clear enable bit. Set the AVGCLR bit to 1 to clear the average and
hysteresis memory for all lookup operations.
D2
D1
D0
FIFOCLR
DAC2RST
DAC1RST
NA
NA
NA
FIFO clear bit. Set to 1 to clear the FIFO.
DAC 2 reset bit. Set to 1 to clear DAC2 input and output registers.
DAC 1 reset bit. Set to 1 to clear DAC1 input and output registers.
X = Don’t care.
NA = Not applicable.
64 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Tabꢄe 26ꢀ Fꢄag Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
D[15:12]
Reserved
X
Reserved bits.
ALU busy bit. Set to 1 when the MAX11008 is performing internal
calculations. Set to 0 after calculations are complete.
D11
D10
D9
ALUBUSY
RESTART
FIFOEMP
1
0
0
Restart flag bit. Set to 1 after a full software reset is performed. Returns to 0
after the Flag register is read. Set to 0 after initial power-up.
FIFO empty flag bit. Set to 1 when FIFO is empty. Set to 0 when data is
placed into the FIFO.
FIFO overflow/full flag bit. Set to 1 when in ADC monitoring mode and FIFO
overflow occurs. Returns to 0 when after Flag register is read. Set to 1 when
in LUT streaming mode and the FIFO is full. Returns to 0 after a data word
is moved out of the FIFO.
D8
D7
D6
D5
D4
FIFOOVER
HIGHI2
LOWI2
0
0
0
0
0
Channel 2 high current flag bit. Set to 1 when the channel 2 current-sense
measurement exceeds the channel 2 high current threshold and returns to
0 after the Flag register is read. When the INTEMP2 bit is set, this bit
functions as the internal temperature sensor’s alarm status.
Channel 2 low current flag bit. Set to 1 when the channel 2 current-sense
measurement exceeds the channel 2 low current threshold and returns to 0
after the Flag register is read. When the INTEMP2 bit is set, this bit
functions as the internal temperature sensor’s alarm status.
Channel 2 high temperature flag bit. Set to 1 when the channel 2
temperature measurement exceeds the channel 2 high temperature
threshold and returns to 0 after the Flag register is read. When the
INTEMP2 bit is set, this bit is unused and may read as 1 or 0.
HIGHT2
LOWT2
Channel 2 low temperature flag bit. Set to 1 when the channel 2
temperature measurement exceeds the channel 2 low temperature
threshold and returns to 0 after the Flag register is read. When the
INTEMP2 bit is set, this bit is unused and may read as a 1 or 0.
Channel 1 high current flag bit. Set to 1 when the channel 1 current-sense
measurement exceeds the channel 1 high current threshold and returns to
0 after the Flag register is read.
D3
D2
D1
HIGHI1
LOWI1
0
0
0
0
Channel 1 low current flag bit. Set to 1 when the channel 1 current-sense
measurement exceeds the channel 1 low current threshold and returns to 0
after the Flag register is read.
Channel 1 high temperature flag bit. Set to 1 when the channel 1
temperature measurement exceeds the channel 1 high temperature
threshold and returns to 0 after the Flag register is read.
HIGHT1
LOWT1
Channel 1 low temperature flag bit. Set to 1 when the channel 1
temperature measurement exceeds the channel 1 low temperature
threshold and returns to 0 after the Flag register is read.
D0
X = Don’t care.
______________________________________________________________________________________ 65
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Tabꢄe 2.ꢀ LUT Streaming Register
DATA BITS
BIT NAME
RESET STATE
FUNCTION
LUT length bits. Specifies the number of data words to be written to the
EEPROM. Up to 256 data words can be written. The actual length written is
LUTSL + 1.
D[15:8]
LUTSL[7:0]
0
LUT address bits. Specifies the starting address of the data to be written to
the EEPROM.
D[7:0]
LUTSA[7:0]
0
MAX108
only and results directly from the ADC’s resolution (N
Definitions
Integral Nonlinearity
bits):
SNR = (6.02 x N + 1.76)dB
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX11008 is measured using the end-point
method.
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first five har-
monics, and the DC offset.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of greater than -1 LSB guarantees no
missing codes and a monotonic transfer function.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS noise plus distortion. RMS noise plus distortion
includes all spectral components to the Nyquist fre-
quency excluding the fundamental and the DC offset:
ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
SINAD (dB) = 20 x log (Signal /Noise
RMS
)
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ADC Gain Error
When a positive full-scale voltage is applied to the con-
verter inputs, the digital output is all ones (FFFh). The
transition from FFEh to FFFh occurs at 1.5 LSB below
full scale. Gain error is the amount of deviation between
the measured full-scale transition point and the ideal
full-scale transition point with the offset error removed.
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
⎡
⎢
⎤
⎛
⎞
2
2
2
2
2
THD = 20 x log
V
+ V + V + V + V
6
/V1
⎥
⎜
⎟
2
3
4
5
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization error
⎝
⎢
⎣
⎠
⎥
⎦
where V1 is the fundamental amplitude, and V2 through
V6 are the amplitudes of the first five harmonics.
66 ______________________________________________________________________________________
Dual RF LDMOS Bias Controller with
Nonvolatile Memory
MAX108
Spurious-Free Dynamic Range
Pin Configuration
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest spec-
tral component.
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation prod-
ucts are (f1 f2), (2 x f1), (2 x f2), (2 x f1 f2), (2 x f2
f1). The individual input tone levels are at -7dB FS.
AV
N.C.
N.C.
N.C.
24
23
22
37
38
39
DD
AGND
AGND
21 AGND
PGAOUT1 40
A2/N.C. 41
20 AV
DD
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as the
full-power input bandwidth frequency.
N.C.
42
43
19 N.C.
MAX11008
18
GATE1
SCL/SCLK
17 GATE2
SDA/DIN 44
A1/DOUT 45
16 PGAOUT2
ADCIN2
14 ADCIN1
13
BUSY
15
46
47
48
EP*
DV
DD
+
DXN2
N.C.
2
3
4
5
6
7
8
9
10
1
11
12
Chip Information
PROCESS: BiCMOS
THIN QFN
.mm x .mm x 0ꢀ8mm
*EP = EXPOSED PAD.
Package Information
For the latest package outline information and land patterns, go
to wwwꢀmaxim-icꢀcom/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NOꢀ
48 TQFN-EP
T4877M-1
21-0144
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 6.
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明