MAX1190ECM_技术文档

19-2524; Rev 0; 7/02

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

General Description

Features

The MAX1190 is a 3.3V, dual 10-bit analog-to-digital con-

verter (ADC) featuring fully differential wideband track-

and-hold (T/H) inputs, driving two ADCs. The MAX1190 is

optimized for low power, small size, and high-dynamic

performance for applications in imaging, instrumentation,

and digital communications. This ADC operates from a

single 2.8V to 3.6V supply, consuming only 492mW while

delivering a typical signal-to-noise and distortion (SINAD)

of 57dB at an input frequency of 60MHz and a sampling

rate of 120Msps. The T/H driven input stages incorporate

400MHz (-3dB) input amplifiers. The converters can also

be operated with single-ended inputs. In addition to low

operating power, the MAX1190 features a 3mA sleep

mode, as well as a 1µA power-down mode to conserve

power during idle periods.

ꢀ Single 3.3V Operation

ꢀ Excellent Dynamic Performance

57dB SINAD at f = 60MHz

IN

64dBc SFDR at f = 60MHz

IN

ꢀ -71dBc Interchannel Crosstalk at f = 60MHz

IN

ꢀ Low Power

492mW (Normal Operation)

10mW (Sleep Mode)

3.3µW (Shutdown Mode)

ꢀ 0.08dB Gain and 0.8° Phase Matching

ꢀ Wide 1V

Differential Analog Input Voltage

P-P

Range

ꢀ 400MHz -3dB Input Bandwidth

An internal 2.048V precision bandgap reference sets the

full-scale range of the ADC. A flexible reference structure

allows the use of this internal or an externally applied ref-

erence, if desired, for applications requiring increased

accuracy or a different input voltage range.

ꢀ On-Chip 2.048V Precision Bandgap Reference

ꢀ User-Selectable Output Format—Two’s Complement

or Offset Binary

ꢀ Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit

Versions Available

The MAX1190 features parallel, CMOS-compatible three-

state outputs. The digital output format can be set to two’s

complement or straight offset binary through a single con-

trol pin. The device provides for a separate output power

supply of 1.7V to 3.6V for flexible interfacing with various

logic families. The MAX1190 is available in a 7mm ✕

7mm, 48-pin TQFP-EP package, and is specified for the

extended industrial (-40°C to +85°C) temperature range.

Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

MAX1190ECM

-40°C to +85°C

48 TQFP-EP*

*EP = Exposed paddle.

Functional Diagram appears at end of data sheet.

Pin-compatible lower speed versions of the MAX1190 are

also available. Refer to the MAX1180–MAX1184 data

sheets for 105Msps/80Msps/65Msps/40Msps. In addition

to these speed grades, this family includes two multi-

plexed output versions (MAX1185/MAX1186 for

20Msps/40Msps), for which digital data is presented

time-interleaved and on a single, parallel 10-bit output

port.

Pin Configuration

COM

1

2

36 D1A

35 D0A

34 OGND

V

DD

For lower speed, pin-compatible, 8-bit versions of the

MAX1190, refer to the MAX1195–MAX1198 data sheets.

GND

INA+

INA-

3

4

33 OV

32 OV

DD

5

Applications

V

6

31 OGND

30 D0B

29 D1B

DD

MAX1190

Baseband I/Q Sampling

Multichannel IF Sampling

Ultrasound and Medical Imaging

Battery-Powered Instrumentation

WLAN, WWAN, WLL, MMDS Modems

Set-Top Boxes

GND

INB-

INB+

GND

7

8

D2B

D3B

D4B

D5B

9

28

27

26

25

10

11

12

V

DD

CLK

VSAT Terminals

TQFP-EP

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

ABSOLUTE MAXIMUM RATINGS

V

, OV

to GND ...............................................-0.3V to +3.6V

Continuous Power Dissipation (T = +70°C)

DD

A

OGND to GND.......................................................-0.3V to +0.3V

48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

INA+, INA-, INB+, INB- to GND ...............................-0.3V to V

REFIN, REFOUT, REFP, REFN, COM,

DD

CLK to GND............................................-0.3V to (V

+ 0.3V)

DD

OE, PD, SLEEP, T/B,

D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OV

+ 0.3V)

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= 3.3V; OV

= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a

DD

10kΩ resistor; V

= 2.048V; V = 2V

(differential with respect to COM); C = 10pF at digital outputs; f

= 120MHz; T =

CLK A

REFIN

IN

P-P

L

T

MIN

to T

, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization;

MAX

typical values are at T = +25°C.)

A

PARAMETER

DC ACCURACY

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

10

Bits

LSB

Integral Nonlinearity

INL

f

= 7.47MHz

0.75

0.4

3

IN

= 7.47MHz, no missing codes

Differential Nonlinearity

DNL

-1

+1.5

LSB

guaranteed

Offset Error

< 1

0

1.8

2

%FS

Gain Error

ANALOG INPUT

Differential Input Voltage Range

V

Differential or single-ended inputs

Switched capacitor load

1.0

V

DIFF

Common-Mode Input Voltage

Range

V

/ 2

DD

0.5

V

CM

Input Resistance

R

20

kΩ

IN

Input Capacitance

C

5

pF

IN

CONVERSION RATE

Maximum Clock Frequency

f

120

MHz

CLK

Clock

Cycles

Data Latency

5

DYNAMIC CHARACTERISTICS (f

= 120MHz, 4096-point FFT)

CLK

f

T

= 20.01MHz at -0.5dB FS,

= +25°C

INA or B

55

58.5

A

Signal-to-Noise Ratio

SNR

dB

f

= 30.09MHz at -0.5dB FS

= 59.74MHz at -0.5dB FS

= 20.01MHz at -0.5dB FS,

58.2

58

INA or B

54.5

57.5

T

= +25°C

A

Signal-to-Noise and Distortion

SINAD

f

= 30.09MHz at -0.5dB FS

= 59.74MHz at -0.5dB FS

57

INA or B

2

_______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3.3V; OV

= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a

DD

10kΩ resistor; V

= 2.048V; V = 2V

(differential with respect to COM); C = 10pF at digital outputs; f

= 120MHz; T =

CLK A

REFIN

IN

P-P

L

T

MIN

to T

, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization;

MAX

typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

f

T

= 20.01MHz at -0.5dB FS,

= +25°C

INA or B

58

67

A

Spurious-Free Dynamic Range

SFDR

dBc

f

= 30.09MHz at -0.5dB FS

= 59.74MHz at -0.5dB FS

67

64

INA or B

f

T

= 20.01MHz at -0.5dB FS,

= +25°C

INA or B

-67

A

Third-Harmonic

Distortion

HD3

dBc

f

= 30.09MHz at -0.5dB FS

= 59.74MHz at -0.5dB FS

-67

-64

INA or B

f

= 43.393MHz at -6.5dB FS,

= 48.9017MHz at -6.5dB FS

IN1(A or B)

Intermodulation Distortion

(First Five Odd-Order IMDs)

IMD

IM3

-73

IN2(A or B)

dBc

(Note 1)

f

= 43.393MHz at -6.5dB FS,

= 48.9017MHz at -6.5dB FS

IN1(A or B)

IN2(A or B)

Third-Order Intermodulation

Distortion

-83

-65

(Note 1)

f

= 20.01MHz at -0.5dB FS,

= +25°C

INA or B

-58

T

A

Total Harmonic Distortion

(First Four Harmonics)

THD

dBc

f

= 30.09MHz at -0.5dB FS

= 59.74MHz at -0.5dB FS

-65

-63

500

400

1

INA or B

Small-Signal Bandwidth

Full-Power Bandwidth

Aperture Delay

Input at -20dB FS, differential inputs

Input at -0.5dB FS, differential inputs

MHz

ns

FPBW

t

AD

Aperture Jitter

t

2

ps

RMS

AJ

Overdrive Recovery Time

INTERNAL REFERENCE

For 1.5 × full-scale input

2

ns

2.048

3%

Reference Output Voltage

V

REFOUT

Load Regulation

1.25

mV/mA

ppm/°C

Reference Temperature

Coefficient

TC

60

REF

BUFFERED EXTERNAL REFERENCE (V

= 2.048V)

(Note 2)

REFIN

Positive Reference Output

V

2.162

V

REFP

Voltage

Negative Reference Output

Voltage

V

(Note 2)

1.138

1.651

1.024

>50

V

REFN

Common-Mode Level

V

COM

Differential Reference Output

Voltage Range

∆V

= V

- V

REFN

0.95

1.09

V

REF

REFP

REFIN Resistance

R

MΩ

REFIN

_______________________________________________________________________________________

3

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3.3V; OV

= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a

DD

10kΩ resistor; V

= 2.048V; V = 2V

(differential with respect to COM); C = 10pF at digital outputs; f

= 120MHz; T =

CLK A

REFIN

IN

P-P

L

T

MIN

to T

, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization;

MAX

typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Maximum REFP, COM Source

Current

I

5

mA

SOURCE

Maximum REFP, COM Sink

Current

I

-250

µA

SINK

Maximum REFN Source Current

I

250

-5

µA

SOURCE

Maximum REFN Sink Current

I

mA

SINK

UNBUFFERED EXTERNAL REFERENCE (V

= AGND, reference voltage applied to REFP, REFN, and COM)

REFIN

R

,

Measured between REFP and COM, and

REFN and COM

REFP

REFP, REFN Input Resistance

3.4

kΩ

REFN

Differential Reference Input

Voltage Range

1.024

10%

∆V

= V

- V

REFN

V

REF

REFP

COM Input Voltage Range

REFP Input Voltage

V

/ 2 10%

DD

V

COM

REFP

REFN

V

+ ∆V

/ 2

COM

REF

REFN Input Voltage

V

- ∆V

COM

DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)

0.8 ×

CLK

V

DD

Input High Threshold

Input Low Threshold

V

IH

V

0.8 ×

OV

PD, OE, SLEEP, T/B

CLK

DD

0.2 ×

V

DD

V

IL

V

0.2 ×

OV

PD, OE, SLEEP, T/B

DD

Input Hysteresis

Input Leakage

V

0.1

5

HYST

V

= V

(CLK)

DD

5

IH

IL

I

IH

= OV

(PD, OE, SLEEP, T/B)

µA

pF

DD

I

IL

= 0

Input Capacitance

C

IN

DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)

Output Voltage Low

V

I

= -200µA

0.2

10

V

OL

SINK

OV

0.2

-

DD

Output Voltage High

V

= 200µA

SOURCE

OH

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

Analog Supply Voltage Range

Output Supply Voltage Range

I

OE = OV

µA

pF

LEAK

DD

C

5

OUT

DD

V

2.8

1.7

3.3

2.5

3.6

V

DD

OV

DD

4

_______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

ELECTRICAL CHARACTERISTICS (continued)

(V

= 3.3V; OV

= 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a

DD

10kΩ resistor; V

= 2.048V; V = 2V

(differential with respect to COM); C = 10pF at digital outputs; f

= 120MHz; T =

CLK A

REFIN

IN

P-P

L

T

MIN

to T

, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization;

MAX

typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

= 20.01MHz at

MIN

TYP

MAX

UNITS

mA

Operating, f

-0.5dB FS

INA and B

149

185

Analog Supply Current

I

VDD

Sleep mode

3

1

Shutdown, clock idle, PD = OE = OV

15

µA

DD

Operating, f

= 20.01MHz at -0.5dB

INA and B

FS; see Typical Operating Characteristics

section, Digital Supply Current vs. Analog

Input Frequency

16

mA

Output Supply Current

I

OVDD

Sleep mode

100

2

µA

Shutdown, clock idle, PD = OE = OV

10

DD

Operating, f

-0.5dB FS

= 20.01MHz at

INA and B

492

611

mW

Analog Power Dissipation

PDISS

PSRR

Sleep mode

10

mW

µW

Shutdown, clock idle, PD = OE = OV

Offset, V 5%

3.3

3.4

0.81

50

DD

mV/V

%/V

DD

Power-Supply Rejection Ratio

Gain, V

5%

DD

TIMING CHARACTERISTICS

CLK Rise to Output Data Valid

Time

t

C = 20pF (Note 3)

L

4.8

7.4

ns

DO

OE Fall to Output Enable Time

OE Rise to Output Disable Time

t

4.7

1.2

ns

ENABLE

t

DISABLE

Clock period: 8.34ns; see Typical Operating

Characteristics section, AC Performance vs.

Clock Duty Cycle

Clock period: 8.34ns; see Typical Operating

Characteristics section, AC Performance vs.

Clock Duty Cycle

CLK Pulse Width High

t

4.17

ns

CH

CLK Pulse Width Low

Wake-Up Time

t

ns

µs

CL

Wake up from sleep mode (Note 4)

0.65

1.2

t

WAKE

Wake up from shutdown mode (Note 4)

CHANNEL-TO-CHANNEL MATCHING

Crosstalk

f

= 20.01MHz at -0.5dB FS

-71

0.08

0.8

dBc

dB

INA or B

Gain Matching

= 20.01MHz at -0.5dB FS (Note 5)

= 20.01MHz at -0.5dB FS (Note 6)

0.2

Phase Matching

Degrees

Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.

Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.

Note 3: Digital outputs settle to V , V . Parameter guaranteed by design.

IH IL

Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.

Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-

mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.

Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of

the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.

_______________________________________________________________________________________

5

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Typical Operating Characteristics

(V = 3.3V, OV = 2.5V, V

= 2.048V, differential input at -0.5dB FS, f

= 120MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)

DD

REFIN

CLK L A

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

0

-25

0

-25

f

= 20.0119MHz

= 12.9799MHz

= 120.0128MHz

INA

INB

CLK

f

= 12.9799MHz

= 20.0119MHz

= 120.0128MHz

INA

INB

CLK

CHA

CHB

CHA

= 31.0873MHz

f

INA

f

-25

-50

= 23.9967MHz

= 120.0128MHz

INB

AINA/AINB = -0.52dB FS

f

CLK

f

AINA/AINB = -0.52dB FS

f

INA

INB

-50

-75

-100

-125

-100

-125

-100

-125

0

12

24

36

48

60

0

12

24

36

48

60

0

12

24

36

48

60

ANALOG INPUT FREQUENCY (MHz)

FFT PLOT CHA (8192-POINT RECORD,

DIFFERENTIAL INPUT)

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

FFT PLOT CHB (8192-POINT RECORD,

DIFFERENTIAL INPUT)

0

-25

0

-25

0

-25

CHA

CHB

INA

CHB

f

= 59.7427MHz

= 49.0189MHz

= 120.0128MHz

f

= 49.0189MHz

= 59.7427MHz

= 120.0128MHz

f

= 23.9967MHz

= 31.0873MHz

= 120.0128MHz

INA

INB

CLK

INA

INB

CLK

f

INB

f

CLK

AINA/AINB = -0.52dB FS

f

INB

-50

f

INA

f

INB

-75

-100

-125

-100

-125

-100

-125

0

12

24

36

48

60

0

12

24

36

48

60

0

12

24

36

48

60

ANALOG INPUT FREQUENCY (MHz)

TWO-TONE IMD PLOT

(8192-POINT RECORD, DIFFERENTIAL INPUT)

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

0

60

58

56

54

52

50

60

58

56

54

52

50

f

= 43.3933MHz

= 48.9017MHz

= 120.0128MHz

IN1

IN2

CLK

CHB

CHA

-25

-50

AIN = -6.5dB FS

f

IN1

f

IN2

CHA

-75

-100

-125

0

12

24

36

48

60

0

20

40

60

80

100

120

0

20

40

60

80

100

120

ANALOG INPUT FREQUENCY (MHz)

6

_______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Typical Operating Characteristics (continued)

(V = 3.3V, OV = 2.5V, V

= 2.048V, differential input at -0.5dB FS, f

= 120MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)

DD

REFIN

CLK L A

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

TOTAL HARMONIC DISTORTION

vs. ANALOG INPUT FREQUENCY

SNR/SINAD, THD/SFDR

vs. CLOCK DUTY CYCLE

80

72

64

56

48

40

-40

100

80

60

40

20

0

SFDR

CHB

-48

-56

-64

-72

-80

THD

SNR

CHA

SINAD

CHB

f

= 20.02536MHz

INA/B

0

20

40

60

80

100

120

0

20

40

60

80

100

120

40

44

48

52

56

60

ANALOG INPUT FREQUENCY (MHz)

CLOCK DUTY CYCLE (%)

FULL-POWER INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

SIGNAL-TO-NOISE RATIO

vs. INPUT POWER (f = 20.02536MHz)

SMALL-SIGNAL INPUT BANDWIDTH

vs. ANALOG INPUT FREQUENCY

IN

5

2

60

56

52

48

44

40

6

4

2

-1

0

-2

-4

-6

-8

-4

-7

V

= 100mV

IN

P-P

10

-10

1

10

100

1000

-20

-16

-12

-8

-4

0

1

100

1000

ANALOG INPUT FREQUENCY (MHz)

INPUT POWER (dB FS)

ANALOG INPUT FREQUENCY (MHz)

SIGNAL-TO-NOISE + DISTORTION

TOTAL HARMONIC DISTORTION

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f = 20.02536MHz)

IN

60

56

52

48

44

40

-50

-56

-62

-68

-74

-80

80

74

68

62

56

50

-20

-16

-12

-8

-4

0

-20

-16

-12

-8

-4

0

-20

-16

-12

-8

-4

0

INPUT POWER (dB FS)

_______________________________________________________________________________________

7

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Typical Operating Characteristics (continued)

(V = 3.3V, OV = 2.5V, V

= 2.048V, differential input at -0.5dB FS, f

= 120MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)

DD

REFIN

CLK

L

A

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

GAIN ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE

0.6

0.3

0.1

0.5

0.3

CHB

CHA

0.2

-0.2

-0.6

0.1

-0.1

-0.3

-0.1

-0.3

0

341

682

1023

0

341

682

1023

-40

-15

10

35

60

85

DIGITAL OUTPUT CODE

TEMPERATURE (°C)

OFFSET ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

DIGITAL SUPPLY CURRENT

vs. ANALOG INPUT FREQUENCY

0.8

0.3

180

170

160

150

140

130

120

30

25

20

15

10

5

CHB

-0.2

-0.7

-1.2

CHA

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

0

6

12 18 24 30 36 42 48 54 60

ANALOG INPUT FREQUENCY (MHz)

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

2.038

2.034

2.030

2.026

2.022

2.018

2.014

2.010

2.035

2.030

2.025

2.020

2.015

-40

-15

10

35

60

85

2.70 2.85 3.00 3.15 3.30 3.45 3.60

TEMPERATURE (°C)

V

(V)

DD

8

_______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Pin Description

NAME

FUNCTION

1

COM

Common-Mode Voltage I/O. Bypass to GND with a ≥0.1µF capacitor.

2, 6, 11,

14, 15

V

Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.

Analog Ground

DD

3, 7, 10,

13, 16

GND

4

5

INA+

INA-

INB-

INB+

CLK

Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.

Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.

Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.

Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.

Converter Clock Input

8

9

12

T/B selects the ADC Digital Output Format:

High: Two’s complement

Low: Straight offset binary

17

18

19

20

T/B

SLEEP

PD

Sleep-Mode Input:

High: Disables both quantizers, but leaves the reference bias circuit active

Low: Normal operation

High-Active Power-Down Input:

High: Power-down mode

Low: Normal operation

Low-Active Output Enable Input:

High: Digital outputs disabled

Low: Digital outputs enabled

OE

21

22

D9B

D8B

D7B

D6B

D5B

D4B

D3B

D2B

D1B

D0B

OGND

Three-State Digital Output, Bit 9 (MSB), Channel B

Three-State Digital Output, Bit 8, Channel B

Three-State Digital Output, Bit 7, Channel B

Three-State Digital Output, Bit 6, Channel B

Three-State Digital Output, Bit 5, Channel B

Three-State Digital Output, Bit 4, Channel B

Three-State Digital Output, Bit 3, Channel B

Three-State Digital Output, Bit 2, Channel B

Three-State Digital Output, Bit 1, Channel B

Three-State Digital Output, Bit 0, Channel B

Output Driver Ground

23

24

25

26

27

28

29

30

31, 34

Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with

0.1µF.

32, 33

OV

DD

35

36

37

38

39

D0A

D1A

D2A

D3A

D4A

Three-State Digital Output, Bit 0, Channel A

Three-State Digital Output, Bit 1, Channel A

Three-State Digital Output, Bit 2, Channel A

Three-State Digital Output, Bit 3, Channel A

Three-State Digital Output, Bit 4, Channel A

_______________________________________________________________________________________

9

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Pin Description (continued)

40

41

42

43

44

45

46

47

48

NAME

D5A

D6A

D7A

D8A

D9A

FUNCTION

Three-State Digital Output, Bit 5, Channel A

Three-State Digital Output, Bit 6, Channel A

Three-State Digital Output, Bit 7, Channel A

Three-State Digital Output, Bit 8, Channel A

Three-State Digital Output, Bit 9 (MSB), Channel A

REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.

REFIN

REFP

REFN

Reference Input. V

= 2 × (V

- V

REFN

). Bypass to GND with a >0.1µF capacitor.

REFIN

REFP

Positive Reference I/O. Conversion range is (V

- V

REFN

). Bypass to GND with a >0.1µF capacitor.

REFP

Negative Reference I/O. Conversion range is (V

- V

REFN

). Bypass to GND with a >0.1µF capacitor.

REFP

Input Track-and-Hold Circuits

Detailed Description

Figure 2 displays a simplified functional diagram of the

input T/H circuits in both track and hold mode. In track

mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b

are closed. The fully differential circuits sample the input

signals onto the two capacitors (C2a and C2b) through

switches S4a and S4b. S2a and S2b set the common

mode for the amplifier input, and open simultaneously

with S1, sampling the input waveform. Switches S4a,

S4b, S5a, and S5b are then opened before switches

S3a and S3b connect capacitors C1a and C1b to the

output of the amplifier and switch S4c is closed. The

resulting differential voltages are held on capacitors

C2a and C2b. The amplifiers are used to charge capac-

itors C1a and C1b to the same values originally held on

C2a and C2b.

The MAX1190 uses a nine-stage, fully differential,

pipelined architecture (Figure 1) that allows for high-

speed conversion while minimizing power consump-

tion. Samples taken at the inputs move progressively

through the pipeline stages every half-clock cycle.

Including the delay through the output latch, the total

clock-cycle latency is five clock cycles.

Flash ADCs convert the held input voltages into a digi-

tal code. Internal MDACs convert the digitized results

back into analog voltages, which are then subtracted

from the original held input signals. The resulting error

signals are then multiplied by 2, and the residues are

passed along to the next pipeline stages, where the

process is repeated until the signals have been

processed by all nine stages.

2-BIT FLASH

ADC

2-BIT FLASH

ADC

STAGE 1

STAGE 2

STAGE 8

STAGE 9

STAGE 1

STAGE 2

STAGE 8

STAGE 9

DIGITAL ALIGNMENT LOGIC

10

DIGITAL ALIGNMENT LOGIC

10

T/H

D9A–D0A

D9B–D0B

V

INB

INA

V

INA

V

INB

= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)

= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)

Figure 1. Pipelined Architecture—Stage Blocks

10 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

INTERNAL

COM

S5a

BIAS

S2a

C1a

S3a

S4a

S4b

INA+

INA-

OUT

C2a

C2b

S4c

S1

C1b

S3b

S5b

COM

S2b

INTERNAL

BIAS

CLK

INTERNAL

NONOVERLAPPING

CLOCK SIGNALS

HOLD

INTERNAL

BIAS

TRACK

COM

S5a

S2a

C1a

S3a

S4a

S4b

INB+

INB-

OUT

C2a

C2b

S4c

S1

MAX1190

C1b

S3b

S5b

COM

S2b

INTERNAL

BIAS

Figure 2. MAX1190 T/H Amplifiers

These values are then presented to the first-stage quan-

tizers and isolate the pipelines from the fast-changing

inputs. The wide input bandwidth T/H amplifiers allow the

MAX1190 to track and sample/hold analog inputs of high

frequencies (>Nyquist). Both ADC inputs (INA+, INB+,

INA- and INB-) can be driven either differentially or sin-

gle ended. Match the impedance of INA+ and INA-, as

well as INB+ and INB-, and set the common-mode volt-

age to midsupply (V /2) for optimum performance.

DD

______________________________________________________________________________________ 11

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

these nodes become high-impedance inputs and can be

driven through separate, external reference sources.

Analog Inputs and Reference

Configurations

The full-scale range of the MAX1190 is determined by the

internally generated voltage difference between REFP

For detailed circuit suggestions and how to drive this

dual ADC in buffered/unbuffered external reference

mode, see the Applications Information section.

(V /2 + V

/4) and REFN (V /2 - V

/4). The full-

REFIN

DD

REFIN

DD

scale range for both on-chip ADCs is adjustable through

the REFIN pin, which is provided for this purpose.

Clock Input (CLK)

The MAX1190’s CLK input accepts a CMOS-compati-

ble clock signal. Since the interstage conversion of the

device depends on the repeatability of the rising and

falling edges of the external clock, use a clock with low

jitter and fast rise and fall times (<2ns). In particular,

sampling occurs on the rising edge of the clock signal,

requiring this edge to provide the lowest possible jitter.

Any significant aperture jitter would limit the SNR per-

formance of the on-chip ADCs as follows:

The MAX1190 provides three modes of reference oper-

ation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, connect the internal refer-

ence output REFOUT to REFIN through a resistor (e.g.,

10kΩ) or resistor-divider, if an application requires a

reduced full-scale range. For stability and noise filtering

purposes, bypass REFIN with a >10nF capacitor to

GND. In internal reference mode, REFOUT, COM,

REFP, and REFN become low-impedance outputs.





1

SNR = 20 × log





2 × π × f × t





IN AJ

where f represents the analog input frequency and t

IN

AJ

In buffered external reference mode, adjust the refer-

ence voltage levels externally by applying a stable and

accurate voltage at REFIN. In this mode, COM, REFP,

and REFN are outputs. REFOUT can be left open or

connected to REFIN through a >10kΩ resistor.

In unbuffered external reference mode, connect REFIN to

GND. This deactivates the on-chip reference buffers for

REFP, COM, and REFN. With their buffers shut down,

is the time of the aperture jitter. Clock jitter is especially

critical for undersampling applications. The clock input

should always be considered as an analog input and

routed away from any analog input or other digital signal

lines. The MAX1190 clock input operates with a voltage

threshold set to V /2. Clock inputs with a duty cycle

DD

other than 50%, must meet the specifications for high and

low periods as stated in the Electrical Characteristics.

5-CLOCK-CYCLE LATENCY

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

ANALOG INPUT

CLOCK INPUT

t

AD

t

CH

t

DO

CL

DATA OUTPUT

N - 6

N - 5

N - 4

N - 3

N - 2

N - 1

N

N + 1

D9A–D0A

DATA OUTPUT

N - 6

N - 5

N - 2

N + 1

D9B–D0B

Figure 3. System Timing Diagram

12 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

System Timing Requirements

Figure 3 depicts the relationship between the clock

OE

input, analog input, and data output. The MAX1190

samples at the rising edge of the input clock. Output

t

DISABLE

ENABLE

data for channels A and B is valid on the next rising

edge of the input clock. The output data has an internal

latency of five clock cycles. Figure 3 also determines

the relationship between the input clock parameters

and the valid output data on channels A and B.

OUTPUT

HIGH-Z

VALID DATA

D9A–D0A

OUTPUT

D9B–D0B

Digital Output Data (D0A/B–D9A/B), Output

Data Format Selection (T/B), Output

Figure 4. Output Timing Diagram

Enable (OE)

All digital outputs, D0A–D9A (channel A) and D0B–D9B

(channel B), are TTL/CMOS-logic compatible. There is

a five-clock-cycle latency between any particular sam-

ple and its corresponding output data. The output cod-

ing can be chosen to be either straight offset binary or

two’s complement (Table 1) controlled by a single pin

(T/B). Pull T/B low to select offset binary and high to

activate two’s complement output coding. The capaci-

tive load on digital outputs D0A–D9A and D0B–D9B

should be kept as low as possible (<15pF) to avoid

large digital currents that could feed back into the ana-

log portion of the MAX1190, thereby degrading its

dynamic performance. Using buffers on the digital out-

puts of the ADCs can further isolate the digital outputs

from heavy capacitive loads. To further improve the

dynamic performance of the MAX1190, small series

resistors (e.g., 100Ω) can be added to the digital output

paths, close to the MAX1190.

(both ADCs are disabled), and current consumption is

reduced to 3mA.

To enter full power-down mode, pull PD high. With OE

simultaneously low, all outputs are latched at the last

value prior to the power down. Pulling OE high forces

the digital outputs into a high-impedance state.

Applications Information

Figure 5 depicts a typical application circuit containing

two single-ended to differential converters. The internal

reference provides a V /2 output voltage for level-

DD

shifting purposes. The input is buffered and then split

to a voltage follower and inverter. One lowpass filter per

amplifier suppresses some of the wideband noise

associated with high-speed operational amplifiers. The

user can select the R

and C values to optimize the

IN

ISO

filter performance to suit a particular application. For

the application in Figure 5, a R of 50Ω is placed

ISO

Figure 4 displays the timing relationship between out-

put enable and data output valid, as well as power-

down/wakeup and data output valid.

before the capacitive load to prevent ringing and oscil-

lation. The 22pF C capacitor acts as a small filter

IN

capacitor.

Power-Down (PD) and Sleep

(SLEEP) Modes

The MAX1190 offers two power-save modes—sleep

mode and full power-down mode. In sleep mode

(SLEEP = 1), only the reference bias circuit is active

Table 1. MAX1190 Output Codes For Differential Inputs

DIFFERENTIAL INPUT

VOLTAGE*

STRAIGHT OFFSET BINARY

TWO’S COMPLEMENT

DIFFERENTIAL INPUT

T/B = 0

T/B = 1

V

× 512/512

+FULL SCALE - 1LSB

+1LSB

11 1111 1111

10 0000 0001

10 0000 0000

01 1111 1111

00 0000 0001

00 0000 0000

01 1111 1111

00 0000 0001

00 0000 0000

11 1111 1111

10 0000 0001

10 0000 0000

REF

V

× 1/512

0

REF

Bipolar Zero

-V

× 1/512

-1LSB

REF

-V

× 511/512

× 512/512

-FULL SCALE + 1LSB

-FULL SCALE

REF

-V

*V

REF

= V

- V

REFP REFN

______________________________________________________________________________________ 13

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

+5V

0.1µF

LOWPASS FILTER

INA-

MAX4108

300Ω

R

IS0

50Ω

0.1µF

C

IN

22pF

0.1µF

-5V

600Ω

300Ω

+5V

COM

INA+

0.1µF

+5V

0.1µF

600Ω

INPUT

0.1µF

LOWPASS FILTER

MAX4108

300Ω

MAX4108

R

IS0

C

IN

22pF

50Ω

-5V

+5V

300Ω

600Ω

MAX1190

0.1µF

LOWPASS FILTER

INB-

MAX4108

300Ω

R

IS0

50Ω

0.1µF

C

IN

22pF

-5V

600Ω

+5V

600Ω

300Ω

0.1µF

+5V

INPUT

LOWPASS FILTER

0.1µF

MAX4108

300Ω

INB+

MAX4108

R

IS0

50Ω

C

IN

22pF

-5V

0.1µF

-5V

300Ω

600Ω

Figure 5. Typical Application for Single-Ended to Differential Conversion

14 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

25Ω

INA+

22pF

0.1µF

6

5

4

1

2

T1

V

IN

N.C.

COM

2.2µF

0.1µF

3

MINICIRCUITS

TT1–6-KK81

25Ω

INA-

INB+

22pF

MAX1190

25Ω

0.1µF

6

5

4

1

2

3

T1

V

IN

N.C.

2.2µF

0.1µF

MINICIRCUITS

TT1-6-KK81

25Ω

INB-

22pF

Figure 6. Transformer-Coupled Input Drive

Using Transformer Coupling

An RF transformer (Figure 6) provides an excellent solu-

tion to convert a single-ended source signal to a fully dif-

ferential signal, required by the MAX1190 for optimum

performance. Connecting the center tap of the trans-

Single-Ended AC-Coupled Input Signal

Figure 7 shows an AC-coupled, single-ended applica-

tion. Amplifiers like the MAX4108 provide high speed,

high bandwidth, low noise, and low distortion to main-

tain the integrity of the input signal.

former to COM provides a V /2 DC level shift to the

DD

Buffered External Reference Drives

Multiple ADCs

Multiple-converter systems based on the MAX1190 are

well suited for use with a common reference voltage.

The REFIN pin of those converters can be connected

directly to an external reference source.

input. Although a 1:1 transformer is shown, a step-up

transformer can be selected to reduce the drive require-

ments. A reduced signal swing from the input driver, such

as an op amp, can also improve the overall distortion.

In general, the MAX1190 provides better SFDR and

THD with fully differential input signals than single-

ended drive, especially for very high input frequencies.

In differential input mode, even-order harmonics are

lower as both inputs (INA+, INA- and/or INB+, INB-) are

balanced, and each of the ADC inputs only requires

half the signal swing compared to single-ended mode.

A precision bandgap reference like the MAX6062 gen-

erates an external DC level of 2.048V (Figure 8), and

exhibits a noise voltage density of 150nV/√Hz. Its output

passes through a 1-pole lowpass filter (with 10Hz cutoff

frequency) to the MAX4250, which buffers the reference

before its output is applied to a second 10Hz lowpass

filter. The MAX4250 provides a low offset voltage (for

______________________________________________________________________________________ 15

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

REFP

1kΩ

R

ISO

50Ω

V

IN

0.1µF

INA+

COM

INA-

MAX4108

C

IN

22pF

100Ω

REFN

0.1µF

R

ISO

50Ω

C

IN

22pF

REFP

MAX1190

R

1kΩ

ISO

50Ω

V

IN

0.1µF

INB+

MAX4108

C

IN

22pF

100Ω

1kΩ

REFN

0.1µF

R

ISO

50Ω

INB-

C

IN

22pF

Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive

high-gain accuracy) and a low noise level. The passive

10Hz filter following the buffer attenuates noise pro-

duced in the voltage reference and buffer stages. This

filtered noise density, which decreases for higher fre-

quencies, meets the noise levels specified for preci-

sion-ADC operation.

Those three voltages are buffered by the MAX4252,

which provides low noise and low DC offset. The indi-

vidual voltage followers are connected to 10Hz lowpass

filters, which filter both the reference voltage and ampli-

fier noise to a level of 3nV/√Hz. The 2.0V and 1.0V refer-

ence voltages set the differential full-scale range of the

associated ADCs at 2V . The 2.0V and 1.0V buffers

P-P

Unbuffered External Reference Drives

Multiple ADCs

drive the ADCs’ internal ladder resistances between

them. Note that the common power supply for all active

components removes any concern regarding power-

supply sequencing when powering up or down.

Connecting each REFIN to analog ground disables the

internal reference of each device, allowing the internal

reference ladders to be driven directly by a set of exter-

nal reference sources. Followed by a 10Hz lowpass fil-

ter and precision voltage-divider, the MAX6066

generates a DC level of 2.500V. The buffered outputs of

this divider are set to 2.0V, 1.5V, and 1.0V, with an

accuracy that depends on the tolerance of the divider

resistors (Figure 9).

With the outputs of the MAX4252 matching better than

0.1%, the buffers and subsequent lowpass filters can

be replicated to support as many as 32 ADCs. For

applications that require more than 32 matched ADCs,

a voltage reference and divider string common to all

converters is highly recommended.

16 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

3.3V

0.1µF

N.C.

29

31

32

1

REFOUT

REFIN

REFP

2.048V

0.1µF

1

MAX6062

3

0.1µF

16.2kΩ

REFN

N = 1

5

2

3

4

2

162Ω

COM

1

MAX1190

MAX4250

2

1µF

100µF

10Hz LOWPASS

FILTER

0.1µF 0.1µF 0.1µF

10Hz LOWPASS

FILTER

2.2µF

10V

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.

0.1µF

29

31

32

1

N.C.

REFOUT

REFIN

REFP

N = 1000

0.1µF

REFN

MAX1190

2

COM

0.1µF 0.1µF 0.1µF

Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference

MAX1190, the mixed-down signal components can be

filtered by matched analog filters, such as Nyquist or

pulse-shaping filters, which remove unwanted images

from the mixing process, thereby enhancing the overall

SNR performance and minimizing intersymbol interfer-

ence.

Typical QAM Demodulation Application

A frequently used modulation technique in digital com-

munications applications is quadrature amplitude modu-

lation (QAM). Typically found in spread-spectrum-based

systems, a QAM signal represents a carrier frequency

modulated in both amplitude and phase. At the transmit-

ter, modulating the baseband signal with quadrature

outputs, a local oscillator followed by subsequent

upconversion can generate the QAM signal. The result

is an in-phase (I) and a quadrature (Q) carrier compo-

nent, where the Q component is 90° phase shifted with

respect to the in-phase component. At the receiver, the

QAM signal is divided down into its I and Q compo-

nents, essentially representing the modulation process

reversed. Figure 10 displays the demodulation process

performed in the analog domain, using the dual-

matched 3.3V, 10-bit ADC MAX1190 and the MAX2451

quadrature demodulator to recover and digitize the I

and Q baseband signals. Before being digitized by the

Grounding, Bypassing, and

Board Layout

The MAX1190 requires high-speed board layout design

techniques. Locate all bypass capacitors as close to the

device as possible, preferably on the same side as the

ADC, using surface-mount devices for minimum induc-

tance. Bypass V , REFP, REFN, and COM with two

DD

parallel 0.1µF ceramic capacitors and a 2.2µF bipolar

capacitor to GND. Follow the same rules to bypass the

digital supply (OV ) to OGND. Multilayer boards with

DD

separated ground and power planes produce the

______________________________________________________________________________________ 17

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

3.3V

0.1µF

N.C.

29

31

32

1

REFOUT

REFIN

REFP

1

MAX6066

3

2.0V

3.3V

4

21.5kΩ

REFN

N = 1

2.0V AT 8mA

2

3

2

1/4 MAX4252

1

47Ω

MAX1190

2

COM

10µF

6V

330µF

6V

11

21.5kΩ

1.47kΩ

0.1µF 0.1µF 0.1µF

1.5V

3.3V

1.5V AT 0mA

5

6

1/4 MAX4252

7

47Ω

1µF

10µF

330µF

11

6V

21.5kΩ

2.2µF

10V

1.47kΩ

0.1µF

3.3V

0.1µF

1.0V

3.3V

1.0V AT -8mA

10

9

1/4 MAX4252

8

47Ω

21.5kΩ

330µF

6V

29

31

32

1

N.C.

10µF

11

REFOUT

REFIN

REFP

MAX4254 POWER-SUPPLY

6V

BYPASSING. PLACE CAPACITOR

AS CLOSE AS POSSIBLE TO

THE OP AMP.

1.47kΩ

N = 32

REFN

MAX1190

2

COM

0.1µF 0.1µF 0.1µF

NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.

Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066

MAX2451

INA+

INA-

0°

DSP

90°

POST-

MAX1190

PROCESSING

INB+

INB-

DOWNCONVERTER

÷

8

Figure 10. Typical QAM Application Using the MAX1190

18 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

highest level of signal integrity. Consider the use of a split

Dynamic Parameter Definitions

ground plane arranged to match the physical location of

Aperture Jitter

the analog ground (GND) and the digital output driver

ground (OGND) on the ADC’s package. The two ground

planes should be joined at a single point such that the

noisy digital ground currents do not interfere with the ana-

log ground plane. The ideal location of this connection

can be determined experimentally at a point along the

gap between the two ground planes, which produces

optimum results. Make this connection with a low-value,

surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a

direct short. Alternatively, all ground pins could share the

same ground plane if the ground plane is sufficiently iso-

lated from any noisy, digital systems ground plane (e.g.,

downstream output buffer or DSP ground plane). Route

high-speed digital signal traces away from the sensitive

analog traces of either channel. Make sure to isolate the

analog input lines to each respective converter to mini-

mize channel-to-channel crosstalk. Keep all signal lines

short and free of 90° turns.

Figure 11 depicts the aperture jitter (t ), which is the

AJ

sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (t ) is the time defined between the

AD

falling edge of the sampling clock and the instant when

an actual sample is taken (Figure 11).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital

samples, the theoretical maximum SNR is the ratio of

the full-scale analog input (RMS value) to the RMS

quantization error (residual error). The ideal, theoretical

minimum analog-to-digital noise is caused by quantiza-

tion error only and results directly from the ADC’s reso-

lution (N bits):

SNR

= 6.02 ✕ N + 1.76

dB dB

dB[max]

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an

actual transfer function from a straight line. This straight

line can be either a best-straight-line fit or a line drawn

between the endpoints of the transfer function, once off-

set and gain errors have been nullified. The static linearity

parameters for the MAX1190 are measured using the

best-straight-line fit method.

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har-

monics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to all spectral components minus the fundamental

and the DC offset.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actu-

al step width and the ideal value of 1LSB. A DNL error

specification of less than 1LSB guarantees no missing

codes and a monotonic transfer function.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a

specific input frequency and sampling rate. An ideal

ADC’s error consists of quantization noise only. ENOB for

a full-scale sinusoidal input waveform is computed from:

CLK

SINAD−1.76





ENOB=









6.02

ANALOG

INPUT

t

AD

t

AJ

SAMPLED

DATA (T/H)

HOLD

TRACK

T/H

Figure 11. T/H Aperture Timing

______________________________________________________________________________________ 19

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four

harmonics of the input signal to the fundamental itself.

This is expressed as:

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of

either input tone to the worst 3rd-order (or higher) inter-

modulation products. The individual input tone levels are

at -6.5dB full scale and their envelope is at -0.5dB full

scale.













2

V

+ V + V + V

3 4 5

2

THD = 20 × log

V

1

Chip Information

TRANSISTOR COUNT: 10,811

where V is the fundamental amplitude, and V through

1

2

V

are the amplitudes of the 2nd- through 5th-order

harmonics.

PROCESS: CMOS

5

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next largest spurious

component, excluding DC offset.

Functional Diagram

V

DD

OGND

OV

GND

DD

INA+

10

OUTPUT

DRIVERS

D9A–D0A

ADC

DEC

T/H

INA-

CONTROL

CLK

OE

INB+

INB-

10

OUTPUT

DRIVERS

DEC

T/H

ADC

D9B–D0B

T/B

PD

SLEEP

REFERENCE

MAX1190

REFOUT

REFN COM REFP

REFIN

20 ______________________________________________________________________________________

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC

with Internal Reference and Parallel Outputs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1190ECM
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs 双路10位， 120Msps ， 3.3V ，低功耗ADC ，内置电压基准及并行输出
文件：	总21页 (文件大小：737K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1190ECM [MAXIM]

相关型号：

MAX1190ECM+

MAX1190ECM+D

MAX1190ECM+TD

MAX1190ECM-T

MAX1191

MAX1191ETI

MAX1191ETI+

MAX1191ETI+T

MAX1191ETI-T

MAX1192

MAX1192ETI

MAX1192ETI-T