MAX1333ETE-T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, 3 X 3 MM, 0.8 MM HEIGHT, MO-220, TQFN-16;
| 型号： | MAX1333ETE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, 3 X 3 MM, 0.8 MM HEIGHT, MO-220, TQFN-16 信息通信管理 转换器 |
| 文件： | 总25页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3712; Rev 0; 5/05
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
General Description
Features
The MAX1332/MAX1333 2-channel, serial-output,
12-bit, analog-to-digital converters (ADCs) feature two
true-differential analog inputs and offer outstanding noise
immunity and dynamic performance. Both devices easily
interface with SPI™/QSPI™/MICROWIRE™ and standard
digital signal processors (DSPs).
♦ 3Msps Sampling Rate (+5V, MAX1332)
♦ 2Msps Sampling Rate (+3V, MAX1333)
♦ Separate Logic Supply: +2.7V to +3.6V
♦ Two True-Differential Analog Input Channels
♦ Bipolar/Unipolar Selection Input
The MAX1332 operates from a single supply of +4.75V
to +5.25V with sampling rates up to 3Msps. The
MAX1333 operates from a single supply of +2.7V to
+3.6V with sampling rates up to 2Msps. These devices
feature a partial power-down mode and a full power-
down mode that reduce the supply current to 3.3mA
and 0.2µA, respectively. Also featured is a separate
♦ Only 38mW (typ) Power Consumption
♦ Only 2µA (max) Shutdown Current
♦ High-Speed, SPI-Compatible, 3-Wire Serial
Interface
power supply input (DV ) that allows direct interfacing
DD
♦ 2MHz Full-Linear Bandwidth
to +2.7V to +3.6V digital logic. The fast conversion
speed, low power dissipation, excellent AC perfor-
mance, and DC accuracy ( 0.6 ꢀSB Iꢁꢀ) maꢂe the
MAX1332/MAX1333 ideal for industrial process control,
motor control, and base-station applications.
♦ 71.4dB SINAD and -93dB THD at 525kHz Input
Frequency
♦ No Pipeline Delays
♦ Space-Saving (3mm x 3mm), 16-Pin, TQFN
The MAX1332/MAX1333 are available in a space-sav-
ing (3mm x 3mm), 16-pin, TQFꢁ pacꢂage and operate
over the extended (-40°C to +85°C) temperature range.
Package
Ordering Information
Applications
PART
TEMP RANGE PIN-PACKAGE
Data Acquisition
Bill Validation
MAX1332ETE* -40°C to +85°C 16 TQFꢁ-EP** (3mm x 3mm)
MAX1333ETE -40°C to +85°C 16 TQFꢁ-EP** (3mm x 3mm)
Motor Control
*Future product—contact factory for availability.
**EP = Exposed paddle.
Base Stations
High-Speed Modems
Optical Sensors
Industrial Process Control
Selector Guide and Pin Configuration appear at end of data
sheet.
Typical Operating Circuit
+2.7V TO +3.6V
+4.75V TO +5.25V
1µF
0.1µF
0.1µF
1µF
AV
DD
DV
DD
SHDN
+
AIN1P
AIN1N
AIN0P
AIN0N
BIP/UNI
-
DIFFERENTIAL
INPUTS
µC/DSP
+
MAX1332
CHSEL
CNVST
SCLK
-
REF INPUT
VOLTAGE
REF
DOUT
0.1µF
1µF
AGND
AGND DGND
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Continuous Power Dissipation (T = +70°C)
A
16-Pin TQFꢁ (derate 17.5mW/°C above +70°C) ....1398.6mW
Operating Temperature Range
AGꢁD to DGꢁD.....................................................-0.3V to +0.3V
MAX133_ETE...................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
ꢀead Temperature (soldering, 10s) .................................+300°C
SCꢀK, CꢁVST, SHDN, CHSEꢀ, BIP/UNI,
DOUT to DGꢁD ...................................-0.3V to (DV
AIꢁ0P, AIꢁ0ꢁ, AIꢁ1P, AIꢁ1ꢁ, REF to
+ 0.3V)
DD
AGꢁD...................................................-0.3V to (AV
+ 0.3V)
DD
Maximum Current into Any Pin ......................................... 50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (MAX1332)
(AV
= +4.75V to +5.25V, DV
= +2.7V to +3.6V, f
= 48MHz, V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
DD
SCꢀK
REF
A
MIꢁ
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (BIP/UNI = DGND) (Note 1)
Resolution
ꢁ
12
Bits
ꢀSB
ꢀSB
ꢀSB
ꢀSB
Integral ꢁonlinearity
Differential ꢁonlinearity
Offset Error
Iꢁꢀ
Dꢁꢀ
0.6
0.6
0.9
0.6
1.0
1.0
3.0
6.0
Gain Error
Offset-Error Temperature
Coefficient
0.2
1.1
ppm/°C
ppm/°C
Gain-Error Temperature
Coefficient
DYNAMIC SPECIFICATIONS (A = -0.2dBFS, f = 525kHz, BIP/UNI = DV , unless otherwise noted) (Note 1)
IN
IN
DD
Signal-to-ꢁoise Ratio
SꢁR
SIꢁAD
THD
70
70
71.5
71.4
-93
93
76
2
dB
dB
Signal-to-ꢁoise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
Full-ꢀinear Bandwidth
-84
dBc
dBc
dB
SFDR
84
SIꢁAD > 68dB
MHz
MHz
MHz
Full-Power Bandwidth
6
Small-Signal Bandwidth
CONVERSION RATE
6
Minimum Conversion Time
Maximum Throughput Rate
t
Figure 5
Figure 5
271
52
ns
COꢁV
3
Msps
Minimum Tracꢂ-and-Hold
Acquisition Time
t
ns
ACQ
2
_______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AV
= +4.75V to +5.25V, DV
= +2.7V to +3.6V, f
= 48MHz, V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
DD
SCꢀK
REF
A
MIꢁ
Typical values are at T = +25°C.)
A
PARAMETER
Aperture Delay
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
Figure 21
Figure 21
<10
<10
AD
Aperture Jitter
t
ps
AJ
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N)
BIP/UNI = DGꢁD
0
V
V
V
REF
Differential Input Voltage Range
V
Iꢁ
(V
AIꢁ_P
- V
)
AIꢁ_ꢁ
BIP/UNI = DV
-V
/ 2
+V
REF
/ 2
DD
REF
AV
DD
+
AGꢁD
- 50mV
Absolute Input Voltage Range
50mV
DC ꢀeaꢂage Current
Input Capacitance
I
1
µA
pF
ꢀKG
C
14
14
Iꢁ
REFERENCE INPUT (REF)
AV
DD
+
50mV
REF Input Voltage Range
V
1.0
V
REF
REF Input Capacitance
REF DC ꢀeaꢂage Current
C
pF
µA
REF
I
10
REF
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI)
0.3 x
Input-Voltage ꢀow
Input-Voltage High
V
V
V
Iꢀ
DV
DD
0.7 x
V
IH
DV
DD
Input Hysteresis
100
0.2
15
mV
µA
pF
Input ꢀeaꢂage Current
Input Capacitance
I
IꢀKG
5
C
Iꢁ
DIGITAL OUTPUT (DOUT)
Output-Voltage ꢀow
V
I
I
= 5mA
0.4
V
V
Oꢀ
SIꢁK
DV
0.5
-
DD
Output-Voltage High
V
= 1mA
SOURCE
OH
Tri-State ꢀeaꢂage Current
Tri-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
I
Between conversions, CꢁVST = DV
Between conversions, CꢁVST = DV
1
µA
pF
ꢀKGT
DD
C
15
11
OUT
DD
AV
DV
4.75
2.7
5.25
3.6
V
V
DD
Digital Supply Voltage
DD
ꢁormal mode; average current (f
=
SAMPꢀE
12
3MHz, f
= 48MHz)
mA
µA
SCꢀK
Analog Supply Current
I
AVDD
Partial power-down mode
Full power-down mode
3.5
0.1
6
2
_______________________________________________________________________________________
3
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AV
= +4.75V to +5.25V, DV
= +2.7V to +3.6V, f
= 48MHz, V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
DD
SCꢀK
REF
A
MIꢁ
Typical values are at T = +25°C.)
A
PARAMETER
Digital Supply Current
Power-Supply Rejection
SYMBOL
CONDITIONS
Average current (f = 3MHz, f
MIN
TYP
MAX
UNITS
=
SCꢀK
SAMPꢀE
4.5
15
7
mA
48MHz, zero-scale input)
Power-down (f = 48MHz), CꢁVST =
SCꢀK
I
30
DVDD
PSR
DV
DD
µA
Static; all digital inputs are connected to
0.2
2
2
DV
or DGꢁD
DD
AV
= 4.75V to 5.25V, full-scale input
mV
DD
TIMING CHARACTERISTICS (MAX1332) (Figure 4)
(AV
= +4.75V to +5.25V, DV
= +2.7V to +3.6V, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
DD
MIꢁ
PARAMETER
SYMBOL
CONDITIONS
MIN
20.8
6
TYP
MAX
UNITS
ns
SCꢀK Clocꢂ Period
t
CP
SCꢀK Pulse Width
t
ns
SPW
CꢁVST Rise to DOUT Disable
CꢁVST Fall to DOUT Enable
CHSEꢀ to CꢁVST Fall Setup
BIP/UNI to CꢁVST Fall Setup
CꢁVST Fall to CHSEꢀ Hold
SCꢀK Fall to BIP/UNI Hold
t
15
15
40
40
0
ns
CRDD
t
ns
CFDE
t
ns
CHCF
t
ns
BUCF
t
ns
CFCH
t
0
ns
CFBU
DOUT Remains Valid After SCꢀK
SCꢀK Rise to DOUT Transition
CꢁVST to SCꢀK Rise
t
C
C
= 0pF (ꢁote 2)
= 30pF
1
2
ns
DHOꢀD
ꢀOAD
ꢀOAD
t
6
ns
DOT
t
6
0
6
ns
SETUP
SCꢀK Rise to CꢁVST
t
ns
HOꢀD
CꢁVST Pulse Width
t
ns
CSW
Minimum Recovery Time (Full
Power-Down)
t
From CꢁVST fall or SHDN rise
4
µs
ns
FPD
Minimum Recovery Time (Partial
Power-Down)
t
From CꢁVST fall
500
PPD
Note 1: Tested with AV
= 4.75V and DV
= +2.7V.
DD
DD
Note 2: Guaranteed by design, not production tested.
4
_______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1333)
(AV
= +2.7V to +3.6V, DV
= +2.7V to AV , f
= 32MHz, V
= 2.5V, T = T
to T
, unless otherwise noted. Typical
MAX
DD
DD
DD SCꢀK
REF
A
MIꢁ
values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 3) (BIP/UNI = DGND)
Resolution
ꢁ
12
Bits
ꢀSB
ꢀSB
ꢀSB
ꢀSB
Relative Accuracy
Differential ꢁonlinearity
Offset Error
Iꢁꢀ
Dꢁꢀ
0.6
0.6
0.9
0.6
1.0
1.0
3.0
6.0
Gain Error
Offset-Error Temperature
Coefficient
1.1
0.2
ppm/°C
ppm/°C
Gain-Error Temperature
Coefficient
DYNAMIC SPECIFICATIONS (A = -0.2dBFS, f = 525kHz, BIP/UNI = DV , unless otherwise noted) (Note 3)
IN
IN
DD
Signal-to-ꢁoise Ratio
SꢁR
SIꢁAD
THD
70
70
71.5
71.4
-93
93
dB
dB
Signal-to-ꢁoise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Isolation
Full-ꢀinear Bandwidth
-86.5
dBc
dBc
dB
SFDR
83.5
76
SIꢁAD > 68dB
1.7
5.5
5
MHz
MHz
MHz
Full-Power Bandwidth
Small-Signal Bandwidth
CONVERSION RATE
Minimum Conversion Time
Maximum Throughput Rate
t
Figure 5
Figure 5
406
78
ns
COꢁV
2.0
Msps
Minimum Tracꢂ-and-Hold
Acquisition Time
t
ns
ACQ
Aperture Delay
Aperture Jitter
t
Figure 21
Figure 21
<10
<10
ns
ps
AD
t
AJ
DIFFERENTIAL ANALOG INPUTS (AIN0P, AIN0N, AIN1P, AIN1N)
BIP/UNI = DGꢁD
0
V
REF
Differential Input Voltage Range
V
V
Iꢁ
(V
AIꢁ_P
- V
)
AIꢁ_ꢁ
BIP/ UNI = DV
-V
/ 2
+V
/ 2
DD
REF
REF
AV
+
50mV
DD
AGꢁD
- 50mV
Absolute Input Voltage Range
DC ꢀeaꢂage Current
V
I
1
µA
ꢀKG
_______________________________________________________________________________________
5
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1333) (continued)
(AV
= +2.7V to +3.6V, DV
= +2.7V to AV , f
= 32MHz, V
= 2.5V, T = T
to T
, unless otherwise noted. Typical
MAX
DD
DD
DD SCꢀK
REF
A
MIꢁ
values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
C
14
pF
Iꢁ
REFERENCE INPUT (REF)
AV
DD
+
REF Input Voltage
V
1.0
V
REF
50mV
REF Input Capacitance
REF DC ꢀeaꢂage Current
C
14
pF
µA
REF
I
10
REF
DIGITAL INPUTS (SCLK, CNVST, SHDN, CHSEL, BIP/UNI)
0.3 x
Input-Voltage ꢀow
Input-Voltage High
V
V
V
Iꢀ
DV
DD
0.7 x
V
IH
DV
DD
Input Hysteresis
100
0.2
15
mV
µA
pF
Input ꢀeaꢂage Current
Input Capacitance
I
IꢀKG
5
C
Iꢁ
DIGITAL OUTPUT (DOUT)
Output-Voltage ꢀow
V
I
I
= 5mA
0.4
V
V
Oꢀ
SIꢁK
= 1mA
SOURCE
DV
0.5
-
DD
Output-Voltage High
V
OH
Tri-State ꢀeaꢂage Current
Tri-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage
I
Between conversions, CꢁVST = DV
Between conversions, CꢁVST = DV
1
µA
pF
ꢀKGT
DD
C
15
OUT
DD
AV
DV
2.7
2.7
3.6
AV
V
V
DD
Digital Supply Voltage
DD
DD
ꢁormal mode; average current (f
=
SAMPꢀE
9.5
11.5
2MHz, f
= 32MHz)
SCꢀK
mA
Analog Supply Current
I
AVDD
Partial power-down mode
Full power-down mode
3.3
0.1
4
2
µA
Average current (f
32MHz, zero-scale input)
= 2MHz, f
=
SAMPꢀE
SCꢀK
3
5.4
20
mA
Power-down (f = 32MHz, CꢁVST =
SCꢀK
Digital Supply Current
I
10
0.2
DVDD
PSR
DV
)
DD
µA
Static; all digital inputs are connected to
2
3
DV
or DGꢁD
DD
Positive Supply Rejection
AV
= 2.7V to 3.6V, full-scale input
mV
DD
6
_______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
TIMING CHARACTERISTICS (MAX1333) (Figure 4)
(AV
= +2.7V to +3.6V, DV
= +2.7V to AV , T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
DD
DD
A
MIꢁ
PARAMETER
SYMBOL
CONDITIONS
MIN
31.2
10
15
15
50
50
0
TYP
MAX
UNITS
ns
SCꢀK Clocꢂ Period
SCꢀK Pulse Width
t
CP
t
ns
CPW
CꢁVST Rise to DOUT Disable
CꢁVST Fall to DOUT Enable
CHSEꢀ to CꢁVST Fall Setup
BIP/UNI to CꢁVST Fall Setup
CꢁVST Fall to CHSEꢀ Hold
SCꢀK Fall to BIP/UNI Hold
DOUT Remains Valid After SCꢀK
SCꢀK Rise to DOUT Transition
CꢁVST to SCꢀK Rise
t
ns
CRDD
t
ns
CFDE
t
ns
CHCF
t
ns
BUCF
t
ns
CFCH
t
0
ns
CFBU
t
C
= 0pF (ꢁote 4)
= 30pF
1
2
ns
DHOꢀD
ꢀOAD
ꢀOAD
t
C
6
ns
DOT
t
6
0
6
ns
SETUP
SCꢀK Rise to CꢁVST
t
ns
HOꢀD
CꢁVST Pulse Width
t
ns
CSW
Minimum Recovery Time (Full
Power-Down)
t
From CꢁVST fall or SHDN rise
4
µs
ns
FPD
Minimum Recovery Time (Partial
Power-Down)
t
From CꢁVST fall
500
PPD
Note 3: Tested with AV
= DV
= +2.7V.
DD
DD
Note 4: Guaranteed by design, not production tested.
DV
DD
6kΩ
DOUT
DOUT
30pF
30pF
6kΩ
DGND
DGND
a) HIGH IMPEDANCE TO V , V TO V
OH OL
,
b) HIGH IMPEDANCE TO V , V TO V
OL OH
,
OH
OL
AND V TO HIGH IMPEDANCE
AND V TO HIGH IMPEDANCE
OH
OL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
7
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Typical Operating Characteristics
(AV
= +5V, DV
= +3V, V
= 4.096V, f
= 64MHz. T = +25°C, unless otherwise noted.)
DD
DD
REF
SCꢀK
A
MAX1332
OFFSET ERROR vs. AV
GAIN ERROR vs. AV
DD
DD
2.0
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
DV = +3V
DV = +3V
DD
DD
f
= 64MHz
f
= 64MHz
SCLK
SCLK
4.75
4.75
0
4.85
4.95
5.05
5.15
5.25
4.75
4.85
4.95
5.05
5.15
5.25
AV (V)
AV (V)
DD
DD
GAIN ERROR vs. AV
AV SUPPLY CURRENT vs. TEMPERATURE
DD
DD
2.0
1.5
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
DV = +3V
DD
ZERO-SCALE INPUT
f
= 64MHz
SCLK
f
= 64MHz
SCLK
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
AV (V)
TEMPERATURE (°C)
DD
AV SUPPLY CURRENT vs. f
DD
AV SUPPLY CURRENT vs. AV
DD DD
SCLK
12.0
11.5
11.0
10.5
10.0
9.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
DV = +3V
DD
9.0
ZERO-SCALE INPUT
8.5
f
= 64MHz
SCLK
8.5
8.0
8.0
8
16 24 32 40 48 56 64
(MHz)
4.75
4.85
4.95
5.05
5.15
5.25
f
AV (V)
SCLK
DD
8
_______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Typical Operating Characteristics (continued)
(AV
= +5V, DV
= +3V, V
= 4.096V, f = 64MHz. T = +25°C, unless otherwise noted.)
SCꢀK A
DD
DD
REF
MAX1332
DV SUPPLY CURRENT vs. TEMPERATURE
DD
DV SUPPLY CURRENT vs. f
DD
DV SUPPLY CURRENT vs. DV
DD
SCLK
DD
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
6
5
4
3
2
1
0
8
7
6
5
4
3
2
AV = +5V
DD
ZERO-SCALE INPUT
= 64MHz
ZERO-SCALE INPUT
f
SCLK
f
= 64MHz
SCLK
-40
-15
10
35
60
85
0
8
16 24 32 40 48 56 64
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
TEMPERATURE (°C)
f
(MHz)
DV (V)
DD
SCLK
TOTAL SUPPLY CURRENT
vs. THROUGHPUT RATE
100
10
1
NO POWER-DOWN
FULL POWER-DOWN
PARTIAL POWER-DOWN
0.1
0.001
0.01
0.1
(MHz)
1
10
f
CNVST
_______________________________________________________________________________________
9
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Typical Operating Characteristics (continued)
(AV
= +3V, DV
= +3V, V
= 2.5V, f
= 40MHz. T = +25°C, unless otherwise noted.)
SCꢀK A
DD
DD
REF
MAX1333
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE
1.0
1.0
0.8
2.0
1.5
1.0
0.5
0
f
= 32MHz
f
= 32MHz
SCLK
SCLK
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
-1.0
-1.5
-2.0
AV = +3V
DD
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
OFFSET ERROR vs. AV
DD
GAIN ERROR vs. AV
GAIN ERROR vs. TEMPERATURE
DD
4
3
2
1
2.0
1.5
1.0
0.5
0
2.0
1.5
DV = AV
DD
DD
DV = AV
DD DD
1.0
0.5
0
-1
-2
-3
-4
0
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
AV = +3V
DD
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AV (V)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
-40
-15
10
35
60
85
AV (V)
DD
TEMPERATURE (°C)
DD
AV SUPPLY CURRENT vs. f
DD
SCLK
AV SUPPLY CURRENT vs. AV
DD DD
AV SUPPLY CURRENT vs. TEMPERATURE
DD
12.0
11.5
11.0
10.5
10.0
9.5
12.0
12.0
11.5
11.0
10.5
10.0
9.5
11.5
11.0
10.5
10.0
9.5
9.0
9.0
9.0
8.5
AV = DV
DD
DD
ZERO-SCALE INPUT
= 40MHz
ZERO-SCALE INPUT
8.5
8.5
f
SCLK
f
= 40MHz
SCLK
8.0
8.0
8.0
0
5
10 15 20 25 30 35 40
(MHz)
-40
-15
10
35
60
85
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
f
SCLK
AV (V)
DD
TEMPERATURE (°C)
10 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Typical Operating Characteristics (continued)
(AV
= +3V, DV
= +3V, V
= 2.5V, f = 40MHz. T = +25°C, unless otherwise noted.)
SCꢀK A
DD
DD
REF
MAX1333
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
DV SUPPLY CURRENT vs. f
DV SUPPLY CURRENT vs. DV
DD DD
DD
SCLK
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
AV = +3V
DD
ZERO-SCALE INPUT
= 40MHz
ZERO-SCALE INPUT
f
SCLK
f
= 40MHz
SCLK
-40
-15
10
35
60 85
0
5
10 15 20 25 30 35 40
(MHz)
2.70 2.75 2.80 2.85 2.90 2.95 3.00
TEMPERATURE (°C)
f
DV (V)
DD
SCLK
THD vs. INPUT FREQUENCY
SINAD vs. INPUT FREQUENCY
SFDR vs. INPUT FREQUENCY
-70
-76
-82
-88
-94
72
100
94
88
82
76
70
70
68
66
64
62
f = 32MHz
SCLK
f
= 32MHz
400
f
= 32MHz
SCLK
SCLK
-100
0
400
800
1200
1600
2000
0
800
1200
1600
2000
0
400
800
1200
1600
2000
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
TOTAL SUPPLY CURRENT
vs. THROUGHPUT RATE
OUTPUT AMPLITUDE
vs. INPUT FREQUENCY
100
0
-1
-2
-3
-4
-5
-6
NO POWER-DOWN
10
1
FULL POWER-DOWN
PARTIAL POWER-DOWN
f
= 32MHz
SCLK
AIN = -0.1dBFS
0.1
0.001
0.01
0.1
(MHz)
1
10
0
1
2
3
4
5
6
7
8
f
CNVST
INPUT FREQUENCY (MHz)
______________________________________________________________________________________ 11
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Pin Description
PIN
1
NAME
AIꢁ0P
AIꢁ0ꢁ
AIꢁ1P
AIꢁ1ꢁ
FUNCTION
Positive Analog-Input Channel 0
ꢁegative Analog-Input Channel 0
Positive Analog-Input Channel 1
ꢁegative Analog-Input Channel 1
2
3
4
External Reference Voltage Input. V
and a 1µF.
= 1V to (AV
+ 50mV). Bypass REF to AGꢁD with a 0.1µF
DD
REF
5
6
7
REF
Shutdown Input. Pull SHDN low to enter full power-down mode. Drive SHDN high to resume normal
operation regardless of previous software entered into power-down mode.
SHDN
BIP/UNI
Analog-Input-Mode Select. Drive BIP/UNI high to select bipolar-input mode. Pull BIP/UNI low to select
unipolar-input mode.
8
9
AGꢁD
Analog Ground. Connect all AGꢁDs and EP to the same potential.
CHSEꢀ
Channel-Select Input. Drive CHSEꢀ high to select channel 1. Pull CHSEꢀ low to select channel 0.
Conversion-Start Input. The first rising edge of CꢁVST powers up the MAX1332/MAX1333 and begins
acquiring the analog input. A falling edge samples the analog input and starts a conversion. CꢁVST
also controls the power-down mode of the device (see the Partial Power-Down (PPD) and Full Power-
Down (FPD) Mode section).
10
CꢁVST
11
12
SCꢀK
DOUT
Serial-Clocꢂ Input. Clocꢂs data out of the serial interface. SCꢀK also sets the conversion speed.
Serial-Data Output. Data is clocꢂed out on the rising edge of SCꢀK (see the Starting a Conversion
section).
Positive-Digital-Supply Input. DV
is the positive supply input for the digital section of the
DD
MAX1332/MAX1333. Connect DV to a 2.7V to 3.6V power supply. Bypass DV to DGꢁD with a
0.1µF capacitor in parallel with a 1µF capacitor. Place the bypass capacitors as close to the device
as possible.
DD
DD
13
14
15
DV
DD
DGꢁD
Digital Ground. Ensure that the potential difference between AGꢁD and DGꢁD is less than 0.3V.
Positive-Analog-Supply Input. AV
MAX1332/MAX1333. Connect AV
is the positive supply input for the analog section of the
to a 4.75V to 5.25V power supply for the MAX1332. Connect
DD
DD
AV
DD
AV
to a 2.7V to 3.6V power supply for the MAX1333. Bypass AV to AGꢁD with a 0.1µF capacitor
DD
DD
in parallel with a 1µF capacitor. Place the bypass capacitors as close to the device as possible.
16
—
AGꢁD
EP
Analog Ground. Connect all AGꢁDs and EP to the same potential.
Exposed Paddle. Internally connected to AGꢁD. Connect the exposed paddle to the analog ground plane.
12 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Detailed Description
AV
DD
DV
DD
The MAX1332/MAX1333 use an input tracꢂ and hold
(T/H) circuit along with a successive-approximation
register (SAR) to convert a differential analog input sig-
nal to a digital 12-bit output. The serial interface
requires only three digital lines (SCꢀK, CꢁVST, and
DOUT) and provides easy interfacing to microcon-
trollers (µCs) and DSPs. Figure 2 shows the simplified
blocꢂ diagram for the MAX1332/MAX1333.
CHSEL
BIP/UNI
AIN0P
AIN0N
AIN1P
AIN1N
INPUT
MUX
AND T/H
OUTPUT
BUFFER
12-BIT SAR
ADC
DOUT
Power Supplies
The MAX1332/MAX1333 accept two power supplies
that allow the digital noise to be isolated from sensitive
analog circuitry. For both the MAX1332 and MAX1333,
the digital power-supply input accepts a supply voltage
of +2.7V to +3.6V. However, the supply voltage range
for the analog power supply is different for each
device. The MAX1332 accepts a +4.75V to +5.25V
analog power supply, and the MAX1333 accepts
a +2.7V to +3.6V analog power supply. See the Layout,
Grounding, and Bypassing section for information on
how to isolate digital noise from the analog power input.
REF
CNVST
SCLK
CONTROL
LOGIC AND
TIMING
MAX1332
MAX1333
SHDN
AGND
DGND
Figure 2. Simplified Functional Diagram
the acquisition time lengthens. The acquisition time,
, is the minimum time needed for the signal to be
t
The MAX1332/MAX1333s’ analog power supply con-
ACQ
acquired. It is calculated by the following equation:
sists of one AV
input, two AGꢁD inputs, and the
DD
exposed paddle (EP). The digital power input consists
of one DV input and one DGꢁD input. Ensure that
the potential on both AGꢁD inputs is the same.
Furthermore, ensure that the potential between AGꢁD
and DGꢁD is limited to 0.3V. Ideally there should be
no potential difference between AGꢁD and DGꢁD.
t
≥ ꢂ x (R
+ R ) x C
Iꢁ Iꢁ
ACQ
SOURCE
DD
where:
ꢁ
ꢂ = 9 ≈ln(2×2 )
The constant ꢂ is the number of RC time constants
required so that the voltage on the internal sampling
capacitor reaches ꢁ-bit accuracy, i.e., so that the dif-
ference between the input voltage and the sampling
capacitor voltage is equal to 0.5 ꢀSB. ꢁ = 12 for the
MAX1332/MAX1333.
There are no power sequencing issues between AV
DD
and DV . The analog and digital power supplies are
DD
insensitive to power-up sequencing.
True-Differential Analog Input T/H
The equivalent input circuit of Figure 3 shows the
MAX1332/MAX1333s’ input architecture, which is com-
posed of a T/H, a comparator, and a switched-capaci-
tor DAC. On power-up, the MAX1332/MAX1333 enter
full power-down mode. Drive CꢁVST high to exit full
power-down mode and to start acquiring the input. The
positive input capacitor is connected to AIꢁ_P and the
negative input capacitor is connected to AIꢁ_ꢁ. The
T/H enters its hold mode on the falling edge of CꢁVST
and the ADC starts converting the sampled difference
between the analog inputs. Once a conversion has
been initiated, the T/H enters acquisition mode for the
next conversion on the 13th falling edge of SCꢀK after
CꢁVST has been transitioned from high to low.
R
= 250Ω is the equivalent differential analog input
resistance, C = 14pF is the equivalent differential ana-
log input capacitance, and R
impedance of the input signal. ꢁote that t
less than 52µs for the MAX1332 and 78µs for the
MAX1333, and any source impedance below 160Ω does
not significantly affect the ADC’s AC performance.
Iꢁ
Iꢁ
is the source
SOURCE
is never
ACQ
Input Bandwidth
The ADC’s input-tracꢂing circuitry has a 5MHz small-
signal bandwidth, maꢂing it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
The time required for the T/H to acquire an input signal
is determined by how quicꢂly its input capacitance is
charged. If the input signal’s source impedance is high,
______________________________________________________________________________________ 13
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
AV
DD
CAPACITIVE
DAC
C
IN+
R
IN+
AIN_P
AIN_N
CONTROL
LOGIC
COMP
C
IN-
R
IN-
AGND
Figure 3a. Equivalent Input Circuit (Acquisition Mode)
AV
DD
CAPACITIVE
DAC
C
IN+
R
IN+
AIN_P
AIN_N
CONTROL
LOGIC
COMP
C
IN-
R
IN-
AGND
Figure 3b. Equivalent Input Circuit (Hold/Conversion Mode)
of interest, lowpass or bandpass filtering is recom-
mended to limit the bandwidth of the input signal.
wideband amplifier that settles quicꢂly and is stable
with the ADC’s 14pF input capacitance.
See the Maxim website (www.maxim-ic.com) for appli-
cation notes on how to choose the optimum buffer
amplifier for an ADC application. The MAX4430 is one
of the devices that is ideal for this application.
Input Buffer
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (14pF) and
settle quicꢂly. Most applications require an input buffer
to achieve 12-bit accuracy. Although slew rate and
bandwidth are important, the most critical input buffer
specification is settling time. The sampling requires an
acquisition time of 52µs for the MAX1332 and 78µs for
the MAX1333. At the beginning of the acquisition, the
ADC internal sampling capacitors connect to the ana-
log inputs, causing some disturbance. Ensure the
amplifier is capable of settling to at least 12-bit accura-
cy during this interval. Use a low-noise, low-distortion,
Differential Analog Input Range and
Protection
The MAX1332/MAX1333 produce a digital output that
corresponds to the differential analog input voltage as
long as the differential analog inputs are within the
specified range. When operating in unipolar mode
(BIP/UNI = 0), the usable differential analog input range
is from 0 to V
. When operating in bipolar mode
REF
(BIP/UNI = 1), the differential analog input range is from
-V /2 to +V /2. In both unipolar and bipolar
REF
REF
14 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
t
t
HOLD
t
SETUP
CSW
SCLK
DOUT
t
CP
t
DOT
t
t
CRDD
CFDE
t
DHOLD
Figure 4. Detailed Serial-Interface Timing
t
CONV
CNVST
t
POWER- MODE SELECTION WINDOW
10
t
SETUP
ACQ
SCLK
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
HIGH-Z
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
DOUT
ANALOG
INPUT TRACK
AND HOLD STATE
HOLD
TRACK
Figure 5. Interface Timing Sequence
modes, the input common-mode voltage can vary as
long as the voltage at any single analog input (V
AIꢁ_ꢁ
and Full Power-Down (FPD) Mode section). SCꢀK
clocꢂs data out of the serial interface and sets the con-
version speed. Figures 4 and 5 show timing diagrams
that outline the serial-interface operation.
,
AIꢁ_P
V
) remains within 50mV of the analog power sup-
ply rails (AV , AGꢁD).
DD
As shown in Figure 3, internal protection diodes confine
the analog input voltage within the region of the analog
Starting a Conversion
On power-up, the MAX1332/MAX1333 enter full power-
down mode. The first rising edge of CꢁVST exits the full
power-down mode and the MAX1332/MAX1333 begin
acquiring the analog input. A CꢁVST falling edge initi-
ates a conversion sequence. The T/H stage holds the
input voltage; DOUT changes from high impedance to
logic low; and the ADC begins to convert at the first
SCꢀK rising edge. SCꢀK is used to drive the conver-
sion process, and it shifts data out of DOUT. SCꢀK
begins shifting out the data after the 4th rising edge of
power-supply rails (AV , AGꢁD) and allow the analog
DD
input voltage to swing from AGꢁD - 0.3V to AV
+ 0.3V
DD
without damage. Input voltages beyond AGꢁD - 0.3V
and AV + 0.3V forward bias the internal protection
DD
diodes. In this situation, limit the forward diode current to
50mA to avoid damaging the MAX1332/MAX1333.
Serial Digital Interface
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CꢁVST and SCꢀK digital inputs. CꢁVST
controls the state of the T/H as well as when a conver-
sion is initiated. CꢁVST also controls the power-down
mode of the device (see the Partial Power-Down (PPD)
SCꢀK. DOUT transitions t
after each SCꢀK’s rising
after the next rising
DOT
edge and remains valid for t
DHOꢀD
edge. The 4th rising clocꢂ edge produces the MSB of
the conversion result at DOUT, and the MSB remains
valid t
after the 5th rising edge of SCꢀK. Sixteen
DHOꢀD
______________________________________________________________________________________ 15
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
1
13
16
1
SCLK
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 6. Continuous Conversion with Burst or Continuous Clock
CONVST MUST GO HIGH AFTER 4TH BUT BEFORE 13TH SCLK RISING EDGE
CNVST
ONE 8-BIT TRANSFER
SCLK
1ST SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CONVST GOES HIGH
DOUT
MODE
0
0
0
D11
D10
D9
D8
D7
NORMAL
PPD
Figure 7. SPI Interface—Partial Power-Down
rising SCꢀK edges are needed to clocꢂ out the three
leading zeros, 12 data bits, and a trailing zero. For con-
tinuous operation, pull CꢁVST high between the 14th
and the 15th rising edges of SCꢀK. The highest
throughput is achieved when performing continuous
conversions. If CꢁVST is low during the rising edge of
the 16th SCꢀK, the DOUT line goes to a high-imped-
ance state on either CꢁVST’s rising edge or the next
SCꢀK’s rising edge, enabling the serial interface to be
shared by multiple devices. Figure 6 illustrates a con-
version using a typical serial interface.
of the SCꢀK to enter partial power-down mode (see
Figure 7). Drive CꢁVST low and then drive high before
the 4th SCꢀK to remain in partial power-down mode. This
reduces the supply current to 3.3mA. Drive CꢁVST low
and allow at least 13 SCꢀK cycles to elapse before dri-
ving CꢁVST high to exit partial power-down mode.
Full power-down mode reduces the supply current to
0.2µA and is ideal for infrequent data sampling. To
enter full power-down mode, the MAX1332/MAX1333
must first be in partial power-down mode. While in par-
tial power-down mode, repeat the sequence used to
enter partial power-down mode to enter full power-
down mode (see Figure 8). Drive CꢁVST low and allow
at least 13 SCꢀK cycles to elapse before driving
CꢁVST high to exit full power-down mode.
Partial Power-Down (PPD) and Full Power-
Down (FPD) Mode
Power consumption is reduced significantly by placing
the MAX1332/MAX1333 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast
waꢂe-up time applications. Once CꢁVST is transitioned
from high to low, pull CꢁVST high any time after the 4th
rising edge of the SCꢀK but before the 13th rising edge
Maintain a logic low or a logic high on SCꢀK and all
digital inputs at DV
or DGꢁD while in either partial
DD
power-down or full power-down mode to minimize
power consumption.
16 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
SCLK
EXECUTE PARTIAL POWER-DOWN TWICE
1ST 8-BIT TRANSFER
2ND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
D8 D7
DOUT
MODE
0
0
0
D11
D10
D9
0
0
0
0
0
0
0
0
NORMAL
PPD
RECOVERY
FPD
Figure 8. SPI Interface—Full Power-Down
FULL-SCALE
TRANSITION
FULL-SCALE
TRANSITION
V
REF
2
FS
V
=
REF
V
+FS
=
FFF
FFE
FFD
7FF
ZS = 0
ZS = 0
-FS =
REF
7FE
1 LSB =
-V
4096
REF
2
V
4096
REF
1 LSB =
FFC
FFB
001
000
FFF
FFE
004
003
002
001
000
801
800
0
1
2
3
4
FS
-FS
0
+FS
FS - 1.5 LSB
-FS + 0.5 LSB
+FS - 1.5 LSB
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 9. Unipolar Transfer Function
Figure 10. Bipolar Transfer Function
Another way of entering the full power-down mode is
using the SHDN input. Drive SHDN to a logic low to put
the device into the full power-down mode. Drive SHDN
high to exit full power-down mode and return to normal
operating mode. SHDN overrides any software-controlled
power-down mode and every time it is deasserted, it
places the MAX1332/MAX1333 in its normal mode of
operation regardless of its previous state.
Transfer Function
The MAX1332/MAX1333 output is straight binary in
unipolar mode and is two’s complement in bipolar mode.
Figure 9 shows the unipolar transfer function for the
MAX1332/MAX1333. Table 1 shows the unipolar relation-
ship between the differential analog input voltage and
the digital output code. Figure 10 shows the bipolar
transfer function for the MAX1332/MAX1333. Table 2
shows the bipolar relationship between the differential
analog input voltage and the digital output code.
______________________________________________________________________________________ 17
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Table 1. Unipolar Code Table (MAX1332)
BINARY DIGITAL OUTPUT HEXADECIMAL EQUIVALENT
DECIMAL EQUIVALENT OF
DIFFERENTIAL INPUT
VOLTAGE (V) (V = 4.096V )
CODE D11–D0
OF D11–D0
D11–D0 (CODE )
10
REF
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
0xFFF
0xFFE
0x801
0x800
0x7FF
0x001
0x000
4095
4094
2049
2048
2047
1
+4.095 0.5 ꢀSB
+4.094 0.5 ꢀSB
+2.049 0.5 ꢀSB
+2.048 0.5 ꢀSB
+2.047 0.5 ꢀSB
+0.001 0.5 ꢀSB
+0.000 0.5 ꢀSB
0
Table 2. Bipolar Code Table (MAX1332)
TWO’s-COMPLEMENT
HEXADECIMAL EQUIVALENT
DIGITAL OUTPUT CODE
OF D11–D0
DECIMAL EQUIVALENT OF
DIFFERENTIAL INPUT
D11–D0 (CODE
)
VOLTAGE (V) (V
= 4.096V)
10
REF
D11–D0
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0001
1000 0000 0000
0x7FF
0x7FE
0x001
0x000
0xFFF
0x801
0x800
+2047
+2046
+1
+2.047 0.5 ꢀSB
+2.046 0.5 ꢀSB
+0.001 0.5 ꢀSB
0.000 0.5 ꢀSB
-0.001 0.5 ꢀSB
-2.047 0.5 ꢀSB
-2.048 0.5 ꢀSB
0
-1
-2047
-2048
Determine the differential analog input voltage as a
function of V and the digital output code with the fol-
Applications Information
REF
External Reference
lowing equation:
The MAX1332/MAX1333 use an external reference
between 1V and (AV
+ 50mV). Bypass REF with
DD
∆V
=ꢀSB×CODE
0.5×ꢀSB
AIꢁ
10
a 1µF capacitor in parallel with a 0.1µF capacitor
to AGꢁD for best performance (see the Typical
Operating Circuit).
where:
∆V
= V
− V
AIꢁ
AIꢁ_P AIꢁ_ꢁ
Connection to Standard Interfaces
The MAX1332/MAX1333 serial interface is fully compat-
ible with SPI, QSPI and MICROWIRE (see Figure 11). If
a serial interface is available, set the µC’s serial inter-
face in master mode so the µC generates the serial
V
V
REF
REF
ꢀSB=
=
212 4096
CODE = the decimal equivalent of the digital output
10
code (see Tables 1 and 2).
clocꢂ. Choose a clocꢂ frequency based on the AV
DD
and DV
amplitudes.
DD
0.5 x ꢀSB represents the quantization error that is
inherent to any ADC.
SPI and MICROWIRE
When using a 4.096V reference, 1 ꢀSB equals 1.0mV.
When using a 2.5V reference, 1 ꢀSB equals 0.61mV.
When using SPI or MICROWIRE, the MAX1332/
MAX1333 are compatible with all four modes pro-
grammed with the CPHA and CPOꢀ bits in the SPI or
MICROWIRE control register. (This control register is in
18 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
the bus master, not the MAX1332/MAX1333.)
Conversion begins with a CꢁVST falling edge. DOUT
goes low, indicating a conversion is in progress. Two
consecutive 1-byte reads are required to get the full 12
bits from the ADC. DOUT transitions on SCꢀK rising
I/O
SCK
CNVST
SCLK
MISO
DOUT
+3V TO +5V
edges and is guaranteed to be valid t
later and
DOT
MAX1332
MAX1333
remain valid until t
after the following SCꢀK rising
DHOꢀD
SS
edge. When using CPOꢀ = 0 and CPHA = 0 or CPOꢀ =
1 and CPHA = 1, the data is clocꢂed into the µC on the
following or next SCꢀK rising edge. When using CPOꢀ
= 0 and CPHA = 1 or CPOꢀ = 1 and CPHA = 0, the
data is clocꢂed into the µC on the next falling edge.
See Figure 11 for connections and Figures 12 and 13
for timing. See the Timing Characteristics table to deter-
mine the best mode to use.
a) SPI
CS
SCK
CNVST
SCLK
DOUT
MISO
+3V TO +5V
MAX1332
MAX1333
SS
QSPI
Unliꢂe SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows acquiring
the conversion data with a single 16-bit transfer. The
MAX1332/MAX1333 require 16 clocꢂ cycles from the
µC to clocꢂ out the 12 bits of data. Figure 14 shows a
transfer using CPOꢀ = 1 and CPHA = 1. The conver-
sion result contains three zeros, followed by the 12 data
bits and a trailing zero with the data in MSB-first format.
b) QSPI
I/O
SK
SI
CNVST
SCLK
DOUT
MAX1332
MAX1333
DSP Interface to the TMS320C54_
The MAX1332/MAX1333 can be directly connected to
the TMS320C54_ family of DSPs from Texas
Instruments. Set the DSP to generate its own clocꢂs or
use external clocꢂ signals. Use either the standard or
buffered serial port. Figure 15 shows the simplest inter-
face between the MAX1332/MAX1333 and the
TMS320C54_, where the transmit serial clocꢂ (CꢀKX)
drives the receive serial clocꢂ (CꢀKR) and SCꢀK, and
the transmit frame sync (FSX) drives the receive frame
sync (FSR) and CꢁVST.
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1332/MAX1333
down modes. The CꢁVST pin must idle high to remain
in either power-down state.
Another method of connecting the MAX1332/MAX1333
to the TMS320C54_ is to generate the clocꢂ signals
external to either device. This connection is shown in
Figure 16 where serial clocꢂ (CꢀOCK) drives the
receive serial clocꢂ (CꢀKR) and SCꢀK, and the convert
signal (COꢁVERT) drives the receive frame sync (FSR)
and CꢁVST.
For continuous conversion, set the serial port to trans-
mit a clocꢂ and pulse the frame sync signal for a clocꢂ
period before data transmission. Use the serial port
configuration (SPC) register to set up with internal
frame sync (TXM = 1), CꢀKX driven by an on-chip clocꢂ
source (MCM = 1), burst mode (FSM = 1), and 16-bit
word length (FO = 0).
The serial port must be set up to accept an external
receive clocꢂ and external receive frame sync. Write
the serial port configuration (SPC) register as follows:
• TXM = 0, external frame sync
This setup allows continuous conversions provided that
the data transmit register (DXR) and the data-receive
register (DRR) are serviced before the next conversion.
Alternately, autobuffering can be enabled when using
the buffered serial port to execute conversions and
• MCM = 0, CꢀKX is taꢂen from the CꢀKX pin
• FSM = 1, burst mode
• FO = 0, data transmitted/received as 16-bit words
read the data without µC intervention. Connect DV
to
DD
This setup allows continuous conversion provided that
the data-receive register (DRR) is serviced before the
next conversion. Alternately, autobuffering can be
the TMS320C54_ supply voltage. The word length can
be set to 8 bits with FO = 1 to implement the power-
______________________________________________________________________________________ 19
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
1
8
9
16
SCLK
DOUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1ST BYTE READ
2ND BYTE READ
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion
CNVST
1
13
14
16
1
SCLK
DOUT
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion
CNVST
1
2
16
SCLK
DOUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. QSPI Serial-Interface Timing
DV
DD
DV
DD
DV
DV
DD
DD
CLKX
CLKR
FSX
SCLK
CLKR
SCLK
TMS320C54x
TMS320C54x
FSR
DR
CNVST
DOUT
MAX1332
MAX1333
MAX1332
MAX1333
CNVST
FSR
CLOCK
CONVERT
DR
DOUT
Figure 16. Interfacing to the TMS320C54_ External Clocks
20 ______________________________________________________________________________________
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
SCLK
1
8
16
1
DOUT
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface—Continuous Conversion
CNVST
1
1
SCLK
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface—Single Conversion—Continuous/Burst Clock
enabled when using the buffered serial port to read the
high frame (ꢀTFS = 0, ꢀRFS = 0) signal. In this mode,
the data-independent frame-sync bit (DITFS = 1) can
be selected to eliminate the need for writing to the
transmit data register more than once. For single con-
versions, idle CꢁVST high and pulse it low for the entire
conversion. Configure the ADSP21_ _ _ STCTꢀ and
SRCTꢀ registers for late framing (ꢀAFR = 1) and for an
active-low frame (ꢀTFS = 1, ꢀRFS = 1) signal. This is
also the best way to enter the power-down modes by
setting the word length to 8 bits (SꢀEꢁ = 0111).
data without µC intervention. Connect DV
TMS320C54_ supply voltage.
to the
DD
The MAX1332/MAX1333 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CꢁVST and the transmit clocꢂ (CꢀKX) generated
internally to drive SCꢀK. A pullup resistor is required on
the CꢁVST signal to ꢂeep it high when DX goes high
impedance and write (0001)h to the data transmit regis-
ter (DXR) continuously for continuous conversions. The
power-down modes can be entered by writing (00FF)h
to the DXR (see Figures 17 and 18).
Connect the DV
pin to the ADSP21_ _ _ supply volt-
DD
age (see Figures 17 and 18).
Layout, Grounding, and Bypassing
DSP Interface to the ADSP21_ _ _
The MAX1332/MAX1333 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices.
Figure 19 shows the direct connection of the
MAX1332/MAX1333 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to inter-
face with the MAX1332/MAX1333. For continuous con-
versions, idle CꢁVST low and pulse it high for one
clocꢂ cycle during the ꢀSB of the previous transmitted
word. Configure the ADSP21_ _ _ STCTꢀ and SRCTꢀ
registers for early framing (ꢀAFR = 0) and for an active-
For best performance, use PC boards. Wire-wrap
boards must not be used. Board layout must ensure
that digital and analog signal lines are separated from
each other. Do not run analog and digital (especially
clocꢂ) lines parallel to one another, or digital lines
underneath the ADC pacꢂage.
Figure 20 shows the recommended system ground
connections. Establish an analog ground point at
AGꢁD and a digital ground point at DGꢁD. Connect all
other analog grounds to the analog ground point.
______________________________________________________________________________________ 21
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
DIGITAL
GROUND
POINT
ANALOG SUPPLY
RETURN
DIGITAL SUPPLY
RETURN DV
AV
DD
DD
ANALOG
GROUND
POINT
DV
VDDINT
TCLK
DD
SCLK
CNVST
DOUT
10Ω*
ADSP21_ _ _
RCLK
TFS
RFS
DR
MAX1332
MAX1333
AV
DD
DGND
AGND
DV
DGND
DV
DD
DD
DIGITAL
CIRCUITRY
DATA
MAX1332
MAX1333
*OPTIONAL
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20. Power-Supply Grounding Condition
Connect all digital grounds to the digital ground point.
For lowest noise operation, maꢂe the power supply
returns as low impedance and as short as possible.
Connect the analog ground point to the digital ground
point together at the IC.
the transfer function once offset and gain errors have
been nullified. Iꢁꢀ deviations are measured at every
step and the worst-case deviation is reported in the
electrical characteristics table.
Differential Nonlinearity (DNL)
Dꢁꢀ is the difference between an actual step width and
the ideal value of 1 ꢀSB. A Dꢁꢀ error specification of
less than 1 ꢀSB guarantees no missing codes and a
monotonic transfer function. For the MAX1332/
MAX1333, Dꢁꢀ deviations are measured at every step
and the worst-case deviation is reported in the electri-
cal characteristics table.
High-frequency noise in the power supplies degrades
the ADC’s performance. Bypass AV
to AGꢁD with
DD
0.1µF and 1µF bypass capacitors. ꢀiꢂewise, bypass
DV to DGꢁD with 0.1µF and 1µF bypass capacitors.
DD
Minimize capacitor lead lengths for best supply noise
rejection. To reduce the effects of supply noise, a 10Ω
resistor can be connected as a lowpass filter to attenu-
ate supply noise (see Figure 20).
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Typically, the point at which
the offset error is specified is at or near the zero-scale
of the transfer function or at or near the midscale of the
transfer function.
Exposed Paddle
The MAX1332/MAX1333 TQFꢁ pacꢂage has an exposed
paddle on the bottom of the pacꢂage, providing a very
low thermal resistance path for heat removal from the IC,
as well as a low-inductance path to ground. The pad is
electrically connected to AGꢁD on the MAX1332/
MAX1333 and must be soldered to the circuit board ana-
log ground plane for proper thermal and electrical perfor-
mance. Refer to the Maxim Application ꢁote HFAꢁ-08.1:
Thermal Considerations for QFN and Other Exposed Pad
Packages, for additional information.
For the MAX1332/MAX1333, operating with a unipolar
transfer function, the ideal zero-scale digital output
transition from 0x000 to 0x001 occurs at 0.5 ꢀSB above
AGꢁD. Unipolar offset error is the amount of deviation
between the measured zero-scale transition point and
the ideal zero-scale transition point.
Definitions
For the MAX1332/MAX1333, operating with a bipolar
transfer function, the ideal midscale digital output tran-
sition from 0xFFF to 0x000 occurs at 0.5 ꢀSB below
AGꢁD. Bipolar offset error is the amount of deviation
Integral Nonlinearity (INL)
Iꢁꢀ is the deviation of the values on an actual transfer
function from a straight line. For the MAX1332/
MAX1333, this straight line is between the end points of
22 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
tion error only and results directly from the ADC’s reso-
lution (ꢁ bits):
CNVST
SꢁR
= 6.02 x ꢁ + 1.76
dB dB
dB[max]
In reality, there are other noise sources such as thermal
noise, reference noise, and clocꢂ jitter that also
degrade SꢁR.
ANALOG
INPUT
t
AD
For the MAX1332/MAX1333, SꢁR is computed by taꢂ-
ing the ratio of the RMS signal to the RMS noise. RMS
noise includes all spectral components to the ꢁyquist
frequency excluding the fundamental, the first five har-
monics, and the DC offset.
t
AJ
SAMPLED
DATA (T/H)
TRACK
HOLD
TRACK
T/H
Signal-to-Noise Plus Distortion (SINAD)
SIꢁAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance.
Figure 21. T/H Aperture Timing
SIꢁAD is computed by taꢂing the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
ꢁyquist frequency excluding the fundamental and the
DC offset:
between the measured midscale transition point and
the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1332/
MAX1333, the gain error is the difference of the mea-
sured full-scale and zero-scale transition points minus
the difference of the ideal full-scale and zero-scale
transition points.
⎡
⎢
⎣
⎤
⎥
⎦
SIGꢁAꢀ
(ꢁOISE+DISTORTIOꢁ)
RMS
SIꢁAD(dB) = 20×log
RMS
Effective Number of Bits (ENOB)
EꢁOB specifies the global accuracy of an ADC at a spe-
cific input frequency and sampling rate. An ideal ADC’s
error consists of quantization noise only. EꢁOB for a full-
scale sinusoidal input waveform is computed from:
For the unipolar input, the full-scale transition point is
from 0xFFE to 0xFFF and the zero-scale transition point
if from 0x000 to 0x001.
For the bipolar input, the full-scale transition point is
from 0x7FE to 0x7FF and the zero-scale transition point
is from 0x800 to 0x801.
SIꢁAD−1.76
EꢁOB=
6.02
Aperture Jitter
Total Harmonic Distortion (THD)
THD is a dynamic figure of merit that indicates how much
harmonic distortion the converter adds to the signal.
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the aperture delay.
Aperture Delay
THD is the ratio of the RMS sum of the first five harmon-
ics of the fundamental signal to the fundamental itself.
This is expressed as:
Aperture delay (t ) is the time defined between the
AD
falling edge of the CꢁVST and the instant when an
actual sample is taꢂen (Figure 21).
⎛
⎞
⎟
2
2
2
2
2
Signal-to-Noise Ratio (SNR)
SꢁR is a dynamic figure of merit that indicates the con-
verter’s noise performance.
V2 + V3 + V4 + V5 + V6
⎜
THD = 20×log
V1
⎜
⎟
⎠
⎝
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SꢁR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
where V is the fundamental amplitude, and V through
6
harmonics.
1
2
V
are the amplitudes of the 2nd- through 6th-order
______________________________________________________________________________________ 23
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
then swept up to the point where the amplitude of the
Spurious-Free Dynamic Range (SFDR)
SFDR is a dynamic figure of merit that indicates the
lowest usable input signal amplitude. SFDR is the ratio
of the RMS amplitude of the fundamental (maximum
signal component) to the RMS value of the next-largest
spurious component, excluding DC offset. SFDR is
specified in decibels relative to the carrier (dBc).
digitized conversion result has decreased by -3dB.
Power-Supply Rejection (PSR)
PSR is defined as the shift in offset error when the ana-
log power supply is moved from 2.7V to 3.6V.
Pin Configuration
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation
products to the ꢁyquist frequency relative to the total
TOP VIEW
input power of the two input tones f
and f . The
Iꢁ2
Iꢁ1
individual input tone levels are at -7dBFS. The inter-
modulation products are as follows:
• 2nd-order intermodulation products (IM2): f
+
DV
DD 13
Iꢁ1
8
7
6
5
AGND
BIP/UNI
SHDN
REF
f
, f
- f
Iꢁ2 Iꢁ2 Iꢁ1
DGND
14
15
• 3rd-order intermodulation products (IM3): 2f
-
Iꢁ1
Iꢁ1
Iꢁ1
MAX1332
MAX1333
f
, 2f
- f , 2f
Iꢁ2 Iꢁ1
+ f , 2f
+ f
Iꢁ2 Iꢁ1
Iꢁ2
Iꢁ1
Iꢁ2
AV
DD
• 4th-order intermodulation products (IM4): 3f
, 3f - f , 3f + f , 3f + f
-
f
Iꢁ2
Iꢁ2 Iꢁ1
Iꢁ1
Iꢁ2
Iꢁ2
Iꢁ1
AGND 16
• 5th-order intermodulation products (IM5): 3f
2f , 3f - 2f , 3f + 2f , 3f + 2f
-
Iꢁ2
Iꢁ2
Iꢁ1
Iꢁ1
Iꢁ2
Iꢁ2
Iꢁ1
Channel-to-Channel Isolation
Channel-to-channel isolation is a figure of merit that
indicates how well each analog input is isolated from
the others. The channel-to-channel isolation for the
MAX1332/MAX1333 is measured by applying a low-fre-
quency 500ꢂHz -0.5dBFS sine wave to the on channel
while a high-frequency 900ꢂHz -0.5dBFS sine wave is
applied to the off channel. An FFT is taꢂen for the on
channel. From the FFT data, channel-to-channel
crosstalꢂ is expressed in dB as the power ratio of the
500ꢂHz low-frequency signal applied to the on channel
and the 900ꢂHz high-frequency crosstalꢂ signal from
the off channel.
Selector Guide
AV
(V)
MAX SAMPLING RATE
(Msps)
DD
PART
MAX1332ETE
MAX1333ETE
+5
+3
3
2
Full-Power Bandwidth
A large -0.5dB FS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
Chip Information
PROCESS: BiCMOS
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the sig-
nal-to-noise plus distortion (SIꢁAD) is equal to 68dB.
The amplitude of the analog input signal is -0.5dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
24 ______________________________________________________________________________________
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
Package Information
(The pacꢂage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢂage outline information,
go to www.maxim-ic.com/packages.)
D2
b
0.10 M
C
A
B
D
D2/2
D/2
E/2
E2/2
(NE - 1)
X e
C
E2
E
L
L
k
e
C
L
(ND - 1)
X e
C
L
C
L
0.10
C
0.08 C
A
A2
A1
L
L
e
e
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
1
21-0136
E
2
PKG
12L 3x3
16L 3x3
NOM.
0.75
REF. MIN. NOM.
MAX.
0.80
MIN.
0.70
MAX.
EXPOSED PAD VARIATIONS
DOWN
BONDS
ALLOWED
0.70
0.75
0.80
A
b
D2
E2
PKG.
PIN ID
JEDEC
CODES
MIN. NOM. MAX. MIN. NOM. MAX.
0.20
2.90
2.90
0.25
3.00
0.30
3.10
3.10
0.20
2.90
2.90
0.25
3.00
3.00
0.30
3.10
3.10
T1233-1
T1233-3
T1633-1
T1633-2
T1633F-3
T1633-4
0.95
0.95
0.95
0.95
0.65
0.95
1.10
1.10
1.10
1.10
0.80
1.10
1.25
1.25
1.25
1.25
0.95
1.25
0.95
0.95
0.95
0.95
0.65
0.95
1.10
1.10
1.10
1.10
0.80
1.10
1.25
1.25
1.25
1.25
0.95
1.25
0.35 x 45∞ WEED-1
0.35 x 45∞ WEED-1
0.35 x 45∞ WEED-2
0.35 x 45∞ WEED-2
0.225 x 45∞ WEED-2
0.35 x 45∞ WEED-2
NO
YES
NO
D
E
e
L
3.00
0.50 BSC.
0.55
0.50 BSC.
0.40
0.45
0.65
0.30
0.50
YES
N/A
NO
N
12
3
16
4
ND
NE
3
4
A1
A2
k
0
0.02
0.05
-
0
0.02
0.05
-
0.20 REF
-
0.20 REF
-
0.25
0.25
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
2
21-0136
E
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2005 Maxim Integrated Products
Printed USA
is a registered trademarꢂ of Maxim Integrated Products, Inc.
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