MAX1454AUE/V+ [MAXIM]
Analog Circuit, 1 Func, BICMOS, PDSO16, ROHS COMPLIANT, TSSOP-16;
| 型号： | MAX1454AUE/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, BICMOS, PDSO16, ROHS COMPLIANT, TSSOP-16 信息通信管理 光电二极管 |
| 文件： | 总25页 (文件大小：1102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
19-5945 Rev 0; 6/11
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
General Description
Benefits and Features
The MAX1454 is a highly integrated analog sensor
signal conditioner targeted for automotive applications.
The device provides amplification, calibration, and tem-
perature compensation to enable an overall performance
approaching the inherent repeatability of the sensor. The
fully analog signal path introduces no quantization noise
in the output signal while enabling digitally controlled
trimming of the output. Offset and span are calibrated
with integrated 16-bit DACs, allowing sensors to be truly
interchangeable.
S Complete Signal Conditioning in a Single IC
Package
Provides Amplification, Calibration, and
Temperature Compensation
Accommodates Sensor Output Sensitivities
from 1mV/V to 200mV/V
Overvoltage Protection to 45V
Reverse-Voltage Protection to 45V
S High-Precision Compensation Reduces
Downstream Circuit Complexity
The device architecture includes a programmable sen-
sor excitation, a 32-step programmable-gain amplifier
(PGA), a 2K x 8 bits internal flash memory, four 16-bit
DACs, and an on-chip temperature sensor. In addition
to offset and span compensation, the device provides a
unique temperature-compensation method for offset TC
and FSO TC to provide a remarkable degree of flexibility
while minimizing manufacturing costs.
Fully Analog Signal Path
16-Bit Offset and Span-Calibration Resolution
On-Chip Lookup Table Supports Multipoint
Calibration Temperature Correction
S Supports Both Current and Voltage-Bridge
Excitation
S Fast 85µs Step Response
S Sensor Fault Detection
The device is packaged in a 16-pin TSSOP and covers
the automotive AEC-Q100 Grade 1 temperature range of
-40NC to +125NC.
S Simple PCB Layout
S Single-Pin Digital Programming
S No External Trim Components Required
Applications
Pressure Sensors
Strain Gauges
Pressure Calibrators and Controllers
Resistive Element Sensors
Humidity Sensors
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX1454.related.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
Operating Temperature Range........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) .............................. +300NC
Soldering Temperature (reflow) ......................................+260NC
V
, V
............................................................-0.3V to +3.0V
DD DDF
V
.......................................................................-45V to +45V
DDX
All Other Pins............................. -0.3V to Min (V
+ 0.3V, 6V)
DDX
Continuous Power Dissipation (T = +70NC)
A
16-Pin TSSOP (derate 11.1mW/NC above +70NC) ...888.9mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (q ) ..........90NC/W
JA
Junction-to-Case Thermal Resistance (q )...............27NC/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= 5V, V
= 0V, T = +25NC, unless otherwise noted.) (Note 2)
DDX
GND A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
External Supply Voltage
External Supply Current
Oscillator Frequency
V
3.0
5.0
2.5
1
5.5
3
V
DDX
DDX
OSC
I
(Note 3)
mA
MHz
f
0.85
1.15
Not to be loaded by external circuitry, must
be connected to a 0.1FF capacitor to GND
LDO Regulator Output Voltage
Power-On-Reset Threshold
V
2.375
2.5
2.4
2.625
V
V
DD
V
Referred to V pin
DDX
POR
External Supply Voltage-Ramp
Rate
(Note 4)
1
V/ms
ANALOG INPUT
Input Impedance
R
IN
1
MI
Input-Referred Offset-
Temperature Coefficient
(Notes 5, 6)
Q1
FV/NC
Input-Referred Adjustable-
Offset Range
Offset TC = 0 at gain = 44 (Note 7)
-150
+150
mV
%
Percent of 4V span, no load, IRO[3:0] =
0000bin, source impedance = 5kI, V
OUT
Nonlinearity of Signal Path
0.01
90
= 0.5V to 4.5V; measured at V
2.5V, 4.5V] at a gain of 112
= [0.5V,
OUT
Common-Mode Rejection
Ratio
Specified for common-mode voltages
CMRR
dB
between GND and V
DDX
Input-Referred Adjustable FSO
(Note 8)
1
200
mV/V
Maxim Integrated
2
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
= 5V, V
= 0V, T = +25NC, unless otherwise noted.) (Note 2)
DDX
GND A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG OUTPUT
Selectable in 32 steps
6 to 2048
6
PGA[4:0] = 00000bin
PGA[4:0] = 00101bin
PGA[4:0] = 01010bin
PGA[4:0] = 01100bin
PGA[4:0] = 01101bin
PGA[4:0] = 01110bin
PGA[4:0] = 01111bin
PGA[4:0] = 10000bin
PGA[4:0] = 10110bin
PGA[4:0] = 11100bin
PGA[4:0] = 11111bin
5.5
12.5
40
6.5
15.5
48
14
44
58
64
70
72
80
88
Differential Signal Gain
V/V
86
96
106
123
158
458
1267
2253
101
130
374
1037
1823
112
144
416
1152
2048
V
+
V
-
GND
0.02
DDX
0.32
Output-Voltage Swing
Output-Voltage Low
Output-Voltage High
No load
V
V
V
I
I
= 1mA sinking, T = T
to T
MAX
0.25
OUT
A
MIN
V
-
DDX
0.55
= 1mA sourcing, T = T
to T
MAX
OUT
A
MIN
Output Current Drive
Capability
Maintain DC output to 2mV error compared
to no load case (Note 4)
Q1
mA
Output Source Current Limit
Output Sink Current Limit
Output Impedance at DC
8
mA
mA
I
-8
V
= 2.5V
0.2
85
OUT
DV
/
OUT
Output Offset Ratio
0.9
0.9
1.2
1.2
V/V
V/V
DOffset DAC
DV
/
OUT
Output Offset TC Ratio
DOffset TC DAC
Step Response
(63% Final Value)
Fs
FF
Maximum Capacitive Load
0.01
0.5
1.5
3
Gain = 36
Gain = 256
Gain = 512
Gain = 1024
Gain = 2048
DC to 1kHz, source
impedance = 5kI
Noise at Output Pin
mV
RMS
6
12
Maxim Integrated
3
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
= 5V, V
= 0V, T = +25NC, unless otherwise noted.) (Note 2)
DDX
GND A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BRIDGE DRIVE
Bridge Current
I
0.1
4.8
9.6
14.4
24
2.5
7.2
mA
BDR
AA
CMRATIO[1:0] = 00
6
CMRATIO[1:0] = 01
CMRATIO[1:0] = 10
CMRATIO[1:0] = 11
12
18
30
14.4
21.6
36
Current-Mirror Ratio
A/A
Maximum Bridge Load
Capacitance
Voltage excitation mode (Note 4)
1
nF
Hex
V
FSO DAC Code Range
(Note 4)
(Note 4)
0x4000
0.75
0xC000
V
DDX
-
Output Voltage Range
V
BDR
0.75
DIGITAL-TO-ANALOG CONVERTERS (DACs)
DAC Resolution
16
76
38
76
38
Bits
Offset DAC Bit Weight
Offset TC DAC Bit Weight
FSO DAC Bit Weight
DV
DV
DV
DV
/DCode DAC reference = V
/DCode DAC reference = V
/DCode DAC reference = V
/DCode DAC reference = V
= 5V
FV/bit
FV/bit
FV/bit
FV/bit
OUT
OUT
BDR
BDR
DDX
BDR
DDX
BDR
= 2.5V
= 5V
FSO TC DAC Bit Weight
COARSE-OFFSET DAC
IRO DAC Resolution
= 2.5V
Including sign
5
Bits
Input referred, DAC reference = V
(Note 9)
= 5V
DDX
IRO DAC Bit Weight
DV
/DCode
3.7
mV/bit
OUT
INTERNAL RESISTORS
OUT/DIO Pullup Resistance
R
100
10
kI
kI
PULLUP
Current Source Reference
Resistor
R
ISRC
Current Source Reference
Resistor Temperature
Coefficient
TCR
600
ppm/NC
ISRC
FLASH MEMORY
Endurance
(Notes 4, 10)
10,000
10
Cycles
Years
ms
Retention
T = +85NC (Note 4)
A
Page Erase Time
Mass Erase Time
(Notes 4, 11)
(Notes 4, 11)
32
32
ms
Maxim Integrated
4
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
= 5V, V
= 0V, T = +25NC, unless otherwise noted.) (Note 2)
DDX
GND A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mA
Operating Current
(Note 4)
(Note 4)
8
7
Program/Erase Current
mA
TEMPERATURE-TO-DIGITAL CONVERTER
Temperature ADC Resolution
Offset
8
Bits
LSB
NC/Bit
LSB
hex
Q3
Gain
1.5
Nonlinearity
Q0.5
0x00
0xAF
Lowest Digital Output
Highest Digital Output
DIGITAL INPUT (OUT/DIO)
hex
Input Low Voltage
V
0
V
/3
V
V
IL
DDX
V
x
DDX
2/3
Input High Voltage
V
IH
V
DDX
OVERVOLTAGE PROTECTION
Overvoltage-Protection
Threshold
5.53
5.75
6.0
V
FAULT DETECTION
IN+/IN- Low Comparator
Threshold
0.2 x
V
V
V
BDR
IN+/IN- High Comparator
Threshold
0.8 x
V
BDR
Detection-Threshold Accuracy
Comparator Hysteresis
Q25
mV
mV
20
Output Clip Level During Fault
Conditions
I
= 1mA sinking
150
250
mV
OUT
Note 2: All units are production tested at T = +25NC and +125NC. Specifications over temperature are guaranteed by design.
A
Note 3: Excludes sensor or load current. Analog mode with voltage excitation on BDR pin, FSODAC = 0x8000.
Note 4: Specification is guaranteed by design.
Note 5: All electronics temperature errors are compensated together with sensor errors.
Note 6: The sensor and the device must be at the same temperature during calibration and use.
Note 7: This is the maximum allowable sensor offset.
Note 8: This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of V
- 1V and a
DDX
nominal bridge voltage of V
/2.
DDX
Note 9: Bit weight is ratiometric to V
.
DDX
Note 10: Programming of the flash memory at room temperature is recommended.
Note 11: No commands can be executed until the erase operation has completed. During erase operations, all commands sent to
the device are ignored.
Maxim Integrated
5
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
(VA = 5V, T = +25NC, unless otherwise noted.)
DD
A
16-BIT DAC DIFFERENTIAL
NONLINEARITY
OUTPUT NOISE
IRO DAC DIFFERENTIAL NONLINEARITY
20
15
10
5
10
8
0.5
0.4
V
= V = GND, C = 10nF, NO LOAD
IN-
PGA GAIN = 44V/V
IN+
36V/V GAIN SETTTING
6
0.3
4
0.2
2
0.1
0
0
0
-2
-4
-6
-8
-10
-0.1
-0.2
-0.3
-0.4
-0.5
-5
-10
-15
-20
0
100
200
300
400
500
0
16,384
32,768
49,152
65,536
0
5
10
IRO DAC CODE
15
TIME (ms)
16-BIT DAC CODE
SIGNAL-PATH GAIN DEVIATION
vs. TEMPERATURE
OUTPUT VOLTAGE vs. INPUT
SIGNAL FREQUENCY
SIGNAL-PATH NONLINEARITY
0.10
0.08
0.06
0.04
0.02
0
0.50
0.40
0.30
0.20
0.10
0
3
0
SPAN = 4V
OUTPUT VOLTAGES NORMALIZED TO DC
256V/V
6V/V
256V/V
-3
-6
-0.02
-0.04
-0.06
-0.08
-0.10
-0.10
-0.20
-0.30
-0.40
-0.50
44V/V
6V/V
44V/V
-9
1024V/V
-12
-15
20mV SINE-WAVE INPUT SIGNAL,
P-P
PGA GAIN = 52V/V, 112V/V, 208V/V
1024V/V
0
15
2.5
3.5
4.5
-50 -25
0
25
50
75 100 125
100
1k
10k
OUT/DIO VOLTAGE (V)
TEMPERATURE (°C)
INPUT SIGNAL FREQUENCY (Hz)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(FAULT DETECTION ENABLED)
STEP RESPONSE
(VARIOUS GAIN SETTINGS)
MAX1454 toc07
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 2.5V,
1kHz SQUARE
WAVE
BDR
OUTPUT PROGRAMMED TO 2.5V
6V/V
256V/V, 1024V/V
44V/V
OUTPUT CLIP LEVEL
OUT/DIO
1V/div
0
0.5
1.0
1.5
= V (V)
2.0
2.5
100µs/div
V
IN+
IN-
Maxim Integrated
6
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Pin Configuration
TOP VIEW
+
1
16
N.C.
N.C.
GND
IN+
N.C.
V
DDX
2
3
15
14
V
V
DD
MAX1454
4
5
6
7
8
13
12
11
10
9
DDF
BDR
IN-
OUT/DIO
I.C.
I.C.
I.C.
N.C.
GND
TSSOP
Pin Description
PIN
NAME
N.C.
FUNCTION
1, 2, 8, 16
No Connection. Not internally connected.
Ground
3, 9
GND
IN+
4
Positive Bridge Input. IN+ can be swapped to IN- by Configuration Register 1.
Bridge Drive
5
BDR
6
7, 10, 11
12
IN-
Negative Bridge Input. IN- can be swapped to IN+ by Configuration Register 1.
Internally Connected. Connect I.C. to GND.
I.C.
OUT/DIO
Analog Output and Digital I/O (Multiplexed)
13
V
Flash Memory Supply Voltage. Connect V
to V
.
DDF
DDF
DD
14
V
Regulated Supply Voltage. Requires a 0.1FF capacitor from V
to GND.
DD
DD
15
V
DDX
External Supply Voltage. Bypass to GND with a 0.1FF capacitor.
Maxim Integrated
7
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
customer can retest to verify performance as part of a
Detailed Description
regular QA audit, or to generate final test data on indi-
vidual sensors.
The MAX1454 is a highly integrated analog sensor
signal conditioner targeted for automotive applications.
The device provides amplification, calibration, and tem-
perature compensation to enable an overall performance
approaching the inherent repeatability of the sensor. The
fully analog signal path introduces no quantization noise
in the output signal while enabling digitally controlled cal-
ibration of offset and span with integrated 16-bit DACs,
allowing sensors to be truly interchangeable.
The device (Figure 1) provides an analog amplifica-
tion path for the sensor signal. It also uses an analog
architecture for 1st-order temperature correction. A
digitally controlled analog path is then used for nonlin-
ear temperature correction. Calibration and correction
is achieved by varying the offset and gain of a PGA,
and by varying the sensor bridge excitation current or
voltage. The PGA utilizes a switched-capacitor CMOS
The device architecture includes a programmable sen-
sor excitation, a 32-step PGA, a 2K x 8 bits internal flash
memory, four 16-bit DACs, and an on-chip temperature
sensor. In addition to offset and span compensation, the
device provides a unique temperature-compensation
method for offset TC and FSO TC, which was developed
to provide a remarkable degree of flexibility while minimiz-
ing manufacturing costs.
V
DDX
OVERVOLTAGE,
UNDERVOLTAGE, AND
REVERSE-VOLTAGE
PROTECTION
V
V
DDX
DD
LDO
MAX1454
OUT
V
DDX
The device uses four 16-bit DACs (offset, FSO, offset TC,
and FSO TC) with coefficients ranging from 0x0000 to
0xFFFF. The offset DAC and FSO DAC are referenced to
IRO
DAC
V
(76FV resolution when V
DAC and FSO TC DAC are referenced to the bridge volt-
= 5V). The offset TC
DDX
DDX
IN+
IN-
OUT/DIO
PGA
C
age (38FV resolution when bridge voltage is 2.5V).
The user can select from one to 110 temperature points
to compensate their sensor. This allows the latitude
to compensate a sensor with a simple 1st-order linear
correction or to match an unusual temperature curve.
Programming up to 110 independent 16-bit flash mem-
ory locations corrects performance in 1.5NC temperature
increments, over a range of -40NC to +125NC. For sensors
that exhibit a characteristic temperature performance,
a select number of calibration points can be used with
a number of preset values that define the temperature
curve. For full temperature compensation, the sensor and
the device must be at the same temperature. In cases
where the sensor is at a different temperature than the
device, the device can use the sensor excitation voltage
to provide 1st-order temperature compensation.
5V DIO
FAULT
DETECTION
BDR
CURRENT
SOURCE
TEMP
SENSOR
8-BIT
ADC
DIGITAL
INTERFACE
AND
FLASH
MEMORY
V
DDF
The single-pin, multiplexed, serial digital input/output
(DIO) communication architecture, and the ability to time-
share its activity with the sensor’s output signal, enables
output sensing and calibration programming on a single
line.
V
V
BDR
DDX
GND
The device allows complete calibration and sensor veri-
fication to be performed at a single test station. Once
calibration coefficients have been stored in the device, the
Figure 1. Functional Diagram
Maxim Integrated
8
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
technology, with an input-referred offset-trimming range
of more than Q150mV. The PGA provides gain values
trim from the table with one 16-bit value at every 1.5NC,
from -40NC to +125NC.
from 6V/V to 2048V/V in 32 steps.
Linear and Nonlinear
Temperature Compensation
The device includes an internal 2K x 8-bit flash memory
to store calibration coefficients and user data. The inter-
nal memory contains the following information as 16-bit-
wide words:
In most applications, the device and the sensor are at
the same temperature, and coefficients in the offset and
FSO lookup table correct both linear and nonlinear tem-
perature errors to an accuracy approaching the sensor’s
repeatability error. In these applications, the offset TC
DAC and FSO TC DACs should be set to nominal values.
U Configuration Register 1 (CONFIG1)
U Configuration Register 2 (CONFIG2)
U Offset calibration coefficient (ODAC) table
U Offset Temperature Coefficient register (OTCDAC)
In applications where the sensor and the device are at
different temperatures, the FSO and offset DAC lookup
tables cannot be used. Writing 16-bit calibration coef-
ficients into the offset TC and FSO TC registers compen-
sates 1st-order temperature errors. The piezoresistive
sensor is powered by a current source, resulting in a
temperature-dependent bridge voltage due to the sen-
sor’s temperature coefficient of resistance (TCR). The ref-
erence inputs of the offset TC DAC and FSO TC DAC are
connected to the bridge voltage, causing their outputs
to change as a function of temperature. When properly
programmed, they provide 1st-order temperature com-
pensation of the input signal. Only two test temperatures
are required for linear temperature compensation.
U Full-span output calibration coefficient (FSODAC)
table
U FSO Temperature Coefficient register (FSOTCDAC)
U Power-Up Configuration register (PWRUPCFG)
U 256 bytes (2048 bits) uncommitted for customer pro-
gramming of manufacturing data (e.g., serial number
and date)
Offset Correction
Initial offset correction is accomplished at the input
stage of the signal-gain amplifiers by a coarse offset set-
ting. Final offset correction occurs through the use of a
temperature-indexed lookup table with 176 16-bit entries.
The on-chip temperature sensor provides a unique 16-bit
offset-trim value from the table with an indexing resolu-
tion of approximately 1.5NC, from -40NC to +125NC. Every
4ms (programmable through the CONFIG2 register), the
on-chip temperature sensor provides indexing into the
offset lookup table in flash memory, with the resulting
value transferred to the offset DAC register. The result-
ing voltage is fed into a summing junction at the PGA
output, compensating the sensor offset with a resolution
of Q76FV (Q0.0019% FSO). If the offset TC DAC is set
to zero, then the maximum temperature error is typically
one degree of temperature drift of the sensor, given the
offset DAC has corrected the sensor at every 1.5NC.
The device uses a 10kI internal feedback resistor
(R
ISRC
) for FSO temperature compensation. Since the
required feedback resistor value is sensor dependent, the
device offers the ability to adjust the current-mirror ratio
(CMRATIO) of the bridge driver. By selecting one of four
CMRATIO settings in the CONFIG1 register, the bridge
driver’s feedback loop can be optimized for silicon piezo-
resistive sensors typically ranging from 2kIto 10kI.
Internal Temperature Sensor/ADC
The signal conditioner uses an internal temperature sen-
sor to generate an 8-bit temperature index. An ADC con-
verts the integrated temperature-sensor output to an 8-bit
value every 4ms (programmable through the CONFIG2
register). This digitized value is then transferred into the
temperature index register.
FSO Correction
Two functional blocks control the FSO gain calibration.
First, a coarse gain is set by digitally selecting the gain
of the PGA. Second, FSO DAC (and FSO TC DAC in
current excitation mode) sets the sensor bridge current
or voltage with the digital input obtained from the flash
memory. FSO correction occurs through the use of a
temperature-indexed lookup table with 176 16-bit entries.
The on-chip temperature sensor provides a unique FSO
The typical transfer function for the temperature index is
as follows:
TEMPINDEX = 0.6561 x temperature (NC) + 53.6
where TEMPINDEX is truncated to an 8-bit integer value.
Typical values for the temperature index register are
given in Table 13.
Maxim Integrated
9
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
This index determines which FSO and offset DAC
U The internal temperature sensor stores the 8-bit
settings get loaded from the flash memory. The
temperature-indexing boundaries are outside of the
specified Absolute Maximum Ratings to eliminate index-
ing wrap-around errors. The minimum indexing value
is 0x00, corresponding to approximately -82NC. All
temperatures below this value generate the index 0x00.
The maximum indexing value is 0xAF, corresponding
to approximately +185NC. All temperatures higher than
+185NC generate the index 0xAF.
TEMPINDEX value.
U Registers CONFIG1, CONFIG2, ODAC, FSODAC,
OTCDAC, and FSOTCDAC are loaded from flash
memory.
U After each time the DAC refresh timer reaches its set
time period, the internal-temperature ADC updates the
8-bit TEMPINDEX value and the ODAC and FSODAC
registers are refreshed from the temperature-indexed
flash memory locations.
Overvoltage, Undervoltage,
Reverse-Voltage Protection
Calibration Operation
(Registers Updated by Serial Communications)
U Power is applied to the device.
Overvoltage protection shuts down the device when the
supply voltage is typically above 5.75V. A power-on reset
prevents erroneous operation with supply voltages below
2.4V. Reverse voltage protects the device from negative
voltages due to transients, reverse battery, etc. These
protections allow the device to withstand any supply volt-
age from -45V to +45V.
U The power-on-reset functions have completed.
U The digital listening mode detects serial communication.
U The registers can then be loaded from the serial
digital interface by use of serial commands. See the
Serial-Interface Command Format section.
Sensor Fault Detection
When enabled, the fault-detection circuitry on the device
detects faults on the sensor inputs (IN+ and IN-). If either
one of the sensor inputs is below the input low threshold
U (Optionally) After calibration, the device can be set to
run in fixed analog operation using a software com-
mand. Note that the configuration and DAC registers
refresh from flash memory upon entering fixed analog
mode.
(20% of V
) or above the input high threshold (80% of
BDR
V
), a fault signal is asserted internally. If the part is in
BDR
Internal Flash Memory
The internal flash memory is organized as a 2K by 8-bit
memory. It is divided into four pages with 512 bytes
per page. Each page can be individually erased. The
memory structure is arranged as shown in Table 1. The
lookup tables for ODAC and FSODAC are also shown,
with the respective TEMPINDEX pointer. The ODAC table
occupies a segment from address 0x000 to address
0x15F, and the FSODAC table occupies a segment from
0x200 to 0x35F.
analog mode, the internal fault signal causes the voltage
on the OUT/DIO pin to clip to a fixed DC level (typically
150mV). Enable or disable fault detection through the
CONFIG2 register, bit 6 (ENFDET).
Internal Calibration Registers (ICRs)
The device has six 16-bit ICRs (ODAC, FSODAC,
OTCDAC, FSOTCDAC, CONFIG1, and CONFIG2) that
are loaded from flash memory, or loaded from the serial
digital interface when in the digital programming mode.
Data can be loaded into the ICRs under two different
modes of operations (fixed analog operation and calibra-
tion operation).
The flash memory is configured as an 8-bit wide array so
each of the 16-bit registers is stored as two 8-bit quanti-
ties. The configuration registers and the FSOTCDAC
and OTCDAC registers are loaded from the preassigned
locations in the flash memory. The ODAC and FSODAC
registers are loaded from memory lookup tables using an
index pointer that is a function of temperature.
Fixed Analog Operation
U The device has been calibrated.
U Power is applied to the device.
U The power-on-reset functions have completed.
Maxim programs all flash memory locations to 0xFF,
except for the reserved locations, 0x400 and 0x401.
Values stored at 0x400 and 0x401 should be kept at the
factory-programmed defaults.
U The digital listening mode times out and the device
goes into the fixed analog mode.
Maxim Integrated
10
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 1. Flash Memory Address Map
LOW-BYTE
ADDRESS (hex)
HIGH-BYTE
ADDRESS (hex)
TEMPINDEX[7:0]
(hex)
PAGE
CONTENTS
000
002
:
001
003
:
00
01
:
AE
ODAC lookup table
15C
15E
160
162
164
166
168
16A
16C
16E
:
15D
15F
161
163
165
167
169
16B
16D
16F
:
AF to FF
—
CONFIG1
CONFIG2
Reserved
OTCDAC
—
—
—
0
—
Reserved
FSOTCDAC
PWRUPCFG
—
—
—
—
Reserved
17E
180
:
17F
181
:
128 general-purpose user bytes
1FE
200
202
:
1FF
201
203
:
00
01
:
FSODAC lookup table
Reserved
35C
35E
360
:
35D
35F
361
:
AE
AF to FF
1
—
—
37E
380
:
37F
381
:
128 general-purpose user bytes
Reserved*
3FE
400
402
:
3FF
401
403
:
2
3
—
—
Reserved
5FE
600
:
5FF
601
:
Reserved
7FE
7FF
*Do not change values stored at locations 0x400 and 0x401 from the factory defaults.
Maxim Integrated
11
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
where:
Communications Protocol
The DIO serial interface is used for asynchronous serial
data communications between the device and a host
calibration test system. The device automatically detects
the baud rate of the host computer when the host trans-
mits the initialization sequence. Baud rates between
4800bps and 38,400bps can be detected and used
regardless of the internal oscillator frequency setting.
Data format is always 1 start bit, 8 data bits, 1 stop bit,
and no parity. Communications are only allowed when
the device is in digital mode.
IRSA[3:0] is the 4-bit interface register set address
and indicates which register receives the data nibble
IRSD[3:0];
IRSA[0] is the first bit on the serial interface after the
start bit;
IRSD[3:0] is the 4-bit interface register set data;
IRSD[0] is the 5th bit received on the serial interface
after the start bit
The IRSA address decoding is shown in Table 14.
Initialization Sequence
Sending the initialization sequence shown below enables
the device to establish the baud rate that initializes the
serial port. The initialization sequence is 1 byte transmis-
sion of 01hex, as follows: 1111111101000000011111111.
The first start bit 0 initiates the baud-rate synchronization
sequence. The 8 data bits 01hex (LSB first) follow this
and then the stop bit, which is indicated above as a
1, terminates the baud-rate synchronization sequence.
This initialization sequence on OUT/DIO should occur
after a period of 2ms after stable power is applied to the
device. This allows time for the power-on-reset function
to complete.
Special Command Sequences
A special command register to internal logic (CRIL[3:0])
causes execution of special command sequences within
the device. These command sequences are listed as
CRIL command codes, as shown in Table 15.
Write Examples
A 16-bit write to any of the internal calibration registers is
performed as follows:
1) Write the 16 data bits to DHR[15:0] using 4 byte
accesses into the interface register set.
2) Write the address of the target internal calibration
register to ICRA[3:0].
Serial-Interface Command Format
All communication commands into the device follow a
defined format utilizing an interface register set (IRS).
The IRS is an 8-bit command that contains both an
interface register set data (IRSD) nibble (4 bits) and an
interface register set address (IRSA) nibble (4 bits). All
internal calibration registers and flash memory locations
are accessed for read and write through this interface
register set. The IRS byte command is structured as
follows:
3) Write the load internal calibration register (LdICR)
command to CRIL[3:0]. When a LdICR command is
issued to the CRIL register, the calibration register
loaded depends on the address in the internal cali-
bration register address (ICRA). Table 16 specifies
which calibration register is decoded.
IRS[7:0] = IRSD[3:0], IRSA[3:0]
THREE-STATE
NEED WEAK
PULLUP*
THREE-STATE
NEED WEAK
PULLUP*
DRIVEN BY TESTER
1 1
DRIVEN BY MAX1454
OUT/DIO
0
1 1 1 1 1
0
1
0
0
0
1
1 1 1 1
1 1 1 1
0
0
0
0
0
1
0 0 0
1 1 1 1 1 1 1 1 1
*PROGRMMABLE DELAY DETERMINED BY READDLY SETTING.
Figure 2. OUT/DIO Output Data Format
Maxim Integrated
12
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
The data returned on an RdIRS command depends on
the address in IRSP. Table 17 defines what is returned
for the various addresses.
Erasing and Writing the Flash Memory
The internal flash memory needs to be erased (bytes set
to FFhex) prior to programming the desired contents.
When an RdAlg command is written to CRIL[3:0] the
analog signal designated by ALOC[4:0] is asserted on
the OUT/DIO pin. The duration of the analog signal is
determined by ATIM[3:0], after which the pin reverts to a
digital I/O. The host computer or calibration system must
three-state its connection to OUT/DIO after asserting the
stop bit. Do not load the OUT/DIO line when reading
nonbuffered internal signals.
The internal flash memory can be entirely erased with the
ERASE command, or partially erased with the PageErase
command (see Table 15). It is necessary to wait 32ms
after issuing the ERASE or PageErase command before
sending the next command.
After the memory has been erased (value of every byte
= FFhex), the user can program its contents using the
following procedure:
The analog output sequence is shown in Figure 3. The
digital serial interface and analog output are internally
multiplexed onto OUT/DIO. The duration of the analog
signal is controlled by ATIM[3:0], as given in Table 18.
1) Write the 8 data bits to DHR[7:0] using 2 byte accesses
into the interface register set.
2) Write the address of the target internal memory loca-
tion to IEEA[10:0] using 3 byte accesses into the
interface register set.
The analog signal driven onto the OUT/DIO pin is deter-
mined by the value in the ALOC register. The signals are
specified in Table 19.
3) Write the flash memory write command (EEPW) to
CRIL[3:0].
Burst Mode Operation
The device supports burst mode operation for reading/
writing blocks of data from/to flash memory addresses
0x000 to 0x3FF. Addresses 0x400 and 0x401 cannot be
accessed with burst mode. First, program the starting
address of the flash memory into IEEA[10:0]. Next, enable
burst mode by writing a 1 to the burst mode enable bit
(BURSTEN). In burst mode, an internal counter is used
to increment the memory address with every read/write
operation. With the 0-to-1 transition of BURSTEN, the
memory address stored in IEEA[10:0] is latched into the
internal counter as the starting address. Once the burst
enable is high, the internal counter takes precedence
over the memory address bits. All the memory read/
write operations happen on the address indicated by the
internal counter.
Caution: It is not recommended to change values of flash
memory locations 0x400 and 0x401. Changing the values
at these locations (through a memory write or page/total
erasure) can cause the device to lose its factory trim set-
tings, which can affect device performance.
Multiplexed Analog and
Serial Digital Output
When an RdIRS command is written to CRIL[3:0], OUT/
DIO is configured as a digital output and the contents
of the register designated by IRSP[3:0] are sent out as
a byte framed by a start bit. Once the tester finishes
sending the RdIRS command, it must three-state its
connection to OUT/DIO to allow the device to drive the
OUT/DIO line. The device three-states OUT/DIO high for
a programmable number of byte times (determined by
READDLY[1:0]) and then sends out the data byte (with
a start and stop bit). The sequence is shown in Figure 2.
ATIM
THREE-STATE
NEED WEAK
PULLUP
2
+1 BYTE
THREE-STATE
NEED WEAK
PULLUP
TIMES
DRIVEN BY TESTER
OUT/DIO
0
1 1 1 1 1
0
1
0
0
1 1
0
1
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
VALID OUT
Figure 3. Analog Output Timing
Maxim Integrated
13
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
To write to a flash memory location in burst mode, the
an internal read; the device sends the contents of the
flash memory out of the DIO/OUT pin through the serial
interface. Similar to the burst write operation, the burst
read operation does not skip memory locations. To skip
memory locations, first write a zero to BURSTEN to end
burst mode. Next, change the memory address bits
using the corresponding command bytes. Once the
desired starting address is loaded, reenable burst mode
to resume burst reading.
user simply writes DHR[3:0], followed by DHR[7:4].
Since the internal counter keeps track of the memory
address, there is no need to send address information
to the part. After DHR[7:4] is written, a write command
to the flash memory is automatically generated, the data
in DHR[7:0] is written to the memory, and the address
counter is incremented. If the user wishes to skip certain
memory locations, first exit burst mode (by writing a 0 to
BURSTEN), then program a new starting address. The
user can now reenable burst mode again.
Always disable burst mode (IRSD = 0000 when IRSA =
1101) after burst reading/writing all the locations. This is
necessary to continue in digital programming mode after
all the burst read/writes are complete.
During burst read operations, the device waits for a
read command before sending out data whose address
is derived from the internal counter. To start burst read
mode, first program the flash memory address into
IEEA[10:0]. Next, write a 1 to BURSTEN to enable burst
mode. The IRSP register must then be programmed
to 0 (through an IRSA = 8 command). Then, send the
flash memory read (RdEEP) CRIL command to initiate
Note: Use burst mode to program a maximum of 1024
locations. Care must be taken to avoid additional writes
to prevent unintentionally rewriting locations. The internal
address counter wraps around to address 0x000 after
reaching address 0x3FF.
Register Map
Table 2. Registers
REGISTER
DESCRIPTION
CONFIG1
CONFIG2
ODAC
Configuration Register 1
Configuration Register 2
Offset DAC
OTCDAC
FSODAC
FSOTCDAC
PWRUPCFG
Offset Temperature Coefficient DAC
Full-Span Output DAC
Full-Span Output Temperature Coefficient DAC
Power-Up Configuration
Table 3. Configuration Register 1 (CONFIG1[15:0])
BIT
15:11
10
9
NAME
PGA[4:0]
DESCRIPTION
Programmable-gain amplifier setting
Logic 1 inverts IN- and IN+ polarity
PGA Sign
IRO Sign
Logic 1 for positive input-referred offset (IRO), logic 0 for negative input-referred offset (IRO)
Input-referred coarse-offset adjustment
8:5
4:3
2
IRO[3:0]
CMRATIO[1:0]
Reserved
Bridge driver current-mirror ratio
Set to logic 0
1
ODAC Sign
OTCDAC Sign
Logic 1 for positive offset DAC output, logic 0 for negative offset DAC output
Logic 1 for positive offset TC DAC output, logic 0 for negative offset TC DAC output
0
Maxim Integrated
14
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 4. Configuration Register 2 (CONFIG2[15:0])
BIT
15:7
6
NAME
Reserved
DESCRIPTION
Reserved. Set to logic 0.
ENFDET
Enable fault-detection circuitry. Logic 1 enables fault detection.
DAC register refresh rate during fixed analog mode
5:4
3
REFRATE[1:0]
ENPULLUP
READDLY[1:0]
EXCIMODE
Enable internal pullup resistor on OUT/DIO pin. Logic 1 enables pullup.
Number of byte times the part waits before responding to read requests
Logic 1 for voltage excitation mode, logic 0 for current excitation mode
2:1
0
Table 5. Power-Up Configuration Register (PWRUPCFG[15:0])
BIT
15:7
6:3
NAME
Reserved
DESCRIPTION
Reserved. Set to logic 0.
DIGMODETIME[3:0]
CTRLREP[2:0]
Number of ms the part waits to receive a control word before switching to analog mode
Number of repetitions of the control word required to switch the part into digital mode
2:0
Table 6. PGA Setting (PGA[4:0])
PGA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
PGA GAIN (V/V)
PGA[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
PGA GAIN (V/V)
144
6
7
176
9
208
11
12
14
18
22
28
36
44
52
64
80
96
112
256
288
352
416
512
576
704
832
1024
1152
1408
1664
2048
Maxim Integrated
15
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 7. Input-Referred Offset Setting (IRO Sign, IRO[3:0])
INPUT-
REFERRED
OFFSET
INPUT-REFERRED
OFFSET
CORRECTION
INPUT-REFERRED
OFFSET
CORRECTION
INPUT-REFERRED
OFFSET
CORRECTION
IRO SIGN IRO[3:0]
IRO SIGN IRO[3:0]
CORRECTION
AT V
= 5V DC
AT V
= 5V DC
DDX
DDX
AS % OF V
DDX
AS % OF V
(mV)
(mV)
DDX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
1.11
1.04
0.96
0.89
0.81
0.74
0.67
0.59
0.52
0.44
0.37
0.30
0.22
0.15
0.07
0
55.5
51.8
48.1
44.4
40.7
37
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
0
-0.07
-0.15
-0.22
-0.30
-0.37
-0.44
-0.52
-0.59
-0.67
-0.74
-0.81
-0.89
-0.96
-1.04
-1.11
-3.7
-7.4
-11.1
-14.8
-18.5
-22.2
-25.9
-29.6
-33.3
-37
33.3
29.6
25.9
22.2
18.5
14.8
11.1
7.4
-40.7
-44.4
-48.1
-51.8
-55.5
3.7
0
Table 8. Bridge Driver Current-Mirror
Ratio Setting (CMRATIO[1:0])
Table 9. DAC Refresh Rate
(REFRATE[1:0])
REFRATE[1:0]
UPDATE INTERVAL (ms)
CURRENT-
MIRROR RATIO
BRIDGE
RESISTANCE (kI)
CMRATIO[1:0]
00
01
10
11
4.096
16.384
65.536
131.072
00
01
10
11
6
10
5
12
18
30
3.33
2
Table 10. Wait Time for Read Requests (READDLY[1:0])*
READDLY[1:0]
RESPONSE DELAY IN BYTE TIMES (8-BIT TIME)
00
01
10
11
1 byte time (i.e., (1 x 8)/baud rate)
2 byte times
4 byte times
8 byte times
*The selected delay time is applied before and after the requested byte is read.
Maxim Integrated
16
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 11. DIGMODETIME Setting*
(DIGMODETIME[3:0] )
Table 12. CTRLREP Setting
(CTRLREP[2:0])
CTRLREP[2:0]
DESCRIPTION
DIGMODETIME[3:0]
DESCRIPTION
000
001
010
011
100
101
110
111
1 control word expected
1 control word expected
2 control words expected
3 control words expected
4 control words expected
5 control words expected
6 control words expected
Part powers up in digital mode*
Part stays in digital mode for 1ms
after power-up (for each repetition of
the control word)
0000
0001
0010
2ms wait
3ms wait
0011
4ms wait
0100
5ms wait
0101
8ms wait
0110
10ms wait
15ms wait
20ms wait
25ms wait
30ms wait**
*Parts ship with a CTRLREP setting of 111.
0111
Table 13. Temperature Index Typical Values
1000
1001
TEMPERATURE
TEMPINDEX[7:0]
1010 to 1111
(NC)
-40
DECIMAL
HEXADECIMAL
*Wait times specified are based on a typical oscillator fre-
quency of 1MHz. Wait times are proportional to the oscillation
frequency. Actual wait times depend on the factory-trimmed
oscillator frequency.
27
70
1B
46
6D
88
+25
+85
+125
109
136
**Parts ship with a DIGMODETIME setting of 1111.
Table 14. IRSA Decoding (IRSA[3:0])
IRSA[3:0]
DESCRIPTION
0000
0001
0010
0011
0100
0101
Write IRSD[3:0] to DHR[3:0] (data hold register).
Write IRSD[3:0] to DHR[7:4] (data hold register).
Write IRSD[3:0] to DHR[11:8] (data hold register).
Write IRSD[3:0] to DHR[15:12] (data hold register).
Reserved.
Reserved.
Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (internal calibration register address or internal flash memory
address nibble 0).
0110
0111
1000
1001
1010
1011
1100
Write IRSD[3:0] to IEEA[7:4] (internal flash memory address nibble 1).
Write IRSD[3:0] to IRSP[3:0] or IEEA[10:8] (interface register set pointer where IRSP[2:0] is IEEA[10:8]).
Write IRSD[3:0] to CRIL[3:0] (command register to internal logic).
Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read).
Write IRSD[3:0] to ALOC[3:0] (analog location).
Write IRSD[0] to ALOC[4] (analog location).
Write IRSD[0] to the burst mode enable bit (BURSTEN). See the Burst Mode Operation section for details
regarding read/write operations in this mode. Logic 1 enables burst mode.
1101
1100 to 1111
Reserved.
Maxim Integrated
17
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 15. CRIL Command Codes (CRIL[3:0])
CRIL[3:0]
0000
NAME
LdlCR
EEPW
ERASE
RdICR
RdEEP
DESCRIPTION
Load internal calibration register at address given in ICRA with data from DHR[15:0].
Flash memory write of 8 data bits from DHR[7:0] to address location pointed by IEEA[10:0].
Erase all flash memory (all bytes equal FFhex).
0001
0010
0011
Read internal calibration register as pointed to by ICRA and load data into DHR[15:0].
Read internal flash memory location pointed by IEEA[10:0] and load data into DHR[7:0].
0100
Read interface register set pointer IRSP[3:0] and output the multiplexed digital signal onto
OUT/DIO (see Table 17).
0101
RdIRS
Output the multiplexed analog signal (i.e., test mux output) onto OUT/DIO. The duration (in
byte times) that the signal is asserted onto the pin is specified by ATIM[3:0] (Table 18) and
the analog location is specified by ALOC[4:0] (Table 19).
0110
RdAlg
0111
1000
PageErase
SwToANA
Reserved
RELEARN
Erases the page of the flash memory as pointed by IEEA[10:9]. There are 512 bytes per page.
Switch to fixed analog mode.
Reserved.
1001 to 1110
1111
Relearn the baud rate.
Table 16. ICRA Decoding (ICRA[3:0])
IRCA[3:0]
0000
NAME
CONFIG1
CONFIG2
ODAC
DESCRIPTION
Configuration Register 1
Configuration Register 2
Offset DAC
0001
0010
0011
OTCDAC
FSODAC
FSOTCDAC
PWRUPCFG
Reserved
Offset Temperature Coefficient DAC
Full-Span Output DAC
0100
0101
Full-Span Output Temperature Coefficient DAC
Power-Up Configuration
0110
0111 to 1111
Reserved (do not write to these locations)
Table 17. IRSP Decoding (IRSP[3:0])
IRSP[3:0]
0000
RETURNED VALUE
IRSP[3:0]
0110
RETURNED VALUE
IEED[7:0] flash memory data byte
TEMPINDEX[7:0]
DHR[7:0]
0001
DHR[15:8]
0111
0010
0bin, IEEA[10:8], ICRA[3:0] concatenated
CRIL[3:0], IRSP[3:0] concatenated
0000bin, ATIM[3:0] concatenated
1000
BitClock[7:0]
0011
1001
00bin, BURSTEN, ALOC[4:0] concatenated
Reserved
0100
1010 to 1110
11001010 (CAhex) (this can be used to test
communication)
0101
IEEA[7:0] flash memory address byte
1111
Maxim Integrated
18
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Table 18. ATIM Definition (ATIM[3:0])
DURATION OF ANALOG SIGNAL SPECIFIED
IN BYTE TIMES (8-BIT TIME)
DURATION OF ANALOG SIGNAL
SPECIFIED IN BYTE TIMES (8-BIT TIME)
ATIM[3:0]
ATIM[3:0]
0000
0001
0010
0011
0100
0101
20 + 1 = 2 byte times (i.e., (2 x 8)/baud rate)
21+ 1 = 3 byte times
0111
1000
27 + 1 = 129 byte times
28 + 1 = 257 byte times
29 + 1 = 513 byte times
210 + 1 = 1025 byte times
211 + 1 = 2049 byte times
212 + 1 = 4097 byte times
213 + 1 = 8193 byte times
214 + 1 = 16,385 byte times
22 + 1 = 5 byte times
1001
23+ 1 = 9 byte times
1010
24 + 1 = 17 byte times
1011
25 + 1 = 33 byte times
1100
1101
0110
26 + 1 = 65 byte times
1110 or 1111
Table 19. ALOC Definition (ALOC[4:0])
ALOC[4:0]
BUFFERED OUTPUTS
00000
NAME
DESCRIPTION
OUT
PGA output
00001
BDR1
Bridge drive voltage
00010
V
Bridge drive current-setting voltage (see the Detailed Block Diagram)
ISRC
00011
V
Internal regulated supply
DD
00100
AGND
Internal analog ground; approximately 1/2 of V
DD
00101
V
Full-scale output plus full-scale output TC DAC (see the Detailed Block Diagram)
Offset DAC (see the Detailed Block Diagram)
Offset TC DAC (see the Detailed Block Diagram)
Bandgap voltage reference (nominally 1.25V)
Reserved
DUALDAC
00110
V
ODAC
00111
V
OTCDAC
01000
V
REF
01001
Reserved
Reserved
REFD3BUF
Reserved
Reserved
IN+
01010
Reserved
01011
Ratiometric reference; approximately 1/3 of V
Reserved
DDX
01100
01101
Reserved
01110
Sensor’s positive input
Sensor’s negative input
01111
IN-
NONBUFFERED OUTPUTS
10000
10001
BDR2
Bridge drive voltage
Internal positive supply
Internal ground
V
DDI
10010
GND
10011 to 11101
Reserved
Reserved
SPECIAL-PURPOSE OUTPUTS
11110
11111
CLIPLVL
Hi-Z
Output clip level during fault conditions (buffered output)
High-impedance state on OUT/DIO
Maxim Integrated
19
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
POWER-ON
POWER-ON RESET LOADS VALUES
FROM FLASH MEMORY.
SERIAL COMMUNICATION READY
AFTER 2ms
NO
YES
CTRLREP = 0x7?
NO
SET DIGITAL MODE TIMEOUT
COUNTER AND CONTROL WORD
REPETITION COUNTER BASED ON
PWRUPCFG REGISTER SETTING
NO
NO
NO
NO
YES
INITIALIZATION
BYTE RECEIVED?
INITIALIZATION
BYTE RECEIVED?
DECREMENT DIGITAL MODE
TIMEOUT COUNTER
TIMEOUT
COUNTER = 0?
YES
YES
SYNCHRONIZE BAUD RATE FROM
INITIALIZATION BYTE
SYNCHRONIZE BAUD RATE FROM
INITIALIZATION BYTE
RESET DIGITAL MODE TIMEOUT
COUNTER BASED ON
DIGMODETIME SETTING
NO
NO
NO
YES
CONTROL WORD
RECEIVED? (0xAD)
DECREMENT DIGITAL MODE
TIMEOUT COUNTER
TIMEOUT
COUNTER = 0?
YES
DECREMENT CONTROL WORD
REPETITION COUNTER
NO
REPETITION
COUNTER = 0?
YES
DEVICE ENTERS DIGITAL
PROGRAMMING MODE
NO
COMMAND BYTE
RECEIVED?
YES
NO
YES
COMMAND
BYTE = 0x89?
DEVICE ENTERS FIXED
ANALOG MODE
EXECUTE COMMAND
Figure 4. Power-Up Flow Chart
Maxim Integrated
20
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
DAC based on sensor parameters (offset, sensitivity,
bridge resistance, etc). Select a current-mirror ratio value
corresponding to the sensor in use. Initialization is an
important step to ensure that the device output remains
in range over the full operating conditions. When the
device is initialized successfully, the excitation voltage is
within the normal range, and the output voltage is around
the desired offset value (when zero pressure is applied).
Power-Up Control Sequence
The device uses a power-up state machine to determine
whether the device should switch to the fixed analog
mode, or enable the digital programming mode (Figure 4).
At power-up, the device loads the PWRUPCFG register to
establish a wait time (Table 11), and the number of control
words (Table 12) required to enter the digital program-
ming mode. If the wait time expires, the device automati-
cally switches to the fixed analog mode. However, if the
interface receives the correct number of control words
within the established wait times, the device enters the
digital programming mode. A serial command enables the
device to switch into the fixed analog mode after the part
has been programmed.
Characterize the Sensor at Test Temperatures
1) Set the temperature to the first test temperature point
and allow the system to reach equilibrium.
2) By changing the FSO DAC through an iterative pro-
cess, set the bridge voltage to a value that produces
the desired output span. Change the offset DAC as
necessary.
Note: Setting CTRLREP[2:0] to 111 in the PWRUPCFG
flash memory location forces the part into the digital pro-
gramming mode without the need for control words (an
initialization byte is still required). By default, parts shipped
from the factory are programmed to start in the digital
programming mode.
3) Once the desired output span is achieved, change
the offset DAC to produce the final offset.
4) Record the values of TEMPINDEX, FSODAC, and
ODAC. The device flash memory can be used to store
the information.
Sensor Compensation Overview
The device compensates for sensor offset, FSO, and
temperature errors by loading the internal calibra-
tion registers with the compensation values. These
compensation values can be loaded to registers directly
through the serial digital interface during calibration, or
loaded automatically from flash memory at power-on.
During the calibration process, the device is configured,
tested, and compensation values are calculated and
stored in the internal flash memory. Once programmed,
after each power-up, the device autoloads the registers
from flash memory and is ready for use without further
configuration.
5) Change the temperature to the next value and repeat
this procedure to determine a unique value for the
TEMPINDEX, FSODAC, and ODAC at every test tem-
perature.
Calculate Compensation Coefficients
1) FSO Lookup Table: Using a fitting function, fit the
FSODAC and TEMPINDEX values obtained during the
characterization step and generate an array of 176
elements (FSODAC vs. TEMPINDEX array, where 0 ≤
TEMPINDEX ≤ 175).
2) Offset Lookup Table: Using a fitting function, fit the
ODAC and TEMPINDEX values obtained during the
characterization step and generate an array of 176
elements (ODAC vs. TEMPINDEX array).
Program Flash Memory and Final Test
1) Program the device by writing to the ODAC
and FSODAC lookup tables, and the OTCDAC,
FSOTCDAC, CONFIG1, CONFIG2, PWRUPCFG, and
user data locations in flash memory.
Compensation requires an examination of the sensor per-
formance over the operating pressure and temperature
range. A minimum of two test temperatures and two test
pressures (zero and full scale) are required to correct the
linear component of temperature error to achieve pres-
sure calibration. For higher temperature accuracy, more
test temperatures must be used. A typical compensation
procedure can be summarized in the following sections.
2) While the sensor is still at the last test temperature
point, perform a final test to verify the compensation
accuracy.
Initialize the Device
Initialize the device registers with known values (e.g.,
compensation coefficients of a similar device) or deter-
mine values for IRO, PGA gain, FSO DAC, and offset
Maxim Integrated
21
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
U 0.1FF output capacitor (V
)
DD
Applications Information
U Optional output capacitor (OUT/DIO)
Typical Ratiometric Operating Circuit
Ratiometric output configuration provides an output that is
proportional to the power-supply voltage. This output can
then be applied to a ratiometric ADC to produce a digital
value independent of supply voltage. Ratiometricity is an
important consideration for battery-operated instruments,
automotive, and some industrial applications.
Typical Nonratiometric Operating Circuit
(6V DC < V
< 40V DC)
PWR
Nonratiometric output configuration enables the sensor
power to vary over a wide range. A high-performance
voltage reference, such as the MAX15006B, is incorpo-
rated in the circuit to provide a stable supply and refer-
ence for device operation. A typical nonratiometric circuit
is shown in Figure 6. Nonratiometric operation is valuable
when a wide range of input voltage is to be expected
and the system ADC or readout device does not enable
ratiometric operation.
The device provides a high-performance ratiometric output
with a minimum number of external components (Figure 5).
These external components include the following:
U Supply bypass capacitor (V
)
DDX
+5V
15
V
DDX
5
6
14
13
BDR
IN-
V
DD
V
DDF
MAX1454
4
12
OUT/DIO
IN+
OUT/DIO
0.1µF
0.1µF
0.01µF
GND
9
GND
Figure 5. Basic Ratiometric Output Configuration
MAX15006B
8
1
V
PWR
OUT
IN
+6V TO +40V
2N4392
15
5
14
GND
5
V
DDX
BDR
IN-
V
DD
6
4
13
12
V
DDF
MAX1454
OUT/DIO
IN+
OUT/DIO
GND
0.1µF
2.2µF
0.1µF
0.01µF
GND
9
Figure 6. Basic Nonratiometric Output Configuration
Maxim Integrated
22
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Detailed Block Diagram
V
DDX
V
DD
LDO
OVERVOLTAGE,
UNDERVOLTAGE,
AND REVERSE-
VOLTAGE
FLASH MEMORY
(LOOKUP PLUS CONFIGURATION DATA)
FLASH
USAGE
PROTECTION
ADDRESS
0x000 + 0x001
OFFSET DAC LOOKUP TABLE
(176 x 16 BITS)
:
1/3
0x15E + 0x15F
0x160 + 0x161 CONFIGURATION REGISTER 1
0x162 + 0x163 CONFIGURATION REGISTER 2
0x164 + 0x165 RESERVED
V
DDX
1/3 V
DDX
BDR
BDR
16
16
V
DUALDAC
FSO
DAC
C
6x, 12x, 18x,
OR 30x
CURRENT
MIRROR
0x166 + 0x167 OFFSET TC REGISTER
0x168 + 0x169 RESERVED
1/3 V
0x16A + 0x16B FSO TC REGISTER
0x16C + 0x16D POWER-UP CONFIG REGISTER
0x16E + 0x16F
FSO TC
DAC
-1/2
CURRENT
MODE
V
DDF
:
RESERVED
CURRENT
MODE
1/3 V
0x17E + 0x17F
0x180 + 0x181
:
16 + SIGN
V
V
OTCDAC
OFFSET TC
DAC
CURRENT
MODE
USER STORAGE
(128 BYTES)
50kI
0x1FE + 0x1FF
0x200 + 0x201
:
V
ISRC
1/3 V
FSO DAC LOOKUP TABLE
(176 x 16 BITS)
DDX
R
ISRC
16 + SIGN
10kI
0x35E + 0x35F
0x360 + 0x361
:
ODAC
OFFSET
DAC
VOLTAGE
MODE
C
RESERVED
GND
0x37E + 0x37F
0x380 + 0x381
:
1/3
USER STORAGE
(128 BYTES)
0x3FE + 0x3FF
0x400 + 0x401
:
BANDGAP
TEMP
SENSOR
TEMP ADC
RESERVED
0x7FE + 0x7FF
8
DIO
BDR
FAULT
DETECTION
IN-
5V DIO
DRIVER
3
DIGITAL INTERFACE
OUT/DIO
OUT/DIO
MUX
PHASE
REVERSAL
MUX
OUT
C
C
IN+
GND
PROGRAMMABLE GAIN STAGE
INPUT-REFERRED OFFSET (COARSE OFFSET)
IRO SIGN, IRO[3:0] OFFSET (mV) IRO SIGN, IRO[3:0] OFFSET (mV)
PGA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
PGA GAIN (V/V)
PGA[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
PGA GAIN (V/V)
144
1, 1111
1, 1110
1, 1101
1, 1100
1, 1011
1, 1010
1, 1001
1, 1000
1, 0111
1, 0110
1, 0101
1, 0100
1, 0011
1, 0010
1, 0001
1, 0000
55.5
51.8
48.1
44.4
40.7
37.0
33.3
29.6
25.9
22.2
18.5
14.8
11.1
7.4
0, 0000
0, 0001
0, 0010
0, 0011
0, 0100
0, 0101
0, 0110
0, 0111
0, 1000
0, 1001
0, 1010
0, 1011
0, 1100
0, 1101
0, 1110
0, 1111
0
6
7
-3.7
176
-7.4
9
208
-11.1
-14.8
-18.5
-22.2
-25.9
-29.6
-33.3
-37.0
-40.7
-44.4
-48.1
-51.8
-55.5
11
12
14
18
22
28
36
44
52
64
80
96
112
256
288
352
416
512
576
704
832
1024
1152
1408
1664
2048
3.7
0
Maxim Integrated
23
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
Ordering Information
PACKAGE PACKAGE
LAND PATTERN
NO.
OUTLINE NO.
21-0066
PART
TEMP RANGE
PIN-PACKAGE
TYPE
CODE
MAX1454AUE/V+
-40NC to +125NC
16 TSSOP
16 TSSOP
U16M+1
90-0117
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Maxim Integrated
24
MAX1454
Precision Sensor Signal Conditioner
with Overvoltage Protection
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
6/11
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
25
©
2012 Maxim Integrated
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
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