MAX14723ATP+T [MAXIM]
High-Accuracy, Adjustable Power Limiter;
| 型号： | MAX14723ATP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Accuracy, Adjustable Power Limiter |
| 文件： | 总20页 (文件大小：825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
General Description
Benefits and Features
The MAX14721–MAX14723 adjustable overvoltage,
undervoltage, and overcurrent protection devices guard
systems against overcurrent faults in addition to positive
overvoltage and reverse-voltage faults. When used with
an optional external p-channel MOSFET, the devices also
protect downstream circuitry from voltage faults up to
+60V, -60V (for -60V external pFET rating). The devices
feature a low, 76mΩ, on-resistance integrated FET.
During startup, the devices are designed to charge large
capacitances on the output in a continuous mode for
applications where large reservoir capacitors are used
on the inputs to downstream devices. Additionally, the
MAX14721–MAX14723 feature a dual-stage, current-limit
mode in which the current is continuously limited to 1x,
1.5x, and 2x the programmed limit, respectively, for a
short time after startup. This enables faster charging of
large loads during startup.
● Robust, High-Power Protection Reduces System
Downtime
• Wide Input Supply Range: +5.5V to +60V
• Programmable Input Supply Overvoltage Setting
Up to 40V
• Thermal Foldback Current-Limit Protection
• Negative Input Tolerance to -60V (for -60V External
pFET Rating)
• Low 76mΩ (typ) R
ON
• Reverse Current-Blocking Protection with External
pFET
● Enables Safer Startup By Preventing Overheating
of FETs
• Dual-Stage Current Limiting
• 1.0x Startup Current (MAX14721)
• 1.5x Startup Current (MAX14722)
• 2.0x Startup Current (MAX14723)
The MAX14721–MAX14723 also feature reverse-current
and overtemperature protection. The devices are available
in a 20-pin (5mm x 5mm) TQFN package and operate
over a -40°C to 125°C temperature range.
Applications
Industrial Power Systems
Control and Automation
Motion System Drives
Human Machine Interfaces
● Flexible Design Enables Reuse and Less
Requalification
• Adjustable OVLO and UVLO Thresholds
• Programmable Forward Current Limit From 0.2A
to 2A with ±15% Accuracy Over Full Temperature
Range
• Normal and High-Voltage Enable Inputs
(EN and HVEN)
• Protected External pFET Gate Drive
High-Power Applications
● Saves Board Space and Reduces External BOM
Count
• 20-Pin, 5mm x 5mm TQFN Package
• Integrated nFET
Ordering Information appears at end of data sheet.
Typical Application Circuit
VIN
*R1, R2, R3, AND R4 ARE ONLY
REQURED FOR ADJUSTABLE UVLO/
OVLO FUNCTIONALITY. OTHERWISE,
CIN
C
IN_C
TIE THE PIN TO GND TO USE THE
GP
IN
IN IN
INTERNAL, PREPROGRAMMED
VIN
THRESHOLD.
R1*
R3*
OUT
OUT
OUT
SYSTEM
UVLO
OVLO
POWER
CONTROLLER
PROTECTED
POWER
220kΩ
R2*
R4*
SYSTEM
INPUT
ADC
MAX14721–
MAX14723
COUT
VIN
HVEN
SETI
RIPEN
FLAG
EN
GND
ENB
FAULT
EN
HVEN
x
CLTS2
10kΩ
CLTS1
GND
19-7370; Rev 3; 11/17
MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Absolute Maximum Ratings
(All voltages referenced to GND.)
SETI................................................-0.3V to min(V + 0.3V, 6V)
IN
IN (Note 1)..........................................................-0.3V to +60.5V
Continuous Power Dissipation (T = +70°C)
A
OUT..............................................................-0.3V to V + 0.3V
TQFN (derate 31.3mW/ºC above +70°C)..................2500mW
Operating Temperature Range......................... -40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
IN
HVEN (Note 1) .............................................-0.3V to V + 0.3V
IN
GP .....................................max (-0.3V, V - 20V) to V + 0.3V
IN
IN
UVLO, OVLO...............................-0.3V to min (V + 0.3V, 20V)
IN
FLAG, EN, RIPEN, CLTS1, CLTS2.........................-0.3V to +6V
Maximum Current into IN (DC) (Note 2) .................................2A
Note 1: An external pFET or diode is required to achieve negative input protection.
Note 2: DC current-limited by R as well as by thermal design.
SETI
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 20 TQFN
Package Code
T2055+3C
21-0140
90-0008
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
32°C/W
3°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 2
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Electrical Characteristics
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C.) (Note 3)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
IN Voltage Range
V
5.5
60
15
V
IN
V
V
V
V
= 0V, V
= 0V, V
= 5V, V < 40V
5.25
5.25
1.4
EN
HVEN
IN
Shutdown IN Current
I
µA
SHDN
= 5V
150
1.9
100
EN
HVEN
Supply Current
I
= V
= 24V, V = 0V
HVEN
mA
µA
IN
IN
OUT
Shutdown OUT Current
UVLO, OVLO
I
= 0V, V = 5V
HVEN
50
OFF
EN
V
V
falling, UVLO trip point
rising
11.5
11.9
12
12.4
3
12.5
13
IN
Internal UVLO Trip Level
UVLO Hysteresis
V
V
%
V
UVLO
IN
% of typical UVLO
V
V
falling
32.1
34.5
33.8
36
35.6
37.4
IN
Internal OVLO Trip Level
V
OVLO
rising, OVLO trip point
IN
OVLO Hysteresis
% of typical OVLO
6
%
V
External UVLO Adjustment
Range (Note 4)
5.5
24
0.5
External UVLO Select Voltage
V
0.15
-250
0.38
V
UVLO_SEL
External UVLO Leakage
Current
I
+250
nA
UVLO_LEAK
External OVLO Adjustment
Range (Note 4)
6
40
0.5
V
V
External OVLO Select Voltage
V
0.15
-250
0.38
1.22
OVLO_SEL
External OVLO Leakage
Current
I
+250
nA
OVLO_LEAK
External UVLO/OVLO Set
Voltage
V
1.18
1.27
V
V
SET
V
V
falling, UVLO trip point
11.5
11.9
12
12.5
13
OUT
Undervoltage Trip Level on OUT
V
UVLO_OUT
rising
12.4
OUT
GP
Gate Clamp Voltage
Gate Active Pullup
Gate Active Pulldown
Shutdown Gate Active Pullup
V
10
50
16.1
25
20
50
V
Ω
GP
V
V
= 5V
110
2.2
µA
MΩ
EN
= 0V, V
= 5V
EN
HVEN
Maxim Integrated
│ 3
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Electrical Characteristics (continued)
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C.) (Note 3)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL FETs
I
T
= 100mA, V ≥ 10V,
IN
= +25ºC
LOAD
Internal FETs On-Resistance
Current Limit Adjustment Range
R
76
101
mΩ
ON
A
I
0.2
-10
-15
2
A
LIM
0.3A ≤ I
0.2A ≤ I
≤ 2A (T = +25°C)
+10
+15
LIM
A
Current Limit Accuracy
I
%
LIM_ACC
≤ 2A
LIM
FLAG Assertion Drop Voltage
Threshold
Increase in (V - V
FLAG asserts, V = 24V
IN
) drop until
IN
OUT
V
480
-9
mV
mV
FA
Reverse Current-Blocking
Threshold
V
V
- V
OUT
-4
-14
1.55
3900
RIB
IN
(V - V
) changes from 0.2V to
IN
OUT
Reverse Current-Blocking
Response Time
-0.3V in 100nsec, t
is the interval
RIB
t
1
µs
RIB
between V = V
and V
=
IN
OUT
IN-GP
0.5V without capacitive load on GP
Reverse-Blocking Supply
Current
I
V
= 24V
2000
µA
RBS
OUT
LOGIC INPUT (HVEN, CLTS1, CLTS2, EN, RIPEN)
HVEN Threshold Voltage
HVEN Threshold Hysteresis
HVEN Input Leakage Current
V
1
2
5
3.1
67
V
%
HVEN _TH
I
V
= 60V
46
µA
HVEN_LEAK
HVEN
EN, RIPEN, CLTS1, CLTS2
Input Logic-High
V
1.4
V
V
IH
EN, RIPEN, CLTS1, CLTS2
Input Logic-Low
V
0.4
+1
IL
EN Input Leakage Current
RIPEN Leakage Current
I
V
= 0V, 5V
EN
-1
µA
EN_LEAK
I
RIPEN = GND
CLTS_ = GND
25
25
µA
µA
RIPEN_LEAK
CLTS_ Leakage Current
LOGIC OUTPUT (FLAG)
Logic-Low Voltage
Input Leakage Current
SETI
I
= 1mA
0.4
1
V
SINK
V
= 5.5V, FLAG deasserted
µA
IN
R
x I
V
1.5
V
See Setting the Current-Limit
Threshold section
SETI
LIM
RI
Current Mirror Output Ratio
C
8333
IRATIO
Maxim Integrated
│ 4
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Electrical Characteristics (continued)
(V = 5.5V to 60V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 24V, T = +25°C.) (Note 3)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE (NOTE 5)
V
= 24V, switch OFF to ON, R
IN
LOAD
Switch Turn-On Time
t
= 240Ω, I
= 1A, C = 4.7µF,
118
420
µs
µs
ON
LIM
OUT
V
from 20% to 80% of V
IN
OUT
Fault Recovery nFET Turn-on
Time
V
> V
, turn-on delay
OUT
UVLO_OUT
t
730
ON_NFET
after fault timers expired
Reverse-Current Fault
Recovery Time
t
t
2.18
2.40
3
2.64
ms
µs
µs
REV_REC
OVP_RES
OCP_RES
OVP Switch Response Time
Overcurrent Switch Response
time
t
I
= 2A
3
LIM
Initial start current-limit foldback
timeout (Figure 1)
Startup Timeout
t
1090
21.8
0.25
1200
24
1320
26.4
0.75
ms
ms
ms
STO
Current is continuously limited to
1x/1.5x/2x in this interval (Figure 1)
Startup Initial Time
IN Debounce Time
t
STI
Interval between V > V
and
IN
UVLO
t
0.50
DEB
V
= 10% of V (Figure 2)
IN
OUT
Blanking Time
t
(Figure 3 and Figure 4)
(Figure 3, Note 6)
21.8
554
24
26.4
792
ms
ms
BLANK
Autoretry Time
t
720
RETRY
THERMAL PROTECTION
Thermal Foldback
T
145
170
20
°C
°C
°C
J_FB
Thermal Shutdown
Thermal-Shutdown Hysteresis
T
J_MAX
Note 3: All devices are 100% production-tested at T = +25ºC. Specifications over the operating temperature range are guaranteed
A
by design.
Note 4: Not production-tested, user-adjustable. See the Overvoltage Lockout (OVLO) and Undervoltage Lockout (UVLO) sections.
Note 5: All timing is measured using 20% and 80% levels, unless otherwise specified.
Note 6: The autoretry time-to-blanking time ratio is fixed and is equal to 30.
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Timing Diagrams
tDEB
tSTI
tSTO*
OVLO
UVLO
IN
1x /1.5x /2x I LIMIT
ILIMIT
IOUT
VIN
OUT
GND
THERMALLY-CONTROLLED
CURRENT FOLDBACK
TJMAX
TJ
NOT DRAWN TO SCALE
*IF OUT DOES NOT REACH VIN - VFA WITHIN t STO, THE DEVICE IS LATCHED OFF, AND EN, HVEN, OR IN MUST BE TOGGLED TO RESUME NORMAL
OPERATION .
Figure 1. Startup Timing
< tDEB
< tDEB
tDEB
OVLO
IN UVLO
ON
SWITCH
STATUS
OFF
NOT DRAWN TO SCALE
Figure 2. Debounce Timing
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
QUIESCENT IN CURRENT
vs. TEMPERATURE
QUIESCENT IN CURRENT
vs. IN VOLTAGE
HVEN INPUT CURRENT vs. VHVEN
toc03
toc02
toc01
100
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2
1.8
1.6
1.4
1.2
1
VEN = 3V
VEN = 3V
VEN = 3V
VIN = VHVEN
VIN = 34V
VIN = 24V
VIN = 12V
TA = +125°C
TA = +85°C
TA = +25°C
0.8
0.6
0.4
0.2
0
TA = -40°C
0
20
40
60
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
5
10 15 20 25 30 35 40 45 50 55 60
IN VOLTAGE (V)
V
HVEN (V)
NORMALIZED ON-RESISTANCE
vs. SUPPLYVOLTAGE
NORMALIZED ON-RESISTANCE
vs. TEMPERATURE
toc04
toc05
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.1
1.05
1
NORMALIZED TO TA = +25°C
IOUT = 1A
VIN = 24V
NORMALIZED TO VIN = 12V
IOUT = 1A
VEN = 3V
V
EN = 3V
0.95
0.9
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
5
10 15 20 25 30 35 40 45 50 55 60
IN VOLTAGE (V)
NORMALIZED ON-RESISTANCE
NORMALIZED CURRENT LIMIT
vs. SUPPLY VOLTAGE
vs. OUTPUT CURRENT
toc7
toc06
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.03
1.02
1.01
1
NORMALIZED TO IOUT = 1A
VIN = 24V
VEN = 3V
NORMALIZED TO VIN = 12V
RILIM = 13kW
0.99
0.98
0.97
5
10 15 20 25 30 35 40 45 50 55 60
IN VOLTAGE (V)
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT CURRENT (A)
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics (continued)
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
NORMALIZED CURRENT LIMIT
vs. TEMPERATURE
SHUTDOWNIN CURRENT
vs. TEMPERATURE
SHUTDOWN OUTPUT CURRENT
vs. TEMPERATURE
toc9
toc08
toc10
16
14
12
10
8
1.03
1.02
1.01
1.00
0.99
0.98
0.97
250
200
150
100
50
NORMALIZED TO TA = +25°C
IN = 24V
RILIM = 12.4kW
V
VIN = +60V
VIN = +34V
VIN = +34V
VIN = +24V
VIN = +12V
6
4
2
VIN = +24V
VIN = + 12V
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SWITCH TURN-ON TIME
vs. TEMPERATURE
SWITCH TURN-OFF TIME
vs. TEMPERATURE
toc12
toc11
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
200
180
160
140
120
100
80
MAX14721
IN = +24V
RL = 240W
CL = 4.7µF
V
60
40
VIN = +24V
RL = 240W
20
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
REVERSE-BLOCKING
RESPONSE
POWER-UP RESPONSE
toc13
toc14
MAX14723
24V
V
20V/div
20V/div
20V/div
VIN
IN
30V
24V
VOUT
20V/div
1A/div
VOUT
1A/div
IOUT
IOUT
ILIM = 1A
CL = 26mF
V
RIPEN
= 1.7V
200ms/div
10µs/div
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
CURRENT LIMIT RESPONSE
FLAG RESPONSE
toc16
toc15
VIN
0V
20V/div
20V/div
20V/div
20V/div
VIN
0V
VOUT
0V
VOUT
0V
IOUT
1A/div
VFLAG
5V/div
I
= 1A
LIM
IL = 100mA TO SUDDEN SHORT APPLIED
10ms/div
20µs/div
CURRENT LIMIT RESPONSE
BLANKING TIME
toc17
toc18
AUTORETRY MODE
MAX14723
20V/div
20V/div
VIN
0V
VOUT
0V
VOUT
200mV/div
IOUT
1A/div
ILIM = 1A
IL = 100mA TO SHORT ON OUT WITH 1A/s
20ms/div
200ms/div
AUTORETRY TIME
MAX14723
toc19
AUTORETRY MODE
200mV/div
VOUT
200ms/div
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Pin Configurations
TOP VIEW
15
14
13
12
11
16
17
18
19
20
10
9
UVLO
OVLO
RIPEN
HVEN
CLTS2
CLTS1
MAX14721–
MAX14723
8
FLAG
SETI
GP
7
6
GND/EP
EN
+
1
2
3
4
5
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
FUNCTION
1, 5, 11, 15
N.C.
Not Connected
Switch Input. Bypass IN to ground with a 1µF ceramic capacitor for ±15kV Human Body Model
ESD protection on IN. In applications in which an external pFET is used, a 4.7µF capacitor should
be placed at the drain of the pFET and a reduced capacitor of 10nF to 100nF should be placed at
IN. The maximum slew rate allowed at IN is 30V/µs. IN serves as the under/overvoltage sensed
input when preprogrammed UVLO/OVLO is used.
2, 3, 4
IN
6
7
GP
Gate Driver Output for External pFET
Overload Current-Limit Adjust. Connect a resistor from SETI to GND to program the overcurrent
limit. SETI must be connected to a resistor. If SETI is connected to GND during startup, then the
switch does not turn on. Do not connect more than 30pF to SETI.
SETI
Open-Drain Fault Indicator Output. FLAG asserts low when the V - V
voltage exceeds
IN
OUT
8
9
FLAG
OVLO
UVLO
V
, reverse-current is detected, thermal shutdown mode is active, OVLO or UVLO threshold is
FA
reached, or SETI is connected to GND.
Externally-Programmable Overvoltage Lockout Threshold. Connect OVLO to GND to use the
default internal OVLO threshold. Connect OVLO to an external resistor-divider to define a
threshold externally and override the preset internal OVLO threshold.
Externally-Programmable Undervoltage Lockout Threshold. Connect UVLO to GND to use the
default internal UVLO threshold. Connect UVLO to an external resistor-divider to define a threshold
externally and override the preset internal UVLO threshold.
10
Switch Output. Bypass OUT to GND with a 4.7µF ceramic capacitor placed as close to the device
as possible.
12, 13, 14
16
OUT
Reverse-Current Protection Enable. Internally pulled up. Connect RIPEN to GND with 10kW
resistor or lower to disable the reverse-current flow protection.
RIPEN
17
18
19
20
—
HVEN
CLTS2
CLTS1
EN
60V Capable Active-Low Enable Input. See Table 1.
Current-Limit Type Select 2. See Table 2.
Current-Limit Type Select 1. See Table 2.
Active-High Enable Input. See Table 1.
GND/EP
Ground/Exposed Pad. Connect to a large copper ground plane to maximize thermal performance.
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Functional Diagram
GP
IN
IN
IN
OUT
OUT
OUT
MAX14721–
MAX14723
RIPEN
VIN
VIN
SETI
150kΩ
REVERSE-
CURRENT FLOW
CONTROL
CURRENT-
LIMIT
CONTROL
CHARGE
PUMP
CONTROL
VUVLO
UVLO
VSEL
FLAG
VIN
CONTROL LOGIC
VOVLO
OVLO
VSEL
EN
VIN
150kΩ
150kΩ
HVEN
CLTS1 CLTS2 GND
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
power-limiting mode (Figure 1). In this mode, the device
thermally regulates the current through the switch in order
to protect itself while still delivering as much current as
possible to the output regardless of the current limit type
selected. If the output is not charged within the startup
Detailed Description
The MAX14721–MAX14723 adjustable overvoltage,
undervoltage, and overcurrent protection devices guard
systems against overcurrent faults in addition to posi-
tive overvoltage and reverse-voltage faults. When used
with an optional external p-channel MOSFET, these
devices also protect downstream circuitry from voltage
faults up to +60V, -60V (for-60V external pFET rating).
The MAX14721–MAX14723 feature a low, 76mΩ, on-
resistance integrated FET. During startup, the devices
are designed to charge large capacitances on the out-
put in a continuous mode for applications where large
reservoir capacitors are used on the inputs to down-
stream devices. Additionally, the MAX14721, MAX14722,
and MAX14723 feature a dual-stage current-limit mode in
which the current is continuously limited to 1x, 1.5x, and
2x the programmed limit, respectively, for a short time
after startup. This enables faster charging of large loads
during startup.
timeout period (t
), the switch turns off and IN, EN, or
STO
HVEN must be toggled to resume normal operation.
The MAX14721–MAX14723 have a 16ms (typ) time delay
at the end of startup, during which the reverse threshold
is set at -90mV (typ) to prevent false reverse faults due to
oscillation. After this delay, the reverse current-blocking
threshold is reduced to -9mV (V , typ).
RIB
Overvoltage Lockout (OVLO)
The devices feature two methods for determining the
OVLO threshold. By connecting the OVLO pin to GND, the
preset internal OVLO threshold of 36V (typ) is selected.
If the voltage at OVLO rises above the OVLO select
threshold (V ), the device enters adjustable
OVLO_SEL
OVLO mode. Connect an external voltage divider to the
OVLO pin as shown in the Typical Application Circuit
to adjust the OVLO threshold. The permitted overvoltage
lockout set point range of the device is 6V to 40V.
R3 = 2.2MΩ is a good starting value for minimum current
The MAX14721–MAX14723 feature the option to set the
overvoltage lockout (OVLO) and undervoltage lockout (UVLO)
thresholds manually using external voltage dividers or to use
the factory-preset internal thresholds by connecting the OVLO
and/or UVLO pin(s) to GND. The permitted overvoltage lockout
set point range of the devices is 6V to 40V, while the permitted
undervoltage lockout set point range is 5.5V to 24V. Therefore,
the pFET and internal nFET must be kept off in the 40V to 60V
range by appropriate OVLO resistor divider.
The devices’ programmable current-limit threshold can be
set for currents up to 2A in autoretry, latchoff, or continuous
fault response mode. When the device is set to autoretry
mode and the current exceeds the threshold for more than
24ms (typ), both FETs are turned off for 720ms (typ), then
turned back on. If the fault is still present, the cycle repeats.
In latchoff mode, if a fault is present for more than 24ms
(typ), both FETs are turned off until enable is toggled or the
power is cycled. In continuous mode, the current is limited
continuously to the programmed current-limit value. In all
consumption. Since V
is known (1.22V, typ), R3 has
is the target OVLO value, R4
SET
been chosen, and V
OVLO
can then be calculated by the following equation:
R3× V
SET
R4 =
V
− V
SET
OVLO
Undervoltage Lockout (UVLO)
The devices feature two methods for determining the
UVLO threshold. By connecting the UVLO pin to GND,
the preset, internal UVLO threshold of 12V (typ) is
selected. If the voltage at UVLO rises above the UVLO
select threshold (V ) the device enters adjustable
UVLO_SEL
UVLO mode. Connect an external voltage divider to the
UVLO pin as shown in the Typical Application Circuit to
adjust the UVLO threshold. The permitted undervoltage
lockout set point range of the device is 5.5V to 24V.
R1 = 2.2MΩ is a good starting value for minimum current
modes, FLAG asserts if V - V
is greater than the
IN
OUT
FLAG assertion drop voltage threshold (V ).
FA
Startup Control
These devices feature a dual-stage startup sequence
that continuously limits the current to 1x/1.5x/2x the set
current limit during the startup initial time (t ), allowing
STI
consumption. Since V
is known (1.22V, typ), R1 has
is the target value, R2 can then
SET
been chosen, and V
UVLO
be calculated by the following equation:
large capacitors present on the output of the switch to be
rapidly charged. The MAX14721 limits the current to 1x
the set limit during this period while the MAX14722 and
MAX14723 limit the current to 1.5x and 2x the set limit,
respectively. If the temperature of any device rises to the
R1× V
SET
R2 =
V
− V
SET
UVLO
Switch Control
There are two independent enable inputs on the devices:
HVEN and EN. HVEN is a high-voltage-capable input,
thermal foldback threshold (T
), the device will enter
J_FB
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Table 1. Enable Inputs
Table 2. Current-Limit Type Select
HVEN
EN
0
SWITCH STATUS
CLTS2
CLTS1
CURRENT-LIMIT TYPE
LATCHOFF MODE
0
0
1
1
ON
ON
0
0
1
1
0
1
0
1
AUTORETRY MODE
CONTINUOUS MODE
CONTINUOUS MODE
1
0
OFF
ON
1
accepting signals up to 60V. EN is a low-voltage input,
accepting a maximum voltage of 5V. In case of a fault
condition, toggling HVEN or EN resets the fault. The
enable inputs control the state of the switch based on the
truth table (Table 1).
if there is no fault. In Latchoff mode, the device will latch
off if the overcurrent fault last longer than t
.
BLANK
Autoretry Mode (Figure 3)
In autoretry current-limit mode, when current through the
device reaches the threshold, the t timer begins
BLANK
Input Debounce
The MAX14721–MAX14723 feature a built-in input
counting. The FLAG output asserts low when the voltage
drop across the switch rises above V . If the overcurrent
FA
condition is present for t
, the switch is turned off.
debounce time (t
between a POR event and the switch being turned on. If
the input voltage rises above the UVLO threshold voltage
). The debounce time is a delay
BLANK
DEB
The timer resets if the overcurrent condition disappears
before t has elapsed. A retry time delay (t
)
RETRY
BLANK
starts immediately once t
retry time, the switch remains off and, once t
elapsed, the switch is turned back on. If the fault still
exists, the cycle is repeated and FLAG remains low. If the
fault has been removed, the switch stays on.
has elapsed. During the
or if, with a voltage greater than V
present on IN,
BLANK
UVLO
has
the enable pins toggle to the on state, the switch turns on
after t . In cases where the voltage at IN falls below
RETRY
DEB
V
UVLO
before t
has passed, the switch remains
DEB
off (Figure 2). If the voltage at OUT is already above
when the device is turned on through either
V
UVLO_OUT
The autoretry feature reduces system power in case of
overcurrent or short-circuit conditions. When the switch is
enable pin or coming out of OVLO, there is no debounce
interval. This is due to the device already being out of the
on during t
time, the supply current is held at the
BLANK
POR condition with OUT above V
.
UVLO_OUT
currentlimit.Whentheswitchisoffduringt
time,there
RETRY
is no current through the switch. Thus, the output current
is much less than the programmed current limit. Calculate
the average output current using the following equation.
Current-Limit Type Select
The MAX14721–MAX14723 feature three selectable
current-limiting modes. During power-up, all devices
default to continuous mode and follow the procedure
defined in the Startup Control section. Once the part has
t
+ t
×K
+ t
BLANK
STI
+ t
RETRY
I
= I
LOAD LIM
t
BLANK
STI
been successfully powered on and t
has expired,
STO
the device senses the condition of CLTS1 and CLTS2.
The condition of CLTS1 and CLTS2 sets the current-limit
mode type according to Table 2. CLTS1,2 are internally
pulled up to an internal 5V supply. Therefore, the device is
in continuous current-limit mode when CLTS1 and CLTS2
are open. To set CLTS_ state to low, connect a 10kΩ
resistor or below to ground.
where K is the multiplication factor of the initial current
limit (1x, 1.5x or 2x). With a 24ms (typ) t 24ms
BLANK,
t
, K = 1 and 720ms (typ) t , the duty cycle is
STI RETRY
3.1%, resulting in 97% power saving as compared to the
switch being on the entire time.
Latchoff Mode (Figure 4)
In latchoff current-limit mode, when current through the
In addition to the selectable current-limiting modes, the
device has a protection feature against a severe over
load condition. If the output current exceeds 2 times the
set current limit, the device will turn off the internal nFET
and external pFET immediately and will attempt to restart
device reaches the threshold, the t
timer begins
BLANK
counting. The FLAG asserts when the voltage drop across
the switch rises above V . The timer resets if the overcurrent
FA
condition disappears before t
has elapsed. The
BLANK
switch turns off if the overcurrent condition remains for the
blanking time. The switch remains off until the control logic
(EN or HVEN) is toggled or the input voltage is cycled.
to allow the overcurrent to last for t
time. The OFF
BLANK
duration depends on fault condition occurred after the
FETs turn off, with the shortest duration of 420µs (t
)
ON_FET
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
tBLANK
tBLANK
tRETRY
tDEB
tSTI
tBLANK
tRETRY
tSTI
1x /1.5x /2x ILIMIT
1x /1.5x /2x ILIMIT
ILIMIT
IOUT
VIN
VOUT
VFA
VUVLO_OUT
FLAG
NOT DRAWN TO SCALE
VUVLO < VIN < VOVLO, HVEN= LOW, EN = HIGH
Figure 3. Autoretry Fault Diagram
tBLANK
tBLANK
tSTI
tBLANK
tDEB
tSTI
1x /1.5x /2x ILIMIT
ILIMIT
1x /1.5x /2x ILIMIT
IOUT
VIN
VOUT
VFA
VUVLO
_
OUT
EN
HVEN
FLAG
NOT DRAWN TO SCALE
VUVLO < VIN < VOVLO
Figure 4. Latchoff Fault Diagram
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
time, the device monitors the voltage difference between
OUT and IN pins to determine whether the reverse current
Continuous Mode (Figure 5)
In continuous current-limit mode, when current through
the device reaches the threshold, the device limits the
current to the programmed limit. FLAG asserts when
the voltage drop across the switch rises above V , and
deasserting when it falls below V
is still present. Once t
expired and the reverse-
REV_REC
current condition has been removed, the nFET and pFET
are turned back on after an additional time delay follows by
the dual-stage startup control mechanism as defined in the
Startup Control section above. The additional time delay
FA
.
FA
Reverse-Current Blocking (Figure 6)
will be 420us (t
equal to V
otherwise the delay will be 0.5ms (t
) if voltage at OUT is more than or
ON_NFET
falling at the end of t
delay,
The MAX14721–MAX14723 feature current-blocking func-
tionality to be used with external pFET. To enable the
reverse-current blocking feature, pull RIPEN high. With
UVLO_OUT
REV_REC
). After a reverse-
DEB
current event, the device will attempt a restart regardless
of the current-type select.
RIPEN high, if a reverse-current condition is detected (V
IN
- V
OUT
< V ), the internal nFET and the external pFET
RIB
are turned off for 2.4ms (t
). During and after this
REV_REC
tDEB
tSTI
tSTO
tSTI
OVLO
UVLO
IN
ILIMIT
1x /1.5x /2x ILIMIT
1x /1.5x /2x ILIMIT
IOUT
THERMAL CURRENT LIMIT
THERMAL CURRENT
LIMIT
VIN
VFA
VOUT_UVLO
VOUT
TJMAX
TJ
HVEN
EN
FLAG
NOT DRAWN TO SCALE
Figure 5. Continuous Fault Diagram
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
t
t
t
t
t
t
STI
REV_REC
ON_NFET
STI
REV_REC
DEB
t
t
RIB
RIB
I
IN
IN_REF
(V /R
1x/1.5x/2x
1x/1.5x/2x
I
I
LIMIT
I
LIMIT
)
RIB DSON
V
OUT
V
UVLO_OUT
I
LOAD
NOT DRAWN TO SCALE
Figure 6. Reverse-Current Timing Diagram
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Do not use a R
current-limit thresholds for different resistor values at
SETI.
A current mirror with a ratio of C
with a current sense auto-zero operational amplifier. The
mirrored current of the IN-OUT FET is provided on the
SETI pin. Therefore, the voltage (V
SETI pin should be interpreted as the current through the
IN-OUT FET, as shown below:
smaller than 6kΩ. Table 3 shows
Fault Indicator (FLAG) Output
SETI
FLAG is an open-drain fault indicator output. It requires
an external pullup resistor to a DC supply. FLAG asserts
when any of the following conditions occur:
is implemented
IRATIO
●
●
●
●
●
●
V
- V
> V
IN
OUT FA
The reverse-current protection is tripped
The die temperature exceeds +170ºC
SETI is connected to ground
UVLO threshold has not been reached
OVLO threshold is reached
) read on the
SETI
V
(V)
SETI
I
= I
× C
=
IRATIO
IN−OUT
SETI
R
(kW)
SETI
Thermal Shutdown Protection
V
(V)
SETI
× C
=
×I
LIM
Thermal shutdown circuitry protects the devices from
overheating. The switch turns off and FLAG asserts
when the junction temperature exceeds +170ºC (typ).
The MAX14721–MAX14723 exit thermal shutdown and
resume normal operation once the junction tempera-
ture cools by 20ºC (typ) if the device is in autoretry or
continuous current-limiting mode. When in latchoff mode,
the device remains latched off until the input voltage is
cycled or one of the enable pins is toggled.
IRATIO
V (V)
RI
IN Bypass Capacitor
In applications in which an external PFET is not used,
connect a minimum of 1µF capacitor from IN to GND
to limit the input voltage drop during momentary output
short-circuit conditions. Larger capacitor values further
reduce the voltage droop at the input caused by load
transients.
The thermal-shutdown technology built into the
MAX14721–MAX14723 behaves in accordance with
the selected current limit mode. While the devices are
in autoretry mode, the thermal limit uses the autore-
try timing when coming out of a fault condition. When
the MAX14721–MAX14723 detects an overtemperature
fault, the switch turns off. Once the temperature of the
junction falls below the falling thermal threshold, the
In applications in which an external PFET is used, a
4.7µF capacitor is placed at the drain of the PFET and
capacitor at IN is reduced to 10nF (100nF, max).
Hot Plug-In
In many power applications, an input filtering capacitor
is required to lower the radiated emission, enhance the
ESD capability, etc. In hot plug applications, parasitic
cable inductance, along with the input capacitor, causes
overshoot and ringing when a powered cable is suddenly
connected to the input terminal. This effect causes the
protection device to see almost twice the applied voltage.
An input voltage of 24V can easily exceed 40V due to
ringing. The MAX14721–MAX14723 contain internal
protection against hot plug input transients on the IN
pins, with slew rate up to 30V/µs. However, in the case
where the harsh industrial EMC test is required, use a
device turns on after the time interval t . In latchoff
RETRY
mode, the device latches off until the input is cycled or
one of the enable pins is toggled. In continuous current-
limiting mode, the device turns off while the temperature
is over the limit, then turns back on after t
when the
DEB
temperature reaches the falling threshold. There is no
retry time for thermal protection.
Applications Information
Setting the Current-Limit Threshold
Connect a resistor between SETI and ground to program
the current-limit threshold for the MAX14721–MAX14723.
Leaving SETI unconnected sets the current-limit thresh-
old to 0A and, since connecting SETI to ground is a fault
condition, this causes the switch to remain off and FLAG
to assert. Use the following formula to calculate the
current-limit threshold:
Table 3. Current-Limit Threshold
vs. Resistor Values
R
(kΩ)
CURRENT LIMIT (A)
SETI
62.5
0.2
0.5
1.0
1.5
2.0
25.0
12.5
8.3
V (W × A)
RI
R
(kW) =
× C
IRATIO
SETI
I
(mA)
LIM
6.25
transient voltage suppressor (TVS) placed close to the
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
input terminal that is capable of limiting the input surge to
a maximimum of 60V.
OUT Freewheeling Diode for Inductive Hard
Short to Ground
OUT Capacitance
In applications with a highly inductive load, a freewheeling
diode is required between the OUT terminal and GND.
This protects the device from inductive kickback that
occurs during short-to-ground events.
For stable operation over the full temperature range and
over the entire programmable current-limit range, connect
a 4.7µF ceramic capacitor from OUT to ground. Other
circuits connected to the output of the device may
introduce additional capacitance, but it should be noted
that excessive output capacitance on the MAX14721–
MAX14723 can cause faults. If the capacitance is too
high, the MAX14721–MAX14723 may not be able to
charge the capacitor before the startup timeout. Calculate
Layout and Thermal Dissipation
To optimize the switch response to output short-circuit
conditions, it is important to reduce the effect of undesir-
able parasitic inductance by keeping all traces as short as
possible. Place input and output capacitors as close as
possible to the device (no more than 5mm). IN and OUT
must be connected with wide short traces to the power
bus. During steady-state operation, the power dissipation
is typically low and the package temperature change is
usually minimal.
Attention must be given when using continuous current-
limit mode. In this mode, the power dissipation during a
fault condition can quickly cause the device to reach the
thermal shutdown threshold. A large copper plane and
multiple thermal vias from the exposed pad to ground
plane are necessary to increase the thermal capacitance
and reduce the thermal resistance of the board.
the maximum capacitive load (C
connected to OUT using the following formula:
) value that can be
MAX
M x t (ms) + t
(ms)
STO
STI
V
C
(mF) = I (A)
LIM
MAX
(V)
IN_MAX
where M is the multiplier (1x/1.5x/2x) applied to the current
limit during startup. For example, when using MAX14721,
if V
= 20V, t
(min) = 1090ms, t
(min) = 22ms,
results in the theoretical maximum
IN_MAX
STO
STI
and I = 2A, C
LIM
MAX
of 111mF. In this case, any capacitance larger than 111mF
will cause a fault condition because the capacitor cannot
be charged to a sufficient voltage before t
In practical applications, the output capacitor size is lim-
ited by the thermal performance of the PCB board. Poor
thermal design can cause the thermal foldback current-
limiting function of the device to kick in too early, which may
further limit the maximum capacitance that can be charged.
Therefore, good thermal PCB design is imperative in order
to charge large capacitor banks.
ESD Test Conditions
has expired.
STO
The MAX14721–MAX14723 are specified for ±15kV
(HBM) ESD on IN when IN is bypassed to ground with a
1µF, low ESR ceramic capacitor. No capacitor is required
for ±2kV (HBM) (typ) ESD on IN. All pins have ±2kV
(HBM) ESD protection. In applications in which an external
pFET is used, see IN Bypass Capacitor section.
HBM ESD Protection
Figure 7 shows the Human Body Model and Figure 8
shows the current waveform it generates when discharged
into low impedance. This model consists of a 100pF
capacitor charged to the ESD voltage of interest, which is
then discharged into the device through a 1.5kΩ resistor.
RC
RD
1MΩ
1.5KΩ
IP 100%
90%
IR
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
AMPERES
36.8%
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
10%
0
TIME
SOURCE
tRL
tDL
CURRENT WAVEFORM
Figure 7. Human Body ESD Test Model
Figure 8. Human Body Current Waveform
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Typical Application Circuit
VIN
*R1, R2, R3, AND R4 ARE ONLY
REQURED FOR ADJUSTABLE UVLO/
OVLO FUNCTIONALITY. OTHERWISE,
TIE THE PIN TO GND TO USE THE
INTERNAL, PREPROGRAMMED
CIN
C
IN_C
GP
IN
IN IN
VIN
THRESHOLD.
R1*
R3*
OUT
SYSTEM
CONTROLLER
UVLO
POWER
OUT
OUT
PROTECTED
POWER
220kΩ
R2*
R4*
SYSTEM
INPUT
ADC
MAX14721–
MAX14723
COUT
VIN
OVLO
HVEN
SETI
RIPEN
FLAG
EN
GND
ENB
FAULT
EN
HVEN
x
CLTS2
10kΩ
CLTS1
GND
Ordering Information
PART
INITIAL CURRENT LIMIT
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
MAX14721ATP+T
MAX14722ATP+T
MAX14723ATP+T
1.0x
1.5x
2.0x
20 TQFN-EP*
20 TQFN-EP*
20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
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MAX14721/
MAX14722/
MAX14723
High-Accuracy, Adjustable Power Limiter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
10/14
7/16
0
1
2
3
Initial release
—
1–19
Improved latch-up and more robust protection capability
Updated text and functional diagrams
Updated the Benefits and Features section
7/17
1, 10, 11, 17,
1
11/17
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
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