MAX15013CASA+ [MAXIM]
Half Bridge Based MOSFET Driver, 2A, BICMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8;
| 型号： | MAX15013CASA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Half Bridge Based MOSFET Driver, 2A, BICMOS, PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总18页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0530; Rev 1; 12/07
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
General Description
Features
The MAX15012/MAX15013 high-frequency, 175V half-
bridge, n-channel MOSFET drivers drive high- and low-
side MOSFETs in high-voltage applications. These
drivers are independently controlled and their 35ns typ-
ical propagation delay, from input to output, are
matched to within 2ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities make
these devices suitable for the high-power, high-fre-
quency telecom power converters. A reliable on-chip
♦ HIP2100/HIP2101 Pin Compatible (MAX15012A/C
and MAX15013A/C)
♦ Up to 175V Input Operation
♦ 8V to 12.6V V
Input Voltage Range
DD
♦ 2A Peak Source and Sink Current Drive Capability
♦ 35ns Typical Propagation Delay
♦ Guaranteed 8ns Propagation Delay Matching
Between Drivers
bootstrap diode connected between V
and BST
♦ Up to 500kHz Switching Frequency
DD
eliminates the need for an external discrete diode.
♦ Available in CMOS (V /2) or TTL Logic-Level
DD
The MAX15012A/C and MAX15013A/C offer both nonin-
verting drivers (see the Selector Guide). The
MAX15012B/D and MAX15013B/D offer a noninverting
high-side driver and an inverting low-side driver. The
Inputs with Hysteresis
♦ Up to 14V Logic Inputs Independent of Input
Voltage
♦ Low 2.5pF Input Capacitance
♦ Low 70µA Supply Current
MAX15012A/B/C/D feature CMOS (V /2) logic inputs.
DD
The MAX15013A/B/C/D feature TTL logic inputs. The
drivers are available in the industry-standard 8-pin SO
footprint and pin configuration and a thermally
enhanced 8-pin SO package. All devices operate over
the -40°C to +125°C automotive temperature range.
♦ Versions Available with Combination of
Noninverting and Inverting Drivers (MAX15012B/D
and MAX15013B/D)
♦ Available in Industry-Standard 8-Pin SO and
Thermally Enhanced SO Packages
Applications
Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
Ordering Information
PIN-
PKG
PART
TEMP RANGE
PACKAGE CODE
MAX15012AASA+ -40°C to +125°C 8 SO
S8-5
S8-5
Active-Clamp Forward Converters
Power-Supply Modules
MAX15012BASA+ -40°C to +125°C 8 SO
MAX15012CASA+* -40°C to +125°C 8 SO-EP** S8E+14
MAX15012DASA+* -40°C to +125°C 8 SO-EP** S8E+14
Motor Control
Ordering Information continued at end of data sheet.
+Denotes lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
Pin Configurations and Typical Operating Circuit appear at
the end of data sheet.
Selector Guide
PART
HIGH-SIDE DRIVER
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
Noninverting
LOW-SIDE DRIVER
Noninverting
Inverting
LOGIC LEVELS
CMOS (V /2)
PIN COMPATIBLE
MAX15012AASA+
MAX15012BASA+
MAX15012CASA+
MAX15012DASA+
MAX15013AASA+
MAX15013BASA+
MAX15013CASA+
MAX15013DASA+
HIP 2100IB
DD
CMOS (V /2)
—
HIP 2100IB
—
DD
Noninverting
Inverting
CMOS (V /2)
DD
CMOS (V /2)
DD
Noninverting
Inverting
TTL
TTL
TTL
TTL
HIP 2101IB
—
Noninverting
Inverting
HIP 2101IB
—
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
, IN_H, IN_L......................................................-0.3V to +14V
Junction-to-Case Thermal Resistance (θ )(Note 1)
JC
8-Pin SO .......................................................................40°C/W
8-Pin SO-EP....................................................................6°C/W
V
DD
DL...............................................................-0.3V to (V
+ 0.3V)
DD
HS............................................................................-5V to +180V
DH to HS.....................................................-0.3V to (V + 0.3V)
BST to HS ...............................................................-0.3V to +14V
dV/dt at HS ........................................................................50V/ns
Continuous Power Dissipation (T = +70°C)
A
8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW
8-Pin SO-EP (derate 19.2mW/°C above +70°C) .....1538.5mW
Junction-to-Ambient Thermal Resistance (θ )(Note 1)
JA
8-Pin SO .....................................................................170°C/W
8-Pin SO-EP..................................................................52°C/W
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
*Per JEDEC 51 Standard Multilayer board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JE5D51-7, using a four-
layer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= V
= +8V to +12.6V, V = GND = 0V, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at V
=
DD
BST
HS
A
J
DD
V
= +12V and T = +25°C.) (Note 2)
BST
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Operating Supply Voltage
V
(Notes 3 and 4)
IN_H = IN_L = GND (for A/C versions),
IN_H = GND, IN_L = V (for B/D versions)
8.0
12.6
140
3
V
DD
V
Quiescent Supply Current
DD
I
70
15
µA
mA
µA
DD
(No Switching)
DD
V
Operating Supply Current
I
f
= 500kHz, V
= +12V
DD
DD
DDO
SW
IN_H = IN_L = GND (for A/C versions),
IN_H = GND, IN_L = V (for B/D versions)
BST Quiescent Supply Current
BST Operating Supply Current
I
40
BST
DD
I
f
= 500kHz, V
V rising
DD
= V = +12V
BST
3
mA
V
BSTO
SW
DD
UVLO (V
to GND)
UVLO
6.5
6.0
7.3
6.9
0.5
8.0
7.8
DD
VDD
UVLO (BST to HS)
UVLO Hysteresis
LOGIC INPUT
UVLO
BST rising
V
BST
V
0.67 x
0.55 x
V
DD
MAX15012_, CMOS (V /2) version
DD
V
Input-Logic High
V
DD
V
IH_
MAX15013_, TTL version
2
1.65
0.4 x
0.33 x
MAX15012_, CMOS (V /2) version
DD
V
V
Input-Logic Low
V
V
V
DD
DD
IL_
MAX15013_, TTL version
1.4
1.6
0.8
MAX15012_, CMOS (V /2) version
DD
Logic-Input Hysteresis
V
HYS
MAX15013_, TTL version
0.25
2
_______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= +8V to +12.6V, V = GND = 0V, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at V
=
DD
BST
HS
A
J
DD
V
= +12V and T = +25°C.) (Note 2)
BST
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= V
for MAX15012B/MAX15012D/
IN_L
DD
MAX15013B/MAX15013D
V
= 0V
Logic-Input Current
Input Resistance
I
-1
+0.001
+1
µA
IN_H
_IN
V
= 0V for MAX15012A/MAX15012C/
IN_L
MAX15013A/MAX15013C
IN_H to GND
IN_L to V for MAX15012B/MAX15012D/
DD
MAX15013B/MAX15013D
R
C
1
MΩ
IN
IN_L to GND for MAX15012A/MAX15012C/
MAX15013A/MAX15013C
Input Capacitance
2.5
pF
IN
HIGH-SIDE GATE DRIVER
HS Maximum Voltage
BST Maximum Voltage
V
V
V
≤ 10.5V (Note 4)
≤ 10.5V (Note 4)
175
189
V
V
HS_MAX
DD
DD
V
BST_MAX
T
A
T
A
T
A
T
A
= +25°C
= +125°C
= +25°C
= +125°C
2.5
3.5
2.1
3.2
3.3
4.6
2.8
4.2
Driver Output Resistance
(Sourcing)
V
= 12V, I
= 100mA
DD
DH
R
Ω
Ω
ON_HP
(sourcing)
Driver Output Resistance
(Sinking)
V
DD
(sinking)
= 12V, I
= 100mA
DH
R
ON_HN
DH Reverse Current (Latchup
Protection)
(Note 5)
400
mA
V
Power-Off Pulldown Clamp
Voltage
V
= 0V or floating, I
= 1mA (sinking)
0.94
1.16
BST
DH
Peak Output Current (Sourcing)
Peak Output Current (Sinking)
LOW-SIDE GATE DRIVER
C = 10nF, V
= 0V
2
2
A
A
L
DH
I
DH_PEAK
C = 10nF, V
L
= 12V
DH
T
A
T
A
T
A
T
A
= +25°C
= +125°C
= +25°C
= +125°C
2.5
3.5
2.1
3.2
3.3
4.6
2.8
4.2
Driver Output Resistance
(Sourcing)
V
= 12V, I = 100mA
DD DL
R
R
Ω
Ω
ON_LP
(sourcing)
V = 12V, I = 100mA
DD
Driver Output Resistance
(Sinking)
DL
ON_LN
(sinking)
Reverse Current at DL (Latchup
Protection)
(Note 5)
400
mA
V
Power-Off Pulldown Clamp
Voltage
V
= 0V or floating, I = 1mA (sinking)
0.95
1.16
1.11
DD
DL
Peak Output Current (Sourcing)
Peak Output Current (Sinking)
INTERNAL BOOTSTRAP DIODE
Forward Voltage Drop
I
C = 10nF, V = 0V
L
2
2
A
A
PK_LP
DL
I
C = 10nF, V = 12V
L
PK_LN
DL
V
I
I
= 100mA
0.91
40
V
F
BST
Turn-On and Turn-Off Time
t
= 100mA
ns
R
BST
_______________________________________________________________________________________
3
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= +8V to +12.6V, V = GND = 0V, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at V
=
DD
BST
HS
A
J
DD
V
= +12V and T = +25°C.) (Note 2)
BST
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (V
= V
= +12V)
DD
BST
C = 1000pF
L
7
Rise Time
Fall Time
t
ns
ns
C = 5000pF
L
33
65
7
R
C = 10,000pF
L
C = 1000pF
L
t
C = 5000pF
L
33
65
30
35
30
35
F
C = 10,000pF
L
CMOS
TTL
55
63
55
63
Figure 1, C = 1000pF
L
(Note 5)
Turn-On Propagation Delay Time
Turn-Off Propagation Delay Time
t
ns
ns
D_ON
CMOS
TTL
Figure 1, C = 1000pF
L
(Note 5)
t
D_OFF
Delay Matching Between Driver-
Low and Driver-High
t
C = 1000pF, Figure 1 (Note 5)
2
8
ns
ns
ns
MATCH
L
Internal Nonoverlap
1
V
V
= V
= V
= 12V
= 8V
135
170
Minimum Pulse Width Input Logic
(Note 6)
DD
DD
BST
BST
t
PW-min
Note 2: All devices are 100% tested at T = +125°C. Limits over temperature are guaranteed by design.
A
Note 3: Ensure that the V -to-GND or BST-to-HS transient voltage does not exceed 13.2V.
DD
Note 4: Maximum operating supply voltage (V ) reduces linearly from 12.6V to 10.5V with its maximum voltage (V
) increasing
HS_MAX
DD
from 125V to 175V. See the Typical Operating Characteristics and Applications Information sections.
Note 5: Guaranteed by design, not production tested.
Note 6: See the Minimum Input Pulse Width section.
4
_______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
BST A
DD
UNDERVOLTAGE LOCKOUT
V
DD
AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE
(V AND V
RISING) vs. TEMPERATURE
I
DD
vs. V
DD
DD
BST
MAX15012/13 toc03
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IN_H = GND
IN_L = V
DD
UVLO
VDD
BST
UVLO
HYSTERESIS
VDD
V
DD
2V/div
UVLO
HYSTERESIS
BST
UVLO
0V
I
DD
0μA
50μA/div
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
4ms/div
TEMPERATURE (°C)
TEMPERATURE (°C)
I
+ I
vs. V
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
DDO BSTO DD
(f = 250kHz)
SW
200
180
160
140
120
100
80
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
T
T
T
= +125°C
= +25°C
= 0°C
A
A
A
A
= -40°C
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0.5
0.6
0.7
0.8
0.9
1.0
1.1
V
(V)
V
DD
- V (V)
BST
DD
V
QUIESCENT CURRENT
DD
BST QUIESCENT CURRENT
vs. BST VOLTAGE
DD
vs. V (NO SWITCHING)
160
140
120
100
80
21
18
15
12
9
V
V
= V
= GND
V
= V + 1V,
DD
DD
HS
BST
BST
NO SWITCHING
IN_H = GND
IN_L = V
DD
T
= +125°C
A
T
= +125°C
A
T
= +25°C
A
60
6
40
3
20
T
= -40°C
T = -40°C, T = 0°C, T = +25°C
A A A
A
6
0
0
0
2
4
10
12
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
8
V
(V)
V
(V)
DD
BST
_______________________________________________________________________________________
5
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics (continued)
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
DD
BST
A
V
DD
AND BST OPERATING SUPPLY
CURRENT vs. FREQUENCY
DH OR DL OUTPUT LOW VOLTAGE
vs. TEMPERATURE
10
9
8
7
6
5
4
3
2
1
0
0.34
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
SINKING 100mA
C = 0
L
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
DH OR DL RISE TIME
vs. TEMPERATURE (C = 10nF)
PEAK DH AND DL
SOURCE/SINK CURRENT
L
MAX15012/13 toc10
120
108
96
84
72
60
48
36
24
12
0
C
= 100nF
L
V
= V = 8V
BST
DD
DH OR DL
5V/div
V
= V = 12V
BST
DD
SINK AND SOURCE
CURRENT
2A/div
-40 -25 -10
5
20 35 50 65 80 95 110 125
1μs/div
TEMPERATURE (°C)
DH OR DL FALL TIME
vs. TEMPERATURE (C = 10nF)
DH OR DL RISE PROPAGATION DELAY
vs. TEMPERATURE
LOAD
120
110
100
90
80
70
60
50
40
30
20
10
0
60
55
50
45
40
35
30
25
20
15
10
5
V
= V = 8V
BST
DD
DH
DL
V
= V = 12V
BST
DD
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Characteristics (continued)
(Typical values are at V
= V
= +12V and T = +25°C, unless otherwise specified.)
BST A
DD
DH OR DL FALL PROPAGATION DELAY
vs. TEMPERATURE
V
vs. V
HS_MAX
DD_MAX
60
55
50
45
40
35
30
25
20
15
10
5
175
125
DH
DL
0
0
8
10.5
12.6
-40 -25 -10
5
20 35 50 65 80 95 110 125
V
(V)
TEMPERATURE (°C)
DD_MAX
DELAY MATCHING (DH/DL FALLING)
DELAY MATCHING (DH/DL RISING)
MAX15012/13 toc17
MAX15012/13 toc16
C
= 0
C
= 0
L
L
INPUT
5V/div
INPUT
5V/div
DH/DL
5V/div
DH/DL
5V/div
10ns/div
10ns/div
DH/DL RESPONSE TO V GLITCH
DD
MAX15012/13 toc18
DH
10V/div
DL
10V/div
V
DD
10V/div
INPUT
5V/div
40μs/div
_______________________________________________________________________________________
7
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Pin Description
PIN
NAME
FUNCTION
1
V
Power Input. Bypass V to GND with a parallel combination of 0.1µF and 1µF ceramic capacitors.
DD
DD
Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
2
BST
3
4
5
DH
HS
High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.
Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
High-Side Noninverting Logic Input
IN_H
Low-Side Noninverting Logic Input (MAX15012A/C and MAX15013A/C). Low-side inverting logic
input (MAX15012B/D and MAX15013B/D).
6
IN_L
7
8
GND
DL
Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.
Low-Side-Gate Driver Output. Drives low-side MOSFET gate.
Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX15012C/D and MAX15013C/D only).
—
EP
V
IH
IN_L
(MAX15012A/C
MAX15013A/C)
V
IL
90%
10%
DL
t
D_OFF1
t
D_ON1
t
F
t
R
IN_L
(MAX15012B/D
MAX15013B/D)
V
IH
V
IL
t
D_OFF2
t
D_ON2
V
IH
IN_H
V
IL
90%
10%
DH
t
D_OFF3
t
D_ON3
t
F
t
R
t
t
= (t
= (t
- t
) or (t
) or (t
- t
) FOR "A/C" VERSION
- t ) FOR "B/D" VERSION
D_OFF3 D_OFF2
MATCH
D_ON3 D_ON1
D_OFF3 D_OFF1
- t
MATCH
D_ON3 D_ON2
Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs
_______________________________________________________________________________________
8
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
escent current. The maximum on-time is dependent on
Detailed Description
the size of C
, I
(40µA max), and UVLO
.
BST
BST BST
The MAX15012/MAX15013 are 175V/2A high-speed,
half-bridge MOSFET drivers that operate from a supply
voltage of +8V to +12.6V. The drivers are intended to
drive a high-side switch without any isolation device
like an optocoupler or drive transformer. The high-side
driver is controlled by a TTL/CMOS logic signal refer-
enced to ground. The 2A source and sink drive capa-
Output Driver
The MAX15012/MAX15013 have low 2.5Ω R p-
DS_ON
channel and n-channel devices (totem pole) in the out-
put stage. This allows for a fast turn-on and turn-off of the
high gate-charge switching MOSFETs. The peak source
and sink current is typically 2A. Propagation delays from
the logic inputs to the driver outputs are matched to
within 8ns. The internal p- and n-channel MOSFETs have
a 1ns break-before-make logic to avoid any cross con-
duction between them. This internal break-before-make
logic eliminates shoot-through currents reducing the
bility is achieved by using low R
, p- and
DS_ON
n-channel driver output stages. The BiCMOS process
allows extremely fast rise/fall times and low propaga-
tion delays. The typical propagation delay from the
logic-input signal to the driver output is 35ns with a
matched propagation delay of 2ns typical. Matching
these propagation delays is as important as the
absolute value of the delay itself. The high 175V input
voltage range allows plenty of margin above the 100V
transient specification per telecom standards.
operating supply current as well as the spikes at V
.
DD
See the Minimum Input Pulse Width section to under-
stand the effects of propagation delays on DH and DL.
The DL voltage is approximately equal to V , the DH-
DD
to-HS voltage is approximately equal to V
minus a
DD
diode drop, when they are in a high state and to zero
when in a low state. The driver R is lower at higher
The maximum operating supply voltage (V ) must be
DD
DS_ON
reduced linearly from 12.6V to 10.5V when the maxi-
V
. Lower R
means higher source and sink cur-
DD
DS_ON
mum voltage (V
) increases from 125V to 175V.
HS_MAX
rents and faster switching speeds.
See the Typical Operating Characteristics.
Internal Bootstrap Diode
Undervoltage Lockout
An internal diode connects from V to BST and is used
DD
Both the high- and low-side drivers feature undervolt-
age lockout (UVLO). The low-side driver’s UVLO
in conjunction with a bootstrap capacitor externally con-
nected between BST and HS. The diode charges the
when the DL low-side switch is on
when HS is pulled high as the high-
side driver turns on (see the Typical Operating Circuit).
LOW
threshold is referenced to GND and pulls both driver
outputs low when V falls below 6.8V. The high-side
capacitor from V
DD
DD
and isolates V
DD
driver has its own UVLO threshold (UVLO
), refer-
HIGH
enced to HS, and pulls DH low when BST falls below
6.4V with respect to HS.
The internal bootstrap diode has a typical forward volt-
age drop of 0.9V and has a 10ns typical turn-off/turn-on
During turn-on, once V
rises above its UVLO thresh-
DD
time. For lower voltage drops from V
to BST, connect
and BST.
DD
old, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
an external Schottky diode between V
DD
the BST-to-HS voltage is below UVLO . For synchro-
BST
Driver Logic Inputs (IN_H, IN_L)
The MAX15012A/B/C/D are CMOS (V /2) logic-input
DD
drivers while the MAX15013A/B/C/D have TTL-compati-
ble logic inputs. The logic-input signals are independent
of V . For example, the IC can be powered by a 10V
DD
nous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and nor-
mal operation begins in a few microseconds after the
BST-to-HS voltage exceeds UVLO . In the two-switch
BST
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
supply while the logic inputs are provided from a 12V
CMOS logic. Also, the logic inputs are protected against
voltage above UVLO
.
BST
voltage spikes up to 14V, regardless of the V
voltage.
DD
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected care-
fully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capaci-
tance of the MOSFET. Use a low-ESR-type X7R dielec-
tric ceramic capacitor at BST (typically a 0.1µF ceramic
capacitor is adequate) and a parallel combination of
The TTL and CMOS logic inputs have 250mV and 1.6V
hysteresis, respectively, to avoid double pulsing during
transition. The logic inputs are high-impedance pins and
should not be left floating. The low 2.5pF input capaci-
tance reduces loading and increases switching speed.
The noninverting inputs are pulled down to GND and the
inverting inputs are pulled up to V
internally using a
DD
1MΩ resistor. The PWM output from the controller must
assume a proper state while powering up the device.
With the logic inputs floating, the DH and DL outputs pull
1µF and 0.1µF ceramic capacitors from V
to GND.
DD
The high-side MOSFET’s continuous on-time is limited
due to the charge loss from the high-side driver’s qui-
low as V
rises up above the UVLO threshold.
DD
_______________________________________________________________________________________
9
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
At high duty cycle (close to 100%), the DH minimum low
pulse width (t ) must be higher than the DL min-
Minimum Input Pulse Width
The MAX15012/MAX15013 use a single-shot level-shifter
architecture to achieve low propagation delay. Typical
level shifter architecture causes a minimum (high or low)
Dmin-DH-L
imum low pulse width (t
) to avoid the overlap
Dmin-DL-L
and shoot-through. See Figure 3. In case of the
MAX15012/MAX15013, there is a possibility of about
40ns overlap if an external BBM delay is not provided. It
is recommended to add external delay in the INH path
so that the minimum low pulse width seen at INH is
pulse width (t
) at the output that may be higher than
Dmin
the logic-input pulse width. For the MAX15012/
MAX15013 devices, the DH minimum high pulse-width
(t
) is lower than the DL minimum low pulse
) to avoid any shoot-through in the
Dmin-DH-H
always longer than t
. See the Electrical
width (t
PW-min
Dmin-DL-L
Characteristics table for the typical values of t
.
absence of external BBM delay during the narrow pulse
at low duty cycle. See Figure 2.
PW-min
V
DD
V
IN
PW-MIN
INH
INL
DH
N
V
OUT
HS
DL
N
MAX15012B/
MAX15012D/
MAX15013B/
MAX15013D
PW-MIN
t
DMIN-DH-H
DH
IN-BUILT
DEAD TIME
DL
t
DMIN-DL-L
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-Cycle Input (On-Time < t
)
PW-min
10 ______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
V
DD
V
IN
EXTERNAL
BBM DELAY
PW-MIN
INH
INL
DH
N
N
V
OUT
HS
DL
MAX15012B/
MAX15012D/
MAX15013B/
MAX15013D
V
DD
V
IN
EXTERNAL
BBM DELAY
PW-MIN
INH
INL
DH
N
V
OUT
HS
DL
N
MAX15012A/C
MAX15013A/C
PW-MIN
EXTERNAL
BBM DELAY
t
DMIN-DH-L
DH
POTENTIAL
OVERLAP TIME
DL
t
DMIN-DL-H
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < t
)
PW-min
______________________________________________________________________________________ 11
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Layout Information
Applications Information
The MAX15012/MAX15013 drivers source and sink
large currents to create very fast rise and fall edges at
the gates of the switching MOSFETs. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. Use the following
PC board layout guidelines when designing with the
MAX15012/MAX15013:
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX15012/MAX15013. Peak supply and output cur-
rents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
• It is important that the V
voltage (with respect to
DD
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
ground return path. Any series inductance in the V
,
DD
from V
to GND or BST to HS can damage the
DD
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX15012/
MAX15013 with any capacitive load. Place one or more
0.1µF ceramic capacitors in parallel as close to the
device. Place one or more low ESL 0.1µF decou-
pling ceramic capacitors from V to GND, and
DD
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least 20
times the gate capacitance being driven.
device as possible to bypass V
to GND. Use a
DD
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX15012/MAX15013 to further min-
imize board inductance and AC path resistance.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET dri-
ver (either GND or HS). When the gate of the MOSFET
is being pulled high, the active current loop is from
the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor is either the flying capacitor
connected between BST and HS or the decoupling
Power Dissipation
Power dissipation in the MAX15012/MAX15013 is pri-
marily due to power loss in the internal boost diode and
the nMOS and pMOS FETs.
For capacitive loads, the total power dissipation for the
device is:
2
⎛
⎞
P = C × V
× f
+ I
(
⎠
+ I
× V
)
D
L
DD
SW
DDO
BSTO DD
⎝
where C is the combined capacitive load at DH and
L
DL. V
is the supply voltage and f
is the switching
SW
DD
frequency of the converter. P includes the power dis-
D
capacitor for V . Care must be taken to minimize the
DD
physical length and the impedance of these AC cur-
rent paths.
sipated in the internal bootstrap diode. The internal
power dissipation reduces by P
, if an external
DIODE
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) is the charge through the diode per switching
period multiplied by the maximum diode forward volt-
age drop (V = 1V).
f
P
≅ C
× V − 1 × f
× V
(
)
DIODE
DH
DD
SW f
The total power dissipation when using the internal
boost diode is P and, when using an external
D
Schottky diode, is P - P
. The total power dissi-
DIODE
D
pated in the device must be kept below the maximum
of 0.471W for the 8-pin SO package at T = +70°C
A
ambient.
12 ______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Application Circuits
V
= 8V TO 12.6V
V = 0 TO 175V*
IN
DD
V
DD
BST
DH
N
N
MAX15012A/C
MAX15013A/C
IN_H
IN_L
PWM
CONTROLLER
HS
DL
V
OUT
GND
PIN COMPATIBLE WITH THE HIP2100/HIP2101
*DERATE V IF V INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
DD
IN
Figure 4. MAX15012A/MAX15013A Half-Bridge Conversion
V
= 8V TO 12.6V
V
= 0 TO 175V*
DD
IN
C
BST
V
DD
BST
N
DH
HS
MAX15012A/C
MAX15013A/C
IN_H
IN_L
V
OUT
PWM
DL
N
GND
*DERATE V IF V INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
DD
IN
Figure 5. Two-Switch Forward Conversion
______________________________________________________________________________________ 13
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Functional Diagrams
MAX15012A/C
MAX15012B/D
V
DD
/2 CMOS
V
DD
/2 CMOS
BST
BST
2
2
3
IN_H
IN_L
IN_H
IN_L
DH
HS
DH
3
5
6
5
6
HS
4
4
1
V
V
DD
DD
1
DL
DL
8
8
GND
GND
7
7
SO
SO
MAX15013B/D
MAX15013A/C
TTL
TTL
BST
BST
2
3
2
3
IN_H
IN_L
IN_H
IN_L
DH
HS
DH
HS
5
6
5
6
4
1
4
1
V
V
DD
DD
DL
DL
8
8
GND
GND
7
7
SO
SO
14 ______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Typical Operating Circuit
V
IN
= 0 TO 175V*
V
DD
= 8V TO 12.6V
C
BST
V
DD
BST
N
N
DH
HS
DL
PWM
MAX15012B/D
MAX15013B/D
IN_H
IN_L
V
OUT
GND
*DERATE V IF V INCREASES ABOVE 125V. SEE NOTE 3 IN THE ELECTRICAL CHARACTERISTICS.
DD
IN
Pin Configurations
Ordering Information (continued)
PIN-
PKG
PART
TEMP RANGE
TOP VIEW
PACKAGE CODE
MAX15013AASA+ -40°C to +125°C 8 SO
S8-5
S8-5
+
V
1
2
3
4
8
7
6
5
DL
MAX15013BASA+ -40°C to +125°C 8 SO
DD
MAX15013CASA+* -40°C to +125°C 8 SO-EP** S8E+14
MAX15013DASA+* -40°C to +125°C 8 SO-EP** S8E+14
BST
DH
HS
GND
IN_L
IN_H
MAX15012A/B
MAX15013A/B
+Denotes lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
SO
Chip Information
TRANSISTOR COUNT: 790
+
V
1
2
3
4
8
7
6
5
DL
DD
PROCESS: HV BiCMOS
BST
DH
HS
GND
IN_L
IN_H
MAX15012C/D
MAX15013C/D
SO-EP
______________________________________________________________________________________ 15
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
MAX
MAX
1.75
0.25
0.49
0.25
DIM
A
MIN
MIN
1.35
0.10
0.35
0.19
0.053
0.004
0.014
0.007
0.069
0.010
0.019
0.010
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
MAX
0.197
0.344
0.394
MAX
5.00
DIM
D
MIN
MIN
4.80
8.55
9.80
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
16 ______________________________________________________________________________________
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD
1
21-0111
C
1
______________________________________________________________________________________ 17
175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
5/06
Initial release
—
Added exposed paddle versions of the MAX15012A/B and MAX15013A/B,
added Figures 2 and 3 and added SO-EP package outline
12/07
1–4, 8–11, 13–17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
Heaney
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