MAX1531ETJ+T [MAXIM]
Multiple-Output Power-Supply Controllers for LCD Monitors; 多路输出电源控制器，用于液晶显示器
| 型号： | MAX1531ETJ+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multiple-Output Power-Supply Controllers for LCD Monitors |
| 文件： | 总33页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2866; Rev 1; 11/09
Multiple-Output Power-Supply
Controllers for LCD Monitors
0/MAX531
General Description
Features
The MAX1530/MAX1531 multiple-output power-supply
controllers generate all the supply rails for thin-film tran-
sistor (TFT) liquid-crystal display (LCD) monitors. Both
devices include a high-efficiency, fixed-frequency,
step-down regulator. The low-cost, all N-channel, syn-
chronous topology enables operation with efficiency as
high as 93%. High-frequency operation allows the use
of small inductors and capacitors, resulting in a com-
pact solution. The MAX1530 includes three linear regu-
lator controllers and the MAX1531 includes five linear
regulator controllers for supplying logic and LCD bias
voltages. A programmable startup sequence enables
easy control of the regulators.
o 4.5V to 28V Input Voltage Range
o 250kHz/500kHz Current-Mode Step-Down Converter
Small Inductor/Capacitors
No Sense Resistor
o Three Positive Linear Regulator Controllers
One Positive and One Negative Additional
Controller (MAX1531)
Small Input and Output Capacitors
o Timed Reset Output
o Uncommitted Overcurrent Protection (MAX1531)
o Soft-Start for All Regulators
o Programmable Input Undervoltage Comparator
o Programmable Startup Sequencing
The MAX1530/MAX1531 include soft-start functions to
limit inrush current during startup. An internal step-
down converter current-limit function and a versatile
overcurrent shutdown protect the power supplies against
fault conditions. The MAX1530/MAX1531 use a current-
mode control architecture, providing fast load transient
response and easy compensation. An internal linear
regulator provides MOSFET gate drive and can be
used to power small external loads.
Minimal Operating Circuit
V
IN
V
P
V
IN
V
L
CSH
CSL
V
N
The MAX1530/MAX1531 can operate from inputs as
high as 28V and are well suited for LCD monitor and TV
applications running directly from AC/DC wall adapters.
Both devices are available in a small (5mm x 5mm),
ultra-thin (0.8mm), 32-pin QFN package and operate
over the -40°C to +85°C temperature range.
BST
IN
V
= 12V
IN
DRV4
FBL4
V
SOURCE
10V/500mA
DH
V
OUT
3.3V/1.5A
LX
MAX1530
Applications
DL
EN
LCD Monitors and TVs
Automotive LCDs
PGND
ILIM
FREQ
VL
V
L
FB
COMP
AGND
RESET
RSTIN
Ordering Information
V
IN
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
32 TQFN-EP*
DRV2
FBL2
V
OUT
MAX1530ETJ+
MAX1530ETJ+T
MAX1531ETJ+
MAX1531ETJ+T
MAX1531ETJ/V+
MAX1531ETJ/V+T
*EP = Exposed pad.
V
9.7V
GAMMA
DRV1
FBL1
V
LOGIC
2.5V/500mA
ONL2
ONL3
ONL4
ONL5
V
L
SEQ
V
P
V
N
+Denotes lead(Pb)-free/RoHS-compliant package.
/V indicates an automotive-qualified part.
T indicates tape and reel.
DRV3
FBL3
DRV5
FBL5
V
GON
25V
V
GOFF
-9V
Pin Configuration appears at end of data sheet.
VL
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Multiple-Output Power-Supply
Controllers for LCD Monitors
ABSOLUTE MAXIMUM RATINGS
IN, DRV1, DRV2, DRV3, DRV4, CSH,
SEQ, ONL2, ONL3, ONL4, ONL5, COMP,
CSL to AGND .....................................................-0.3V to +30V
DRV5 to VL .............................................................-28V to +0.3V
CSH to CSL ..............................................................-0.3V to +6V
VL to AGND..............................................................-0.3V to +6V
PGND to AGND................................................................... 0.3V
LX to BST..................................................................-6V to +0.3V
BST to AGND..........................................................-0.3V to +36V
DH to LX .....................................................-0.3V to (BST + 0.3V)
DL to PGND ..................................................-0.3V to (VL + 0.3V)
ILIM to AGND............................................-0.3V to (VL + 0.3V)
RSTIN, RESET, EN, FB, FBL1, FBL2, FBL3, FBL4, FBL5,
FREQ to AGND.....................................................-0.3V to +6V
VL Short Circuit to AGND ...........................................Momentary
Continuous Power Dissipation (T = +70°C)
A
32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ...1702mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
EN
SEQ
A
A
0/MAX531
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
Operating Input Voltage Range
Quiescent Supply Current
IC Disable Supply Current
VL REGULATOR
(Note 1)
4.5
28.0
3.0
V
V
= V
= V
= V
= V
= 1.5V, V = 0
FBL5
1.7
mA
µA
FB
FBL1
FBL2
FBL3
FBL4
EN = AGND
200
400
VL Output Voltage
5.5V < V < 28V, 0 < I < 30mA
4.75
3.2
5
5.25
3.8
V
V
IN
VL
VL Undervoltage Lockout
Threshold
VL rising, 3% hysteresis
3.5
CONTROL AND SEQUENCE
SEQ, FREQ Input Logic High
Level
2.0
-1
V
V
SEQ, FREQ Input Logic Low
Level
0.6
+1
SEQ, FREQ Input Leakage
Current
µA
ONL_ Input Threshold
ONL_ Source Current
ONL_ rising, 25mV hysteresis
1.201
1.8
1.238
2.0
1.275
2.2
V
SEQ = EN = VL, V
_ = 0 to 1.24V
µA
nA
ONL
ONL_ Input Leakage Current
SEQ = EN = VL, ONL_ = VL
-500
+500
ONL_ Input Discharge Clamp
Resistance
SEQ = 0
800
1500
3000
Ω
EN Input Threshold
EN rising, 5% hysteresis
1.201
-50
1.238
1.275
+50
V
EN Input Leakage Current
FAULT DETECTION
nA
FB, FBL1, FBL2, FBL3, FBL4
Undervoltage Fault Trip Level
FB, FBL1, FBL2, FBL3, FBL4 falling, 25mV hysteresis
FBL5 rising, 25mV hysteresis
1.081
300
1.114
400
1.147
500
V
FBL5 Undervoltage Fault
Trip Level
mV
2
_______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
ELECTRICAL CHARACTERISTICS (continued)
0/MAX531
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
EN
SEQ
A
A
PARAMETER
CONDITIONS
MIN
TYP
10
MAX
UNITS
kHz
ms
Comparator Bandwidth
Duration to Trigger Fault Latch
For EN, FB, FBL_
For FB, FBL_
51
64
77
Overcurrent Protection Threshold (V
- V
)
270
300
330
mV
CSH
CSL
Overcurrent Sense Common-
Mode Range
V
, V
CSH CSL
2.7
28.0
V
CSH Input Current
CSL Input Current
V
V
= 2.7V to 28V
100
+50
µA
nA
CSH
CSL
= V
= 12V
-50
CSH
Overcurrent Sense Filter RC Time
Constant
50
µs
THERMAL PROTECTION
Thermal Shutdown
Temperature rising, 15°C hysteresis
RSTIN falling, 25mV hysteresis
160
°C
RESET FUNCTION
RSTIN Reset Trip Level
RSTIN Input Leakage Current
Comparator Bandwidth
Reset Timeout Period
1.081
-50
1.114
1.147
+50
V
nA
kHz
ms
V
V
= 1.5V
RSTIN
10
102
128
154
0.4
1
RESET Output Low Level
RESET Output High Leakage
I
= -1mA
= 5V
RESET
V
µA
RESET
STEP-DOWN CONTROLLER
ERROR AMPLIFIER
FB Regulation Voltage
Transconductance
1.223
70
1.238
100
200
15
1.253
140
V
µS
V/V
%
nA
V
FB to COMP
FB to COMP
Voltage Gain
Minimum Duty Cycle
FB Input Leakage Current
FB Input Common-Mode Range
COMP Output Minimum Voltage
COMP Output Maximum Voltage
V
= 1.5V
-50
+50
FB
(Note 2)
-0.1
+1.5
V
V
= 1.5V
1
3
V
FB
FB
= 1.175V
V
Current-Sense Amplifier Voltage
Gain
V
- V
2.75
190
3.5
4.0
V/V
mV
IN
LX
Current-Limit Threshold
(Default Mode)
PGND - LX, ILIM = VL
250
310
Current-Limit Threshold
(Adjustable Mode)
PGND - LX, V
= 1.25V
190
3.0
250
3.5
310
mV
V
ILIM
ILIM Input Dual Mode™ Threshold
4.00
OSCILLATOR
FREQ = AGND
FREQ = VL
200
425
75
250
500
80
300
575
88
Switching Frequency
Maximum Duty Cycle
kHz
%
FREQ = AGND
FREQ = VL
75
80
88
Dual Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
3
Multiple-Output Power-Supply
Controllers for LCD Monitors
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
EN
SEQ
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Step Size
Measured at FB
FREQ = GND
FREQ = VL
1.238 / 32
V
s
1024 / f
2048 / f
OSC
OSC
Period
FET DRIVERS
DH, DL On-Resistance
DH, DL Output Drive Current
LX, BST Leakage Current
3
10
20
Ω
A
Sourcing or sinking, V
or V = V / 2
0.5
DH
DL
VL
V
= V = V = 28V
µA
BST
LX
IN
LINEAR REGULATOR CONTROLLERS
POSITIVE LINEAR REGULATOR (LR1)
FBL1 Regulation Voltage
FBL1 Input Bias Current
V
V
= 5V, I
= 1.5V
= 100µA
1.226
-50
1.245
-1.5
1.264
+50
V
DRV1
FBL1
DRV1
nA
0/MAX531
FBL1 Effective Load Regulation
Error (Transconductance)
V
= 5V, I
= 100µA to 2mA
-2
5
%
DRV1
DRV1
DRV1
FBL1 Line Regulation Error
DRV1 Sink Current
I
= 100µA, 5.5V < V < 28V
mV
mA
µA
IN
V
V
= 1.175V, V
= 5V
3
10
FBL1
FBL1
DRV1
DRV1 Off-Leakage Current
= 1.5V, V
= 28V
0.1
10
DRV1
FBL1 Input Common-Mode
Range
(Note 2)
-0.1
+1.5
V
V
s
Soft-Start Step Size
Measured at FBL1
FREQ = GND
FREQ = VL
1.238 / 32
1024 / f
2048 / f
OSC
OSC
Soft-Start Period
POSITIVE LINEAR REGULATORS (LR2 AND LR3)
FBL_ Regulation Voltage
FBL_ Input Bias Current
V
V
_ = 5V, I
_ = 100µA
1.226
-50
1.245
-1.5
1.264
+50
V
DRV
DRV
_ = 1.5V
nA
FBL
FBL_ Effective Load Regulation
Error (Transconductance)
V
_ = 5V, I
DRV
_ = 50µA to 1mA
DRV
-2
5
%
FBL_ Line Regulation Error
DRV_ Sink Current
I
_ = 100µA, 5.5V < V < 28V
mV
mA
µA
DRV
IN
V
V
= 1.175V, V
= 5V
2
4
FBL_
DRV_
DRV_ Off-Leakage Current
_ = 1.5V, V
_ = 28V
DRV
0.1
10
FBL
FBL_ Input Common-Mode
Range
(Note 2)
Measured at FBL_
-0.1
+1.5
V
V
Soft-Start Step Size
1.238 / 32
4
_______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
IN
EN
SEQ
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FREQ = GND
FREQ = VL
1024 / f
2048 / f
OSC
OSC
Soft-Start Period
s
POSITIVE LINEAR REGULATOR (LR4)
FBL4 Regulation Voltage
FBL4 Input Bias Current
V
V
= 5V, I
= 1.5V
= 500µA
1.226
-50
1.245
-1.5
1.264
+50
V
DRV4
FBL4
DRV4
nA
FBL4 Effective Load Regulation
Error (Transconductance)
V
= 5V, I
= 500µA to 10mA
-2
5
%
DRV4
DRV4
DRV4
FBL4 Line Regulation Error
DRV4 Sink Current
I
= 500µA, 5.5V < V < 28V
mV
mA
µA
IN
V
V
= 1.175V, V
= 5V
10
28
FBL4
FBL4
DRV4
DRV4_Off-Leakage Current
= 1.5V, V
= 28V
0.1
10
DRV4
FBL4 Input Common-Mode
Range
(Note 2)
-0.1
+1.5
V
V
s
Soft-Start Step Size
Measured at FBL4
FREQ = GND
FREQ = VL
1.238 / 32
1024 / f
2048 / f
OSC
OSC
Soft-Start Period
NEGATIVE LINEAR REGULATOR (LR5)
FBL5 Regulation Voltage
FBL5 Input Bias Current
V
V
= -10V, I
= 0
= 100µA
100
-50
125
-1.5
150
+50
mV
nA
DRV5
FBL5
DRV5
DRV5
FBL5 Effective Load Regulation
Error (Transconductance)
V
= -10V, I
= 50µA to 1mA
-2
5
%
DRV5
DRV5
FBL5 Line Regulation Error
DRV5 Source Current
I
= 100µA, 5.5V < V < 28V
mV
mA
µA
IN
V
V
= 200mV, V
= -10V
2
9
FBL5
FBL5
DRV5
DRV5 Off-Leakage Current
= 0, V
= -20V
0.1
10
DRV5
FBL5 Input Common-Mode
Range
(Note 2)
-0.1
+1.5
V
V
s
Soft-Start Step Size
Measured at FBL5
FREQ = AGND
FREQ = VL
1.238 / 32
1024 / f
2048 / f
OSC
OSC
Soft-Start Period
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
IN
EN
SEQ
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL
Operating Input Voltage Range
VL REGULATOR
(Note 1)
4.5
28.0
V
VL Output Voltage
5.5V < V < 28V, 0 < I < 30mA
4.75
3.2
5.25
3.8
V
V
IN
VL
VL Undervoltage Lockout
Threshold
VL rising, 3% hysteresis
_______________________________________________________________________________________
5
Multiple-Output Power-Supply
Controllers for LCD Monitors
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V = V
= 5V, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
A
IN
EN
SEQ
PARAMETER
CONTROL AND SEQUENCE
ONL_ Input Threshold
EN Input Threshold
CONDITIONS
MIN
TYP
MAX
UNITS
ONL_ rising, 25mV hysteresis
EN rising, 5% hysteresis
1.201
1.201
1.275
1.275
V
V
FAULT DETECTION
FB, FBL1, FBL2, FBL3, FBL4
Fault Trip Level
FB, FBL1, FBL2, FBL3, FBL4 falling, 25mV hysteresis
FBL5 rising, 25mV hysteresis
1.081
1.147
V
FBL5 Fault Trip Level
300
270
500
330
mV
mV
Overcurrent Protection Threshold (V
- V
)
CSH
CSL
RESET FUNCTION
RSTIN Reset Trip Level
RSTIN falling, 25mV hysteresis
STEP-DOWN CONTROLLER
1.081
1.147
V
ERROR AMPLIFIER
0/MAX531
FB Regulation Voltage
1.215
170
1.260
330
V
Current-Limit Threshold
(Default Mode)
PGND - LX, ILIM = VL
mV
Current-Limit Threshold
(Adjustable Mode)
PGND - LX, V
= 1.25V
170
330
mV
ILIM
LINEAR REGULATOR CONTROLLERS
POSITIVE LINEAR REGULATOR (LR1)
FBL1 Regulation Voltage
FBL1 Input Bias Current
V
V
= 5V, I
= 100µA
DRV1
1.220
-50
1.270
+50
V
DRV1
FBL1
= 1.5V
nA
POSITIVE LINEAR REGULATORS (LR2 AND LR3)
FBL_ Regulation Voltage
FBL_ Input Bias Current
V
V
_ = 5V, I
_ = 100µA
DRV
1.220
-50
1.270
+50
V
DRV
_ = 1.5V
nA
FBL
POSITIVE LINEAR REGULATOR (LR4)
FBL4 Regulation Voltage
FBL4 Input Bias Current
V
V
= 5V, I
= 1.5V
= 500µA
1.220
-50
1.270
+50
V
DRV4
FBL4
DRV4
nA
NEGATIVE LINEAR REGULATOR (LR5)
FBL5 Regulation Voltage
FBL5 Input Bias Current
DRV5 Source Current
V
V
V
= -10V, I
= 0
= 100µA
DRV5
100
-50
2
150
+50
mV
nA
DRV5
FBL5
FBL5
= 200mV, V
= -10V
mA
DRV5
Note 1: Operating supply range is guaranteed by VL line regulation test for the range of 5.5V to 28V. Between 4.5V and 5.5V, the V
L
regulator might be in dropout; however, the part continues to operate properly.
Note 2: Guaranteed by design and not production tested.
Note 3: Specifications to -40°C are guaranteed by design and not production tested.
6
_______________________________________________________________________________________
Multiple-Output Power-Supply
Controllers for LCD Monitors
0/MAX531
Typical Operating Characteristics
(Circuit of Figure 1; including R5, R6, and D2; T = +25°C, unless otherwise noted.)
A
STEP-DOWN EFFICIENCY vs. LOAD CURRENT
STEP-DOWN LOAD REGULATION
SWITCHING FREQUENCY vs. LOAD CURRENT
520
100
90
80
70
60
50
0
f
= 500kHz
SW
515
510
505
500
495
490
485
480
-0.04
-0.08
-0.12
-0.16
V
= 12V
IN
V
= 20V
IN
0
300
600
900
1200
1500
0
300
600
900
1200
1500
0
300
600
900
1200
1500
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
STEP-DOWN REGULATOR
SWITCHING WAVEFORM
STEP-DOWN REGULATOR
SOFT-START
STEP-DOWN REGULATOR LOAD TRANSIENT
MAX1530 toc05
MAX1530 toc06
MAX1530 toc04
A
A
B
A
B
C
0V
0V
0A
B
3.3V
3.3V
0V
0A
C
C
0A
0A
2µs/div
1ms/div
40µs/div
A: LOAD CURRENT, 1A/div
B: OUTPUT VOLTAGE, 200mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 1A/div
A: LX, 10V/div
A: EN, 2V/div
B: OUTPUT VOLTAGE, 20 mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 1A/div
B: OUTPUT VOLTAGE, 2V/div
C: INDUCTOR CURRENT, 1A/div
LR1 BASE CURRENT
vs. DRV1 VOLTAGE
STARTUP SEQUENCE
VL LOAD REGULATION
MAX1530 toc08
0
-0.1
-0.2
-0.3
-0.4
-0.5
15
12
9
A
B
V
= 1.175V
FBL1
C
D
E
6
F
3
G
0
4ms/div
0
5
10
15
20
25
30
0
2
4
6
8
10
A: V , 10V/div
B: V , 5V/div
OUT
E: V
, 20V/div
GAMMA
L
LOAD CURRENT (mA)
DRV1 VOLTAGE (V)
F: V
GOFF
, 20V/div
C: V
D: V
, 5V/div
G: V , 40V/div
GON
LOGIC
, 20V/div
SOURCE
_______________________________________________________________________________________
7
Multiple-Output Power-Supply
Controllers for LCD Monitors
Typical Operating Characteristics (continued)
(Circuit of Figure 1; including R5, R6, and D2; T = +25°C, unless otherwise noted.)
A
LR1 NORMALIZED LOAD REGULATION
LR1 NORMALIZED LINE REGULATION
LR1 LOAD TRANSIENT
MAX1530 toc12
0
-0.5
-1.0
-1.5
-2.0
0.2
0
A
2.5V
-0.2
-0.4
-0.6
-0.8
-1.0
B
0mA
200mA LOAD CURRENT
0
100
200
300
400
500
2
3
4
5
6
40µs/div
A: LR1 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: LR1 LOAD CURRENT, 500mA/div
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
0/MAX531
LR2/LR3 BASE CURRENT
vs. DRV2/DRV3 VOLTAGE
LR2 NORMALIZED LOAD REGULATION
LR2 NORMALIZED LINE REGULATION
0
-0.3
-0.6
-0.9
-1.2
-1.5
0.2
0
5
4
3
2
1
0
V
= V
FBL3
= 1.175V
FBL2
-0.2
-0.4
-0.6
-0.8
-1.0
20mA LOAD CURRENT
0
10
20
30
40
50
9
13
17
21
25
0
1
2
3
4
5
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
DRV2/DRV3 VOLTAGE (V)
LR4 BASE CURRENT
vs. DRV VOLTAGE
LR3 NORMALIZED LOAD REGULATION
LR3 NORMALIZED LINE REGULATION
0
-0.5
-1.0
-1.5
-2.0
0.2
0
30
25
20
15
10
5
V
= 1.175V
FBL4
-0.2
-0.4
-0.6
-0.8
-1.0
20mA LOAD CURRENT
0
0
4
8
12
16
20
24
28
32
36
40
0
2
4
6
8
10
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
DRV4 VOLTAGE (V)
8
_______________________________________________________________________________________
Multiple-Output Power-Supply
Controllers for LCD Monitors
0/MAX531
Typical Operating Characteristics (continued)
(Circuit of Figure 1; including R5, R6, and D2; T = +25°C, unless otherwise noted.)
A
LR4 NORMALIZED LINE REGULATION
LR4 NORMALIZED LOAD REGULATION
0.2
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.2
-0.4
-0.6
-0.8
-1.0
200mA LOAD CURRENT
9
13
17
21
25
0
100
200
300
400
500
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
LR4 PULSED LOAD TRANSIENT
LR4 LOAD TRANSIENT
MAX1530 toc22
MAX1530 toc21
A
B
A
B
10V
10V
0A
0mA
10µs/div
40µs/div
A: LR4 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: LR4 LOAD CURRENT, 1A/div
A: LR4 OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: LR4 LOAD CURRENT, 500mA/div
MAX1531
LR5 BASE CURRENT
vs. DRV5 VOLTAGE
OVERCURRENT PROTECTION (CSH, CSL)
MAX1530 toc23
10
8
V
= 0V
FBL5
A
B
6
4
C
D
2
0
0
1
2
3
4
5
20µs/div
A: V , 10V/div
LX
B: V , 5V/div
OUT
C: V
, 5V/div
- V , 500mV/div
CSL
RESET
DRV5 VOLTAGE (V)
D: V
CSH
_______________________________________________________________________________________
9
Multiple-Output Power-Supply
Controllers for LCD Monitors
Typical Operating Characteristics (continued)
(Circuit of Figure 1; including R5, R6, and D2; T = +25°C, unless otherwise noted.)
A
LR5 NORMALIZED LOAD REGULATION
LR5 NORMALIZED LINE REGULATION
0
-0.2
-0.4
-0.6
-0.8
-1.0
1.0
0.8
0.6
0.4
0.2
0
20mA LOAD CURRENT
-0.2
0
10
20
30
40
50
-25
-21
-17
-13
-9
0/MAX531
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
Pin Description
PIN
NAME
FUNCTION
MAX1530
MAX1531
Gamma Linear Regulator (LR2) Base Drive. Open drain of an internal N-channel MOSFET.
Connect DRV2 to the base of an external PNP pass transistor to form a positive linear
regulator. (See the Pass Transistor Selection section.)
1
1
DRV2
FBL2
FBL3
Gamma Linear Regulator (LR2) Feedback Input. FBL2 regulates at 1.245V nominal.
Connect FBL2 to the center tap of a resistive voltage-divider between the LR2 output and
AGND to set the output voltage. Place the divider close to the FBL2 pin.
2
3
4
2
3
Gate-On Linear Regulator (LR3) Feedback Input. FBL3 regulates at 1.245V nominal.
Connect FBL3 to the center tap of a resistive voltage-divider between the LR3 output and
AGND to set the output voltage. Place the divider close to the FBL3 pin.
Gate-On Linear Regulator (LR3) Base Drive. Open drain of an internal N-channel MOSFET.
Connect DRV3 to the base of an external PNP pass transistor to form a positive linear
regulator. (See the Pass Transistor Selection section.)
4
DRV3
N. C.
5–10, 18, 19
—
No Connection. Not internally connected.
Adjustable Reset Input. RESET asserts low when the monitored voltage is less than the
reset trip threshold. RESET goes to a high-impedance state only after the monitored
voltage remains above the reset trip threshold for the duration of the reset timeout period.
Connect RSTIN to the center tap of a resistive voltage-divider between the monitored
output voltage and AGND to set the reset trip threshold. The internal RSTIN threshold of
90% of 1.238V allows direct connection of RSTIN to any of the device’s positive feedback
pins.
11
11
RSTIN
10 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1530
MAX1531
Open-Drain Reset Output. RESET asserts low when the monitored voltage is less than the
reset trip threshold. RESET goes to a high-impedance state only after the monitored
12
12
RESET voltage remains above the reset trip threshold for the duration of the reset timeout period.
RESET also asserts low when VL is less than the VL undervoltage lockout threshold, EN is
low, or the thermal, overcurrent or undervoltage fault latches are set.
Step-Down Regulator Compensation Input. A pole-zero pair must be added to
compensate the control loop by connecting a series resistor and capacitor from COMP to
AGND. (See the Compensation Design section.)
13
14
13
14
COMP
FB
Step-Down Regulator Feedback Input. FB regulates at 1.238V nominal. Connect FB to the
center tap of a resistive voltage-divider between the step-down regulator output and
AGND to set the output voltage. Place the divider close to the FB pin.
Step-Down Regulator Current-Limit Control Input. Connect this dual-mode input to VL to
set the current-limit threshold to its default value of 250mV. The overcurrent comparator
compares the voltage across the low-side N-channel MOSFET with the current-limit
threshold. Connect ILIM to the center tap of a resistive voltage-divider between VL and
AGND to adjust the current-limit threshold to other values. In adjustable mode, the actual
current-limit threshold is 1/5th of the voltage at ILIM over a 0.25V to 3.0V range. The dual-
mode threshold for switchover to the 250mV default value is approximately 3.5V.
15
16
17
15
16
17
ILIM
ONL2
ONL3
Gamma Linear Regulator (LR2) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL2 is greater than the internal reference, LR2 is
enabled. Drive ONL2 with a logic signal or, for automatic sequencing, connect a capacitor
from ONL2 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
Gate-On Linear Regulator (LR3) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL3 is greater than the internal reference, LR3 is
enabled. Drive ONL3 with a logic signal or, for automatic sequencing, connect a capacitor
from ONL3 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
20
21
20
21
PGND
DL
Power Ground
Low-Side Gate Driver Output. DL drives the synchronous rectifier of the step-down
regulator. DL swings from PGND to VL. DL remains low until VL rises above the UVLO
threshold.
Step-Down Regulator Current-Sense Input. The IC’s current-sense amplifier inputs for
current-mode control connect to IN and LX. Connect IN and LX directly to the high-side N-
channel MOSFET drain and source, respectively. The low-side current-limit comparator
inputs connect to LX and PGND to sense voltage across a low-side N-channel MOSFET.
22
22
LX
______________________________________________________________________________________ 11
Multiple-Output Power-Supply
Controllers for LCD Monitors
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1530
MAX1531
High-Side Gate Driver Output. DH drives the main switch of the step-down regulator. DH
swings from LX to BST.
23
23
DH
BST
Step-Down Regulator Boostrap Capacitor Connection for High-Side Gate Driver. Connect
a 0.1µF ceramic capacitor from BST to LX.
24
25
26
24
25
26
Sequence Control Input for LR2, LR3, LR4, and LR5. Controls the current sources and
switches that charge and discharge the capacitors connected to the ONL_ pins.
SEQ
FREQ
Oscillator Frequency Select Input. Connect FREQ to VL for 500kHz operation. Connect
FREQ to AGND for 250kHz operation.
Main Input Voltage (+4.5V to 28V). Bypass IN to AGND with a 1µF ceramic capacitor
close to the pins. IN powers the VL linear regulator. Connect IN to the drain of the high-
side MOSFET (for current sense) through a 1Ω resistor.
27
27
IN
0/MAX531
Internal 5V Linear Regulator Output. Connect a minimum 1µF ceramic capacitor from VL
to AGND. Place the capacitor close to the pins. VL can supply up to 30mA for gate drive
and external loads. VL remains active when EN is low.
28
29
28
29
VL
AGND Analog Ground
Enable Input. This general-purpose on/off control input has an accurate 1.238V (typ) rising
threshold with 5% hysteresis. This allows EN to monitor an input voltage level or other
analog parameter. If EN is less than its threshold, then the main step-down and all linear
regulators are turned off. VL and the internal reference remain active when EN is low. The
rising edge of EN clears any latched faults except for a thermal fault, which is cleared only
by cycling the input power. An internal filter with a 10µs time constant prevents short
glitches from accidentally clearing the fault latch.
30
30
EN
Low-Voltage Logic Linear Regulator (LR1) Feedback Input. FBL1 regulates at 1.245V
nominal. Connect FBL1 to the center tap of a resistive voltage-divider between LR1 output
AGND to set the output voltage. Place the divider close to the FBL1 pin. LR1 starts
automatically after the step-down converter soft-start ends.
31
32
31
32
FBL1
DRV1
Low-Voltage Logic Linear Regulator (LR1) Base Drive. Open drain of an internal N-channel
MOSFET. Connect DRV1 to the base of an external PNP pass transistor. (See the Pass
Transistor Selection section.)
Overcurrent Protection Positive Input. CSH is also the supply input for the overcurrent
sense block. CSH and CSL can be used to sense any current in the application circuit and
to shut the device down in an overcurrent condition. This feature is typically used to
protect the main input or the input to one of the linear regulators since they do not have
their own current limits. Insert an appropriate sense resistor in series with the protected
input and connect CSH and CSL to its positive and negative terminals. The controller sets
—
—
5
6
CSH
CSL
the fault latch when V
- V
exceeds the 300mV (typ) overcurrent threshold. An
CSH
CSL
internal lowpass filter prevents large currents of short duration (less than 50µs) or noise
glitches from setting the latch. If the overcurrent protection is not used, connect CSH and
CSL to VL.
Overcurrent Protection Negative Input. See CSH above.
12 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1530
MAX1531
Source Drive Linear Regulator (LR4) Feedback Input. FBL4 regulates at 1.245V nominal.
Connect FBL4 to the center tap of a resistive voltage-divider between the LR4 output and
AGND to set the output voltage. Place the divider close to the FBL4 pin.
—
7
FBL4
Source Drive Linear Regulator (LR4) Base Drive. Open drain of an internal N-channel
MOSFET. Connect DRV4 to the base of an external PNP pass transistor to form a positive
linear regulator. (See the Pass Transistor Selection section.)
—
—
—
8
9
DRV4
FBL5
DRV5
Gate-Off Linear Regulator (LR5) Feedback Input. FBL5 regulates at 125mV nominal.
Connect FBL5 to the center tap of a resistive voltage-divider between the LR5 output and
the internal 5V linear regulator output (VL) to set the output voltage. Place the divider close
to the FBL5 pin.
Gate-Off Linear Regulator (LR5) Base Drive. Open drain of an internal P-channel MOSFET.
Connect DRV5 to the base of an external NPN pass transistor to form a negative linear
voltage regulator. (See the Pass Transistor Selection section.)
10
Source Drive Linear Regulator (LR4) Enable Input. When EN is above its enable threshold,
VL is above its UVLO threshold, and ONL4 is greater than the internal reference, LR4 is
enabled. Drive ONL4 with a logic signal or, for automatic sequencing, connect a capacitor
from ONL4 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
—
18
ONL4
Gate-Off Linear Regulator (LR5) Enable Input. When EN is above its enable threshold, VL
is above its UVLO threshold, and ONL5 is greater than the internal reference, LR5 is
enabled. Drive ONL5 with a logic signal or, for automatic sequencing, connect a capacitor
from ONL5 to AGND. If SEQ is high, EN is above its threshold, and VL is above its UVLO
threshold, an internal 2µA (typ) current source charges the capacitor. Otherwise, an
internal switch discharges the capacitor. Connecting various capacitors to each ONL_ pin
allows the programming of the startup sequence.
—
—
19
—
ONL5
EP
Exposed Paddle. Internally connected to GND. Connect EP to a large ground plane to
improve thermal dissipation. Do not use as the main ground connection of the IC.
______________________________________________________________________________________ 13
Multiple-Output Power-Supply
Controllers for LCD Monitors
V
IN
= 12V
C3
4.7μF
25V
R3
D1
C5
0.1μF
R5*
10Ω
124kΩ
1%
R4
20.0kΩ
1%
IN
24
BST
R12
1Ω
30
27
23
22
21
EN
VL
IN
DH
LX
C1
1μF
V
L
5V/30mA
28
26
25
12
16
N1-A
N1-B
C4
1μF
V
OUT
L1
10μH
3.3V/1.5A
FREQ
SEQ
C7
22μF
6.3V
C23
150pF
R1
R6*
10Ω
17.8kΩ
R7
100kΩ
1%
DL
RESET
ONL2
R2
10.7kΩ
1%
D2*
20
29
R8
6.8kΩ
C22
2.2μF
PGND
AGND
0/MAX531
R14
121kΩ
1%
17
18
19
ONL3
ONL4
ONL5
32
31
MAX1531
DRV1
FBL1
Q1
V
LOGIC
R15
68.1kΩ
1%
2.5V/500mA
C9
10μF
6.3V
R9
10kΩ
1%
R10
10kΩ
1%
R16
43.2kΩ
1%
11
14
RSTIN
FB
VL
C10
470pF
R11
100kΩ
C11
0.1μF
13
15
R12
300kΩ
COMP
ILIM
R17
6.8kΩ
V
IN
C2, OPEN
C20
0.1μF
D4
D3
R13
1
2
Q2
DRV2
FBL2
V
150kΩ
IN
R18
68.1kΩ
1%
C15
C8
0.1μF
V
GAMMA
C14
C6
0.1μF
0.1μF
R24
6.8kΩ
9.7V/50mA
0.1μF
LX
C12
0.47μF
4
R19
10kΩ
1%
DRV3
FBL3
Q3
R25
200kΩ
Q6
V
GON
25V/20mA
IN
1%
3
6
5
CSL
CSH
C16
0.47μF
R26
10.5kΩ
1%
V
IN
R20
0.5Ω
1%
D5
C21
2.2μF
C18
0.1μF
C17
0.1μF
R27
6.8kΩ
R21
1.5kΩ
LX
8
7
10
9
Q4
DRV4
FBL4
DRV5
FBL5
Q5
R28
90.9kΩ
1%
R22
75kΩ
1%
V
GOFF
V
SOURCE
10V/500mA
-9V/50mA
C19
0.47μF
C13
4.7μF
16V
D6
R23
10.7kΩ
1%
R29
48.7kΩ
1%
VL
*OPTIONAL
Figure 1. MAX1531 Standard Application Circuit
14 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
V
IN
= 12V
C3
4.7μF
25V
D1
R3
124kΩ
1%
C5
0.1μF
R5*
10Ω
R4
20.0kΩ
1%
IN
24
BST
R12
1Ω
30
27
23
22
21
EN
VL
IN
DH
LX
C1
1μF
V
L
5V/30mA
28
26
25
N1-A
N1-B
C4
1μF
V
OUT
L1
10μH
3.3V/1.5A
FREQ
SEQ
C7
22μF
6.3V
R1
C23
150pF
R6*
10Ω
17.8kΩ
R7
100kΩ
1%
DL
12
16
RESET
ONL2
R2
10.7kΩ
1%
C22
2.2μF
D2*
20
29
R8
PGND
AGND
MAX1530
6.8kΩ
R14
121kΩ
1%
17
32
31
ONL3
DRV1
FBL1
Q1
V
LOGIC
C11
0.1μF
2.5V/500mA
5
6
7
8
N.C.
N.C.
N.C.
N.C.
C9
10μF
6.3V
R10
10kΩ 10kΩ
1%
R9
11
14
RSTIN
FB
1%
VL
C10
470pF
R11
100kΩ
13
15
R12
300kΩ
COMP
ILIM
R17
6.8kΩ
V
IN
C2, OPEN
C20
0.1μF
1
2
R13
150kΩ
Q2
DRV2
FBL2
V
IN
R18
68.1kΩ
1%
C21
2.2μF
V
GAMMA
9.7V/50mA
R24
6.8kΩ
4
3
R19
10kΩ
1%
C12
0.47μF
DRV3
FBL3
Q4
R22
75kΩ
1%
V
SOURCE
10V/500mA
C13
4.7μF
R23
10.7kΩ
1%
9
19
18
N.C.
N.C.
N.C.
N.C.
10
*OPTIONAL
Figure 2. MAX1530 Standard Application Circuit
______________________________________________________________________________________ 15
Multiple-Output Power-Supply
Controllers for LCD Monitors
Table 1. Selected Component List
DESIGNATION
DESCRIPTION
DESIGNATION
DESCRIPTION
200mA, 25V dual Schottky diodes (SOT23)
Fairchild BAT54S
4.7µF, 25V X7R ceramic capacitor (1210)
TDK C3225X7R1E475K
D3*, D4*, D5*
C3
10µH, 2.3A (DC) inductor
Sumida CDR7D28MN-100
22µF, 6.3V X7R ceramic capacitor
TDK C3216X7R0J226M
L1
C7
C9
10µF, 6.3V X5R ceramic capacitor
TDK C2012X5R0J106M
2.5A, 30V dual N-channel MOSFET (6-pin
Super SOT)
N1
Fairchild FDC6561AN
0.47µF, 16V X7R ceramic capacitors (0805)
TDK C2012X7R1C474K
C12, C19*
C13
3A, 60V low-saturation PNP bipolar transistors
(SOT-223)
Fairchild NZT660A
Q1, Q4
4.7µF, 16V X7R ceramic capacitor
TDK C3216X7R1C475K
200mA, 40V PNP bipolar transistors (SOT23)
Fairchild MMBT3906
2.2µF, 25V X7R ceramic capacitors (1206)
TDK C3216X7R1C475M
Q2, Q3*
C21, C22
0/MAX531
200mA, 40V NPN bipolar transistors (SOT23)
Fairchild MMBT3904
100mA, 30V Schottky diodes (SOD523)
Central Semiconductor CMOSH-3
Q5*, Q6*
D1, D6*
D2
100mA, 75V, small-signal switching diode,
SOT23 Fairchild Semiconductor MMBD4148
*For MAX1531 only.
Table 2. Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
Central Semi
516-435-1110
888-522-5372
847-956-0666
847-803-6100
516-435-1824
972-910-8036
847-956-0702
847-390-4405
www.centralsemi.com
www.fairchildsemi.com
www.sumida.com
Fairchild
Sumida
TDK
www.components.tdk.com
Standard Application Circuit
Detailed Description
The standard application circuit (Figure 1) of the
MAX1531 is a complete power-supply system for TFT
LCD monitors. The circuit generates a 3.3V/1.5A main
output, a 2.5V/500mA output for the timing controller
and digital sections of source/gate drive ICs, a
10V/500mA source drive supply voltage, a 9.7V/50mA
gamma reference, a 25V/20mA gate-on voltage, and a
-10V/50mA gate-off voltage. The input voltage is 12V
10%. Table 1 lists the selected components and Table
2 lists the component suppliers. The standard applica-
tion circuit (Figure 2) of the MAX1530 is similar to the
MAX1531 application circuit except that gate-on and
gate-off voltages are eliminated.
The MAX1530/MAX1531 power-supply controllers pro-
vide logic and bias power for LCD monitors. Figure 3
shows the IC functional diagram. The main step-down
controller employs a current-mode PWM control method
to ease compensation requirements and provide excel-
lent load- and line-transient response. The use of syn-
chronous rectification yields excellent efficiency.
The MAX1530 includes three analog gain blocks to
control three auxiliary positive linear regulators, and the
MAX1531 includes five analog gain blocks to control
four positive and one negative linear regulators. Use
the positive gain blocks to generate low-voltage rails
directly from the input voltage or the main step-down
converter output, or higher voltages using charge
16 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
THERMAL
MAX1531
FREQ
EN
RSTIN
RESET
V
REF
OSC
REF
IN
VLOK
VL
VL
TIMER
GND
HIGH-SIDE
DRIVER
BST
DH
CLOCK SLOPE
IN
COMP
FB
COMP
FB
DH
STEP-DOWN
CONTROLLER
LX
LX
DL
VL
ILIM
ILIM
DL
PGND
SS DONE DC-DC EN FLTM
LOW-SIDE
DRIVER
PGND
DRV3
FBL3
ON2
ON3
ON4
ONL2
ONL3
ONL4
ONL5
SEQ
V
REF
SOFT-
START
SEQUENCE
ON5
FLTM
SEQ
LR3
FLT3
DRV1
0.9VREF
LDO3EN
V
REF
SOFT-
START
DRV4
FBL4
EN
FBL1
V
REF
FAULT
LOGIC
SOFT-
START
LR1
FLT1
0.9VREF
LDO4EN
FLT4
LR4
CSH
0.9VREF
FLTCS
300mV
CSL
DRV2
DRV5
FBL5
V
V
REF
SOFT-
START
SOFT-
START
REF
LDO2EN
FLT2
LDO5EN
FLT5
FBL2
LR5
LR2
0.9VREF
400mV
EN
VLOK
Figure 3. IC Functional Diagram
______________________________________________________________________________________ 17
Multiple-Output Power-Supply
Controllers for LCD Monitors
During the second half of the cycle, the high-side MOS-
FET turns off and the low-side N-channel MOSFET turns
on. Now the inductor releases the stored energy as its
current ramps down, providing current to the output.
The output capacitor stores charge when the inductor
current exceeds the load current and discharges when
the inductor current is lower, smoothing the voltage
across the load. Under overload conditions, when the
inductor current exceeds the selected current limit (see
Current Limit Circuit), the high-side MOSFET is not
turned on at the rising edge of the clock and the low-
side MOSFET remains on to let the inductor current
ramp down.
CURRENT
SENSE
AND
CURRENT
LIMIT
IN
∑
SLOPE
SS DONE
DC-DC EN
SOFT-
START
V
REF
R
Q
Q
DH
DL
GM
FB
PWM COMP
COMP
CLOCK
S
LX
CURRENT
LIMIT
ILIM
Under light-load conditions, the MAX1530/MAX1531
maintain a constant switching frequency to minimize
cross-regulation errors in applications that use a trans-
former. The low-side gate-drive waveform is the comple-
ment of the high-side gate-drive waveform, which
causes the inductor current to reverse under light loads.
PGND
FAULT COMPARATOR
FLTM
0.9VREF
0/MAX531
Figure 4. Step-Down Controller Block Diagram
Current-Sense Amplifier
The MAX1530/MAX1531s’ current-sense circuit ampli-
fies the current-sense voltage generated by the high-
side MOSFET’s on-resistance. This amplified
current-sense signal and the internal slope compensa-
tion signal are summed together and fed into the PWM
comparator’s inverting input. Place the high-side MOS-
FET near the controller, and connect IN and LX to the
MOSFET using Kelvin-sense connections to guarantee
current-sense accuracy and improve stability.
pumps attached to the switching node or extra wind-
ings coupled to the step-down converter inductor. The
negative gain block (MAX1531) can be used in con-
junction with a charge pump or coupled winding to
generate the LCD gate-off voltage or other negative
supplies.
Step-Down Controller
The MAX1530/MAX1531 include step-down controllers
that use a fixed-frequency current-mode PWM control
scheme (Figure 4). An internal transconductance
amplifier establishes an integrated error voltage at the
COMP pin. The heart of the current-mode PWM con-
troller is an open-loop comparator that compares an
integrated voltage-feedback signal with an amplified
current-sense signal plus a slope-compensation ramp.
At each rising edge of the internal clock, the high-side
MOSFET turns on until the PWM comparator trips or the
maximum duty cycle is reached. During this on-time,
current ramps up through the inductor, sourcing cur-
rent to the output and storing energy in a magnetic
field. The current-mode feedback system regulates the
peak inductor current as a function of the output volt-
age error signal. Since the average inductor current is
nearly the same as the peak inductor current (assum-
ing that the inductor value is relatively high to minimize
ripple current), the circuit acts as a switch-mode
transconductance amplifier. That pushes the output LC
filter pole, normally found in a voltage-mode PWM, to a
higher frequency. To preserve loop stability, the slope-
compensation ramp is summed into the main PWM
comparator.
Current-Limit Circuit
The MAX1530/MAX1531 include two current-limit cir-
cuits that use the two MOSFETs’ on-resistances as cur-
rent-sensing elements (Figure 4). The high-side
MOSFET’s voltage is used with a fixed 400mV (typ) cur-
rent-limit threshold during the high-side on-times. The
low-side MOSFET’s voltage is used with an adjustable
current-limit threshold during the low-side on-times.
Using both circuits together ensures that the current is
always measured and controlled.
The high-side MOSFET current limit employs a peak
current limit. If the voltage across the high-side MOS-
FET, measured from IN to LX, exceeds the 400mV
threshold during an on-time, the high-side MOSFET
turns off and the low-side MOSFET turns on.
The low-side MOSFET current-limit circuit employs a
“valley” current limit. If the voltage across the low-side
MOSFET, measured from LX to PGND, exceeds the
low-side threshold at the end of a low-side on-time, the
low-side MOSFET remains on and the high-side MOS-
FET stays off for the entire next cycle.
18 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
The ILIM pin is a dual-mode input. When ILIM is con-
nected to VL, a default low-side current limit of 250mV
(typ) is used. If ILIM is connected to a voltage between
250mV and 3V, the low-side current limit is typically
1/5th the ILIM voltage.
charged from the VL supply and placed parallel to the
high-side MOSFET’s gate-source terminals.
On startup, the synchronous rectifier (low-side MOS-
FET) forces LX to ground and charges the boost
capacitor from VL through diode D1. On the second
half-cycle, the switch-mode power supply turns on the
high-side MOSFET by closing an internal switch
between BST and DH. This provides the necessary
gate-to-source voltage to turn on the high-side switch,
an action that boosts the 5V gate-drive signal above
the input voltage.
The MAX1530/MAX1531s’ current limits are compara-
tively inaccurate, since the maximum load current is a
function of the MOSFETs’ on-resistances and the induc-
tor value, as well as the accuracy of the two thresholds.
However, using MOSFET current sensing reduces both
cost and circuit size and increases efficiency, since
sense resistors are not needed.
Oscillator Frequency Selection (FREQ)
The FREQ pin can be used to select the switching fre-
quency of the step-down regulator. Connect FREQ to
VL for 500kHz operation. Connect FREQ to AGND for
250kHz operation. The 500kHz operation minimizes the
size of the inductor and capacitors. The 250kHz opera-
tion improves efficiency by 2% to 3%.
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving mod-
erate-size high-side and low-side MOSFETs. Adaptive
dead-time circuits monitor the DL and DH drivers and
prevent either FET from turning on until the other is fully
off. This algorithm allows operation without shoot-
through with a wide range of MOSFETs, minimizing
delays and maintaining efficiency. When the gates are
turning off, there must be low-resistance, low-induc-
tance paths from the gate drivers to the MOSFET gates
for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1530/
MAX1531 interpret the MOSFET gate as "off" while gate
charge actually remains. Use short, wide traces mea-
suring less than 50 squares (at least 20 mil wide if the
MOSFET is 1in from the device).
Linear Regulator Controllers
The MAX1530/MAX1531 include three positive linear
regulator controllers, LR1, LR2, and LR3. These linear
regulator controllers can be used with external pass
transistors to regulate supplies for TFT LCDs. The
MAX1531 includes an additional positive linear regula-
tor controller (LR4) and a negative linear regulator con-
troller (LR5).
Low-Voltage Logic Regulator Controller (LR1)
LR1 is an analog gain block with an open-drain N-
channel output. It drives an external PNP pass transis-
tor with a 6.8kΩ base-to-emitter resistor. Its guaranteed
base drive sink current is at least 3mA. The regulator
including transistor Q1 in Figure 1 uses a 10µF output
capacitor and is designed to deliver 500mA at 2.5V.
It is advantageous to slow down the turn-on of both
gate drivers if there is noise coupling between the
switching regulator and the linear regulators. The noise
coupling can result in excessive switching ripple on the
linear regulator outputs. Slowing down the turn-on of
the gate drivers proves to be an effective way of reduc-
ing the output ripple. Take care to ensure that the turn-
off times are not affected at the same time. As
explained above, slowing down the turn-off times may
result in shoot-through problems. In Figure 1, a 10Ω
resistor (R5) is inserted in series with the BST pin to
slow down the turn-on of the high-side MOSFET (N1-B)
without affecting the turn-off. A 10Ω resistor (R6) is also
inserted between DL and the gate of the low-side MOS-
FET (N1-A) to slow its turn-on. Because the gate resis-
tor would slow down the turn-off time, connect a
switching diode (D2) (such as 1N4148) in parallel with
the gate resistor as shown in Figure 1 to prevent poten-
tial shoot-through.
LR1 is typically used to generate low-voltage logic sup-
plies for the timing controller and the digital sections of
the TFT LCD source/gate driver ICs.
LR1 is enabled when the soft-start of the main step-
down regulator is complete. (See the Startup Sequence
(ONL_,SEQ) section.) Each time it is enabled, the con-
troller goes through a soft-start routine that ramps up its
internal reference DAC. (See the Soft-Start section.)
Gamma Regulator Controller (LR2)
LR2 is an analog gain block with an open-drain N-
channel output. It drives an external PNP pass transis-
tor with a 6.8kΩ base-to-emitter resistor. Its guaranteed
base drive sink current is at least 2mA. The regulator
including transistor Q2 in Figure 1 uses a 0.47µF output
capacitor and is designed to deliver 50mA at 9.7V.
High-Side Gate-Drive Supply (BST)
A flying-capacitor bootstrap circuit generates gate-
drive voltage for the high-side N-channel switch (Figure
1). The capacitor C5 between BST and LX is alternately
______________________________________________________________________________________ 19
Multiple-Output Power-Supply
Controllers for LCD Monitors
LR2 is typically used to generate the TFT LCD gamma
reference voltage, which is usually 0.3V below the
source drive supply voltage.
LR4 is typically used to generate the TFT LCD source
drive supply voltage. The input for this regulator can
come directly from the input supply, be produced from
an external step-up regulator, or from an extra winding
coupled to the main step-down regulator inductor.
LR2 is enabled when the step-down regulator is
enabled and the voltage on ONL2 exceeds ONL2 input
threshold (1.238V typ). (See the Startup Sequence
(ONL_,SEQ) section.) Each time it is enabled, the con-
troller goes through a soft-start routine that ramps up its
internal reference DAC. (See the Soft-Start section).
LR4 is enabled when the step-down regulator is
enabled and the voltage on ONL4 exceeds the ONL4
input threshold (1.238V typ). (See the Startup
Sequence (ONL_,SEQ) section.) Each time it is
enabled, the regulator goes through a soft-start routine
that ramps up its internal reference DAC from 0V to
1.238V (typ). (See the Soft-Start section.)
Linear Regulator Controller (LR3)
LR3 is an analog gain block with an open-drain N-
channel output. It drives an external PNP pass transis-
tor with a 6.8kΩ base-to-emitter resistor. Its guaranteed
base drive sink current is at least 2mA. The regulator,
including Q3 in Figure 1, uses a 0.47µF output capaci-
tor and is designed to deliver 20mA at 25V. The regula-
tor including Q3 in Figure 2 uses a 4.7µF output
capacitor and is designed to deliver 500mA at 10V.
The standard application circuit in Figure 1 powers the
LR4 regulator directly from the input supply and uses
the MAX1531’s general-purpose overcurrent protection
function to protect the input supply from excessive load
currents. (See the Overcurrent Protection section.)
0/MAX531
Gate-Off Regulator Controller (LR5) (MAX1531 Only)
LR5 is an analog gain block with an open-drain P-chan-
nel output. It drives an external NPN pass transistor
with a 6.8kΩ base-to-emitter resistor. Its guaranteed
base drive sink current is at least 2mA. The regulator
including Q5 in Figure 1 uses a 0.47µF output capacitor
and is designed to deliver 10mA at -10V.
For the MAX1531 (Figure 1), LR3 is typically used to gen-
erate the TFT LCD gate driver’s gate-on voltage. A suffi-
cient input voltage can be produced using a
charge-pump circuit as shown in Figure 1. Note that the
voltage rating of the DRV3 output is 28V. If higher volt-
ages are present, an external cascode NPN transistor
(Q6) should be used with the emitter connected to
LR5 is typically used to generate the TFT LCD gate dri-
ver’s gate-off voltage. A negative input voltage can be
produced using a charge-pump circuit as shown in
Figure 1. Use as many stages as necessary to obtain
the required output voltage.
DRV3, the base to V (which is the connection point of
IN
C1 and R12 in Figure 1), and the collector to the base of
the PNP pass transistor (Figure 1). For the MAX1530
(Figure 2), LR3 is typically used to generate the TFT LCD
source drive supply voltage. The input for this regulator
can come directly from the input supply, be produced
from an external step-up regulator, or from an extra wind-
ing coupled to the main step-down regulator inductor.
LR5 is enabled when the step-down regulator is
enabled and the voltage on ONL5 exceeds the ONL5
input threshold (1.238V typ). (See the Startup
Sequence (ONL_,SEQ) section.) Each time it is
enabled, the regulator goes through a soft-start routine
that ramps down its internal reference DAC from VL to
125mV (typ). (See the Soft-Start section.)
LR3 is enabled when the step-down regulator is
enabled and the voltage on ONL3 exceeds the ONL3
input threshold (1.238V typ). (See the Startup Sequence
(ONL_,SEQ) section.) Each time it is enabled, the con-
troller goes through a soft-start routine that ramps up its
internal reference DAC. (See the Soft-Start section.)
Internal 5V Linear Regulator (VL)
All MAX1530/MAX1531 functions, except the thermal
sensor, are internally powered from the on-chip, low-
dropout 5V regulator. The maximum regulator input
Source Drive Regulator Controller (LR4)
(MAX1531 Only)
voltage (V ) is 28V. Bypass the regulator’s output (VL)
IN
LR4 is an analog gain block with an open-drain N-
channel output. It drives an external PNP pass transis-
tor with a 1.5kΩ base-to-emitter resistor. Its guaranteed
base drive sink current is at least 10mA. The regulator
including Q4 in Figure 1 uses a 4.7µF output capacitor
and is designed to deliver 500mA at 10V. The regula-
tor’s fast transient response allows it to handle brief
peak currents up to 2A.
with at least a 1µF ceramic capacitor to AGND. The
V -to-VL dropout voltage is typically 200mV, so when
IN
V
IN
is less than 5.2V, VL is typically V - 200mV. The
IN
internal linear regulator can source up to 30mA to sup-
ply the device, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving particularly large MOSFETs, little or
no regulator current may be available for external
20 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
loads. For example, when switched at 500kHz, large
EN > 1.24V
AND
MOSFETs with a total of 40nC total gate charge would
VL > 3.5V
require 40nC × 500kHz, which is approximately 20mA.
SEQ = HIGH
On/Off Control (EN)
STEP-DOWN
REGULATOR
STARTUP
SEQUENCE
BLOCK
ENABLED
ONL_
CURRENT
SOURCES ON
The EN pin has an accurate 1.238V (typ) rising thresh-
old with 5% hysteresis. The accurate threshold allows it
to be used to monitor the input voltage or other analog
signals of interest. If V voltage is less than its thresh-
EN
STEP-DOWN
old, then the step-down regulator and all linear regula-
tors are turned off. VL and the internal reference remain
active when EN is low to allow an accurate EN thresh-
old. A rising edge on the pin clears any latched faults
except for a thermal fault, which is cleared only by
cycling the input power.
SOFT-START
DONE
ONL2 > 1.24V ONL3 > 1.24V ONL4 > 1.24V
ONL5 > 1.24V
LR2
STARTUP
LR1
STARTUP
LR3
LR4
LR5
STARTUP
STARTUP
STARTUP
Figure 5. Startup Conditions
Undervoltage Lockout
If VL drops below 3.4V (typ), the MAX1530/MAX1531
assume that the supply voltage is too low to make valid
decisions. Therefore, the undervoltage lockout (UVLO)
circuitry turns off all the internal bias supplies. Switching
is inhibited, and the DL and DH gate drivers are forced
low. After VL rises above 3.5V (typ), the fault and thermal
shutdown latches are cleared and startup begins if EN is
above its threshold.
ONLa
ONLb
ONLc
ONLd
R3
150kΩ
R2
75kΩ
R1
51kΩ
C1
0.1μF
SEQ
5V
ONLa ONLb ONLc
ONLd
Startup Sequence (ONL_, SEQ)
The MAX1530/MAX1531 are not enabled unless all four
of the following conditions are met: 1) VL exceeds the
UVLO threshold, 2) EN is above 1.238V, 3) the fault
latch is not set, and 4) the thermal shutdown latch is not
set. After all four conditions are met, the step-down con-
troller starts switching and enables soft-start (Figure 5).
After the step-down regulator soft-start is done, the low-
voltage logic linear regulator controller (LR1) soft-starts.
1.238V
ONL_
OFF
ON
ON
ON
ON
0V
The remaining linear regulator controllers and the
sequence block that can be used to control them are
enabled at the same time as the step-down regulator.
The SEQ logic input is used in combination with the
ONL_ pins to control the startup sequence. When SEQ
is high and the sequence block is enabled, each ONL_
pin sources 2µA (typ). When the voltage on an ONL_
pin reaches 1.238V (typ), its respective linear regulator
controller (LR_) is enabled. When SEQ is low or the
sequence block is not enabled, each ONL_ pin is con-
nected to ground through a 1.5kΩ internal MOSFET.
OFF
OFF
OFF
OFF
LRa
OFF
OFF
LRb
LRc
LRd
OFF
16ms
Figure 6. Single-Capacitor Sequence Configuration
The sequence block allows the user to program the
startup of LR2 to LR5 in any desired sequence. If no
capacitor is placed on an ONL_ pin, its LR_ controller
starts immediately after the sequence block is enabled
and SEQ goes high. Placing a 1.5nF capacitor on an
ONL_ pin provides about 1ms delay for the respective
LR_ controller. Placing different size capacitors on
each ONL_ pin allows any arbitrary startup sequence.
An arbitrary startup sequence can also be created with
a single capacitor (Figure 6). Capacitor C1, together
with the 8µA current (2µA per ONL_ pin), is chosen to
provide the desired delay for the controller that starts
last (ONLd). Using 0.1µF for C1 provides about 16ms
______________________________________________________________________________________ 21
Multiple-Output Power-Supply
Controllers for LCD Monitors
total delay. Because of the 6µA current flowing through
R1 (51kΩ), the voltage on ONLc is 0.31V greater than
the voltage on ONLd and it crosses the 1.238V thresh-
old and enables its LR_ controller about 4ms before
ONLd’s controller. Similarly, the 4µA current through R2
(75kΩ) and the 2µA current through R3 (150kΩ) cause
their LR_ controllers to each start about 4ms before the
next one. Any desired sequence and delay can be pro-
grammed by calculating the charge rate of C1 and volt-
age drops across R1 through R3.
entire fault timer duration, the MAX1530/MAX1531 set
the fault latch, shutting down all the regulator outputs.
Undervoltage faults do not turn off VL. Once the fault
condition is removed, cycling the input voltage or
applying a rising edge on SEQ or EN clears the fault
latch and reactivates the device.
Thermal Protection
The thermal protection limits total power dissipation in
the MAX1530/MAX1531. If the junction temperature
exceeds +160°C, a thermal sensor immediately sets the
thermal fault latch, shutting off all the IC’s outputs
including VL, allowing the device to cool down. The only
way to clear the thermal fault latch is to cycle the input
voltage after the device cools down by at least 15°C.
Soft-Start
The soft-start function controls the slew rate of the out-
put voltages and reduces inrush currents during start-
up. Each regulator (step-down, LR1 to LR5) goes
through a soft-start routine after it is enabled. During
soft-start, the reference voltage for each positive regu-
lator gradually ramps up from 0V to the internal refer-
ence in 32 steps. The reference voltage of the negative
regulator ramps down from VL to 125mV in 32 steps.
The total soft-start period for each regulator is 1024
clock cycles for 250kHz switching frequency and 2048
clock cycles for 500kHz switching frequency.
Overcurrent Protection Block (CSH, CSL)
(MAX1531 Only)
The MAX1531 includes an uncommitted overcurrent
protection block that can be used to measure any input
or output current, using a current-sense resistor or
other sense element. If the measured current exceeds
the overcurrent protection threshold (300mV typ), the
MAX1531 immediately sets the undervoltage fault latch,
shutting down all the regulator outputs. Overcurrent
faults do not turn off VL. An internal lowpass filter pre-
vents large current transients of short duration (less
than 50µs) from setting the latch. Once the overcurrent
condition is removed, cycling the input voltage clears
the fault latch and reactivates the device. A rising edge
on SEQ or EN also clears the fault latch.
0/MAX531
Reset
The MAX1530/MAX1531 include an open-drain timed
microprocessor supervisor function to ensure proper
startup of digital circuits. The RESET output asserts low
whenever RSTIN is less than the RSTIN trip threshold.
RESET also asserts low when VL is less than the VL
UVLO threshold, EN is low, or the thermal, undervolt-
age or overcurrent fault latches are set. RESET enters
the high-impedance state only after RSTIN remains
above the trip threshold for the duration of the reset
timeout period. The state of RESET has no effect on
other portions of the IC.
In Figure 1’s circuit, the overcurrent protection is used
with the LR4 source driver regulator since that regulator
is powered directly from the input supply and has no
current limit of its own. The current-sense resistor is
placed in series with the input supply, before the linear
regulator’s external PNP pass transistor. CSH and CSL
are connected to the positive and negative sides of the
sense resistor.
The RSTIN threshold (1.114V typ) is designed to allow
RSTIN to directly connect to any of the MAX1530/
MAX1531s’ feedback input pins, eliminating the need
for an additional resistive divider. Typically, RSTIN is
connected to FB or FBL1 to monitor the supply voltage
for digital logic ICs, but it can be used to monitor any
desired output voltage or it can even be used as a gen-
eral-purpose comparator.
Design Procedures
Main Step-Down Regulator
Inductor Selection
Three key inductor parameters must be specified:
Fault Protection
inductance value (L), peak current (I
), and DC
PEAK
resistance (R ). The following equation includes a
DC
Undervoltage Protection
After its soft-start is done, if the output of the main step-
down regulator or any of the linear-regulator outputs
(LR1 to LR5) are below 90% of their normal regulation
point, the MAX1530/MAX1531 activate an internal fault
timer. If the fault condition remains continuously for the
constant, LIR, which is the ratio of peak-to-peak induc-
tor ripple current to DC load current. A higher LIR value
allows smaller inductance, but results in higher losses
and higher ripple. A good compromise between size
and losses is typically found at a 30% ripple current to
22 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
load current ratio (LIR = 0.3), which corresponds to a
peak inductor current 1.15 times the DC load current:
R
is not specified at a suitable temperature, use
DS(ON)
the maximum room temperature specification and add
0.5% per °C for the R
increase with temperature:
DS(ON)
V
×(V − V
OUT
)
OUT
IN
L =
I
×R
< 340mV
PEAK
DS(ON)_HOT
V
× f ×I
×LIR
IN SW LOAD(MAX)
To ensure stable operation of the current-mode PWM,
the minimum current-sense ripple signal should exceed
12mV. Since this value depends on the minimum
where I
is the maximum DC load current,
LOAD(MAX)
and the switching frequency f
is 500kHz when FREQ
SW
is tied to VL, and 250kHz when FREQ is tied to AGND.
The exact inductor value is not critical and can be
adjusted to make trade-offs among size, cost, and effi-
ciency. Lower inductor values minimize size and cost,
but they also increase the output ripple and reduce the
efficiency due to higher peak currents. On the other
hand, higher inductor values increase efficiency, but at
some point increased resistive losses due to extra turns
of wire will exceed the benefit gained from lower AC
current levels.
R
of the high-side MOSFET, which is not typical-
DS(ON)
ly a specified parameter, a good rule of thumb is to
choose the typical room temperature R
times the amount needed for this:
about 2
DS(ON)
I
×R
> 24mV
RIPPLE
DS(ON)_TYP
For example, Figure 1’s circuit is designed for 1.5A and
uses a dual MOSFET (N1) for both the high-side and
The inductor’s saturation current must exceed the peak
inductor current. The peak current can be calculated by:
low-side MOSFETs. Its maximum R
at room tem-
DS(ON)
perature is 145mΩ and an estimate of its maximum
at our chosen maximum temperature of +85°C
V
×(V − V
)
OUT
IN
OUT
R
DS(ON)
I
=
RIPPLE
f
×L × V
is 188mΩ. Since the inductor ripple current is 0.5A, the
peak current through the MOSFET is 1.75A. So the maxi-
mum peak current-sense signal is 330mV, which is less
SW
IN
I
RIPPLE
2
I
=I
+
PEAK LOAD(MAX)
than 340mV. Using the typical R
of 113mΩ and
DS(ON)
The inductor’s DC resistance should be low for good
efficiency. Find a low-loss inductor having the lowest
possible DC resistance that fits in the allotted dimen-
sions. Ferrite cores are often the best choice, though
powdered iron is inexpensive and can work well at
250kHz. Shielded-core geometries help keep noise,
EMI, and switching waveform jitter low.
the ripple current of 0.5A, the current ripple signal for the
PWM is 56mV, much greater than the required 24mV.
The R
of the low-side MOSFET (also N1) pro-
DS(ON)
vides current-limit information during the low-side on-
time that inhibits a high-side on-time if the MOSFET
voltage is too high. The voltage is measured across the
low-side MOSFET from PGND to LX and the threshold
is set by ILIM. To use the preset 250mV (typ) threshold,
connect ILIM to VL and choose a MOSFET with
MOSFET Selection and Current-Limit Setting
The MAX1530/MAX1531s’ step-down controller drives
two external logic-level N-channel MOSFETs. Since the
R
low enough that the “valley” current does not
DS(ON)
generate more than 190mV across the MOSFET, even
when the MOSFET is hot. If the MOSFET’s R is
R
of each MOSFET is used as a sense resistor to
DS(ON)
DS(ON)
provide current-sense signals to the PWM, their
values are important considerations in compo-
not specified at a suitable temperature, use the maxi-
mum room temperature specification and add 0.5% per
R
DS(ON)
nent selection.
°C for the R
increase with temperature:
DS(ON)
The R of the high-side MOSFET (N1) provides an
DS(ON)
inductor current-sense signal for current-mode opera-
tion and also provides a crude maximum current limit
during the high-side on-time that prevents runaway cur-
rents if the inductor saturates. The MOSFET voltage is
I
=I
−I
/2
VALLEY OUT RIPPLE
I
×R
<190mV
VALLEY
DS(ON)_HOT
measured across the high-side MOSFET from V to LX
IN
If the MOSFET’s R
is lower than necessary, there
and is limited to 400mV (typ). To ensure the desired
output current with sufficient margin, choose a MOSFET
DS(ON)
is no need to adjust the current-limit threshold using
ILIM. If the MOSFET’s R is too high, adjust the
with R
low enough that the peak current does
DS(ON)
DS(ON)
current-limit threshold using a resistive-divider between
not generate more than 340mV across the MOSFET,
even when the MOSFET is hot. If the MOSFET’s
______________________________________________________________________________________ 23
Multiple-Output Power-Supply
Controllers for LCD Monitors
VL and AGND at ILIM. The threshold is approximately
1/5th the voltage on ILIM over a range of 0.25V to 3V:
the voltage drop across the capacitor’s ESR caused by
the current into and out of the capacitor:
V
= V + V
RIPPLE(C)
I
× R
< 0.2 × V
× (1−K)
RIPPLE
RIPPLE(ESR)
VALLEY
DS(ON)_HOT
ILIM
V
= I
×R
RIPPLE(ESR)
RIPPLE ESR
I
RIPPLE
K is the accuracy of the current-limit threshold, which is
20% when the threshold is 250mV.
V
=
RIPPLE(C)
8×C
× f
OUT SW
For example, Figure 1’s N1 MOSFET has a maximum
DS(ON)
where C
is the output capacitance, and R
is the
OUT
ESR
R
at room temperature of 145mΩ and an esti-
ESR of the output capacitor. In Figure 1’s circuit, the
inductor ripple current is 0.5A. Assume the voltage-rip-
ple requirement is 2% (peak-to-peak) of the 3.3V out-
put, which corresponds to 66mV total peak-to-peak
ripple. Assuming that the ESR ripple component and
the capacitive ripple component each should be less
than 50% of the 66mV total peak-to-peak ripple, then
the ESR should be less than 66mΩ and the output
capacitance should be more than 7.6µF to meet the
total ripple requirement. A 22µF ceramic capacitor with
ESR (including PC board trace resistance) of 10mΩ is
selected for the standard application circuit in Figure 1,
which easily meets the voltage ripple requirement.
mate of its maximum at our chosen maximum tempera-
ture of +85°C is 188mΩ. Since the inductor ripple
current is 0.5A, the valley current through the MOSFET
is 1.25A. So the maximum valley current-sense signal is
235mV, which is too high to work with the 190mV mini-
mum of the default current-limit threshold. Adding a
divider at ILIM (R12 and R13) adjusts the ILIM voltage to
1.7V and the current-limit threshold to 340mV, providing
more than adequate margin for threshold accuracy.
0/MAX531
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduce noise and voltage
ripple on the input caused by the regulator’s switching.
It is usually selected according to input ripple current
requirements and voltage rating, rather than capaci-
tance value. The input voltage and load current deter-
The step-down regulator’s output capacitance and ESR
also affect the voltage undershoot and overshoot when
the load steps up and down abruptly. The undershoot
and overshoot have three components: the voltage
steps caused by ESR, the voltage undershoot and
overshoot due to the current-mode control’s AC load
regulation, and the voltage sag and soar due to the
finite capacitance and inductor slew rate.
mine the RMS input ripple current (I
):
RMS
V
×(V − V
)
OUT
IN
OUT
I
=I
×
RMS LOAD
V
IN
The amplitude of the ESR steps is a function of the load
step and the ESR of the output capacitor:
The worst case is I
= 0.5 × I , which occurs at
LOAD
RMS
V
= 2 × V
.
IN
OUT
For most applications, ceramic capacitors are used
because of their high ripple current and surge current
capabilities. For long-term reliability, choose an input
capacitor that exhibits less than +10°C temperature
rise at the RMS input current corresponding to the max-
imum load current.
V
= ΔI
×R
ESR_STEP
LOAD ESR
The amplitude of the sag due to the finite output capac-
itance and inductor slew rate is a function of the load
step, the output capacitor value, the inductor value, the
input-to-output voltage differential, and the maximum
duty cycle:
Output Capacitor
The output capacitor and its equivalent series resis-
tance (ESR) affect the regulator’s loop stability, output
ripple voltage, and transient response. The
Compensation Design section discusses the output
capacitance requirement based on the loop stability.
This section deals with how to determine the output
capacitance and ESR needs according to the ripple
voltage and load transient requirements.
2
L ×(ΔI
)
LOAD
V
=
SAG_LC
2×C
×(V
×D
-V
)
OUT
IN(MIN)
MAX OUT
The amplitude of the undershoot due to the AC load
regulation is a function of the high-side MOSFET
R
, the gain of the current-sense amplifier A
,
DS(ON)
VCS
the change of the slope compensation during the under-
shoot (ΔSC ), the transconductance of the error
The output voltage ripple has two components: varia-
tions in the charge stored in the output capacitor, and
UNDER
24 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
amplifier g , the compensation resistor R
, the FB
OUT
Operating Characteristics is 170mV. The voltage soar
due to finite capacitance and inductor slew rate is
155mV, and the voltage overshoot due to the AC load
regulation is 167mV. The total overshoot seen the in the
Typical Operating Characteristics is 200mV.
m
COMP
regulation V , and the output voltage set point V
:
FB
A
×R
× ΔI
LOAD
⎛
⎞
VCS
DS(ON)
V
×
OUT
⎜
⎟
+ΔSC
×R
⎝
⎠
UNDER
V
=
UNDER_AC
V
×g
m
Compensation Design
The step-down controller of the MAX1530/MAX1531
uses a peak current-mode control scheme that regu-
lates the output voltage by forcing the required current
through the inductor. The MAX1530/MAX1531 use the
FB
COMP
Use the following to calculate the slope compensation
change during the sag:
⎛
⎞
V
V
voltage across the high-side MOSFET’s R
to
DS(ON)
OUT
ΔSC
= 437.5mV ×
D
-
UNDER
UNDER
⎜
⎟
sense the inductor current. Using the current-sense
amplifier’s output signal and the amplified feedback
voltage sensed at FB, the control loop sets the peak
inductor current by:
⎝
⎠
IN
where D
is the duty cycle at the valley of the sag,
UNDER
which is usually 50%.
The actual undershoot is always equal to or bigger than
(V
-V
)× V × A
OUT OUT(SET) FB VEA
the worst of V
, V
, and V
.
UNDER_AC
ESR_STEP SAG_LC
I
=
PEAK
V
×R
× A
OUT(SET)
DS(ON) VCS
The amplitude of the soar due to the finite output
capacitance and inductor slew rate is a function of the
load step, the output capacitor value, the inductor
value, and the output voltage:
where V = 1.238V is the FB regulation voltage, A
FB
VCS
is the gain of the current-sense amplifier (3.5 typical),
A
V
is the DC gain of the error amplifier (2000 typ),
VEA
is the output voltage set point, and R
DS(ON)
OUT(SET)
2
L ×(ΔI
)
is the on-resistance of the high-side MOSFET.
LOAD
× V
V
=
SOAR_LC
2×C
The total DC loop gain (A ) is approximately:
DC
OUT
OUT
The amplitude of the overshoot due to the AC load reg-
ulation is:
V
× R
× A
FB
OUT(SET)
LE VEA
A
=
DC
V
×R
× A
DS(ON) VCS
A
×R
× ΔI
LOAD
⎛
⎞
VCS
DS(ON)
V
×
R
is the equivalent load resistance, given by:
LE
OUT
⎜
⎟
+ΔSC
×R
⎝
⎠
OVER
V
=
OVER_AC
⎛
⎜
⎞
V
L × f
SW
n × D'- D
⎞
V
×g
m
OUT
FB
COMP
R
=
⎟ ||⎛⎜⎝
⎟
⎠
LE
I
⎝ LOAD(MAX) ⎠
where ΔSC
is the change of the slope compensa-
tion during the overshoot, given by:
OVER
In the above equation, D’ = 1 - D, n is a factor deter-
mined by the slope compensation m and the inductor
c
⎛
⎞
V
V
current ramp m , as shown below:
1
OUT
ΔSC
= 437.5mV ×
- D
OVER
OVER
⎜
⎟
⎝
⎠
IN
m
m
C
n = 1+
where D
is the duty cycle at the peak of the over-
shoot, which is typically 0%.
OVER
1
Similarly, the actual overshoot is always equal to or big-
The slope compensation of the MAX1530/MAX1531 is
219mV/µs. The inductor current ramp is a function of
the input voltage, output voltage, inductance, high-side
ger than the worst of V
, V
, and
SOAR_LC
ESR_STEP
V
.
OVER_AC
MOSFET on-resistance R
, and the gain of the
DS(ON)
Given the component values in the circuit of Figure 1,
during a 1.5A step load transient, the voltage step due to
capacitor ESR is negligible. The voltage sag due to finite
capacitance and inductor slew rate is 81mV, and the
voltage undershoot due to the AC load regulation is
170mV. The total undershoot seen in the Typical
current-sense amplifier A
, and is:
VCS
V
-V
IN OUT
L
m =
× R
× A
1
DS(ON) VCS
______________________________________________________________________________________ 25
Multiple-Output Power-Supply
Controllers for LCD Monitors
Current-mode control has the effect of splitting the
complex pole pair of the output LC filter into a single
low-frequency pole and a single high-frequency pole.
The low-frequency current-mode pole depends on out-
Unnecessarily high bandwidth can increase noise
sensitivity while providing little benefit. Good tran-
sient response with low amounts of output capaci-
tance is achieved with a crossover frequency
between 20kHz and 100kHz. The series compensa-
tion capacitor (C10) generates a dominant pole that
sets the desired crossover frequency. Determine
C10 using the following expression:
put capacitor C
and the equivalent load resistance
OUT
R
, given by the following:
LE
1
f
=
POLE(LOW)
2π ×R ×C
LE
OUT
g
× A
DC
m
C10 ≈
The high-frequency current-mode pole is given by:
2π × f
× A
VEA
CROSSOVER
f
where g is the error amplifier’s transconductance
m
(100µS typ).
SW
f
=
POLE(HIGH)
2π ×n×D'
2) The compensation resistor R11, together with capac-
itor C10, provides a zero that is used to cancel the
low-frequency current-mode pole. Determine R11
using the following expression:
The COMP pin, which is the output of the IC’s internal
transconductance error amplifier, is used to stabilize
the control loop. A series resistor (R11) and capacitor
(C10) are connected between COMP and AGND to
form a pole-zero pair. Another pole-zero pair can be
added by connecting a feed-forward capacitor (C23) in
parallel with feedback resistor R1. The compensation
resistor and capacitors are selected to optimize the
loop stability.
0/MAX531
1
R11≈
2π × f
× C10
POLE(LOW)
3) Because the error amplifier has limited output cur-
rent (16µA typ), small values of R11 can prevent the
error amplifier from providing an immediate COMP
voltage change required for good transient response
with minimal output capacitance. If the calculated
R11 value is less than 100kΩ, use 100kΩ and recal-
culate C10 using the following formula:
The compensation capacitor (C10) creates a dominant
pole at very low frequency (a few hertz). The zero
formed by R11 and C10 cancels the low-frequency cur-
rent-mode pole. The zero formed by R1 and C23 can-
cels the high-frequency current-mode pole and
introduces a preferable higher frequency pole. In appli-
cations where ceramic capacitors are used, the ESR
zero is usually not a concern because the ESR zero
occurs at very high frequency. If the ESR zero does not
occur at a frequency at least one decade above the
crossover, connect a second parallel capacitor (C2)
between COMP and AGND to cancel the ESR zero. The
component values shown in the standard application
circuits (Figure 1 and 2) yield stable operation and fast
transient response over a broad range of input-to-out-
put voltages.
1
C10 ≈
2π × f
× 100kΩ
POLE(LOW)
Changing C10 also changes the crossover frequen-
cy; the new crossover frequency is:
g
× A
DC
m
f
=
CROSSOVER
2π × C10 × A
VEA
The calculated crossover frequency should be less
than 1/5th the switching frequency. There are two
ways to lower the crossover frequency if the calculat-
ed value is greater than 1/5th the switching frequen-
To design a compensation network for other compo-
nents or applications, use the following procedure to
achieve stable operation:
1) Select the crossover frequency f
cy: increase the high-side MOSFET R
), or
DS(ON
CROSSOVER
(bandwidth) to be 1/5th the switching frequency
or less:
increase the output capacitance. Increasing R
DS(ON)
f
reduces the DC loop gain, which results in lower
crossover frequency. Increasing output capacitance
reduces the frequency of the lower low-frequency
current-mode pole, which also results in lower
crossover frequency. The following formula gives the
SW
f
SW
5
f
≤
CROSSOVER
26 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
crossover frequency as a function the MOSFET
and the output capacitance:
5) For most applications using tantalum or polymer
capacitors, the output capacitor’s ESR forms a sec-
ond zero that occurs either below or close to the
crossover frequency. The zero must be cancelled
with a pole. Verify the frequency of the output capac-
itor’s ESR zero, which is:
R
DS(ON)
g
× V
× V × R11
FB
m
f
=
CROSSOVER
2π × A
×C
×R
VCS
OUT(SET)
OUT DS(ON)
Change one or both of these circuit parameters to
obtain the desired crossover. Recalculate ADC and
repeat steps 1 to 3 after making the changes.
1
f
=
ZERO(ESR)
2π ×C
× R
ESR
OUT
4) If f
is less than the crossover frequency,
POLE(HIGH)
where R
is the ESR of the output capacitor C
.
ESR
OUT
cancel the pole with a feed-forward zero. Determine the
If the output capacitor’s ESR zero does not occur
well after the crossover, add the parallel compensa-
tion capacitor (C2) to form another pole to cancel the
ESR zero. Calculate the value of C2 using:
value of C23 (feedback capacitor) using the following:
1
C23 ≈
2π × f
× R1
POLE(HIGH)
C10
C2 ≈
C23 also forms a secondary pole with R1 and R2
given by the following:
2π × f
× R11 × C10-1
ZERO(ESR)
Applications using ceramic capacitors usually have
ESR zeros that occur at least one decade above the
crossover. Since the ESR zero of ceramic capacitors
has little effect on the loop stability, it does not need to
be cancelled.
1
f
=
POLE_SEC
2π × R1 || R2 × C23
(
)
The frequency of this pole should be above the
crossover frequency for loop stability. The position of
this pole is related to the high-frequency current-
mode pole, which is determined by the inductor cur-
rent ramp signal. The inductor current ramp signal
must satisfy the following condition to ensure the
pole occurs above the crossover frequency:
The following is an example. In the circuit of Figure 1,
the input voltage is 12V, the output voltage is set to
3.3V, the maximum load current is 1.5A, the typical on-
resistance of the high-side MOSFET is 100mΩ, and the
inductor is 10µH. The calculated equivalent load resis-
tance is 1.67Ω. The DC loop gain is:
2π ×D'× R2× f
×m
C
CROSSOVER
m1>
1.238V × 1.67Ω × 2000
R1+R2 × f - 2π ×D'× R2× f
(
)
A
≈
= 4180
SW
CROSSOVER
DC
3.3V ×100mΩ × 3.5
If the frequency of the secondary pole is below the
crossover frequency, the frequency of the secondary
pole must be moved higher, or the crossover fre-
quency must be moved lower. There are two ways to
increase the frequency of the secondary pole:
If the chosen crossover frequency is 20kHz (step 1):
100μS × 4180
C10 ≈
≈1.7nF
2π ×20kHz×2000
increase the high-side MOSFET R
), or reduce
DS(ON
the step-down inductance, L. As explained before, for
given input and output voltages, the current ramp sig-
With a 22µF output capacitor, the output pole of the
step-down regulator is (step 2):
nal is proportional to the high-side MOSFET R
,
DS(ON)
and inversely proportional to the inductance. If the
1
f
=
= 4.3kHz
POLE(OUT)
pole occurs below the crossover frequency, the cur-
2π ×22μF ×1.67Ω
rent feedback signal is too small. Increasing R
DS(ON)
or reducing the inductance can increase the current
feedback signal. To lower the crossover frequency,
use the methods described in step 3. Repeat steps 1
to 4 after making the changes.
Calculate R11 using:
1
R11≈
= 22kΩ
2π × 4.3kHz ×1.7nF
______________________________________________________________________________________ 27
Multiple-Output Power-Supply
Controllers for LCD Monitors
Because R11 is less than 100kΩ, use 100kΩ for R11
Charge Pumps
and recalculate C10 as (step 3):
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement. The number of positive charge-pump
stages is given by:
1
C10 ≈
= 370pF
2π × 4.3kHz ×100kΩ
Use the standard value of 470pF for C10 and recalcu-
late the crossover frequency as:
V
+ V
− V
POS
DROPOUT IN
N
=
POS
V
−2× V
D
IN
100μS × 4180
2π × 470pF ×2000
f
≈
= 70.8kHz
CROSSOVER
where N
is the number of positive charge-pump
is the positive charge-pump output, V is
IN
POS
POS
stages, V
the input voltage of the step-down regulator, V is the
D
Since the crossover frequency is less than 1/5th the switch-
ing frequency, 470pF is an acceptable value for C10.
forward voltage drop of the charge-pump diode, and
V
is the dropout margin for the linear regula-
DROPOUT
Because the high-frequency pole of the current-mode
control is at 64kHz, the feed-forward capacitor is (step 4):
tor. Use V
= 0.3V.
DROPOUT
The number of negative charge-pump stages is given by:
1
0/MAX531
−V + V
NEG
DROPOUT
C23 ≈
=140pF
N
=
NEG
2π × 64kHz ×17.8kΩ
V
−2× V
IN
D
Use a standard value of 150pF for C23. The pole
formed by C23, R1 and R2 occur at 159kHz, above the
70.8kHz crossover frequency.
where N
is the number of negative charge-pump
NEG
stages, V
is the negative charge-pump output, V
IN
NEG
is the input voltage of the step-down regulator, V is
the forward voltage drop of the charge-pump diode,
D
Because a ceramic output capacitor is used in the cir-
cuit of Figure1, the ESR zero occurs well above the
crossover frequency, so no additional compensation
capacitor (C2) is needed (step 5).
and V
is the dropout margin for the linear reg-
DROPOUT
ulator. Use V
= 0.3V.
DROPOUT
The above equations are derived based on the
assumption that the first stage of the positive charge
pump is connected to V and the first stage of the
IN
Output Voltage Selection
The MAX1530/MAX1531 step-down regulator’s output
voltage can be adjusted by connecting a resistive volt-
age-divider from the output to AGND with the center
tap connected to FB (Figure 1). Select R2 in the 5kΩ to
50kΩ range. Calculate R1 with the following equation:
negative charge pump is connected to ground.
Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
stage to V
or another available supply. If the first
OUT
stage of the positive charger pump is powered from the
output of the step-down regulator V
tion becomes:
, then the equa-
OUT
⎛
⎞
V
V
OUT
R1=R2×
−1
⎜
⎟
⎝
⎠
FB
−V
+ V
− V
POS
DROPOUT OUT
−2× V
D
where V = 1.238V, and V
may vary from 1.238V
FB
OUT
N
=
POS
V
to approximately 0.6 × V (V is up to 28V).
IN
IN IN
Boost-Supply Diode
If the first stage of the negative charge pump is pow-
A signal diode, such as the 1N4148, works well in most
applications. If the input voltage goes below 6V, use a
small 100mA Schottky diode for slightly improved effi-
ciency and dropout characteristics. Do not use power
diodes, such as the 1N5817 or 1N4001, since high
junction capacitance can charge up VL to excessive
voltages.
ered from the output of the step-down regulator V
,
OUT
then the equation becomes:
−V
+ V
+ V
NEG
DROPOUT OUT
−2× V
D
N
=
NEG
V
IN
28 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
Flying Capacitors
Increasing the flying capacitor value lowers the effec-
tive source impedance and increases the output cur-
rent capability. Increasing the capacitance indefinitely
has a negligible effect on output current capability
because the internal switch resistance and the diode
impedance place a lower limit on the source imped-
ance. A 0.1µF ceramic capacitor works well in most
low-current applications. The voltage rating for a given
flying capacitor (CX) must exceed the following:
V
to VL with the center tap connected to FBL5
GOFF
(Figure 1). Select R29 in the 10kΩ to 30kΩ range.
Calculate R28 with the following equation:
R28 =R29× V
− V
)/(V − V
(
)
]
[
FBL5
GOFF L FBL5
where V
= 125mV and V = 5.0V.
L
FBL5
Pass Transistor Selection
The pass transistor must meet specifications for DC
current gain (h ), collector-emitter saturation voltage,
FE
and power dissipation. The transistor’s current gain lim-
its the guaranteed maximum output current to:
V
CX
> N x V
IN
⎛
⎞
V
BE
I
= I
−
×h
FE
where N is the stage number in which the flying capaci-
LOAD(MAX)
DRV
⎜
⎟
R
⎝
⎠
BE
tor appears, and V is the input voltage of the step-
IN
down regulator.
where I
is the minimum guaranteed base drive cur-
DRV
Charge-Pump Output Capacitors
Increasing the output capacitance or decreasing the
ESR reduces the charge pump output ripple voltage
and the peak-to-peak transient voltage. With ceramic
capacitors, the output voltage ripple is dominated by
the capacitance value. Use the following equation to
approximate the required capacitor value:
rent, V is the base-emitter voltage of the pass transis-
BE
tor, and R
is the pullup resistor connected between
BE
the transistor’s base and emitter. Furthermore, the tran-
sistor’s current gain increases the linear regulator’s DC
loop gain (see the Stability Requirements section),
which may destabilize the output. Therefore, transistors
with current gain over 300 at the maximum output cur-
rent can be difficult to stabilize and are not recom-
mended unless the high gain is needed to meet the
load current requirements.
I
LOAD
V
C
≥
OUT
2f
OSC RIPPLE
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Also, the package’s power dissipation limits the usable
maximum input-to-output voltage differential. The maxi-
mum power dissipation capability of the transistor’s
package and mounting must exceed the actual power
dissipation in the device. The power dissipation equals
where V
ripple.
is the peak-to-peak value of the output
RIPPLE
Charge-Pump Rectifier Diodes
Use low-cost silicon switching diodes with a current rat-
ing equal to or greater than 2 times the average
charge-pump input current. If it helps avoid an extra
stage, some or all of the diodes can be replaced with
Schottky diodes with an equivalent current rating.
the maximum load current (I
) times the maxi-
LOAD(MAX)
mum input-to-output voltage differential:
Linear Regulator Controllers
P =I
×(V
− V
)
LOAD(MAX)
LRIN(MAX)
LROUT
Output Voltage Selection
Adjust the positive linear regulator (LR1 to LR4) output
voltages by connecting a resistive voltage-divider from
the output to AGND with the center tap connected to
FBL_ (Figure 1). Select the lower resistor of the divider
in the 10kΩ to 30kΩ range. Calculate the upper resistor
with the following equation:
where V
linear regulator, and V
linear regulator.
is the maximum input voltage of the
LRIN(MAX)
is the output voltage of the
LROUT
Output Voltage Ripple
Ideally, the output voltage of a linear regulator should
not contain any ripple. In the MAX1530/MAX1531, the
step-down regulator’s switching noise can couple to
the linear regulators, creating output voltage ripple.
Following the PC board layout guidelines in the PC
Board Layout and Grounding section can significantly
reduce noise coupling. If there is still an unacceptable
R
=R
× V
/V
−1
(
[
)
UPPER
LOWER
OUT_ FBL_
]
where V
_ is 1.238V (typ).
FBL
Adjust the negative linear regulator (LR5) output volt-
age by connecting a resistive voltage-divider from
______________________________________________________________________________________ 29
Multiple-Output Power-Supply
Controllers for LCD Monitors
amount of ripple after the PC board layout has been
optimized, consider increasing output capacitance.
Adding more capacitance does not eliminate the ripple,
but proportionally reduces the amplitude of the ripple. If
increasing the output capacitance is not desirable
because of space or cost concerns, then consider
slowing the turn-on of the step-down DC-to-DC
MOSFETs. Slower turn-on leads to smoother LX rising
and falling edges and consequently reduces the
switching noise. When slowing down MOSFET turn-on,
ensure the turn-off time is not affected. Otherwise, the
adaptive dead-time circuitry may not work properly and
shoot-through may occur. See the MOSFET Gate
Drivers section for details on how to slow down the
turn-on of both DH and DL.
amplifier delay, the pass transistor’s input capacitance,
and the stray capacitance at the feedback node create
additional poles in the system, and the output capacitor’s
ESR generates a zero. For proper operation, use the fol-
lowing steps to ensure the linear regulator’s stability:
1) First, calculate the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
1
f
=
POLE(LR)
2πC
R
LR LOAD
where C
is the output capacitance of the linear
LR
regulator and R
is the load resistance corre-
LOAD
sponding to the maximum load current.
The unity-gain crossover of the linear regulator is:
Stability Requirements
The MAX1530/MAX1531 linear-regulator controllers use
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifi-
er, the pass transistor, the base-emitter resistor, and
the output capacitor determine loop stability. The fol-
lowing applies equally to all linear regulators in the
MAX1530 and MAX1531. Any differences are highlight-
ed where appropriate.
f
= A
f
V(LDO) POLE(LDO)
CROSSOVER
0/MAX531
2) The pole created by the internal amplifier delay is
about 1MHz:
f
≅1MHz
POLE(AMP)
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and
the base-to-emitter pullup resistor:
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
1
f
=
)
POLE(C
IN
2πC (R ||R )
IN BE
IN
⎛
⎞
⎛
⎞
4
I
×h
I
LOAD
BIAS FE
A
≈
× 1+
× V
REF
V(LR)
⎜
⎟
⎜
⎟
V
⎝
⎠
⎝
⎠
T
g
2πf
h
FE
m
where C
=
, R =R =
, g is the
m
IN
IN
π
where V is 26mV at room temperature, I
is the
LOAD
T
g
T
m
output current of the linear regulator, V
is the linear
REF
regulator’s internal reference voltage, and I
current through the base-to-emitter resistor (R ). Each
of the linear regulator controllers is designed for a dif-
ferent maximum output current so they have different
output drive currents and different bias currents (I
is the
transconductance of the pass transistor, and f is the
T
transition frequency. Both parameters can be found
in the transistor’s data sheet.
BIAS
BE
Because R
is much greater than R , the above
IN
equation can be simplified:
BE
).
BIAS
Each controller’s bias current can be found in the
Electrical Characteristics. The current listed in the
Conditions column for the FBL_ regulation voltage
specification is the individual controller’s bias current.
The base-to-emitter resistor for each controller should
1
f
≈
)
POLE(C
IN
2πC R
IN IN
The equation can be further simplified:
be chosen to set the correct I
:
BIAS
f
T
f
=
)
POLE(C
V
IN
BE
h
FE
R
=
BE
I
BIAS
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal
30 ______________________________________________________________________________________
Multiple-Output Power-Supply Controllers for
LCD Monitors
0/MAX531
4) Next, calculate the pole set by each linear regula-
tor’s feedback resistance and the capacitance
(islands) together at only one location, which is a
via connected to the backside pad of the device.
All voltage-feedback dividers should be connected
to the analog ground island. The step-down regula-
tor’s input and output capacitors, and the charge
pump components should be a wide power ground
plane. The power ground plane should be connect-
ed to the power ground pin (PGND) with a wide
trace. Maximizing the width of the power ground
traces improves efficiency, and reduces output
voltage ripple and noise spikes. All other ground
connections, such as the VL and IN pin bypass
capacitor and the linear regulator output capaci-
tors, should be star-connected to the backside of
the device with wide traces. Make no other connec-
tions between these separate ground planes.
(C
) between FBL_ and AGND (approximately
FBL_
5pF including stray capacitance):
1
f
=
POLE(FBL1)
2πC
(R9||R10)
1
FBL1
f
=
POLE(FBL2)
2πC
2πC
2πC
2πC
(R18||R19)
FBL2
1
f
=
=
=
POLE(FBL3)
(R25||R26)
FBL3
FBL4
FBL5
1
f
and
POLE(FBL4)
(R22||R23)
1
(R28||R29)
f
POLE(FBL5)
3) Place the IN pin and VL pin bypass capacitors
within 5mm from the IC and connect them to their
respective pins with short, direct connections.
5) Next, calculate the zero caused by the output
capacitor’s ESR:
4) Since both MOSFETs are used for current sensing,
care must be taken to ensure that noise and DC
errors do not corrupt the sense signals. Place both
MOSFETs close to the IC. Connect PGND to the
source of the low-side MOSFET with a short, wide
trace. Connect DL to the gate of the low-side MOS-
FET with a short, wide trace. Ensure that the traces
from DL to low-side MOSFET to PGND total no
more than 50 squares. Connect LX close to the
connection point between the low-side and high-
side MOSFETs with a short, wide trace. Connect
DH to the gate of the high-side MOSFET with a
short, wide trace. Ensure that the traces from DH to
high-side MOSFET to LX total no more than 50
squares (50 squares corresponds to 20 mils wide if
the total trace is 1in long).
1
f
=
ESR_ZERO
2πC
R
LR ESR
where R
is the equivalent series resistance of C
.
LR
ESR
6) To ensure stability, choose C large enough so that
LR
the crossover occurs well before the poles and zero
calculated in steps 2) to 5). The poles in steps 3)
and 4) generally occur at several megahertz and
using ceramic capacitors ensures the ESR zero
occurs at several megahertz as well. Placing the
crossover below 500kHz is sufficient to avoid the
amplifier-delay pole and generally works well, unless
unusual component choices or extra capacitances
move the other poles or zero below 1MHz.
5) Place all feedback voltage-divider resistors as
close to their respective feedback pins as possible.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up
switching noise. Care should be taken to avoid run-
ning any feedback trace near LX or the switching
nodes in the charge pumps.
PC Board Layout and Grounding
Careful PC board layout is important for proper opera-
tion. Use the following guidelines for good PC board
layout:
1) Place the high-power components of the step-down
regulator (input capacitors, MOSFETs, inductor,
and output capacitors) first, with any grounded
connections adjacent. Connect these components
with short, wide traces. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
6) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
7) Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes and analog ground. Use DC traces as
shield if necessary.
2) Create islands for the analog ground (AGND),
power ground (PGND), and individual linear regula-
tor grounds. Connect all these ground areas
______________________________________________________________________________________ 31
Multiple-Output Power-Supply
Controllers for LCD Monitors
Pin Configuration
Chip Information
PROCESS: BiCMOS
DRV2
FBL2
1
2
3
4
5
6
7
8
24 BST
23 DH
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
FBL3
22 LX
DRV3
CSH*
CSL*
FBL4*
DRV4*
21 DL
MAX1530
MAX1531
20 PGND
19 ONL5*
18 ONL4*
17 ONL3
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
32 TQFN
T-3255-4
21-0140
0/MAX531
* = N.C. FOR MAX1530
THIN QFN
32 ______________________________________________________________________________________
Multiple-Output Power-Supply
Controllers for LCD Monitors
0/MAX531
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
0
Initial release
Changing an existing part to an automotive-qualified part (/V)
—
11/09
1, 13, 32, 33, 34
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products.
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