MAX1601EAI+T [MAXIM]
Power Supply Management Circuit, Fixed, 2 Channel, PDSO28, 0.200 INCH, SSOP-28;
| 型号： | MAX1601EAI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 2 Channel, PDSO28, 0.200 INCH, SSOP-28 光电二极管 |
| 文件： | 总16页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1085; Rev 1; 10/96
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
________________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Supports Two CardBus Sockets
The MAX1601/MAX1604 DC power-switching ICs con-
tain a network of low-resistance MOSFET switches that
d e live r s e le c ta b le VCC a nd VPP volta g e s to two
CardBus or PC Card host sockets. Key features include
ultra-low-resistance switches, small packaging, soft-
switching action, and compliance with PCMCIA specifi-
cations for 3V/5V switching. 3.3V-only power switching
for fast, 32-bit CardBus applications is supported in two
ways: stiff, low-resistance 3.3V switches allow high 3.3V
load currents (up to 1A); and completely independent
internal charge pumps let the 3.3V switch operate nor-
mally, even if the +5V and +12V supplies are discon-
nected or turned off to conserve power. The internal
charge pumps are regulating types that draw reduced
input current when the VCC switches are static. Also,
power consumption is automatically reduced to 10µA
max when the switches are programmed to high-Z or
GND states over the serial interface, unlike other solu-
tions that may require a separate shutdown-control
input.
♦ 1A, 0.08Ω Max VY VCC Switch (MAX1601 only)
1A, 0.14Ω Max VX VCC Switch
♦ Soft Switching for Low Inrush Surge Current
♦ Overcurrent Protection
♦ Overcurrent/Thermal-Fault Flag Output
♦ Thermal Shutdown at Tj = +150°C
♦ Independent Internal Charge Pumps
♦ Break-Before-Make Switching Action
♦ 10µA Max Standby Supply Current
♦ 5V and 12V Not Required for Low-R
3.3V
DS(ON)
Switching
♦ Complies with PCMCIA 3V/5V Switching
Specifications
♦ Super-Small, 28-Pin SSOP Package
(0.2in. or 5mm wide)
♦ System Management Bus (SMBus) Serial
Interface
Other key features include guaranteed specifications for
output current limit level, and guaranteed specifications
for output rise/fall times (in compliance with PCMCIA
specifications). Reliability is enhanced by thermal-over-
load protection, accurate current limiting, an overcur-
rent-fault flag output, undervoltage lockout, and extra
ESD protection at the VCC/VPP outputs. The SMBus ser-
ial interface is flexible, and can tolerate logic input levels
in excess of the positive supply rail.
_______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
MAX1601EAI
MAX1604EAI
28 SSOP
__________S im p lifie d Blo c k Dia g ra m
The MAX1604 a nd MAX1601 a re id e ntic a l, e xc e p t
for the MAX1604’s VY switch, which has roughly three-
time s the on-re s is ta nc e (typ ic a lly 140m Ω).The
MAX1601/MAX1604 fit two complete CardBus/PCMCIA
switches into a space-saving, narrow (0.2in. or 5mm
wide) SSOP package.
VPPA
12IN
VY
VCCA
VCCA
VY
VX
VX
VL
VCCA
________________________Ap p lic a t io n s
MAX1601/MAX1604
Desktop Computers
Data Loggers
VDD
OVERCURRENT
AND
THERMAL
SHUTDOWN
DECODE
LOGIC
SMBALERT
SMBCLK
SMBDATA
SMBSUS
Notebook Computers Digital Cameras
ADDRESS
SELECT
Docking Stations
Handy-Terminals
Printers
ADR
GND
VPPB
PCMCIA Read/Write Drives
12IN
Pin Configuration appears on last page.
VCCB
VCCB
VCCB
VY
VX
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
Inputs/Outputs to GND
(VL, VX, VY, VCCA, VCCB) (Note 1)........................-0.3V, +6V
VPP Inputs/Outputs to GND
VCCA, VCCB Short Circuit to GND............................Continuous
VPPA, VPPB Short Circuit to GND..............................Continuous
Continuous Power Dissipation (T = +70°C)
A
(12INA, 12INB, VPPA, VPPB) (Note 1) ..................-0.3V, +15V
Inputs and Outputs to GND (SMBCLK, SMBDATA,
SMBSUS, SMBALERT) (Note 1) ..............................-0.3V, +6V
ADR Input to GND ...........................................-0.3V, (VL + 0.3V)
VCCA, VCCB Output Current (Note 2).....................................4A
VPPA, VPPB Output Current (Note 2) ...............................250mA
SSOP (derate 9.52mW/°C above +70°C) ....................762mW
Operating Temperature Range
MAX1601EAI/MAX1604EAI .............................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1: There are no parasitic diodes between any of these pins, so there are no power-up sequencing restrictions (for example,
logic input signals can be applied even if all of the supply voltage inputs are grounded).
Note 2: VCC and VPP outputs are internally current-limited to safe values. See the Electrical Characteristics table.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
/MAX1604
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-SUPPLY SECTION
VX, VY or VL
12INA, 12INB
3.0
11
2.4
1.8
5
5.5
13
Input Voltage Range
V
VL falling edge
2.5
3.0
8
2.8
12IN falling edge
12IN rising edge
VX, VY falling edge
Undervoltage Lockout Threshold
V
10
1.4
2.5
2.8
VX or VY, all switches 0V or high-Z,
control inputs = 0V or VL, T = +25°C
A
Standby Supply Current
1
µA
µA
µA
µA
µA
µA
Any combination of VY switches on,
control inputs = 0V or VL, no VCC loads
VY Quiescent Supply Current
VX Quiescent Supply Current
12IN_ Standby Supply Current
12IN_ Quiescent Supply Current
VL Standby Supply Current
20
20
100
100
1
Any combination of VX switches on,
control inputs = 0V or high-Z, no VCC loads
12INA tied to 12INB, all switches 0V or high-Z,
control inputs = 0V or VL, T = +25°C
A
12INA tied to 12INB, VPPA and VPPB 12V switches on,
control inputs = 0V or VL, no VPP loads
15
100
10
All switches 0V or high-Z, control inputs = 0V or VL,
T = +25°C
A
4
VL Quiescent Supply Current
VL Fall Rate
Any combination of switches on
25
150
µA
When using VL as shutdown pin (Note 3)
0.05
V/µs
VCC SWITCHES
Operating Output Current Range VCCA or VCCB, VX = VY = 3V to 5.5V
0
1
A
12INA = 12INB = 0V to 13V,
MAX1601
MAX1604
0.06
0.14
0.08
On-Resistance, VY Switches
On-Resistance, VX Switches
VY = 3V, VX = 0V to 5.5V,
= 1A, T = +25°C
Ω
0.24
0.14
I
SWITCH
A
12INA = 12INB = 0V to 13V, VX = 4.5V, VY = 0V to 5.5V,
= 1A, T = +25°C
0.10
Ω
I
SWITCH
A
2
_______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
ELECTRICAL CHARACTERISTICS (continued)
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
Output Current Limit
CONDITIONS
MIN
1.2
20
TYP
MAX
4.0
UNITS
A
VCCA or VCCB
Output Sink Current
VCCA or VCCB < 0.4V, programmed to 0V state
mA
VCCA or VCCB forced to 0V, high-Z state,
T = +25°C
A
Output Leakage Current
10
10
µA
ms
µs
Output Propagation Delay
Plus Rise Time
VCCA or VCCB, 0V to VX or VY, C = 30µF,
L
R = 25Ω, 50% of input to 90% of output, T = +25°C
L
2
A
VCCA or VCCB, 0V to VX or VY, C = 1µF,
L
Output Rise Time
100
1200
R = open circuit, 10% to 90% points, T = +25°C
L
A
VCCA or VCCB, VX or VY to 0V, C = 30µF,
L
Output Propagation Delay
Plus Fall Time
R = open circuit, 50% of input to 10% of output,
60
6
100
ms
ms
L
T = +25°C
A
VCCA or VCCB, VX or VY to 0V, C = 1µF,
R = 25Ω, 90% to 10% points
L
L
Output Fall Time
VPP SWITCHES
Operating Output Current Range
On-Resistance, 12V Switches
VPPA or VPPB
0
120
1
mA
Ω
12IN = 11.6V, I
= 100mA, T = +25°C
0.70
1
SWITCH
A
On-Resistance, VPP = VCC Switches Programmed to VX (5V) or VY (3.3V), T = +25°C
3
Ω
A
Output Current Limit
Output Sink Current
VPPA or VPPB, programmed to 12V
130
10
200
260
mA
mA
VPPA or VPPB < 0.4V, programmed to 0V state
VPPA or VPPB forced to 0V, high-Z state,
T = +25°C
A
Output Leakage Current
10
30
µA
Output Propagation Delay
Plus Rise Time
VPPA or VPPB, 0V to 12IN_, C = 0.1µF,
L
1.2
800
9
ms
µs
50% of input to 90% of output, T = +25°C
A
VPPA or VPPB, 0V to 12IN_, C = 0.1µF,
L
Output Rise Time
100
10% to 90% points, T = +25°C
A
Output Propagation Delay
Plus Fall Time
VPPA or VPPB, 12IN_ to 0V, C = 0.1µF,
L
60
ms
ms
50% of input to 10% of output, T = +25°C
A
VPPA or VPPB, 12IN_ to 0V, C = 0.1µF,
L
90% to 10% points
Output Fall Time
1
INTERFACE AND LOGIC SECTION
SMBALERT Signal Propagation
Delay
VCC_ or VPP_, load step to SMBALERT output,
50% point to 50% point (Note 3)
3
µs
I
= 1mA, low state
0.4
0.1
V
µA
°C
V
SMBALERT Output Low Voltage
SINK
V
= 5.5V, high state
-0.1
2.2
SMBALERT Output Leakage Current
Thermal Shutdown Threshold
Logic Input Low Voltage
SMBALERT
Hysteresis = +20°C (Note 4)
SMBSUS, SMBCLK, SMBDATA
SMBSUS, SMBCLK, SMBDATA
150
0.8
0.4
Logic Input High Voltage
Logic Output Low Voltage
V
SMBDATA, I
= 4mA
V
SINK
_______________________________________________________________________________________
3
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SMB Input Capacitance
SMBCLK Clock Frequency
SMBCLK Clock Low Time
SMBCLK Clock High Time
CONDITIONS
MIN
TYP
MAX
UNITS
pF
5
SMBSUS, SMBCLK, SMBDATA
SMBus spec = 10kHz min
DC
4.7
4
100
kHz
µs
t
t
10% to 10% points
90% to 90% points
LOW
HIGH
µs
SMB Repeated Start-Condition
Setup Time
t
90% to 90% points
250
ns
SU:STA
SMB Start-Condition Hold Time
SMB Stop-Condition Setup Time
t
t
t
10% of SMBDATA to 90% of SMBCLK
90% of SMBCLK to 10% of SMBDATA
10% or 90% of SMBDATA to
4
4
µs
µs
HD:STA
SU:STO
SMB Data Valid to SMBCLK Rising-
Edge Time
SU:DAT
500
ns
10% of SMBCLK
SMB Data Hold Time
Bus Free Time
t
t
(Note 5)
0
ns
µs
V
HD:DAT
between start and stop conditions
4.7
BUF
/MAX1604
ADR Input Low Voltage
ADR Input High Voltage
Logic Input Bias Current
0.6
1.5
-1
V
1
µA
ADR, SMBSUS, SMBCLK, SMBDATA
SCL Fall to SDA Valid
(Master Clocking-In Data)
100
1000
ns
µs
Start-Condition Setup
4.7
Note 3: Not production tested.
Note 4: Thermal limit not active in standby state (all switches programmed to GND or high-Z state).
Note 5: A transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of the falling
edge of SMBCLK.
4
_______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
ELECTRICAL CHARACTERISTICS
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-SUPPLY SECTION
VX, VY or VL
12INA, 12INB
3.0
11
2.3
1.8
5
5.5
13
Input Voltage Range
V
VL falling edge, hysteresis = 1%
12IN falling edge
2.9
Undervoltage Lockout Threshold
V
12IN rising edge
10
VX, VY falling edge
1.4
2.9
VX or VY, all switches 0V or high-Z,
control inputs = 0V or VL
Standby Supply Current
15
100
100
15
µA
µA
µA
µA
µA
Any combination of VY switches on,
control inputs = 0V or VL, no VCC loads
VY Quiescent Supply Current
VX Quiescent Supply Current
12IN_ Standby Supply Current
12IN_ Quiescent Supply Current
Any combination of VX switches on,
control inputs = 0V or high-Z, no VCC loads
12INA tied to 12INB, all switches 0V or high-Z,
control inputs = 0V or VL
12INA tied to 12INB, VPPA and VPPB 12V switches on,
control inputs = 0V or VL, no VPP loads
100
VL Standby Supply Current
VL Quiescent Supply Current
All switches 0V or high-Z, control inputs = 0V or VL
Any combination of switches on
15
µA
µA
150
INTERFACE AND LOGIC SECTION
I
= 1mA, low state
0.4
0.8
V
V
SMBALERT Output Low Voltage
Logic Input Low Voltage
Logic Input High Voltage
Logic Output Low Voltage
ADR Input Low Voltage
SINK
SMBCLK, SMBDATA, SMBSUS
SMBCLK, SMBDATA, SMBSUS
2.2
1.5
V
V
V
V
SMBDATA, I
= 4mA
0.4
0.6
SINK
ADR Input High Voltage
_______________________________________________________________________________________
5
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(VL = VY = 3.3V, VX = 5V, 12IN, T = +25°C, unless otherwise noted.)
A
VCC_ SWITCHING (RISE)
VCC_ SWITCHING (RISE)
3
2
1
0
6
4
VCC_
(V)
VCC_
(V)
2
0
5
0
5
CONTROL
INPUT
(V)
CONTROL
INPUT
(V)
0
500µs/div
200µs/div
/MAX1604
C = 1µF, R = ∞
L
L
C = 30µF, R = 25Ω
L
L
VCC_ SWITCHING (FALL)
VCC_ SWITCHING (FALL)
6
4
2
0
6
4
2
0
VCC_
(V)
VCC_
(V)
5
0
5
0
CONTROL
INPUT
(V)
CONTROL
INPUT
(V)
10ms/div
10ms/div
C = 33µF, R = ∞
C = 1µF, R = 25Ω
L
L
L
L
VPP_ SWITCHING (RISE)
VPP_ SWITCHING (FALL)
15
15
10
5
10
5
VPP_
(V)
VPP_
(V)
0
0
5
0
5
0
CONTROL
INPUT
(V)
CONTROL
INPUT
(V)
200µs/div
2ms/div
C = 0.1µF, R = ∞
C = 0.1µF, R = ∞
L
L
L
L
6
_______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(VL = VY = 3.3V, VX = 5V, 12IN, T = +25°C, unless otherwise noted.)
A
INPUT CURRENT (VCC OUTPUT SHORTED)
VCC_ CURRENT LIMITING
2.0
1.5
1.0
0.5
0
4
I
(A)
VY
2
0
VCC_
(V)
1ms/div
2ms/div
C = 1µF, RESISTIVE OVERLOAD, R = 1Ω
L
L
VPP_ CURRENT LIMITING
INPUT CURRENT (VPP OUTPUT SHORTED)
10
10
5
5
0
VPP_
(V)
VPP_
(V)
0
300
200
I
12IN_
(mA)
100
0
2ms/div
100µs/div
C = 1µF, R = 50Ω
L
L
R = 0.1Ω
L
VCC_ SHUTDOWN RESPONSE
4
2
0
VL
(V)
4
2
0
VCC_
(V)
100µs/div
CIRCUIT OF FIGURE 2
_______________________________________________________________________________________
7
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(VL = VY = 3.3V, VX = 5V, 12IN, T = +25°C, unless otherwise noted.)
A
MAX1601
VY ON-RESISTANCE vs. CURRENT
VX ON-RESISTANCE
vs. VCC_ LOAD CURRENT
MAX1604
VY ON-RESISTANCE vs. CURRENT
80
75
70
65
60
55
50
45
40
35
30
165
160
155
150
145
140
135
130
125
120
115
110
105
100
95
T = +85°C
A
T = +85°C
A
T = +85°C
A
90
T = +25°C
A
85
T = +25°C
A
T = +25°C
A
80
75
T = -40°C
A
70
65
T = -40°C
A
T = -40°C
A
60
0
200
400
600
800
1000
200
/MAX1604
0
400
600
800
1000
0
200
400
600
800
1000
CURRENT (mA)
VCC_ LOAD CURRENT (mA)
CURRENT (mA)
12IN_ ON-RESISTANCE vs. TEMPERATURE
12IN_ ON-RESISTANCE vs. CURRENT
950
900
850
800
750
700
650
600
725
720
715
710
705
700
695
690
VPPA
VPPB
685
550
-40 -20
0
20
40
60
80 100
0
20
40
60
80 100 120 140
TEMPERATURE (°C)
CURRENT (mA)
VL SUPPLY CURRENT
vs. VL INPUT VOLTAGE
VX, VY SUPPLY CURRENT
vs. INPUT VOLTAGE
12IN SUPPLY CURRENT
vs. INPUT VOLTAGE
70
60
50
0.9
7
6
5
VX = VY = 0V
12IN
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VX
VY
NORMAL
OPERATION
40
30
20
4
3
2
10
0
1
0
SHUTDOWN
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
2
4
6
8
10
12
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
8
_______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1, 25
GND
Ground
2, 3,
26, 27
N.C.
No internal connection
4
5
12INA
VPPA
+12V Supply Voltage Input, internally connects to channel A VPP switch. Tie to VPPA if not used.
Channel A VPP Output
VX Supply-Voltage Inputs. VX pins must be connected together. Input range is 3V to 5.5V. VX is
normally connected to 5V.
6, 8, 10
VX
7, 22, 24
9, 18, 20
11
VCCA
VCCB
VPPB
12INB
ADR
Channel A VCC Outputs
Channel B VCC Outputs
Channel B VPP Output
12
+12V Supply Voltage Input, internally connects to channel B VPP switch. Tie to VPPB if not used.
Address Input, sets SMBus address location. See Table 1 for address selection.
13
SMBus Suspend-Mode Control Input. The device will execute commands previously stored in
the normal-mode register if SMBSUS is high, or will execute commands previously stored in the
suspend-mode register if SMBSUS is low.
14
SMBSUS
15
16
SMBCLK
SMBus Clock Input
SMBDATA
SMBus Data Input/Output, open drain
Fault-Detection Interrupt Output. SMBALERT goes low if either channel VCC or VPP switch is
current limiting or undervoltage lockout, or if the thermal protection circuit is activated.
SMBALERT is an open-drain output that requires an external pull-up resistor.
17
SMBALERT
VY Supply-Voltage Inputs. VY pins must be connected together. Input range is 3V to 5.5V. VY is
normally connected to 3V.
19, 21, 23
VY
Logic Supply-Voltage Inputs. Connect to the +3.3V or +5V host system supply. VL can be sup-
plied via the output of a CMOS-logic gate to produce an overriding shutdown. When used as a
shutdown input, VL should have a 1kΩ series resistor with a 0.1µF capacitor to ground (Figure 2).
Note that VL must be greater than undervoltage lockout for any switches to be turned on.
28
VL
_______________________________________________________________________________________
9
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
VB12
1/2 MAX1601/MAX1604
12IN
VPPA
CHARGE
PUMP
3Ω
CURRENT
LIMIT
40Ω
VB3
VY
VY
0.08Ω*
/MAX1604
VCCA
VCCA
VCCA
CURRENT
LIMIT
CHARGE
PUMP
VX
VX
VB5 0.14Ω
20Ω
CURRENT
LIMIT
CHARGE
PUMP
SMBALERT
GND
SMBCLK
SMBDATA
SMBSUS
ADR
SHDN
SMB
THERMAL
SHUTDOWN
VDD
VL
*0.24Ω FOR THE MAX1604
Figure 1. Functional Diagram (one channel of two)
10 ______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
_______________De t a ile d De s c rip t io n
The MAX1601/MAX1604 power-switching ICs contain a
network of low-resistance MOSFET switches that deliver
3.3V
selectable VCC and VPP voltages to two Cardbus or
PC Card host sockets. The MAX1601/MAX1604 differ
only in the VY switch on-resistance. Figure 1 is the
detailed block diagram.
VY
VPPA
VCCA
1k
MASTER
SHUTDOWN
VL
TO
SOCKETS
A AND B
MAX1601
MAX1604
0.1µF
74HC04
The power-input pins (VY, VX, 12IN_) are completely
independent. Low inrush current is guaranteed by con-
trolled switch rise times. VCC’s 100µs minimum output
rise time is 100% tested with a 1µF capacitive load, and
VPP’s 1ms minimum rise time is guaranteed with a 0.1µF
load. These respective capacitive loads are chosen as
wors t-c a s e c a rd -ins e rtion p a ra me te rs . The inte rna l
switching control allows VCC and VPP rise times to be
controlled, and makes them nearly independent of resis-
tive and capacitive loads (see rise-time photos in the
Typical Operating Characteristics). Fall times are a
function of loading, and are compensated by internal
circuitry.
VPPB
VCCB
Figure 2. Master Shutdown Circuit
low. A continuous short-circuit condition results in a
p uls e d outp ut c urre nt until the rma l s hutd own is
reached. SMBALERT is open-drain and requires an
external pull-up resistor.
Power savings is automatic: internal charge pumps draw
very low current when the VCC switches are static.
Standby mode reduces switch supply current to 1µA.
Driving the VL pin low with an external logic gate (master
shutdown) reduces total supply current to1µA (Figure 2).
Th e rm a l S h u t d o w n
If the IC junction temperature rises above +150°C, the
thermal shutdown circuitry opens all switches, including
the GND switches, and SMBALERT is pulled low. When
the temperature falls below +130°C, the switches turn
on again at the controlled rise rate. If the overcurrent
condition remains, the part cycles between thermal
shutdown and overcurrent.
Op e ra t in g Mo d e s
The MAX1601/MAX1604 have three operating modes:
normal, standby, and shutdown. Normal mode supplies
the selected outputs with their appropriate supply volt-
ages. Standby mode places all switches at ground, high
impedance, or a combination of the two. Shutdown mode
turns all switches off, and puts the VCC and VPP outputs
into a high-impedance state. Pull VL low to enter shutdown
mode. To ensure a 0.05V/µs fall rate on VL, use a 1kΩ
series resistor and a 0.1µF capacitor to ground (Figure 2).
Un d e rvo lt a g e Lo c k o u t
If the VX or VY switch input voltage drops below 1.5V,
the associated switch turns off and SMBALERT goes
low. For example, if VY is 3.3V and VX is 0V, and if the
interface controller selects VY, the VCCA output will be
3.3V. If VX is selected, VCCA changes to a high-imped-
ance output and SMBALERT goes low.
Ove rc u rre n t P ro t e c t io n
Peak detecting circuitry protects both the VCC and
VPP switches against overcurrent conditions. When
current through any switch exceeds the internal current
limit (4A for VCC switches and 200mA for VPP switch-
es), the switch turns off briefly, then turns on again at
the controlled rise rate. If the overcurrent condition
lasts more than 2µs, the SMBALERT output latches
When a voltage is initially applied to 12IN_, it must be
g re a te r tha n 8V to a llow the s witc h to op e ra te .
Operation continues until the voltage falls below 2V (the
VPP output is high impedance).
Whe n VL d rop s to le s s tha n 2.3V, a ll s witc he s a re
turne d off a nd the VCC a nd VPP outp uts a re hig h
impedance.
______________________________________________________________________________________ 11
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
responding to either the A channel address (which will
provide data about faults for both A and B channels) or
to the interrupt pointer address (discussed later).
______S MBu s ™ In t e rfa c e Op e ra t io n
The SMBus serial interface is a two-wire interface with
multi-mastering capability, intended to control low-
The normal start condition consists of a high-to-low
transition on SMBDATA while SMBCLK is high. The
7-bit address is followed by a bit that designates a read
or write operation: high = read, low = write. If the 7-bit
a d d re s s ma tc he s one of the s up p orte d func tion
addresses, the IC issues an acknowledge pulse by
pulling the SMBDATA line low. If the address is not
valid, the IC stays off of the bus and ignores any data
on the bus until a new start condition is detected. Once
the IC receives a valid address that includes a write bit,
it expects to receive one additional byte of data. If a
stop condition or new start condition is detected before
a complete byte of data is clocked in, the IC interprets
this as an error and all of the data is rejected and lost.
SMBDATA and SMBCLK are Schmitt triggered and can
accommodate slower edges. However, rising edges
should still be faster than 1µs, and falling edges should
be faster than 300ns.
speed peripheral devices in low-power portable equip-
me nt a p p lic a tions . SMBus is s imila r to I2C™ a nd
AccessBus, but has slightly different logic threshold
voltage levels, different fixed addresses, and a sus-
pend-mode register capability. To obtain a complete
set of specifications on the SMBus interface, call Intel at
(800) 253-3696 and ask for product code SBS5220.
S MBu s Ad d re s s in g
These dual-channel PC Card switch devices respond to
two of four different addresses, depending on the state
of the ADR address pin. Normal writing to the device is
done by transmitting one of four addresses, followed by
a single data byte, to program the channel selected.
Write transmissions to the interrupt pointer address are
not s up p orte d b y the s e d e vic e s . Re a d ing from the
device is done by transmitting one of two addresses cor-
/MAX1604
Table 1. SMBus Addressing
S MBu s Writ e Op e ra t io n s
If the IC receives a valid address immediately followed
by a write bit, the IC becomes a slave receiver. The
s la ve IC g e ne ra te s a firs t a c knowle d g e a fte r the
address and write bit, and a second acknowledge after
the command byte. A stop condition following the com-
mand (data) byte causes immediate execution of the
command, unless the data included a low SUS/OP bit.
If the data included a low SUS/OP bit, the command is
stored in the suspend-mode register and is executed
only when the SMBSUS pin is pulled low (Figure 3).
SMB
ADDRESS
WRITE
FUNCTION
ADR PIN
READ FUNCTION
0001100
1010000
1010001
1010010
1010011
Don’t care
Grounded
Grounded
Tied to VL
Tied to VL
N/A
Interrupt Pointer
Channel A
Channel B
Channel A
Channel B
Channel A/B faults
Channel A/B faults
Channel A/B faults
Channel A/B faults
Table 2. Command Format for Channel A Write Operations (address 1010000 or 1010010)
BIT
NAME
POR STATE
FUNCTION
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
7 (MSB)
OP/SUS
0
6
VCCAON
VCCA3/5
VCCAHIZ
VPPAON
VPPAPGM
VPPAHIZ
MASKFLT
0
0
0
0
0
0
0
Turns on VCCA when high, pulls VCCA to GND when low.
5
If VCCA is on, a high connects VY to VCCA, and a low connects VX to VCCA.
Puts VCCA in a high-impedance state when high. Overrides VCCAON.
Turns on VPPA when high, pulls VPPA to GND when low.
4
3
2
1
If VPPA is on, a high connects VPPA to 12INA, and a low connects VPPA to VCCA.
Puts VPPA in a high-impedance state when high. Overrides VPPAON.
Masks fault interrupts from both channel A and channel B when high.
0 (LSB)
I2C is a trademark of Philips Corp.
SMBus is a trademark of Intel Corp.
12 ______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
Table 3. Command Format for Channel B Write Operations (address 1010001 or 1010011)
BIT
NAME
POR STATE
FUNCTION
Operate/suspend bit. Selects which latch receives data: high = operation,
low = suspend.
7 (MSB)
OP/SUS
0
6
VCCBON
VCCB3/5
VCCBHIZ
VPPBON
VPPBPGM
VPPBHIZ
RFU
0
0
0
0
0
0
0
Turns on VCCB when high, pulls VCCB to GND when low.
If VCCB is on, a high connects VY to VCCB, and a low connects VX to VCCB.
Puts VCCB in a high-impedance state when high. Overrides VCCBON.
Turns on VPPB when high, pulls VPPB to GND when low.
5
4
3
2
1
If VPPB is on, a high connects VPPB to 12INB, and a low connects VPPB to VCCB.
Puts VPPB in a high-impedance state when high. Overrides VPPBON.
Reserved for future use.
0 (LSB)
Table 4. Read Format for Interrupt Pointer Address (0001100)
BIT
NAME
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
POR STATE
FUNCTION
7 (MSB)
0
0
0
0
0
0
0
0
6
ADD7 to ADD1 provide a return address for any interrupt query. For these devices, the
return addresses are:
5
1010000 = Channel A, ADD = low
1010001 = Channel B, ADD = low
1010010 = Channel A, ADD = high
1010011 = Channel B, ADD = high
4
3
2
1
0 (LSB)
Table 5. Read Format for Power Switch Address (1010000 or 1010010)
BIT
NAME
POR STATE LATCHED?
FUNCTION
7 (MSB) CATFAULT
0
0
0
0
0
0
0
0
Y
Y
Y
Y
Y
N
N
N
Indicates catastrophic (thermal or undervoltage lockout) fault when high.
Indicates VCCA overcurrent/undervoltage lockout when high.
Indicates VPPA overcurrent/undervoltage lockout when high.
Indicates VCCB overcurrent/undervoltage lockout when high.
Indicates VPPB overcurrent/undervoltage lockout when high.
Indicates dual part (single-channel devices would read 1).
Reserved for future use.
6
FAULT1
FAULT2
FAULT3
FAULT4
SIG/DUAL
RFU
5
4
3
2
1
0 (LSB)
RFU
Reserved for future use.
______________________________________________________________________________________ 13
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
A
B
C
D
E
F
G
H
I
J
K
L
M
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
HD:DAT
HD:STA
SU:STA
SU:DAT
t
t
SU:STO
BUF
A = START CONDITION
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
E = SLAVE PULLS SMBDATA LINE LOW
/MAX1604
Figure 3. SMBus Write Timing Diagram
fault condition is to cycle the voltage on VL in order to
g e ne ra te a p owe r-on re s e t (whic h c le a rs a ll of the
SMBus registers). Note that the SMBus registers retain
their data even if the main VX/VY supplies are turned
off, provided that VL remains powered.
S MBu s Re a d Op e ra t io n s
If the IC receives a valid address that includes a read
bit, the IC becomes a slave transmitter. After receiving
the address data, the IC generates an acknowledge
during the acknowledge clock pulse and drives the
SMBDATA line in sync with SMBCLK. The SMB proto-
col requires that the master end the read transmission
by not acknowledging during the acknowledge bit of
SMBCLK. These PC Card ICs support the repeated
start-condition method for changing data-transfer direc-
tion; that is, a write transmission followed by a repeated
start instead of a stop condition prepares the IC for
data reading (Figure 4).
When a fault occurs, SMBALERT is immediately assert-
ed and latched low. If the fault is momentary and disap-
pears before the IC is serviced, the data is still latched
in the interrupt pointer and SMBALERT remains assert-
ed. Normally, the master (host system or PCMCIA digi-
ta l c ontrolle r) now s e nd s out the inte rrup t p ointe r
address (00011000) followed by a read bit. SMBALERT
is cleared and the PC Card IC responds by putting out
its address on the bus. If the fault persists, SMBALERT
is re-asserted, but the data in the fault registers is not
reloaded. The data in the fault latches only reflects the
first time SMBALERT is asserted.
S MBu s In t e rru p t s
These PC Card power-switch ICs are slave devices
only, a nd ne ve r initia te c ommunic a tions e xc e p t b y
a s s e rting a n inte rrup t (b y p ulling SMBALERT low).
Interrupts are generated only for reporting fault condi-
tions, including overcurrent at VCCA, VCCB, VPPA, or
VPPB, undervoltage lockout, and IC thermal overload. If
an interrupt occurs, it can be an indication of impend-
ing system failure. The host system can react by going
into suspend mode or taking other action. It can come
back later to interrogate the IC via the interrupt pointer
to determine status or perform corrective action (such
as disabling the appropriate power switch that might
b e c onne c te d to a s horte d PC c a rd ). The fa s te s t
method for turning off the switches in response to a
When the part enters operating mode, a false interrupt
flag may be issued. The user needs to send the inter-
rupt address to clear the false interrupt.
Normally, the master sends out the appropriate PC Card
switch address on the bus, followed by a read bit. The
data in the fault registers is then clocked out onto the
bus (which also clears the fault registers). If the fault
p e rs is ts , the fa ult b its a nd SMBALERT a re la tc he d
again.
14 ______________________________________________________________________________________
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
/MAX1604
A
B
C
D
E
F
G
H
I
J
K
t
t
HIGH
LOW
SMBCLK
SMBDATA
t
t
t
t
t
BUF
SU:STA HD:STA
SU:DAT
SU:STO
A = START CONDITION
E = SLAVE PULLS SMBDATA LINE LOW
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
Figure 4. SMBus Read Timing Diagram
The interrupt pointer address provides quick fault iden-
tification for simple slave devices that lack the complex,
expensive logic needed to be a bus master. The host
can read the interrupt pointer to determine which slave
device generated an SMBALERT interrupt signal. The
interrupt pointer address can activate several different
Ch a n g in g S MBCLK a n d S MBDATA
S im u lt a n e o u s ly
When clocking data into the MAX1601/MAX1604, SMB-
DATA must not fall before SMBCLK. Otherwise, the
MAX1601/MAX1604 may interpret this as a start condi-
tion. Even when SMBDATA and SMBCLK fall at the
same instant, different fall times for the two signals may
cause the erroneous generation of a start condition. To
ensure that SMBDATA transitions after the falling edge of
SMBCLK, add an RC network to SBMDATA (Figure 6).
2
slave devices simultaneously, similar to an I C general
c a ll. Any s la ve d e vic e tha t g e ne ra te d a n inte rrup t
attempts to identify itself by putting its own address on
the bus during the first read byte. If more than one slave
attempts to respond, bus arbitration rules apply and the
device with the lower address code wins. The losing
device won’t generate an acknowledge and will contin-
ue to hold the SMBALERT line low until serviced, which
imp lie s tha t the hos t inte rrup t inp ut mus t b e le ve l
sensitive.
1k
VL
0.1µF
MAX1601
MAX1604
+5V
VX
VY
__________Ap p lic a t io n s In fo rm a t io n
S u p p ly Byp a s s in g
Bypass the VY, VX, and 12IN_ inputs with ceramic 0.1µF
capacitors. Bypass the VCC_ and VPP_ outputs with a
0.1µF capacitor for noise reduction and ESD protection.
Figure 5. Powering from Either VX or VY
+5V
P o w e r-Up
Apply power to the VL input before any of the switch
inputs. If VX, VY, or 12IN receive power before VL rises
above 2.8V, the supply current may be artificially high
(about 5mA). When the voltage on VL is greater than
2.8V (operating mode), the part consumes its specified
24µA. To avoid power sequencing, diode-OR VX and
VY to VL through a 1kΩ resistor (Figure 5). Take care
not to allow VL to drop below the 2.8V maximum under-
voltage lockout threshold.
10k
CIRRUS LOGIC
PULL-UP
CL-PD6730
1.5k
SMBDATA
SMBDATA
SMBCLK
100pF
MAX1601
MAX1604
SMBCLK
Figure 6. Application with Cirrus Logic Interface
______________________________________________________________________________________ 15
Du a l-Ch a n n e l Ca rd Bu s a n d P CMCIA
P o w e r S w it c h e s w it h S MBu s ™ S e ria l In t e rfa c e
__________________P in Co n fig u ra t io n
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 4372
TOP VIEW
GND
N.C.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
VL
N.C.
N.C.
N.C.
GND
VCCA
VY
12INA
VPPA
VX
MAX1601
MAX1604
VCCA
VCCA
VY
VX 8
9
VCCB
VCCB
10
11
12
13
14
VX
VY
VPPB
VCCB
/MAX1604
12INB
SMBALERT
SMBDATA
SMBCLK
ADR
SMBSUS
SSOP
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.068
MAX
0.078
0.008
0.015
0.008
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
A
A1 0.002
B
C
D
E
e
0.010
0.004
SEE VARIATIONS
α
0.205
0.209
5.20
5.38
E
H
0.0256 BSC
0.65 BSC
H
L
0.301
0.311
0.037
8˚
7.65
0.63
0˚
7.90
0.95
8˚
0.025
0˚
C
α
L
INCHES
MILLIMETERS
DIM PINS
MAX
6.33
MIN MAX MIN
0.239 0.249 6.07
0.239 0.249 6.07
0.278 0.289 7.07
0.317 0.328 8.07
0.397 0.407 10.07
e
D
D
D
D
D
14
16
20
24
28
6.33
SSOP
7.33
SHRINK
A
8.33
SMALL-OUTLINE
PACKAGE
10.33
21-0056A
B
A1
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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