MAX16030TG [MAXIM]
Dual-/Triple-/Quad-Voltage, Capacitor-Adjustable, Sequencing/Supervisory Circuits; 双/三/四电压，电容调节，排序/监控电路
| 型号： | MAX16030TG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-/Triple-/Quad-Voltage, Capacitor-Adjustable, Sequencing/Supervisory Circuits |
| 文件： | 总15页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0525; Rev 3; 1/07
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
General Description
Features
o 2.2V to 28V Operating Voltage Range
The MAX16025–MAX16030 are dual-/triple-/quad-volt-
age monitors and sequencers that are offered in a
small TQFN package. These devices offer enormous
design flexibility as they allow fixed and adjustable
thresholds to be selected through logic inputs and pro-
vide sequence timing through small external capaci-
tors. These versatile devices are ideal for use in a wide
variety of multivoltage applications.
o Fixed Thresholds for 3.3V, 2.5V, 1.8V, 1.5V, and
1.2V Systems
o 1.5% Accurate Adjustable Threshold Monitors
Voltages Down to 0.5V
o 2.7% Accurate Fixed Thresholds Over
Temperature
o Fixed (140ms min)/Capacitor-Adjustable Delay
As the voltage at each monitored input exceeds its
respective threshold, its corresponding output goes
high after a propagation delay or a capacitor-set time
delay. When a voltage falls below its threshold, its
respective output goes low after a propagation delay.
Each detector circuit also includes its own enable input,
allowing the power-good outputs to be shut off inde-
pendently. The independent output for each detector is
available with push-pull or open-drain configuration
with the open-drain version capable of supporting volt-
ages up to 28V, thereby allowing them to interface to
shutdown and enable inputs of various DC-DC regula-
tors. Each detector can operate independently as four
separate supervisory circuits or can be daisy-chained
to provide controlled power-supply sequencing.
Timing
o Independent Open-Drain/Push-Pull Outputs
o Enable Inputs for Each Monitored Voltage
o 9 Logic-Selectable Threshold Options
o Manual Reset and Tolerance Select (5%/10%) Inputs
o Small, 4mm x 4mm TQFN Package
o Fully Specified from -40°C to +125°C
Ordering Information
PIN-
PKG
PART*
TEMP RANGE
PACKAGE
CODE
MAX16025TE+
MAX16026TE+
MAX16027TP+
MAX16028TP+
MAX16029TG+
MAX16030TG+
-40°C to +125°C 16 TQFN
-40°C to +125°C 16 TQFN
-40°C to +125°C 20 TQFN
-40°C to +125°C 20 TQFN
-40°C to +125°C 24 TQFN
-40°C to +125°C 24 TQFN
T1644-4
T1644-4
T2044-3
T2044-3
T2444-4
T2444-4
The MAX16025–MAX16030 also include a reset func-
tion that deasserts only after all of the independently
monitored voltages exceed their threshold. The reset
timeout is internally fixed or can be adjusted externally.
These devices are offered in a 4mm x 4mm TQFN
package and are fully specified from -40°C to +125°C.
+Denotes lead-free package.
*For tape and reel, add a “T” after the “+.” All tape and reel
orders are available in 2.5k increments.
Applications
Multivoltage Systems
Pin Configurations
DC-DC Supplies
Servers/Workstations
TOP VIEW
Storage Systems
18
17
16
15
14
13
12
11
10
9
MR 19
CRESET 20
CDLY4 21
CDLY3 22
CDLY2 23
TH1
EN4
EN3
Networking/Telecommunication Equipment
Selector Guide
MAX16029
MAX16030
EN2
EN1
GND
MONITORED INDEPENDENT
RESET
OUTPUT
PART
VOLTAGES
OUTPUTS
8
MAX16025
MAX16026
MAX16027
MAX16028
MAX16029
MAX16030
2
2
3
3
4
4
2 (Open-drain) Open-drain
2 (Push-pull) Push-pull
3 (Open-drain) Open-drain
3 (Push-pull) Push-pull
4 (Open-drain) Open-drain
4 (Push-pull) Push-pull
24
7
CDLY1
+
1
2
3
4
5
6
THIN QFN
(4mm x 4mm)
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
CRESET......................................................-0.3V to (V
+ 0.3V)
CC
V
.........................................................................-0.3V to +30V
Input/Output Current (all pins).......................................... 20mA
CC
EN1–EN4 ....................................................-0.3V to (V
OUT1–OUT4 (push-pull).............................-0.3V to (V
OUT1–OUT4 (open-drain)......................................-0.3V to +30V
RESET (push-pull) ......................................-0.3V to (V + 0.3V)
RESET (open-drain)..................................................-0.3V to 30V
IN1–IN4.......................................................-0.3V to (V
+ 0.3V)
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
CC
CC
A
16-Pin TQFN (derate 25mW/°C above +70°C) ...........2000mW
20-Pin TQFN (derate 25.6mW/°C above +70°C) ........2051mW
24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
+ 0.3V)
+ 0.3V)
CC
CC
MR, TOL, TH1, TH0 ....................................-0.3V to (V
CDLY1–CDLY4.........................................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.2V to 28V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V and T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Operating Voltage Range
Undervoltage Lockout
V
(Note 2)
(Note 2)
2.2
1.8
28.0
2.0
V
V
CC
25–MAX1630
UVLO
1.9
50
Undervoltage-Lockout Hysteresis UVLO
V
falling
CC
mV
HYST
V
V
V
= 3.3V
= 12V
= 28V
40
47
52
75
75
80
CC
CC
CC
All OUT_ and RESET at
logic-high (IN_ current
excluded)
V
Supply Current
I
CC
µA
CC
INPUTS (IN_)
3.3V threshold, TOL = GND
3.3V threshold, TOL = V
2.970
2.805
2.250
2.125
1.620
1.530
1.350
1.275
1.080
1.020
0.492
0.463
3.052
2.888
2.313
2.187
1.665
1.575
1.387
1.312
1.110
1.050
0.5
3.135
2.970
2.375
2.250
1.710
1.620
1.425
1.350
1.140
1.080
0.508
0.481
CC
2.5V threshold, TOL = GND
2.5V threshold, TOL = V
CC
1.8V threshold, TOL = GND
1.8V threshold, TOL = V
IN_ Thresholds (IN_ Falling)
V
V
V
V
TH
CC
1.5V threshold, TOL = GND
1.5V threshold, TOL = V
CC
1.2V threshold, TOL = GND
1.2V threshold, TOL = V
TOL = GND
CC
Adjustable Threshold (IN_
Falling)
TH
TOL = V
0.472
0.5
CC
IN_ Hysteresis (IN_ Rising)
IN_ Input Resistance
IN_ Input Current
V
%
HYST
Fixed threshold
Adjustable threshold only (V
500
918
kΩ
nA
I
= 1V)
IN_
-100
+100
L
2
_______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.2V to 28V, T = -40°C to +125°C, unless otherwise specified. Typical values are at V
= 3.3V and T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CRESET AND CDLY_
CRESET Threshold
V
CRESET rising, V
= 3.3V
0.465
380
0.5
500
1
0.535
620
V
TH-RESET
CC
CRESET Charge Current
CDLY_ Threshold
I
V
= 3.3V
nA
V
CH-RESET
CC
V
CDLY_ rising, V
= 3.3V
CC
0.95
200
1.05
300
TH-CDLY
CDLY_ Charge Current
I
V
= 3.3V
250
nA
CH-CDLY
CC
DIGITAL LOGIC INPUTS (EN_, MR, TOL, TH1, TH0)
Input Low Voltage
V
0.4
V
V
V
IL
Input High Voltage
V
1.4
-1
IH
TH1, TH0 Logic-Input Floating
0.6
TOL, TH1, TH0 Logic-Input
Current
V
, V
, V
= GND or V
+1
µA
TOL TH1 TH0
CC
EN_ Input Leakage Current
MR Internal Pullup Current
OUTPUTS (OUT_, RESET)
V
V
= V
or GND
CC
-100
250
+100
820
nA
nA
EN_
CC
= 3.3V
535
V
V
V
V
V
≥ 1.2V, I
= 90µA
SINK
0.3
0.3
CC
CC
CC
CC
CC
Output Low Voltage (Open-Drain
or Push-Pull)
V
V
≥ 2.25V, I
= 0.5mA
OL
SINK
≥ 4.5V, I
= 1mA
0.35
SINK
≥ 3V, I
= 500µA
0.8 x V
0.8 x V
SOURCE
CC
CC
Output High Voltage (Push-Pull)
V
V
OH
≥ 4.5V, I
= 800µA
SOURCE
Output Leakage Current (Open-
Drain)
I
Output not asserted low, V
= 28V
OUT
1
µA
ms
LKG
CRESET = V , V
= 3.3V
140
190
260
CC CC
Reset Timeout Period
t
RP
CRESET open
0.030
TIMING
t
IN_ rising, CDLY_ open
IN_ falling, CDLY_ open
IN_ falling
35
20
35
DELAY+
IN_ to OUT_ Propagation Delay
IN_ to RESET Propagation Delay
MR Minimum Input Pulse Width
EN_ or MR Glitch Rejection
µs
µs
µs
ns
t
DELAY-
t
RST-DELAY
(Note 3)
2
280
3
t
From device enabled to device disabled
OFF
EN_ to OUT_ Delay
µs
From device disabled to device enabled
(CDLY_ open)
t
30
3
ON
MR to RESET Delay
MR falling
µs
Note 1: Devices are production tested at T = +25°C. Limits over temperature are guaranteed by design.
A
Note 2: Operating below the UVLO causes all outputs to go low. The outputs are guaranteed to be in the correct state for V
down
CC
to 1.2V.
Note 3: In order to guarantee an assertion, the minimum input pulse width must be greater than 2µs.
_______________________________________________________________________________________
3
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
Typical Operating Characteristics
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
NORMALIZED ADJUSTABLE THRESHOLD
vs. TEMPERATURE
60
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
0.994
0.993
0.992
0.991
0.990
60
MAX16026
V
= 28V
CC
MAX16026
TOL = V
CC
55
50
45
40
35
30
55
50
45
40
35
30
TOL = GND
V
= 12V
CC
V
= 3.3V
CC
ADJUSTABLE THRESHOLD
2
6
10
14
18
22
26
30
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET TIMEOUT PERIOD
NORMALIZED ADJUSTABLE THRESHOLD
vs. TEMPERATURE
25–MAX1630
vs. C
OUT_ DELAY vs. C
CRESET
CDLY_
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
0.994
0.993
0.992
0.991
0.990
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TOL = V
CC
TOL = GND
3.3V THRESHOLD
0
0
100 200 300 400 500 600 700 800 900 1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
100 200 300 400 500 600 700 800 900 1000
(nF)
C
(nF)
TEMPERATURE (°C)
C
CDLY_
CRESET
OUT_ LOW VOLTAGE
vs. SINK CURRENT
OUT_ HIGH VOLTAGE
vs. SOURCE CURRENT
FIXED RESET TIMEOUT PERIOD
vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
195
194
193
192
191
190
189
188
187
186
185
CRESET = V
CC
PUSH-PULL VERSIONS
0
1
2
3
4
6
7
5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
SOURCE CURRENT (mA)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SINK CURRENT (mA)
4
_______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
Typical Operating Characteristics (continued)
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
RESET OUTPUT LOW VOLTAGE
RESET OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
vs. SINK CURRENT
ENABLE TURN-OFF
MAX16025 toc12
1.0
3.5
CRESET = V
CDLY_ = OPEN
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CC
3.0
2.5
2.0
1.5
1.0
0.5
0
EN_
OUT_
RESET
PUSH-PULL VERSIONS
0
1
2
3
4
5
6
7
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
SOURCE CURRENT (mA)
4μs/div
SINK CURRENT (mA)
RESET TIMEOUT DELAY
ENABLE TURN-ON
MR FALLING vs. RESET
MAX16025 toc15
MAX16025 toc14
MAX16025 toc13
CRESET = V
CC
CDLY_ = OPEN
CRESET = V
CDLY_ = OPEN
CRESET = V
CDLY_ = OPEN
CC
CC
IN_
EN_
MR
OUT_
OUT_
RESET
RESET
RESET
100ms/div
40ms/div
4μs/div
MAXIMUM TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE
MR RISING vs. RESET
MAX16025 toc16
100
90
80
70
60
50
40
30
20
10
0
OUTPUT ASSERTED ABOVE THIS LINE
CRESET = V
CDLY_ = OPEN
CC
MR
RESET
1
10
100
1000
40ms/div
THRESHOLD OVERDRIVE (mV)
_______________________________________________________________________________________
5
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
Pin Description
PIN
NAME
FUNCTION
MAX16025/ MAX16027/ MAX16029/
MAX16026 MAX16028 MAX16030
Supply Voltage Input. Connect a 2.2V to 28V supply voltage to power the
1
2
1
2
1
2
3
4
5
V
device. All outputs are low when V
is below the UVLO. For noisy systems,
CC
CC
bypass V
to GND with a 0.1µF capacitor.
CC
Monitored Input 1. When the voltage at IN1 exceeds its threshold, OUT1 goes
high after the capacitor-adjustable delay period. When the voltage at IN1 falls
below its threshold, OUT1 goes low after a propagation delay.
IN1
IN2
IN3
IN4
Monitored Input 2. When the voltage at IN2 exceeds its threshold, OUT2 goes
high after the capacitor-adjustable delay period. When the voltage at IN2 falls
below its threshold, OUT2 goes low after a propagation delay.
3
3
Monitored Input 3. When the voltage at IN3 exceeds its threshold, OUT3 goes
high after the capacitor-adjustable delay period. When the voltage at IN3 falls
below its threshold, OUT3 goes low after a propagation delay.
—
—
4
Monitored Input 4. When the voltage at IN4 exceeds its threshold, OUT4 goes
high after the capacitor-adjustable delay period. When the voltage at IN4 falls
below its threshold, OUT4 goes low after a propagation delay.
—
25–MAX1630
Threshold Tolerance Input. Connect TOL to GND to select thresholds 5%
4
5
5
6
6
7
TOL
below nominal. Connect TOL to V
to select thresholds 10% below nominal.
CC
GND
Ground
Active-High Logic-Enable Input 1. Driving EN1 low causes OUT1 to go low
regardless of the input voltage. Drive EN1 high to enable the monitoring
comparator.
6
7
7
8
8
9
EN1
EN2
EN3
EN4
Active-High Logic-Enable Input 2. Driving EN2 low causes OUT2 to go low
regardless of the input voltage. Drive EN2 high to enable the monitoring
comparator.
Active-High Logic-Enable Input 3. Driving EN3 low causes OUT3 to go low
regardless of the input voltage. Drive EN3 high to enable the monitoring
comparator.
—
—
9
10
11
Active-High Logic-Enable Input 4. Driving EN4 low causes OUT4 to go low
regardless of the input voltage. Drive EN4 high to enable the monitoring
comparator.
—
Threshold Select Input 1. Connect TH1 to V
select the input-voltage threshold option in conjunction with TH0 (see Table 2).
or GND, or leave it open to
CC
8
9
10
11
—
12
13
12
13
14
15
16
TH1
TH0
Threshold Select Input 0. Connect TH0 to V or GND, or leave it open to
select the input-voltage threshold option in conjunction with TH1 (see Table 2).
CC
Output 4. When the voltage at IN4 is below its threshold or EN4 goes low,
OUT4 goes low.
—
—
10
OUT4
OUT3
OUT2
Output 3. When the voltage at IN3 is below its threshold or EN3 goes low,
OUT3 goes low.
Output 2. When the voltage at IN2 is below its threshold or EN2 goes low,
OUT2 goes low.
6
_______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
Pin Description (continued)
PIN
NAME
FUNCTION
MAX16025/ MAX16027/ MAX16029/
MAX16026 MAX16028 MAX16030
Output 1. When the voltage at IN1 is below its threshold or EN1 goes low,
OUT1 goes low.
11
14
17
OUT1
Active-Low Reset Output. RESET asserts low when any of the monitored
voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is
12
15
18
RESET asserted. RESET remains asserted for the reset timeout period after all of the
monitored voltages exceed their respective threshold, all EN_ are high, all
OUT_ are high, and MR is deasserted.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET
13
14
16
17
19
20
MR
remains low for the reset timeout period after MR is deasserted (as long as all
OUT_ are high).
Capacitor-Adjustable Reset Delay Input. Connect an external capacitor from
CRESET to GND to set the reset timeout period or connect to V
for the
CC
CRESET
default 140ms minimum reset timeout period. Leave CRESET open for internal
propagation delay.
Capacitor-Adjustable Delay Input 4. Connect an external capacitor from
—
—
15
—
18
19
21
22
23
CDLY4 CDLY4 to GND to set the IN4 to OUT4 (and EN4 to OUT4) delay period.
Leave CDLY4 open for internal propagation delay.
Capacitor-Adjustable Delay Input 3. Connect an external capacitor from
CDLY3
CDLY2
CDLY3 to GND to set the IN3 to OUT3 (and EN3 to OUT3) delay period.
Leave CDLY3 open for internal propagation delay.
Capacitor-Adjustable Delay Input 2. Connect an external capacitor from
CDLY2 to GND to set the IN2 to OUT2 (and EN2 to OUT2) delay period.
Leave CDLY2 open for internal propagation delay.
Capacitor-Adjustable Delay Input 1. Connect an external capacitor from
16
—
20
—
24
—
CDLY1 CDLY1 to GND to set the IN1 to OUT1 (and EN1 to OUT1) delay period.
Leave CDLY1 open for internal propagation delay.
Exposed Pad. EP is internally connected to GND. Connect EP to the
EP
ground plane.
Table 1. Output State*
Table 2. Input-Voltage Threshold Selector
EN_
Low
High
Low
IN_
OUT_
IN3
IN4
IN1 (ALL
VERSIONS) VERSIONS)
IN2 (ALL
TH1/TH0
LOGIC
(MAX16027/ (MAX16029/
MAX16028) MAX16030)
V
V
V
< V
Low
Low
Low
IN_
IN_
IN_
TH
TH
TH
(V)
(V)
< V
> V
(V)
(V)
Low/Low
3.3
3.3
3.3
3.3
2.5
3.3
3.3
2.5
Adj
2.5
1.8
1.5
1.2
1.8
Adj
Adj
Adj
Adj
1.8
Adj
Adj
1.8
Adj
2.5
Adj
Adj
Adj
1.5
Adj
Adj
2.5
Adj
Adj
Adj
Adj
Adj
OUT_ = high
(MAX16026/MAX16028/
MAX16030)
Low/High
Low/Open
High/Low
High/High
High/Open
Open/Low
Open/High
Open/Open
High
V
> V
IN_
TH
OUT_ = high impedance
(MAX16025/MAX16027/
MAX16029)
*When V
falls below the UVLO, all outputs go low regardless
CC
of the state of EN_ and V . The outputs are guaranteed to be
IN_
in the correct state for V
down to 1.2V.
CC
_______________________________________________________________________________________
7
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
TH0
TH1
EN4 EN3 EN2 EN1
DELAY
THRESHOLD
SELECT
LOGIC
IN1
IN2
IN3
250nA
OUT1
LOGIC
DRIVER
1V
MAX16029
MAX16030
OUT2
DELAY
DRIVER
25–MAX1630
DELAY
OUT3
DRIVER
IN4
OUT4
DELAY
DRIVER
DRIVER
GND
TOL
RESET
DELAY
LOGIC
RESET
REFERENCE
V
CDLY1
CDLY2
CDLY3
CDLY4
CRESET
MR
CC
Figure 1. MAX16029/MAX16030 Simplified Functional Diagram
8
_______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
V
CC
V
UVLO
IN_
V
TH
V
TH
t < t
ON
EN_
OUT_
t
DELAY-
t
t
ON
ON
t
DELAY+
t
OFF
t
RST_DELAY
t
t
RP
t
RP
RP
RESET
Figure 2. Timing Diagram (CDLY_ Open)
power-up initialization. When all of the monitored volt-
ages exceed their respective thresholds, an indepen-
dent reset output deasserts to allow the system
processor to operate.
Detailed Description
The MAX16025–MAX16030 are low-voltage, accurate,
dual-/triple-/quad-voltage microprocessor (µP) supervi-
sors in a small TQFN package. These devices provide
supervisory and sequencing functions for complex mul-
tivoltage systems. The MAX16025/MAX16026 monitor
two voltages, the MAX16027/MAX16028 monitor three
voltages, and the MAX16029/MAX16030 monitor four
voltages.
These devices offer enormous flexibility as there are
nine threshold options that are selected through two
threshold-select logic inputs. Each monitor circuit also
offers an independent enable input to allow both digital
and analog control of each monitor output. A tolerance
select input allows these devices to be used in systems
requiring 5% or 10% power-supply tolerances. In addi-
tion, the time delays and reset timeout can be adjusted
using small capacitors. There is also a fixed 140ms
minimum reset timeout feature.
The MAX16025–MAX16030 offer independent outputs
and enable functions for each monitored voltage. This
configuration allows the device to operate as four sepa-
rate supervisory circuits or be daisy-chained together to
allow controlled sequencing of power supplies during
_______________________________________________________________________________________
9
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
The following equation is provided to help estimate the
Applications Information
value of the resistors based on the amount of accept-
Tolerance
The MAX16025–MAX16030 feature a pin-selectable
threshold tolerance. Connect TOL to GND to select the
thresholds 5% below the nominal value. Connect TOL to
to select the threshold tolerance 10% below the
nominal voltage. Do not leave TOL unconnected.
able error:
e
× V
INTH
A
R =
1
I
L
V
where e is the fraction of the maximum acceptable
A
absolute resistive divider error attributable to the input
CC
leakage current (use 0.01 for 1%), V
is the volt-
INTH
Adjustable Input
age at which the output (OUT_) should assert, and I is
L
These devices offer several monitoring options with
both fixed and/or adjustable reset thresholds (see
Table 2). For the adjustable threshold inputs, the
the worst-case IN_ leakage current (see the Electrical
Characteristics). Calculate R2 as follows:
threshold voltage (V ) at each adjustable IN_ input is
TH
V
×R1
− V
TH
TH
R =
typically 0.5V (TOL = GND) or 0.472V (TOL = V ). To
CC
2
V
INTH
monitor a voltage V
, connect a resistive divider net-
INTH
work to the circuit as shown in Figure 3 and use the fol-
lowing equation to calculate the threshold voltage:
Unused Inputs
Connect any unused IN_ and EN_ inputs to V
.
CC
R1
R2
⎛
⎝
⎞
V
= V × 1+
⎜
TH
OUT_ Output
An OUT_ goes low when its respective IN_ input voltage
drops below its specified threshold or when its EN_ goes
low (see Table 1). OUT_ goes high when EN_ is high and
⎟
⎠
INTH
25–MAX1630
Choosing the proper external resistors is a balance
between accuracy and power use. The input to the volt-
age monitor is a high-impedance input with a small
100nA leakage current. This leakage current con-
tributes to the overall error of the threshold voltage
where the output is asserted. This induced error is pro-
portional to the value of the resistors used to set the
threshold. With lower value resistors, this error is
reduced, but the amount of power consumed in the
resistors increases.
V
is above its threshold after a time delay. The
IN_
MAX16025/MAX16027/MAX16029 feature open-drain,
outputs while the MAX16026/MAX16028/MAX16030
have push-pull outputs. Open-drain outputs require an
external pullup resistor to any voltage from 0 to 28V.
RESET Output
RESET asserts low when any of the monitored voltages
(IN_) falls below its respective threshold, any EN_ goes
low, or MR is asserted. RESET remains asserted for the
reset timeout period after all of the monitored voltages
exceed their respective threshold, all EN_ are high, all
OUT_ are high, and MR is deasserted. The MAX16025/
MAX16027/MAX16029 have an open-drain, active-low
reset output, while the MAX16026/MAX16028/
MAX16030 have a push-pull, active-low reset output.
Open-drain RESET requires an external pullup resistor to
any voltage from 0 to 28V.
V
INTH
R1
R2
MAX16025–
MAX16030
IN_
Adjustable Reset Timeout Period
(CRESET)
V
TH
All of these parts offer an internally fixed reset timeout
(140ms min) by connecting CRESET to V . The reset
CC
V
V
INTH
-1
)
timeout can also be adjusted by connecting a capaci-
tor from CRESET to GND. When the voltage at CRESET
reaches 0.5V, RESET goes high. When RESET goes
high, CRESET is immediately held low.
R1 = R2 x
(
TH
Figure 3. Setting the Adjustable Input
10 ______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
Calculate the reset timeout period as follows:
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
V
TH−RESET
t
=
×C
+ 35×10−6
CRESET
RP
I
CH−RESET
Pullup Resistor Values
The exact value of the pullup resistors for the open-
drain outputs is not critical, but some consideration
should be made to ensure the proper logic levels
when the device is sinking current. For example, if
where V
is 0.5V, I
CRESET
is 0.5µA, t
is in
TH-RESET
seconds, and C
CH-RESET
is in Farads. To ensure timing
RP
accuracy and proper operation, minimize leakage at
C
.
CRESET
V
= 2.25V and the pullup voltage is 28V, keep the
CC
sink current less than 0.5mA as shown in the Electrical
Characteristics table. As a result, the pullup resistor
should be greater than 56kΩ. For a 12V pullup, the
resistor should be larger than 24kΩ. Note that the ability
Adjustable Delay (CDLY_)
When V rises above V with EN_ high, the internal
250nA current source begins charging an external
capacitor connected from CDLY_ to GND. When the
voltage at CDLY_ reaches 1V, OUT_ goes high. When
OUT_ goes high, CDLY_ is immediately held low.
IN
TH
to sink current is dependent on the V
supply voltage.
CC
Power-Supply Bypassing
The device operates with a V supply voltage from
Adjust the delay (t
TH
the equation:
) from when V rises above
IN
DELAY
CC
V
(with EN_ high) to OUT_ going high according to
2.2V to 28V. When V
falls below the UVLO threshold,
CC
all the outputs go low and stay low until V
falls below
CC
1.2V. For noisy systems or fast rising transients on V
,
CC
V
connect a 0.1µF ceramic capacitor from V
to GND
CC
TH−CDLY
t
=
× C
+ 35 ×10−6
CDLY
DELAY
as close to the device as possible to provide better
noise and transient immunity.
I
CH−CDLY
where V
Farads, t
is 1V, I
is 0.25µA, C
is in
TH-CDLY
CH-CDLY
CDLY
is the inter-
Ensuring Valid Output with V
Down to
CC
is in seconds, and t
DELAY
DELAY+
0V (MAX16026/MAX16028/MAX16030 Only)
nal propagation delay of the device. To ensure timing
accuracy and proper operation, minimize leakage
at CDLY.
When V falls below 1.2V, the ability for the output to
CC
sink current decreases. In order to ensure a valid out-
put as V falls to 0V, connect a 100kΩ resistor from
CC
OUT/RESET to GND.
Manual-Reset Input (MR)
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low and during the reset timeout period (140ms fixed
or capacitor adjustable) after MR returns high. The MR
input has a 500nA internal pullup, so it can be left
unconnected, if not used. MR can be driven with TTL or
CMOS logic levels, or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual-reset function. External
Typical Application Circuits
Figures 4 and 5 show typical applications for the
MAX16025–MAX16030. In high-power applications,
using an n-channel device reduces the loss across the
MOSFETs as it offers a lower drain-to-source on-resis-
tance. However, an n-channel MOSFET requires a suffi-
cient V
voltage to fully enhance it for a low R
.
GS
DS_ON
The application in Figure 4 shows the MAX16027 con-
figured in a multiple-output sequencing application.
Figure 5 shows the MAX16029 in a power-supply
sequencing application using n-channel MOSFETs.
______________________________________________________________________________________ 11
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
+12V BUS
+2.5V
+1.8V
+3.3V
IN
DC-DC OUT
EN
IN
DC-DC OUT
EN
IN
DC-DC OUT
EN
EN1
IN1
IN2
IN3
OUT1 EN2
OUT2 EN3
+3.3V
V
CC
OUT3
MAX16027
MR
SYSTEM
RESET
RESET
GND
TOL
TH0
TH1
CDLY1
CDLY3
CRESET
CDLY2
25–MAX1630
Figure 4. Sequencing Multiple-Voltage System
12V
BUS
1.5V
1.8V
2.5V
TO
LOADS
3.3V
+3.3V
IN4
IN1
IN3
OUT3
OUT1
IN2
OUT2
V
CC
OUT4
EN1
EN2
EN3
EN4
MAX16029
SYSTEM
RESET
RESET
MR
CRESET
CDLY3
CDLY4
GND
TOL
TH0
TH1
CDLY1
CDLY2
Figure 5. Multiple-Voltage Sequencing Using n-Channel FETs
12 ______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
Pin Configurations (continued)
TOP VIEW
12
11
10
9
15
14
13
12
11
TH1
EN3
10
9
MR 16
CRESET 17
CDLY3 18
TH1
8
7
6
5
MR 13
CRESET 14
EN2
EN1
GND
8
EN2
EN1
GND
MAX16025
MAX16026
MAX16027
MAX16028
CDLY2
CDLY1
15
16
CDLY2
CDLY1
7
19
20
6
+
+
1
2
3
4
1
2
3
4
5
THIN QFN
(4mm x 4mm)
THIN QFN
(4mm x 4mm)
Chip Information
PROCESS: BICMOS
TRANSISTOR COUNT: 3642
______________________________________________________________________________________ 13
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
25–MAX1630
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
E
21-0139
2
14 ______________________________________________________________________________________
Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
25–MAX1630
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
E
21-0139
2
Revision History
Pages changed at Rev 1: 1, 3, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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