MAX17521ATG+ [MAXIM]
Dual Switching Controller, Current-mode, 1.85A, 600kHz Switching Freq-Max, BICMOS, TQFN-24;
| 型号： | MAX17521ATG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Current-mode, 1.85A, 600kHz Switching Freq-Max, BICMOS, TQFN-24 信息通信管理 开关 |
| 文件： | 总22页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
General Description
Benefits and Features
● Reduces External Components and Total Cost
• No Schottky—Synchronous Operation
• All-Ceramic Capacitors, Compact Layout
The MAX17521 dual-output, high-efficiency, high-voltage,
synchronous step-down DC-DC converter with integrated
MOSFETs operates over a 4.5V to 60V input. The converter
can deliver up to 1A at each output. Each output is
programmable from 0.9V to 92%V . The feedback voltage
regulation accuracy over -40°C to +125°C is ±1.7%.
● Reduces Number of DC-DC Regulators to Stock
IN
• Wide 4.5V to 60V Input
• Each Output Adjustable From 0.9V to 92%V
IN
• Pin-Selectable 560kHz or 300kHz Switching
The MAX17521 uses peak-current-mode control. Each
output can be operated in the pulse-width modulation
(PWM) or pulse-frequency modulation (PFM) control
schemes.
Frequency
• Independent Input Voltage Pin for Each Output
● Reduces Power Dissipation
• Peak Efficiency > 90%
• PFM Mode Enables Enhanced Light-Load Effi-
ciency
The MAX17521 is available in a 24-pin (4mm x 5mm)
TQFN package. Simulation models are available.
• 1μA Shutdown Current
Applications
● Industrial Control Power Supplies
● CPU, DSP, or FPGA Power
● Operates Reliably in Adverse Industrial Environments
• Hiccup Mode Overload Protection
● Distributed Supply Regulation
● General-Purpose Point of Load
• Adjustable Soft-Start Pin for Each Output
• Built-In Output Voltage Monitoring with RESET for
Each Output
• Adjustable EN/UVLO Threshold for Each Output
• Monotonic Startup Into Prebiased Load
• Overtemperature Protection
Ordering Information appears at end of data sheet.
• High Industrial -40°C to +125°C Ambient Operat-
ing Temperature Range/-40°C to +150°C Junction
Temperature Range
Typical Application Circuit
V
IN
7.5V–60V
C1
C2
2.2μF
2.2μF
EN/UVLO1
V
PGND1
PGND2
V
EN/UVLO2
IN2
IN1
MODE1
MODE2
C16
V
V
CC2
CC1
C6
1μF
1μF
SGND2
SGND1
RESET1
LX1
MAX17521
RESET2
L1
22μH
L2
15μH
V
V
OUT1
OUT2
5V, 1A
3.3V, 1A
LX2
C4
22μF
C3
10μF
R9
54.9kΩ
R1
82.5kΩ
SS1
COMP1 FSEL SYNC COMP2
SS2
FB2
FB1
C8
3300pF
C7
3300pF
R10
20.5kΩ
R5
14kΩ
R8
19.1kΩ
R2
18.2kΩ
C12
22pF
C10
33pF
C9
C11
2700pF
2700pF
L1 = XAL5050-223, 5.3 x 5.5mm
L2 = XAL4040-153, 4 x 4mm
f
= 560kHz
SW
19-7479; Rev 2; 6/17
MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Absolute Maximum Ratings
V
to PGND_......................................................-0.3V to +65V
Output Short-Circuit Duration....................................Continuous
IN_
EN/UVLO_ to SGND_............................. -0.3V to (V
LX_ to PGND_......................................... -0.3V to (V
FB_, RESET_, FSEL, MODE_,
+ 0.3V)
+ 0.3V)
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
IN_
IN_
COMP_, V
, SYNC, SS_ to SGND_ ..............-0.3V to +6V
CC_
SGND_ to PGND_................................................-0.3V to +0.3V
LX Total RMS Current ........................................................±1.6A
Continuous Power Dissipation (T = +70°C)
A
(derate 28.6mW/°C above +70°C)
(multilayer board)....................................................2285.7mW
Note 1: Junction temperature greater than +125°C degrades operating lifetimes.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 24-PIN TQFN
Package Code
T2445+1C
21-0201
90-0083
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
35°C/W
1.8°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= +24V, V
= V
= V
= 0V, C
= 2.2μF, C
= 1μF, V
= 1.5V, C
= 0.01μF, FB_ = 0.98 x V
,
IN_
SGND_
PGND_
FSEL
IN_
VCC_
EN/UVLO_
SS_
FB-REG
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. T = -40°C to +125°C, unless otherwise noted. Typical values
A
are at T = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
A
PARAMETER
INPUT SUPPLY (V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
)
IN
Input Voltage Range
V
4.5
60
3.5
260
V
IN_
Input Shutdown Current
I
V
V
= 0V, shutdown mode
1
µA
µA
IN-SH
EN_
I
> 2V
135
5
Q_PFM_
MODE_
Input Switching Current
V
V
> 2V
V
V
< 0.8V,
= 0.8V
FSEL
MODE_
COMP_
I
mA
Q_PWM_
< 0.8V
3.7
FSEL
Maxim Integrated
│ 2
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics (continued)
(V
= +24V, V
= V
= V
= 0V, C
= 2.2μF, C
= 1μF, V
= 1.5V, C
= 0.01μF, FB_ = 0.98 x V
,
IN_
SGND_
PGND_
FSEL
IN_
VCC_
EN/UVLO_
SS_
FB-REG
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. T = -40°C to +125°C, unless otherwise noted. Typical values
A
are at T = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE/UVLO (EN_)
V
V
V
rising
falling
1.19
1.11
1.215
1.135
1.24
1.16
EN_R
EN_
EN_
V
EN_F
EN_ Threshold
V
V
EN_-
TRUESD
V
V
falling, true shutdown
0.75
EN_
EN_
EN_ Input Leakage Current
I
= V = 60V, T = +25°C
300
0.8
nA
EN_
IN
A
FREQUENCY SELECTOR (FSEL)
V
V
V
V
low level
FSELR
FSEL
FSEL
FSEL
FSEL Threshold
V
V
high level
2
FSELF
FSEL Input Leakage Current
I
= V , T = +25°C
-2.5
+2.5
1.9
µA
FSEL
CC
A
MODE SELECTOR (MODE_)
V
V
V
V
low level
V
MODE_ R
MODE_
MODE_
MODE_ Threshold
V
high level
2.5
MODE_ F
MODE_ Input Leakage Current
I
= V , T = +25°C
300
nA
MODE_
MODE
CC
A
LDO (V
)
CC_
6V < V
12V < V
< 12V, 0mA < I
< 10mA
IN_
VCC_
V
Output Voltage Range
V
4.65
5
5.35
80
V
CC_
VCC_
< 60V, 0mA < I
< 2mA
IN_
VCC_
V
V
Current Limit
Dropout
I
V
V
V
V
= 4.3V, V
= 12V
17
40
mA
CC_
CC_
VCC_ -MAX
CC_
IN_
V
= 4.5V, I
= 5mA
4.1
V
V
CC_-DO
IN_
VCC_
V
rising
falling
3.85
3.55
4
4.15
3.85
VCC_-UVR
CC_
CC_
V
UVLO
CC_
V
3.7
CC_ -UVF
POWER MOSFETs
T
T
T
T
= +25°C
0.6
0.2
0.8
1.2
A
A
A
A
High-Side_ pMOS
On-Resistance
I
= 0.5A
LX_
R
Ω
DS_ -ONH
(sourcing)
= T = +125°C (Note 3)
J
= +25°C
0.35
0.45
Low-Side_ nMOS
On-Resistance
I
LX_
(sinking)
= 0.5A
R
Ω
DS_ -ONL
= T = +125°C (Note 3)
J
V
(V
= 0V, T = +25°C, V
=
EN_
A
LX_
LX_ Leakage Current
I
3
μA
LX_LKG
+ 1V) to (V
– 1V)
PGND_
IN_
SOFT-START (SS_)
Charging Current_
FEEDBACK (FB)
I
V
= 0.5V
4.7
5
5.3
0.915
100
μA
SS_
SS_
MODE_ = SGND_
MODE_ = unconnected
= 0.9V
0.885
0.9
0.915
15
FB Regulation Voltage
FB Input Bias Current
V
V
FB_REG
I
V
nA
FB
FB
Maxim Integrated
│ 3
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics (continued)
(V
= +24V, V
= V
= V
= 0V, C
= 2.2μF, C
= 1μF, V
= 1.5V, C
= 0.01μF, FB_ = 0.98 x V
,
IN_
SGND_
PGND_
FSEL
IN_
VCC_
EN/UVLO_
SS_
FB-REG
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. T = -40°C to +125°C, unless otherwise noted. Typical values
A
are at T = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE (V
)
OUT
0.92 x
V
V
> 2V; no load (Note 3)
< 0.8V; no load (Note 3)
0.92
0.92
FSEL
FSEL
V
IN
Output Voltage Range
V
V
OUT
0.96 x
V
IN
TRANSCONDUCTANCE AMPLIFIER (COMP)
Transconductance
GM_
I
= ±2.5μA
510
19
590
33
650
55
μS
μA
COMP_
COMP_ Source Current
I
COMP_ _SRC
I
COMP_
_SINK
COMP_ Sink Current
19
33
55
μA
Ω
Current Sense Transresistance
R
0.455
0.5
0.545
CS_
CURRENT LIMIT
Peak Current Limit Threshold
I
1.35
1.45
1.6
1.85
2.05
A
A
PEAK_-LIMIT
Runaway Current Limit
Threshold
I
RUNAWAY
_-LIMIT
1.85
V
V
V
< 0.8V
> 2V
0.65
0
A
A
A
MODE_
MODE_
MODE_
Sink Current Limit Threshold
I
SINK-LIMIT
PFM Peak Current
I
> 2V
0.2
0.3
0.4
PFM_
TIMINGS
V
V
V
> 2V
510
280
280
560
300
300
600
320
320
FSEL
FSEL
FSEL
V
> V
FB_
OUT_-HICF
<V
OUT_-HICF
< 0.8V
> 2V
Switching Frequency
f
kHz
%
SW_
V
V
FB_
SS_
V
Under Voltage Trip Level
FB_
V
> 0.95V (soft-start is done)
68.5
70
72.5
OUT_-HICF
to Cause HICCUP
HICCUP Timeout
Minimum On-Time
4096
85
94
97
5
Cycles
ns
t
120
96
ON_ _MIN
V
V
> 2V
92
96
FSEL
FSEL
Maximum Duty Cycle
LX_ Dead Time
D
V
= 0.98 x V
FB_ -REG
%
MAX_
FB_
< 0.8V
98
ns
Maxim Integrated
│ 4
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Electrical Characteristics (continued)
(V
= +24V, V
= V
= V
= 0V, C
= 2.2μF, C
= 1μF, V
= 1.5V, C
= 0.01μF, FB_ = 0.98 x V
,
IN_
SGND_
PGND_
FSEL
IN_
VCC_
EN/UVLO_
SS_
FB-REG
COMP_ = unconnected, LX_ = unconnected, RESET_ = unconnected. T = -40°C to +125°C, unless otherwise noted. Typical values
A
are at T = +25°C. All voltages are referenced to SGND_, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FREQUENCY SYNCHRONIZATIONS (SYNC)
V
0.8
SYNC_R
SYNC Threshold
V
V
2
SYNC_F
SYNC Input Leakage Current
SYNC Pulse Duration
I
V
= 5V ; T = +25°C
300
nA
ns
SYNC
SYNC
A
T
50
SYNC
1.1x
1.4x
SYNC Frequency
f
f
= 300kHz or 560kHz
kHz
SYNC
SW
f
f
SW
SW
RESET_
RESET_ Output Level Low
I
= 1mA
0.02
0.5
V
RESET_
RESET_ Output Leakage
Current High
V
V
V
= 1.01 x V
, T = 25°C
μA
FB_
FB_
FB_
FB_-REG
A
V
Threshold for RESET
Threshold for RESET_
OUT_
V
-OKF
falling
rising
90.5
93.5
92.5
95.5
1024
94.5
97.5
%
%
OUT_
Falling
V
OUT_
V
OUT_-OKR
Rising
RESET _ Delay After FB_
Reaches 95% Regulation
Cycles
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
Temperature rising
165
10
°C
°C
Note 2: Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are
A
guaranteed by design and characterization.
Note 3: Guaranteed by design, not production tested.
Maxim Integrated
│ 5
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics
All data measured on the Typical Application Circuit.
OVERALL EFFICIENCY
vs. INPUT VOLTAGE
3.3V OUTPUT,
EFFICIENCY vs. LOAD CURRENT
5V OUTPUT,
EFFICIENCY vs. LOAD CURRENT TOC02
TOC01
TOC03
100
100
90
80
70
60
50
40
30
20
10
0
94
92
90
88
86
84
82
80
PFM MODE
IOUT1 = IOUT2 = 750mA
IOUT1 = IOUT2 = 500mA
PFM MODE
90
80
70
60
50
40
30
20
10
0
PWM MODE
PWM MODE
IOUT1 = IOUT2 = 1A
FSEL = OPEN
38 48
VIN = 24V, FSEL = OPEN
VIN = 24V, FSEL = OPEN
100 1000
1
10
100
1000
1
10
8
18
28
LOAD CURRENT (mA)
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
5V OUTPUT, LOAD REGULATION
VIN = 24V, FSEL = OPEN
3.3V OUTPUT, LOAD REGULATION
TOC05
TOC04
5.15
5.10
5.05
5.00
4.95
4.90
3.45
3.43
3.41
3.39
3.37
3.35
3.33
3.31
3.29
3.27
3.25
VIN = 24V, FSEL = OPEN
PFM MODE
PFM MODE
PWM MODE
200
PWM MODE
200
0
400
600
800
1000
0
400
600
800
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3.3V OUTPUT, LINE REGULATION
5V OUTPUT, LINE REGULATION TOC06
TOC07
4.990
4.988
4.986
4.984
4.982
4.980
4.978
4.976
4.974
4.972
4.970
3.315
3.314
3.313
3.312
3.311
3.310
3.309
3.308
3.307
3.306
3.305
IOUT1 = 1A
IOUT1 = 750mA
IOUT2 = 1A
IOUT2 = 750mA
IOUT1 = 500mA
IOUT1 = 250mA
IOUT2 = 500mA
IOUT2 = 250mA
FSEL = OPEN
38 48
FSEL = OPEN
8
18
28
38
48
8
18
28
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Maxim Integrated
│ 6
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
All data measured on the Typical Application Circuit.
STARTUP FROM VIN,
5V OUTPUT, 1A LOAD CURRENT
STARTUP FROM EN/UVLO,
5V OUTPUT, 1A LOAD CURRENT TOC08
STARTUP FROM EN/UVLO,
3.3V OUTPUT, 1A LOAD CURRENT
TOC10
TOC09
10V/div
VEN/UVLO1
VEN/UVLO2
5V/div
5V/div
2V/div
2V/div
VIN
500mA/div
VOUT2
VOUT1
VOUT1
2V/div
IOUT2
IOUT1
IOUT1
500mA/div
500mA/div
5V/div
5V/div
VRESET1
VRESET1
5V/div
VRESET2
400μs/div
1ms/div
1ms/div
STARTUP WITH 2.5V PREBIAS,
5V OUTPUT, NO LOAD
STARTUP FROM VIN,
3.3V OUTPUT, 1A LOAD CURRENT
TOC12
TOC11
10V/div
5V/div
2V/div
VEN/UVLO1
VOUT1
2V/div
VIN
VOUT2
500mA/div
IOUT1
500mA/div
5V/div
IOUT2
5V/div
VRESET2
VRESET1
400µs/div
400µs/div
STARTUP WITH 2V PREBIAS,
3.3V OUTPUT, NO LOAD
STARTUP IN RATIOMETRIC TRACKING MODE,
1A LOAD ON BOTH OUTPUTS
TOC13
TOC14
10V/div
1V/div
5V/div
2V/div
VEN/UVLO2
VOUT2
VIN
1V/div
IOUT2
500mA/div
5V/div
VOUT1
VOUT2
VRESET2
400μs/div
400µs/div
Maxim Integrated
│ 7
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
All data measured on the Typical Application Circuit.
5V OUTPUT,PWM MODE,
(LOAD CURRENT STEPPED FROM 0.5A—1A)
STARTUP IN SEQUENTIAL TRACKING MODE,
STARTUP IN COINCIDENT TRACKING MODE,
1A LOAD ON BOTH OUTPUTS
1A LOAD ON BOTH OUTPUTS
TOC16
TOC17
TOC15
2V/div
10V/div
1V/div
VOUT1
(AC)
100mV/div
500mA/div
VOUT1
5V/div
2V/div
5V/div
VIN
1V/div
VOUT2
IOUT
VOUT1
VOUT2
1ms/div
400μs/div
100μs/div
5V OUTPUT, PWM MODE,
(LOAD CURRENT STEPPED
FROM 0 TO 0.5A)
5V OUTPUT, PFM MODE,
(LOAD CURRENT STEPPED FROM 5mA—500mA)
TOC19
TOC18
VOUT1
(AC)
VOUT1
(AC)
200mV/div
100mV/div
200mA/div
200mA/div
IOUT1
IOUT1
100μs/div
10ms/div
3.3V OUTPUT, PWM MODE,
3.3V OUTPUT,PWM MODE,
(LOAD CURRENT STEPPED FROM 0—0.5A)
(LOAD CURRENT STEPPED FROM 0.5A—1A)
TOC20
TOC21
VOUT2
(AC)
VOUT2
(AC)
100mV/div
50mV/div
500mA/div
200mA/div
IOUT2
IOUT2
100μs/div
100μs/div
Maxim Integrated
│ 8
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
All data measured on the Typical Application Circuit.
3.3V OUTPUT, PFM MODE,
(LOAD CURRENT STEPPED FROM 5mA—0.5A)
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, NO LOAD, PWM MODE
TOC24
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, 1A LOAD
TOC22
TOC23
VIN = 24V, FSEL = OPEN
VOUT1
(AC)
VOUT1
(AC)
20mV/div
20mV/div
VOUT2
(AC)
100mV/div
10V/div
1A/div
10V/div
VLX1
VLX1
IOUT2
200mA/div
ILX1
ILX1
500mA/div
VIN = 24V, FSEL = OPEN
1µs/div
1µs/div
1ms/div
STEADY-STATE SWITCHING WAVEFORMS,
STEADY-STATE SWITCHING WAVEFORMS,
5V OUTPUT, 5mA LOAD, PFM MODE
3.3V OUTPUT, 1A LOAD
TOC25
TOC26
100mV/div
VOUT2
(AC)
VOUT1
(AC)
10mV/div
10V/div
VLX2
10V/div
1A/div
VLX1
ILX2
200mA/div
ILX1
VIN = 24V, FSEL = OPEN
1µs/div
VIN = 24V, FSEL = OPEN
40µs/div
STEADY-STATE SWITCHING WAVEFORMS,
STEADY-STATE SWITCHING WAVEFORMS,
3.3V OUTPUT, NO LOAD, PWM MODE
3.3V OUTPUT, 5mA LOAD, PFM MODE
TOC27
TOC28
VIN = 24V, FSEL = OPEN
VOUT2
(AC)
10mV/div
VOUT2
(AC)
100mV/div
VLX2
VLX2
10V/div
10V/div
200mA/div
ILX2
ILX2
500mA/div
VIN = 24V, FSEL = OPEN
40µs/div
1µs/div
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Typical Operating Characteristics (continued)
All data measured on the Typical Application Circuit.
OUTPUT SHORT-CIRCUIT PROTECTION,
OUTPUT SHORT-CIRCUIT PROTECTION,
3.3V OUTPUT
5V OUTPUT
TOC29
TOC30
VOUT1
VOUT2
500mV/div
500mV/div
IOUT1
500mA/div
IOUT2
500mA/div
2ms/div
2ms/div
5V OUTPUT, 1A LOAD, BODE PLOT
TOC31
TOC32
3.3V OUTPUT, 1A LOAD, BODE PLOT
PHASE
PHASE
GAIN
GAIN
VOUT = 3.3V
VOUT = 5V
FCR = 51kHz,
Phase Margin = 62.3°
FCR = 51K,
Phase Margin = 62.3°
FREQUENCY(Hz)
FREQUENCY(Hz)
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Pin Configuration
TOP VIEW
24
23
22
21
20
+
PGND1
VIN1
1
2
3
4
5
6
7
19 PGND2
18 VIN2
EN/UVLO1
VCC1
17 EN/UVLO2
16 VCC2
15 FB2
MAX17521
FB1
SS1
14 SS2
SGND1
13 SGND2
EP
8
9
10
11
12
TQFN
(4mm × 5mm)
Pin Description
PIN
NAME
FUNCTION
Power Ground Connection of Converter 1. Connect PGND1 externally to the power ground plane.
Connect SGND and PGND pins together at the ground return path of the V bypass capacitors.
1
PGND1
CC
Power-Supply Input of Converter 1. The input supply range is from 4.5V to 60V. Decouple to PGND1
with a 2.2μF capacitor; place the capacitor close to the V and PGND1 pins.
2
3
VIN1
IN1
Enable/Undervoltage Lockout Input for Converter 1. Drive EN/UVLO1 high to enable converter 1.
Connect to the center of the resistive divider between V and SGND1 to set the input voltage at which
EN/UVLO1
IN1
the converter 1 turns on. Pull up to V
for always-on operation.
IN1
4
5
VCC1
FB1
5V LDO Output for Converter 1. Bypass V
with 1μF ceramic capacitance to SGND1.
CC1
Feedback Input for Converter 1. Connect FB1 to the center of the resistive divider between V
SGND1. See the Adjusting Output Voltage section for more details.
and
OUT1
Soft-start Input for Converter 1. Connect a capacitor from SS1 to SGND1 to set the soft-start time for
converter 1.
6
7
8
SS1
SGND1
COMP1
Analog Ground Connection for Converter 1.
Loop Compensation Pin for Converter 1. Connect an RC network from COMP1 to SGND1. See the
Loop Compensation section for more details.
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Pin Description (continued)
PIN
NAME
FUNCTION
Open-Drain RESET1 Output. The RESET1 output is driven low if FB1 drops below 92.5% of its set
value. RESET1 goes high 1024 clock cycles after FB1 rises above 95.5% of its set value. RESET1 is
9
RESET1
valid when the device is enabled and V is above 4.5V.
IN
Configures the Switching Frequency of the MAX17521. Leaving FSEL unconnected sets the switching
frequency of both the converters at 560kHz. Connecting FSEL pin to SGND_ sets the switching
frequency of both the converters at 300kHz.
10
11
FSEL
Open-Drain RESET2 Output. The RESET2 output is driven low if FB2 drops below 92.5% of its set
value. RESET2 goes high 1024 clock cycles after FB2 rises above 95.5% of its set value. RESET2 is
RESET2
valid when the device is enabled and V is above 4.5V.
IN
Loop Compensation Pin for Converter 2. Connect an RC network from COMP2 to SGND2. See the
Loop Compensation section for more details.
12
13
14
COMP2
SGND2
SS2
Analog Ground Connection for Converter 2.
Soft-Start Input for Converter 2. Connect a capacitor from SS2 to SGND2 to set the soft-start time for
converter 2.
Feedback Input for Converter 2. Connect FB2 to the center of the resistive divider between V
SGND2. See the Adjusting Output Voltage section for more details.
and
OUT2
15
16
FB2
VCC2
5V LDO Output for converter 2. Bypass V
with 1μF ceramic capacitance to SGND2.
CC2
Enable/Undervoltage Lockout Input for Converter 2. Drive EN/UVLO2 high to enable converter 2.
Connect to the center of the resistive divider between V and SGND2 to set the input voltage at which
17
18
EN/UVLO2
VIN2
IN2
the converter 2 turns on. Pull up to V
for always on operation.
IN2
Power-Supply Input of Converter 2. The input supply range is from 4.5V to 60V. Decouple to PGND2
with a 2.2μF capacitor; place the capacitor close to the V and PGND2 pins.
IN2
Power Ground Connection of Converter 2. Connect PGND2 externally to the power ground plane.
Connect SGND and PGND pins together at the ground return path of the V bypass capacitors.
19
20
PGND2
LX2
CC
Switching Node of Converter 2. Connect LX2 to the switching side of the inductor.
Configures Converter 2 to Operate in PWM or PFM Modes of Operation. Leave MODE2 unconnected
for PFM operation (pulse skipping at light loads). Connect MODE2 to SGND2 for constant frequency
PWM operation at all loads. See the MODE Setting section for more details.
21
22
23
MODE2
SYNC
Synchronizes Device to an External Clock. See the External Frequency Synchronization section for
more details.
Configures Converter 1 to Operate in PWM or PFM Modes of Operation. Leave MODE1 unconnected
for PFM operation (pulse skipping at light loads). Connect MODE1 to SGND1 for constant frequency
PWM operation at all loads. See the MODE Setting section for more details.
MODE1
24
–
LX1
EP
Switching Node of Converter 1. Connect LX1 to the switching-side of the inductor.
Exposed Pad. Connect to the SGND pins. Connect to a large copper plane below the IC to improve
heat dissipation capability.
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Block Diagram
MAX17521
V
CC
LDO
SLOPE
COMPENSATION
V
IN
HICCUP
P DRIVER
CURRENT SENSE
+
CURRENT SENSE
LX
PWM,PFM
LOGIC
PWM
COMPARATOR
COMP
N DRIVER
PGND
FSEL
CLK
OSCILLATOR
RESET
SYNC
5μA
SS
V
CC
PWM/PFM
MODE
MODE
SELECTOR
HICCUP
START
EN/UVLO
FB
RESET
LOGIC
REFERENCE
SWITCHOVER
LOGIC
900mV
COMP
GM
SGND
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
all loads, and is useful in applications sensitive to switching
frequency. However, the PWM mode of operation gives
lower efficiency at light loads compared to the PFM mode
of operation.
Detailed Description
The MAX17521 dual step-down regulator operates from
4.5V to 60V and delivers up to 1A load current on each
output. Feedback voltage regulation accuracy meets
±1.7% over load, line and temperature.
PFM Mode Operation
The device uses a peak-current-mode control scheme.
For each output, an internal transconductance error
amplifier generates an integrated error voltage. The error
voltage sets the duty cycle using a PWM comparator, a
high-side current-sense amplifier, and a slope-compensation
generator. At each rising edge of the clock, the high-side
pMOSFET turns on and remains on until either the appro-
priate or maximum duty cycle is reached, or the peak
current limit is detected.
PFM mode of operation disables negative inductor
current and additionally skips pulses at light loads for high
efficiency. In PFM mode, the inductor current is forced to
a fixed peak of 300mA every clock cycle until the output
rises to 103% of the nominal voltage. Once the output
reaches 103% of the nominal voltage, both the high-side
and low-side FETs are turned off and the device enters
hibernate operation until the load discharges the output to
101% of the nominal voltage. Most of the internal blocks
are turned off in hibernate operation to save quiescent
current. After the output falls below 101% of the nominal
voltage, the device comes out of hibernate operation,
turns on all internal blocks and again commences the
process of delivering pulses of energy to the output until it
reaches 103% of the nominal output voltage.
During the high-side MOSFET’s on-time, the inductor
current ramps up. During the second half of the switching
cycle, the high-side MOSFET turns off and the low-side
nMOSFET turns on and remains on until either the next
rising edge of the clock arrives or sink current limit is
detected. The inductor releases the stored energy as its
current ramps down, and provides current to the output
The advantage of the PFM mode is higher efficiency at
light loads because of lower quiescent current drawn
from supply. The disadvantage is that the output-voltage
ripple is higher compared to PWM mode of operation and
switching frequency is not constant at light loads.
(the internal low R
pMOS/nMOS switches ensure
DSON
high efficiency at full load).
This device also integrates switching frequency selector pin
and individual mode of operation selector pins, enable/
undervoltage lockout (EN/UVLO) pins, programmable
soft-start pins, and open-drain RESET signals for each
output.
Linear Regulator (V
)
CC
Two internal linear regulators (V
, V
) provide 5V
CC1
CC2
nominal supplies to power the internal blocks and the
low-side MOSFET drivers. The output of the V linear
Mode of Operation Selection
CC
regulators should be bypassed with 1μF ceramic capacitors
to SGND. The device employs two undervoltage-lockout
circuits that disable the internal linear regulators when
The logic state of the MODE pins are latched when V
CC
and EN/UVLO voltages exceed the respective UVLO
rising thresholds and all internal voltages are ready to
allow LX switching. If the MODE pin is open at power-
up, the corresponding output operates in PFM mode at
light loads. If the MODE pin is grounded at power-up, the
corresponding output operates in constant-frequency
PWM mode at all loads. State changes on the MODE pins
are ignored during normal operation.
V
falls below 3.7V (typ). Each of the V
regulators
CC
CC
can source up to 40mA (typ) to supply the device and to
power the low-side gate drivers.
Switching Frequency Selection
The FSEL pin programs the switching frequency of both
the converters. If the FSEL pin is open at power-up, both
the outputs operate at 560 kHz switching frequency. If the
FSEL pin is grounded at power-up, both the outputs operate
at 300kHz switching frequency.
PWM Mode Operation
In PWM mode, the inductor current is allowed to go negative.
PWM operation provides constant frequency operation at
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
current that built up during the on period of the step-down
converter. One occurrence of the runaway current limit
triggers a hiccup mode. In addition, if due to a fault
condition, output voltage drops to 70% (typ) of its nominal
value any time after soft-start is complete, hiccup mode
is triggered.
Operating Input Voltage Range
The minimum and maximum operating input voltages for
a given output voltage should be calculated as follows:
V
+ (I
×(R
+ R
))
OUT
OUT(MAX)
D
DCR
DSONLS
V
=
IN(MIN)
MAX
In hiccup mode, the converter is protected by suspending
switching for a hiccup timeout period of 4096 clock cycles.
Once the hiccup timeout period expires, soft-start is
attempted again. This operation results in minimal power
dissipation under overload fault conditions.
+(I
×R
− R
DSONHS
)
OUT(MAX)
DSONLS
ON(MIN)
V
OUT
V
=
IN(MAX)
f
× t
SW(MAX)
RESET Output
where V
is the steady-state output voltage, I
OUT
OUT
The device includes two RESET comparators to moni-
tor the output voltages. The open-drain RESET outputs
require an external pull-up resistor. RESET can sink 2mA
of current while low. RESET goes high (high impedance)
1024 switching cycles after the corresponding output voltage
increases above 95.5% of the nominal regulated voltage.
RESET goes low when the output voltage drops to below
92.5% of the nominal regulated voltage. RESET also
goes low during thermal shutdown. RESET is valid when
is the maximum load current, R
is the DC resis-
(MAX)
DCR
tance of the inductor, D
is the maximum allowable
MAX
duty ratio, f
is the maximum switching frequency
SW(MAX)
and t
is the worst-case minimum switch on-time
ON-MIN
(120ns). The following table lists the f
values to be used for calculation for different switching
frequency selection
and D
SW(MAX)
MAX
FSEL
OPEN
SGND
f
(kHz)
D
MAX
SW(MAX)
600
0.92
0.96
the device is enabled and V is above 4.5V.
IN
320
Coincident/Ratiometric Tracking and
Output Voltage Sequencing
External Frequency Synchronization (SYNC)
The soft-start pins (SS_) can be used to track the output
voltages to that of another power supply at startup. This
requires connecting the SS_ pins to an external resistor
divider from the supply which needs to be tracked. The
following figures (Figure 1 to Figure 3) show the possible
ways of configuring the MAX17521 in various tracking
modes.
The internal oscillator of the device can be synchronized
to an external clock signal on the SYNC pin. The external
synchronization clock frequency must be between 1.1 x f
SW
and 1.4 x f , where f
is the frequency selected by the
SW
SW
FSEL pin. The minimum external clock pulse-width high
should be greater than 50ns. See the SYNC section in the
Electrical Characteristics table for details.
Overcurrent Protection/HICCUP Mode
SS1
The device is provided with a robust overcurrent-pro-
tection scheme that protects the device under overload
and output short-circuit conditions. A cycle-by-cycle peak
current limit turns off the high-side MOSFET whenever
the high-side switch current exceeds an internal limit
of 1.6A (typ). A runaway current limit on the high-side
switch current at 1.85A (typ) protects the device under
high input voltage, short-circuit conditions when there is
insufficient output voltage available to restore the inductor
MAX17521
SS2
TIME
INDEPENDENT SOFT-START
Figure 1. Independent Soft-Start of Each Output
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
VOUT1
LX1
R1
R2
SS1
VOUT1
VOUT2
FB1
VOUT1
R5
MAX17521
SS2
VOUT2
LX2
TIME
COINCIDENT TRACKING
R6
R3 = R5
R4 = R6
R3
R4
FB2
Figure 2. Coincident Tracking of the Outputs
VOUT1
LX1
R1
R2
SS1
VOUT1
VOUT2
FB1
MAX17521
FB1
SS2
VOUT2
LX2
TIME
RATIOMETRIC TRACKING
R3
R4
FB2
Figure 3. Ratiometric Tracking of the Outputs
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
EN/UVLO1
VOUT1
LX1
R1
R2
EN/UVLO1
VOUT1
RESET2
FB1
MAX17521
RESET1 = EN/UVLO2
RESET1
EN/UVLO2
VOUT2
LX2
VOUT2
R3
R4
RESET2
FB2
OUTPUT VOLTAGE SEQUENCING
Figure 4. Output Voltage Sequencing
During power-off, the output voltages discharge to ground
at a rate which depends on the respective output capacitor
and load.
thermal shutdown. Carefully evaluate the total power
dissipation (see the Power Dissipation section) to avoid
unwanted triggering of the thermal-overload protection in
normal operation.
The RESET_ pins and EN/UVLO_ pins can be daisy-
chained to generate power sequencing, as shown in
Figure 4.
Applications Information
Input Capacitor Selection
Prebiased Output
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching. The
input capacitor RMS current requirement (I
single output is defined by the following equation:
When the device starts into a prebiased output, both
the high-side and low-side switches of the corresponding
channel are turned off so that the converter does not
sink current from the output. High-side and low-side
switches do not start switching until the PWM comparator
commands the first PWM pulse, at which point switching
commences first with the high-side switch. The output
voltage is then smoothly ramped up to the target value in
alignment with the internal reference.
) for a
RMS
V
×(V − V
)
OUT
OUT
IN
I
= I
×
OUT(MAX)
RMS
V
IN
where, I
is the maximum load current. I
has
OUT(MAX)
RMS
Thermal-Overload Protection
a maximum value when the input voltage equals twice
the output voltage (V = 2 x V ), so I
=
RMS(MAX)
Thermal-overload protection limits total power dissipa-
tion in the device. When the junction temperature of the
device exceeds +165°C, an on-chip thermal sensor shuts
down the device, allowing the device to cool. The ther-
mal sensor turns the device on again after the junction
temperature cools by 10°C. Soft-start resets during
IN
OUT
I
/2 when only one converter is enabled. When
OUT(MAX)
both the converters are enabled and are operating out-
of-phase, the RMS current is shared by both the input
capacitors and therefore the maximum RMS current
carried by each of the input capacitors is I
/4.
OUT(MAX)
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal long-
term reliability. Use low-ESR ceramic capacitors with high-
ripple-current capability at the input. X7R capacitors are
recommended in industrial applications for their temperature
stability. When both the converters are enabled, calculate
the input capacitance using the following equation:
of the output voltage change. The output capacitance
may be calculated as follows:
I
× t
RESPONSE
1
2
STEP
C
=
×
OUT
∆V
OUT
0.33
1
t
≅ (
+
)
RESPONSE
f
f
sw
C
0.5 ×I
×D ×(1− D)
OUT(MAX)
C
=
Where I
is the load current step, t
is the
is the allowable
STEP
RESPONSE
IN
η× f
× ∆V
IN
SW
response time of the controller, ΔV
OUT
output voltage deviation, f is the target closed-loop
C
where D = V
/V is the duty ratio of the controller,
OUT IN
crossover frequency and f
is the switching frequency.
th
SW
f
is the switching frequency, ΔV is the allowable input
SW
IN
f
is generally chosen to be 1/9 of f
.
C
SW
voltage ripple, and η is the efficiency.
Soft-Start capacitor selection
In applications where the source is located distant from
the device input, an electrolytic capacitor should be added
in parallel to the ceramic capacitor to provide necessary
damping for potential oscillations caused by the induc-
tance of the longer input power path and input ceramic
capacitor.
The device implements adjustable soft-start operation
to reduce inrush current. A capacitor connected from
the SS pin to SGND programs the soft-start time for the
corresponding output voltage. The selected output
capacitance (C ) and the output voltage (V
SEL
) determine
OUT
the minimum required soft-start capacitor as follows:
Inductor Selection
Three key inductor parameters must be specified for
operation with the device: inductance value (L), inductor
−6
C
≥ 56×10 × C
× V
SEL OUT
SS
saturation current (I
switching frequency and output voltage determine the
inductor value as follows:
) and DC resistance (R
). The
SAT
DCR
The soft-start time (t ) is related to the capacitor
SS
connected at SS (C ) by the following equation:
SS
C
SS
t
≥
SS
2.2× V
−6
OUT
SW
5.55×10
L =
f
For example, to program a 1ms soft-start time, a 5.6nF
capacitor should be connected from the SS pin to SGND.
where V
and f
are nominal values. Select an
OUT
SW
inductor whose value is nearest to the value calculated by
the previous formula.
Adjusting Output Voltage
Set the output voltages with resistive voltage-dividers
connected from the positive terminal of the output capacitor
Select a low-loss inductor closest to the calculated value
with acceptable dimensions and having the lowest pos-
(V
to SGND (see Figure 5). Connect the centre node
OUT)
sible DC resistance. The saturation current rating (I
)
SAT
of the divider to the FB pin. To optimize efficiency and
output accuracy, use the following calculations to choose
the resistive divider values:
of the inductor must be high enough to ensure that satu-
ration can occur only above the peak current-limit value
of 1.85A.
15× V
OUT
R4 =
Output Capacitor Selection
0.9
R4× 0.9
− 0.9)
X7R Ceramic Output capacitors are preferred due to their
stability over temperature in Industrial applications. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output voltage deviation is contained to 3%
R5 =
(V
OUT
where R4 and R5 are in kΩ.
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
control loop. The basic regulator loop is modeled as a
power modulator, an output feedback divider, and an error
Setting the Undervoltage-Lockout Level
The device offers an adjustable input undervoltage-
lockout level for each output. Set the voltage at which
each converter turns on with a resistive voltage-divider
connected from VIN to SGND (see Figure 6). Connect the
center node of the divider to EN/UVLO pin.
amplifier. The power modulator has DC gain G
,
MOD(dc)
with a pole and zero pair. The following equation defines
the power modulator DC gain:
2
G
=
Choose R1 to be 3.3MΩ, and then calculate R2 as:
MOD(dc)
1
0.4
(0.5 − D)
f ×L
SW
+
+
R
V
LOAD
IN
SEL
R1×1.218
R2 =
(V
−1.218)
INU
Where R
= V
/I
, f
is the switching
LOAD
OUT OUT(MAX) SW
frequency, L
the duty ratio, D = V
is the selected output inductance, D is
SEL
where V
converter is required to turn on.
is the input voltage at which a particular
INU
/V .
OUT IN
The compensation network is shown in Figure 7.
R can be calculated as:
Loop Compensation for Adjustable
Output Version
Z
The MAX17521 uses peak current-mode control scheme
and needs only simple RC networks connected from the
COMP pins to SGND to have a stable, high-bandwidth
R
= 6000× f × C
× V
SEL
Z
C
OUT
th
where R is in Ω. Choose f to be 1/9 of the switching
Z
C
frequency.
C can be calculated as follows:
Z
VOUT
C
× G
MOD(dc)
R4
SEL
C
=
Z
2×R
Z
FB
C can be calculated as follows:
P
R5
1
SGND
C
=
P
π ×R × f
Z
SW
Figure 5. Adjusting Output Voltage
VIN
TO COMP PIN
R1
R
Z
EN/UVLO
R2
C
C
P
Z
SGND
Figure 6. Setting the Undervoltage Lockout Level
Figure 7. Loop Compensation for Adjustable Output Version
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Power Dissipation
PCB Layout Guidelines
The exposed pad of the IC should be properly soldered to
the PCB to ensure good thermal contact.
Careful PCB layout is critical to achieve low switching loss-
es and stable operation. For a sample layout that ensures
first-pass success, refer to the MAX17521 evaluation kit
layouts available at www.maximintegrated.com. Follow
these guidelines for good PCB layout:
At a particular operating condition, the power losses that
lead to temperature rise of the device are estimated as
follows:
•
All connections carrying pulsed currents must be very
short and as wide as possible. The loop area of these
connections must be made very small to reduce stray
inductance and radiated EMI.
1
2
P
= (P
×( −1)) − I
×R
OUT DCR
)
LOSS
(
OUT
η
P
= V
×I
OUT
OUT OUT
•
A ceramic input filter capacitor should be placed close
to the VIN pins of the device. The bypass capaci-
tor for the VCC pins should also be placed close to
the VCC pins. External compensation components
should be placed close to the IC and far from the
inductor. The feedback trace should be routed as far
as possible from the inductor.
where P
is the output power, η is the efficiency of the
OUT
device and R
is the DC resistance of the output inductor
DCR
(refer to the Typical Operating Characteristics for more
information on efficiency at typical operating conditions).
For a typical multilayer board, the thermal performance
metrics for the package are given as:
•
•
The analog small-signal ground and the power
ground for switching currents must be kept separate.
They should be connected together at a point where
switching activity is at minimum, typically the return
terminal of the VCC bypass capacitors. The ground
plane should be kept continuous as much as pos-
sible.
θ
θ
= 35°C/ W
= 1.8°C/ W
JA
JC
The junction temperature of the device can be estimated
at any given maximum ambient temperature (T
from the following equation:
)
A_MAX
T
= T
+ θ ×P
A_MAX JA LOSS
(
)
A number of thermal vias that connect to a large
ground plane should be provided under the exposed
pad of the device, for efficient heat dissipation.
J_MAX
If the application has a thermal-management system that
ensures that the exposed pad of the device is maintained
at a given temperature (T
) by using proper heat
EP_MAX
sinks, then the junction temperature of the device can be
estimated at any given maximum ambient temperature as:
T
= T
+ θ ×P
(
)
J_MAX
EP_MAX JC LOSS
Junction temperatures greater than +125°C degrades
operating lifetimes.
Maxim Integrated
│ 20
www.maximintegrated.com
MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Ordering Information
PART
PIN-PACKAGE
PACKAGE-SIZE
MAX17521ATG+
*EP = Exposed pad.
24 TQFN-EP*
4mm X 5mm
Chip Information
PROCESS: BiCMOS
Maxim Integrated
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MAX17521
60V, 1A, Dual-Output, High-Efficiency,
Synchronous Step-Down DC-DC Converter
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
3/15
Initial release
—
2/17
Updated operating and junction temperature values
1–10, 12, 20
Updated the Typical Application Circuit on first page and replaced the Block
Diagram. Updated Typical Operating Characteristics conditions and Operating
Input Voltage Range section.
1, 6–10,
13, 15
2
6/17
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 22
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