MAX3775CEE [MAXIM]
Dual-Rate Fibre Channel Repeaters; 双速率光纤通道转发器
| 型号： | MAX3775CEE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Rate Fibre Channel Repeaters |
| 文件： | 总9页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2192; Rev 0; 10/01
Dual-Rate Fibre Channel Repeaters
General Description
Features
The MAX3772–MAX3775 are dual-rate (1.0625Gbps
and 2.125Gbps) fibre channel repeaters. They are opti-
mized for use in fibre channel arbitrated loop applica-
tions and operate from a +3.3V supply. The
MAX3772–MAX3775 exceed fibre channel jitter toler-
ance requirements and can recover data signals with
up to 0.7 unit interval (UI) jitter. The circuit’s fully inte-
grated phase-locked loop (PLL) provides a frequency
lock indication and does not need an external reference
clock. These repeaters provide low-jitter CML clock and
data outputs, and are pin compatible with the MAX3770
repeater (except RATESEL pin and exposed paddle).
The MAX3773/MAX3774 can also be used for imped-
ance transformation between 100Ω (differential) and
150Ω (differential) systems. To reduce the number of
external components, all signal inputs and outputs are
internally terminated. The MAX3772–MAX3775 are
available in 16-pin QSOP-EP packages.
ꢀ Pin Selectable 1.0625Gbps/2.125Gbps Dual-Rate
Fibre Channel Operation
ꢀ Exceeds Fibre Channel Jitter Tolerance
Requirements
ꢀ 1400mV Differential Output Swing
ꢀ +3.0V to +3.6V Operation
ꢀ No Reference Clock Required
ꢀ Frequency Lock Indication
ꢀ 290mW Power Consumption (MAX3775) at +3.3V
ꢀ 100Ω/150Ω (differential) Input/Output
Terminations
Ordering Information
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 QSOP-EP
16 QSOP-EP
16 QSOP-EP
16 QSOP-EP
Applications
1.0625Gbps/2.125Gbps Dual-Rate
Fibre Channel
MAX3772CEE
MAX3773CEE
MAX3774CEE
MAX3775CEE
Fibre Channel Data Storage Systems
Storage Area Networks
Fibre Channel Hubs
Pin Configuration appears at end of data sheet.
Selector Guide appears at end of data sheet.
100Ω/150Ω (Differential) Impedance
Transformation
Typical Operating Circuits
0.047µF
CLK+
CLK-
OUT+
Z = 75Ω
Z = 75Ω
IN+
IN-
IN+
IN-
IN+
IN-
OUT+
OUT-
OUT+
OUT-
o
o
MAX3775
MAX3750
MAX3750
Z = 75Ω
o
OUT-
Z = 75Ω
o
3.3V
3.3V
3.3V
0.1µF
0.1µF
0.1µF
FIBRE CHANNEL REPEATER
PORT BYPASS CIRCUIT
PORT BYPASS CIRCUIT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Rate Fibre Channel Repeaters
ABSOLUTE MAXIMUM RATINGS
CC
V
........................................................................-0.5V to +5.0V
Continuous Power Dissipation (T = +70°C)
A
Pin Voltage Levels (IN , CF ,
RATESEL, CLKEN, LOCK) .....................-0.5V to (V
Current into LOCK...............................................-1mA to +10mA
CML Output Currents (OUT , CLK ), R
CML Output Currents (OUT , CLK ), R
16-Pin QSOP-EP (derate 18.9mW/°C above +70°C) ...702mW
Operating Junction Temperature Range...........-55°C to +150°C
Operating Temperature Range .........................-55°C to +110°C
Storage Temperature Range ............................-55°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
+ 0.5V)
CC
= 75Ω........ +22mA
= 50Ω........ +33mA
OUT
OUT
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, 8B/10B data coding, C = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs
CC
F
AC-coupled, T = 0°C to +70°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.)
A
CC
A
PARAMETER
CONDITIONS
MIN
TYP
101
88
MAX
140
124
195
164
UNITS
MAX3772/MAX3773
MAX3774/MAX3775
MAX3772/MAX3773
MAX3774/MAX3775
80
68
CLKEN = GND
Supply Current (Note 1)
mA
115
95
146
121
CLKEN = V
Figure 1
CC
MAX3772/MAX3773,
100Ω terminated
1000
1400
1800
Differential Voltage Signal
at OUT+
mVp-p
mVp-p
MAX3774/MAX3775,
150Ω terminated
1000
1000
1000
1400
1400
1400
1800
1800
1800
MAX3772/MAX3773
100Ω terminated
Differential Voltage Signal
at CLK+
Figure 1
MAX3774/MAX3775,
150Ω terminated
1.0625Gbps operation, RATESEL = GND
-100
-100
136
75
+100
+100
325
160
175
100
0.4
Input Data Rate Range
Input Edge Speed
ppm
ps
2.125Gbps operation, RATESEL = V
20% to 80% 1.0625Gbps operation
20% to 80% 2.125Gbps operation
20% to 80% (Note 2)
CC
Data Transition Time (OUT )
Clock Transition Time (CLK )
LOCK Output Low
100
50
130
75
ps
ps
V
20% to 80% (Note 2)
I
I
= +250µA (sinking)
= -100µA (sourcing)
OL
LOCK Output High
2.4
-50
-0.3
V
OH
CLKEN, RATESEL Input Current
CLKEN, RATESEL Input Low
50
µA
V
0.8
V
+ 0.3
CC
CLKEN, RATESEL Input High
Differential Input Voltage Swing
2
V
200
2200
mVp-p
V
0.45
CC -
Input Common-Mode Voltage
V
Differential Voltage across CF+
CDR Lock Time
(Note 2)
V
V
CC
Input = CJTPAT (Note 3)
500
µs
2
_______________________________________________________________________________________
Dual-Rate Fibre Channel Repeaters
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, 8B/10B data coding, C = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs
CC
F
AC-coupled, T = 0°C to +70°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.)
A
CC
A
PARAMETER
CONDITIONS
MIN
78
TYP
100
150
100
150
100
40
MAX
122
182
122
182
UNITS
MAX3772/MAX3774
MAX3773/MAX3775
MAX3772/MAX3773
MAX3774/MAX3775
10Hz ≤ f < 100Hz
Differential Input Resistance
(IN+)
Ω
118
78
Differential Output Resistance
(OUT+, CLK+)
Ω
118
Supply Noise Tolerance
(Note 4)
100Hz ≤ f < 1MHz
1MHz ≤ f < 2.5GHz
mVp-p
10
OPERATION AT 2.125Gbps (Note 2)
Input = K28.7 (Note 5)
Input = CRPAT (Note 6)
4.4
2.8
2.9
Random Jitter Generation at
OUT+ and CLK+
ps
RMS
Input = CRPAT (Notes 6, 7)
Input = K28.5 (Note 8)
22
48
99
Deterministic Jitter on OUT+
Total Jitter at OUT+
psp-p
psp-p
Input = RPAT (Notes 7, 9)
Input = RPAT (Notes 7, 9, 10)
f = 85kHz
1.5
0.1
0.1
Sinusoidal Component of Jitter
Input = CJTPAT
(Notes 3, 7)
f = 1270kHz
f = 10MHz
UI
Tolerance (BER = 10-12
)
Total High-Frequency Jitter
Tolerance
Input = CJTPAT (Notes 3, 7, 9)
0.7
UI
Jitter Transfer Bandwidth
Measured with 50% edge density
(Note 11)
11
0.05
1.5
MHz
dB
ns
Jitter Transfer Peaking
Propagation Delay
Clock to Q Delay
1.0
Falling clock to data transition
150
280
300
ps
OPERATION AT 1.0625Gbps (Note 2)
Input = K28.7 (Note 5)
6.2
3.6
4.9
Random Jitter Generation at
OUT+ and CLK+
ps
RMS
Input = CRPAT (Note 6)
Input = CRPAT (Notes 6, 7)
Input = K28.5 (Note 8)
40
75
Deterministic Jitter on OUT+
Total Jitter at OUT+
psp-p
psp-p
Input = RPAT (Notes 7, 9)
Input = RPAT (Notes 7, 9, 10)
160
f = 42.5kHz
f = 635kHz
f = 5MHz
1.5
0.1
0.1
Sinusoidal Component of Jitter
Input = CJTPAT
(Notes 3, 7)
UI
Tolerance (BER = 10-12
)
Total High-Frequency Jitter
Tolerance
Input = CJTPAT (Notes 3, 7, 9)
0.7
UI
Jitter Transfer Bandwidth
Jitter Transfer Peaking
Propagation Delay
Measured with 50% edge density
(Note 11)
6
0.05
5
MHz
dB
ns
Clock to Q Delay
Falling clock to data transition
200
510
740
ps
_______________________________________________________________________________________
3
Dual-Rate Fibre Channel Repeaters
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, 8B/10B data coding, C = 0.047µF, lock pin loaded with ≥ 15kΩ resistor, all high-speed inputs and outputs
CC
F
AC-coupled, T = 0°C to +70°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.)
A
A
CC
Note 1: Supply current includes output currents.
Note 2: Guaranteed by design and characterization.
Note 3: Compliant jitter tolerance pattern in hex (CJTPAT):
Pattern Sequence:
Repetitions:
3E AA 2A AA AA
3E AA A6 A5 A9
6
1
87 1E 38 71 E3
87 1E 38 70 BC 78 F4 AA AA AA
AA AA AA AA AA
AA A1 55 55 E3 87 1E 38 71 E1
AB 9C 96 86 E6
41
1
12
1
1
C1 6A AA 9A A6
1
Note 4: Meets jitter output specifications with noise applied.
Note 5: K28.7 Pattern: 00 1111 1000.
Note 6: Compliant random pattern in hex (CRPAT):
Pattern Sequence:
Repetitions:
3E AA 2A AA AA
3E AA A6 A5 A9
6
1
86 BA 6C64 75 D0 E8 DC A8 B4 79 49 EA A6 65
72 31 9A 95 AB
16
1
C1 6A AA 9A A6
1
-12
Note 7: Parameter measured with 0.40UI deterministic jitter (patterns other than K28.7), and 0.20UI random jitter (BER = 10
)
applied to the input. Jitter is in compliance with the inter-enclosure, fibre channel jitter tolerance (at compliance point α )
R
and jitter output (at compliance point α ) specifications (FC-PI rev 10.0). Output jitter is specified as an output total given a
T
non-zero jitter input.
Note 8: K28.5 Pattern: 00 1111 1010 11 0000 0101
Note 9: Random Pattern in hex (RPAT): 3EB0 5C67 85D3 172C A856 D84B B6A6 65
Note 10: Using differential drive over the entire input amplitude range. The input signal bandwidth is limited to 0.75 x (bit-rate) by a 4th-
order Bessel Thompson filter or equivalent. Total jitter (TJ) is the range of the eye pattern where the BER exceeds
10-12. TJ can be estimated as TJ = DJ + 14 x RJ. DJ is deterministic jitter. RJ is a one sigma distribution (RMS) of random jitter.
Note 11: Simulation shows peaking of 0.01dB max. Characterization results limited by test equipment.
4
_______________________________________________________________________________________
Dual-Rate Fibre Channel Repeaters
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
2.125Gbps JITTER TRANSFER
vs. FREQUENCY
1.0625Gbps JITTER TRANSFER
vs. FREQUENCY
2.125Gbps JITTER TOLERANCE
1
0
1
0
100
CJTPAT
TOLERANCE EXCEEDS THE TEST
EQUIPMENT'S GENERATION LIMIT
PATTERN,
DJ = 0.4UI
RJ = 0.2UI
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
10
1
-7
-8
-7
-8
200mVp-p INPUT SIGNAL,
PATTERN = CRPAT
200mVp-p INPUT SIGNAL,
PATTERN = CRPAT
FIBRE
CHANNEL
MASK
-9
-9
-10
-10
0.1
10k
100k
1M
10M
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
OUTPUT EYE DIAGRAM AT
OUT (2.125Gbps CRPAT)
OUTPUT EYE DIAGRAM AT
OUT (1.0625Gbps CRPAT)
1.0625Gbps JITTER TOLERANCE
100
CJTPAT
TOLERANCE EXCEEDS THE TEST
EQUIPMENT'S GENERATION LIMIT
PATTERN,
DJ = 0.4UI
RJ = 0.2UI
10
1
INPUT = 600mV
DJ = 0.4UI
RJ = 0.2UI
INPUT = 600mV
DJ = 0.4UI
RJ = 0.2UI
FIBRE
CHANNEL
MASK
0.1
10k
100k
1M
10M
FREQUENCY (Hz)
1.0625Gbps OUTPUT JITTER
BATHTUB PLOT
2.125Gbps OUTPUT JITTER
BATHTUB PLOT
1E+00
1E+00
1.0625Gbps CRPAT AT INPUT
(DJ = 0.4UI, RJ = 0.2UI)
2.125Gbps CRPAT AT INPUT
(DJ = 0.4UI, RJ = 0.2UI)
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
1E-07
1E-08
1E-09
1E-10
1E-11
1E-12
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
1E-07
1E-08
1E-09
1E-10
1E-11
1E-12
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
DATA-CROSSING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
DATA-CROSSING TIME RELATIVE TO
FIRST ZERO CROSSING (UI)
_______________________________________________________________________________________
5
Dual-Rate Fibre Channel Repeaters
Pin Description
PIN
NAME
CF+
CF-
FUNCTION
CDR Filter Capacitor Positive Connection. C = 0.047µF.
1
2
F
CDR Filter Capacitor Negative Connection. C = 0.047µF.
F
3, 6, 12
4
GND
IN+
Electrical Ground
Noninverted Data Input
Inverted Data Input
Supply Voltage
5
IN-
7, 8
9
V
CC
RATESEL Rate Select Pin. TTL low selects 1.0625Gbps operation. TTL high selects 2.125Gbps operation.
10
OUT-
OUT+
CLKEN
CLK-
Inverted Data Output
11
Noninverted Data Output
13
Clock Output Enable. TTL high enables the clock output. TTL low disables the clock output.
Inverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low.
Noninverted Clock Output. Enabled when CLKEN is forced high; disabled when CLKEN is forced low.
14
15
CLK+
Frequency Lock Indicator. When data is present, a high level indicates the PLL is frequency-locked.
The output of the LOCK pin may chatter when large jitter is applied to the input.
16
EP
LOCK
Exposed
Paddle
The exposed paddle must be soldered to the circuit board ground for proper thermal performance.
Detailed Description
Figure 2 shows the functional block diagram of the
MAX3772–MAX3775 fibre channel repeaters. They con-
sist of a fully integrated PLL, CML input and output
buffers, and a data latch. The PLL consists of a com-
V
V
+
-
OUT
bined phase detector (PD) and frequency detector
500mVp-p MIN
900mVp-p MAX
(FD), a loop filter, and a voltage-controlled oscillator
(VCO). The input and output signal buffers employ low-
noise CML architecture and are terminated on-chip.
OUT
(V +) - (V -)
OUT
OUT
Phase and Frequency Detector
The frequency difference between the VCO clock and
1000mVp-p MIN
1800mVp-p MAX
the received data is derived by sampling the in-phase
and quadrature VCO outputs on the edges of the input
data signal. The FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the PD produces a voltage proportion-
al to the phase difference between the incoming data
and the internal clock. The PLL drives this error voltage
to zero, aligning the recovered clock to the center of
the incoming eye.
Figure 1. Example of Output Signal with Matched Output Loads
6
_______________________________________________________________________________________
Dual-Rate Fibre Channel Repeaters
0.047µF
CF+
CF-
V
CC
D
Q
OUT+
OUT-
IN+
IN-
OPTIONAL
50Ω OR 75Ω
PHASE/FREQ
DETECTOR
LOOP
FILTER
1
0
VCO
V
CC
÷2
OPTIONAL
100Ω OR 150Ω
TERMINATION
CLK+
CLK-
RATESEL
CLKEN
LOCK
Figure 2. Block Diagram
See the Applications Information section for the func-
Loop Filter, VCO, and Latch
The phase detector and frequency detector outputs are
summed into a loop filter. An external capacitor
(between CF+ and CF-) is required to set the PLL
damping factor. The fully integrated VCO contains an
internal current reference and filter circuitry to minimize
tionality of the RATESEL pin.
Applications Information
Input and Output Terminations
Figures 3 and 4 show models for the MAX3772–
MAX3775 inputs and outputs, including packaging parasitics.
the influence of V
noise. The VCO creates a clock
CC
output with frequency proportional to the control volt-
age applied by the loop filter. Data recovery is accom-
plished by using the recovered clock signal to latch the
incoming data to the CML output buffers, significantly
reducing output jitter.
V
CC
ESD
STRUCTURES
LOCK Output
An active high LOCK output monitor derived from the
frequency detector indicates that the PLL is frequency-
locked onto the input data. Without input data, the
LOCK signal may settle high or low. The use of a low-
pass RC filter is recommended to reduce the effects of
chatter that could be caused by high input-jitter con-
tent. For optimum jitter performance, keep the load
≥ 15kΩ on the output of the LOCK pin.
PACKAGE
1.5nH
1kΩ
IN+
0.2pF
0.4pF
1.5nH
0.2pF
0.4pF
RATESEL Input
The RATESEL input is used to select between input
data rates of 2.125Gbps and 1.0625Gbps. This func-
tion allows the repeater to sample data at the correct
data rate by selecting a divide-by-2 network, giving
maximum jitter tolerance at both data rates. The loop
bandwidth of the repeater scales with the selected fre-
quency; i.e., the loop-bandwidth at an input rate of
1.0625Gbps is half that at the input rate of 2.125Gbps.
V
- 0.450V
CC
OPTIONAL
50Ω OR 75Ω
Figure 3. Input Structure
_______________________________________________________________________________________
7
Dual-Rate Fibre Channel Repeaters
Layout Procedure
The MAX3772–MAX3775 performance can be greatly
affected by circuit-board layout and design. Use good
high-frequency design techniques, including minimiz-
ing ground inductance and using fixed-impedance
transmission lines on the data and clock signals. All IN,
OUT, and CLK pins should be connected with 0.1µF
coupling capacitors equivalent or better than X5R.
A 0.047µF capacitor should be used for the loop filter. If
DC coupling is desired pay particular attention to the
DC voltage and current requirements at the pins of
interest (see DC Electrical Characteristics). The
MAX3750/MAX3754/MAX3755 port bypass circuits can
be DC-coupled to the Maxim dual-rate repeaters. The
exposed paddle of the repeater must be connected to
ground and should be soldered onto the circuit board
for optimal thermal and electrical operation.
V
CC
PACKAGE
OPTIONAL
50Ω OR 75Ω
1.5nH
0.4pF
OUT+
OUT-
0.2pF
0.2pF
1.5nH
0.4pF
ESD
STRUCTURES
Pin Configuration
TOP VIEW
Figure 4. Output Structure
CF+
CF-
GND
IN+
1
2
3
4
5
6
7
8
16 LOCK
15 CLK+
14 CLK-
13 CLKEN
12 GND
11 OUT+
10 OUT-
Control Functions
The MAX3772–MAX3775 have two control inputs:
RATESEL and CLKEN.
MAX3772
MAX3773
MAX3774
MAX3775
RATESEL is an input that sets the operational data rate
for the repeaters. Table 1 shows the selected input
data rates when using the RATESEL function.
IN-
GND
V
CLKEN is an input that can be used to enable or dis-
able the output clock, as shown in Table 2.
CC
V
9
RATESEL
CC
QSOP-EP*
*EXPOSED PADDLE MUST BE SOLDERED TO GROUND.
Table 1. Input Data Rate Using RATESEL
Function
RATESEL LEVEL
DATA RATE SELECTED
1.0625Gbps
Selector Guide
GND
DIFFERENTIAL
INPUT
DIFFERENTIAL
OUTPUT
V
2.125Gbps
CC
PART
TERMINATION
TERMINATION
MAX3772CEE
MAX3773CEE
MAX3774CEE
MAX3775CEE
100Ω
150Ω
100Ω
150Ω
100Ω
100Ω
150Ω
150Ω
Table 2. CLKEN Function
CLKEN LEVEL
CLOCK OUTPUT
Disabled
GND
V
Enabled
Chip Information
CC
TRANSISTOR COUNT: 1280
PROCESS: Si
8
_______________________________________________________________________________________
Dual-Rate Fibre Channel Repeaters
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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